Flexible SRAM precharge system and precharge method

Abstract

Embodiments of the present disclosure include a method for precharging an SRAM. A precharge signal can be used to apply a precharge voltage to bit lines of an SRAM memory bank. Features and advantages of the present disclosure include receiving a precharge signal in the SRAM and storing the precharge signal. The precharge signal can be received and stored in the cycle in which the SRAM is performing a memory access. The stored precharge signal can be applied in a later cycle. In some embodiments, the SRAM is divided into multiple sub-banks, and multiple precharge signals are received and stored for different sub-banks. The stored precharge signals can be applied independently to different sub-banks, for example.

Description

[Technical Field]

[0001] background The present disclosure relates generally to computing, and more particularly to a flexible static random access memory (SRAM) precharging system and method. [Background technology]

[0002] SRAM memories typically precharge their bitlines to a high voltage state before a read or write access occurs. When an SRAM's bitlines are in a precharged state, the SRAM typically consumes more leakage power than when it is not precharged. In addition, several large drivers within an SRAM, such as wordline drivers, contribute a large portion of the SRAM's overall leakage power. To improve power consumption in designs using SRAM, it is desirable to minimize the time the SRAM is in a high leakage state. [Brief explanation of the drawings]

[0003] BRIEF DESCRIPTION OF THE DRAWINGS [Figure 1] 1 illustrates an SRAM according to one embodiment. [Figure 2] 1 illustrates a method for precharging an SRAM according to one embodiment. [Figure 3] 1 illustrates precharging of an SRAM according to another embodiment. [Figure 4] 1 illustrates an SRAM circuit configuration according to one embodiment. [Figure 5] 1 illustrates a layout of an SRAM according to one embodiment. [Figure 6] 1 shows a timing diagram of an SRAM. [Figure 7] 1 shows a timing diagram of another SRAM. [Figure 8] 1 shows yet another SRAM timing diagram. DETAILED DESCRIPTION OF THE INVENTION

[0004] Detailed Description Techniques for precharging SRAM are described herein. In the following description, for purposes of explanation, numerous examples and specific details are set forth in order to provide a thorough understanding of certain embodiments. Various embodiments as defined by the claims may include some or all of the features of these examples alone or in combination with other features described below, and may further include modifications and equivalents of the features and concepts described herein.

[0005] Features and advantages of the present disclosure include a mechanism for using a dynamic explicit precharge scheme on SRAMs while allowing the system to initiate a precharge request to the SRAM while a previous access is currently in progress within the SRAM. This leads to reduced leakage power without adding additional latency to SRAM accesses. The techniques described herein can be used to achieve parallel processing as described below with or without grouping SRAMs into "banks."

[0006] In some embodiments, the SRAM includes circuitry that (1) pipelines precharge / SRAM access cycles and (2) determines whether to put the SRAM into a low-leakage state after the current access or to keep the SRAM in a precharged state for the next access. The precharge request can be provided to the SRAM one or more cycles before the SRAM access. However, during the SRAM access, a new precharge request for the next access can be provided to the SRAM (e.g., a pipelined precharge function). In some embodiments, the SRAM can further determine whether to keep the header / footer voltage on and precharge the bitlines after the current access, or to turn off the header / footer voltage and not precharge the bitlines after the current access to put the SRAM into a low-leakage state. These techniques provide a flexible solution without degrading precharge performance, because the SRAM can dynamically either keep the precharge input asserted all the time or explicitly precharge on demand.

[0007] Additionally, in some embodiments, the SRAM allows dynamic precharging of selected memory sub-banks of the SRAM for more refined precharging. Further, a precharge reset input (e.g., pre-charge-reset-all) is provided to the SRAM, which can clear the precharged SRAM bitlines of all sub-banks and, in some embodiments, can clear pipelined precharge requests within the SRAM, for example.

[0008] 1 illustrates an SRAM 101 according to one embodiment. SRAM 101 includes an SRAM memory bank 111 and an SRAM access control circuit 110. SRAM memory bank 111 is configured to store bits of data 120 (e.g., using CMOS transistors in a latch configuration) and includes a plurality of bit lines 121 (e.g., typically two bit lines—BL and BL*). SRAM access control circuit 110 is comprised of digital logic circuitry for performing operations on SRAM memory bank 111, such as reading and writing data to and from an array of bit cells in memory bank 111.

[0009] Advantageously, the SRAM access control circuit 110 is coupled to a plurality of bit lines 121 of the SRAM memory bank 111 to precharge the plurality of bit lines 121 to access bits 120 of stored data. The SRAM access control circuit 110 receives and stores a precharge signal 112. The precharge control signal 112 can be stored to precharge the bit lines for a subsequent cycle when the SRAM access control circuit 110 is accessing bits 120 of data stored in the SRAM memory bank 111 in a current cycle.

[0010] Accordingly, the SRAM circuit may include a pre-charge request input (Pre-chg IN'') that receives a pre-charge signal. The pre-charge signal may be a digital signal and, in various embodiments, may include, for example, one or more bits. The pre-charge signal may be used by the SRAM to assert a pre-charge request, for example, when an SRAM access (e.g., a read or write) is already in progress.

[0011] For example, the SRAM access control circuit 110 can receive and store the precharge signal 112 to implement any of the following scenarios: When the SRAM access control circuit is not accessing a bit of data stored in the SRAM memory bank in the current cycle, the precharge signal can cause a plurality of bit lines to be precharged. Similarly, when the SRAM access control circuit is accessing a bit of data stored in the SRAM memory bank in the current cycle, the precharge signal can be stored in the SRAM access control circuit to automatically precharge a plurality of bit lines when the current memory access is completed. Alternatively, when the precharge signal indicates that there will be no precharge for a subsequent cycle, the SRAM access control circuit does not precharge the bit lines when the current memory access is completed. Furthermore, when the precharge signal indicates that there will be no precharge for a subsequent cycle, the SRAM access control circuit can further turn off one or more head switches that provide power to a plurality of word lines when the current memory access is completed. An example of a head switch is further provided below.

[0012] 2 illustrates a method for precharging an SRAM according to one embodiment. At 201, bits of data are stored in an SRAM memory bank including a plurality of bit lines. At 202, while the SRAM access control circuit is accessing the bits of data stored in the SRAM memory bank in a current cycle, a precharge signal for a subsequent cycle is received and stored by the SRAM access control circuit. At 203, the bit lines are precharged by the SRAM access control circuit based on the precharge signal to access the bits of data stored in the SRAM memory bank.

[0013] FIG. 3 illustrates precharging an SRAM according to another embodiment. During cycle 0 301, upstream logic 302 of the system may generate a precharge signal at 303. The upstream logic may, for example, accommodate an impending memory read or write. A precharge signal 304 is coupled to the SRAM 309, indicating that precharging will occur in a subsequent cycle. The SRAM 309 may be simultaneously performing another read or write when the precharge signal is received. The SRAM 309 may store the precharge signal for use in a later cycle, for example. During cycle 1 305, information for performing an operation may be provided to the SRAM, such as an address, a write command (in the case of a write), e.g., a read / write control signal, and a memory enable signal. During cycle 2, a memory access operation is performed in the current cycle (cycle 2) using the precharge signal received in the previous cycle.

[0014] FIG. 4 illustrates an SRAM circuit configuration according to one embodiment. This exemplary diagram shows an SRAM access control circuit 401, a word line driver section 490, and a column 491 of memory banks, each containing a pair of bit lines (BL / BL*) 450-451 and corresponding bit cells 460a-x. In this example, the precharge signal comprises a four-bit digital signal ("pre-charge<3:0>") for precharging four corresponding sub-banks of the four-division memory shown below. It should be understood that other embodiments may use other memory divisions. The precharge bit may be stored, for example, in a flip-flop (e.g., a set-reset flip-flop) 430-433 and coupled to a precharge output ("pre-charge out*," active low) coupled to a particular bit line.

[0015] This example shows two bit lines 450-451 coupled to a plurality of bit cells 460a-x. Bit cell 460a includes cross-coupled inverters 410-411 coupled to bit lines 450-451 via NMOS transistors 412-413 controlled by word line inputs wL0-x, for example. Each inverter may include two transistors. Accordingly, the bit cell of FIG. 4 is an example of a six-transistor (6T) bit cell. In this example, the precharge output of SRAM access control circuit 401 is coupled to the gates of PMOS transistors 420-421 coupled between bit lines 450-451 and power supply voltage Vdd. When pre-charge out* 499 is high (inactive), PMOS transistors 420-422 are off and the bit lines are floating. However, during precharge, pre-charge out* is low (active) and PMOS transistors 420-422 turn on, connecting bit lines 450-451 together to Vdd, thereby precharging the bit lines before the word line input is applied (at which point precharge is turned off).

[0016] 4 further illustrates another aspect of the present disclosure. The SRAM can include a word line driver section 490 including an inverter-configured transistor for each word line (e.g., 403 / 404 and 405 / 406), which is coupled to Vdd via a head switch transistor 402. Advantageously, the head switches can be turned off when no accesses are occurring, further reducing leakage and power consumption. Thus, the same precharge signal used to control the precharge can be used to control the head switches, further improving performance of the memory circuit.

[0017] 4, the SRAM access control circuit 401 further includes a precharge reset input. The precharge reset can be used to clear the precharge of the plurality of bit lines. In some embodiments, the precharge reset input can also clear the precharge signal stored in the SRAM access control circuit (e.g., in a FF). In some embodiments, the precharge reset input also turns off one or more head switches that provide power to the plurality of word lines (e.g., disables "header_en").

[0018] FIG. 5 illustrates an SRAM layout according to one embodiment. In various implementations, an SRAM memory bank can be divided into multiple sub-banks. FIG. 5 illustrates a division including four sub-banks 510, 511, 512, and 513. One local data input / output bus (LDIO) passes between sub-banks 510 and 511, and one LDIO bus passes between sub-banks 512 and 513. Accordingly, the banks are shown as 510a-b, 511a-b, 512a-b, and 513a-b (on either side of each LDIO). SRAM access control circuitry can be configured, for example, at 550. Word line drivers and head switches can be configured in a layout such as that shown at 520 and 521. In this example, the control circuitry can include, for example, a four-bit digital precharge signal for activating bit lines in different sub-banks 510-513 and four precharge output signals. In some embodiments, multiple precharge voltages can be applied independently within a sub-bank.

[0019] Figure 6 shows a timing diagram for an SRAM. The following example uses the six-transistor (6T) bit cell shown above. 6T SRAM memories can use column multiplexing, such as 4-to-1 or 8-to-1. Typically, only one set of bit lines (such as one of four or one of eight) is in use during a memory operation for a given I / O column of the memory. The other unused sets of bit lines, with their corresponding word lines asserted, have either the true or complement side (BL, BL*) of the bit lines discharged by the bit cells, but the values ​​on those bit lines may not be used (e.g., known as a "dummy read"). Before an SRAM memory access, the bit lines are precharged before the word lines are asserted. While the SRAM is in the idle / ready state, all word lines are deasserted and the bit lines can be precharged in preparation for the next memory operation. However, the bit lines can be left floating in the idle state to prevent leakage, as long as they are precharged before the next memory access. During a memory access, the word line is asserted and the bit line is driven to a logic 0 or logic 1 state. During a read or dummy read, either the true or complement bit line is driven to a logic "0" by the memory bit cell. The other bit line starts from a precharged logic "1" state, then is first held in a logic "1" state by the bit line capacitance, and later held in a "weak 1" state by the bit cell because the bit cell drives only a "weak 1" through its NMOS access transistor. During a write operation, the bit line is driven to a logic 0 or logic 1 state by a write driver coupled to the bit line (not shown).

[0020] Referring to Figure 6, precharge_set_bank <x>The input remains asserted. When idle, the bit lines are precharged (precharge_set_bank <x>When asserted, int_pch_en_rslat_bank <x>is asserted). When the SRAM is accessed (for example, when the word line is turned on), the bit line precharge is turned off and the bit line is driven to logic 0 / 1. After the access, int_pch_en_rslat_bank <x>is asserted, the bit lines are precharged.

[0021] Figure 7 shows a timing diagram for another SRAM. In this example, precharge occurs at least one cycle before the memory access. For example, precharge may occur two, three, or one cycle before the memory access, or more loosely, precharge may occur N cycles before the mem_en cycle, where N is any integer greater than or equal to 1. When precharge_set_bank is asserted on the rising edge of the clock (clk), the corresponding bit lines are precharged. When mem_en is asserted on the rising edge of clk, precharge_set_bank is asserted on those cycles. <x>is not asserted, so int_pch_en_rslat_bank <x>is reset to logic 0. When the SRAM is being accessed (e.g., when the word line is turned on), the bit lines are driven to logic 0 / 1. After the access, int_pch_en_rslat_bank <x>is deasserted, causing the bit lines to float.

[0022] Figure 8 shows yet another timing diagram for an SRAM. This example shows the precharge of two consecutive memory accesses. Three time segments 801, 802, and 803 are shown for the inputs (clk, mem_en, addr<11:10>, and precharge_set_bank <x>) is an internal flip-flop (int_pch_en_rslat_bank) which can be, for example, a reset / set flip-flop. <x>) output. In this particular example, each memory access takes two cycles. Therefore, there are three ways to assert the "precharge_set_bank" input while a memory access is occurring. When mem_en is asserted on the rising edge of the clock, precharge_set_bank <x>is also asserted, the corresponding int_pch_en_rslat_bank <x>remains asserted (801 and 803), otherwise the corresponding int_pch_en_rslat_bank <x>is deasserted (802; deasserted midway between the two clock cycles in which mem_en is asserted).

[0023] Advantageously, in this example, the timing of the precharge signal, here "precharge_set_bank <3> " controls when the precharge voltage is applied to the bit lines of the bank, demonstrating the flexibility of the technique presented herein. During the time period labeled 801, a rising clk edge occurs with addr A1 asserted, and precharge_set_bank <3> remains asserted for two clock cycles. Therefore, the bit line voltage int_pch_en_rslat_bank <3> remains asserted until the rising edge of clk when addr B1 is asserted. <3> The first clock cycle of precharge_set_bank is associated with access A1, while the second clock cycle of precharge_set_bank is associated with access A2. <3> The second clock cycle of the precharge_set_bank associated with access B1 is associated with access B1. <3> This is an example of how the second clock cycle of occurs simultaneously with the mem_en of the ongoing access A1.

[0024] During the time period marked 802, precharge_set_bank <3> is not asserted, the clk rising edge on which addr A2 is asserted is therefore int_pch_en_rslat_bank <3> However, precharge_set_bank is deasserted. <3> During the asserted rising edge of clk (halfway between addr A2 and addr B2), int_pch_en_rslat_bank <3> is asserted to precharge the bit lines in preparation for the B2 memory access. <3> The first clock cycle of precharge_set_bank is associated with access A2, while the second clock cycle of precharge_set_bank is associated with access A3. <3> The second clock cycle of the time period 802 is associated with access B2. <3> 10. This is an example of how the second clock cycle of access A1 occurs simultaneously with the SRAM bitcell access of access A2 in progress.

[0025] During the time period marked 803, precharge_set_bank <3> The int_pch_en_rslat_bank input is asserted for 3 clock cycles. <3> has the same behavior. Time segment 803 shows a combination of 801 and 802. precharge_set_bank <3> The first clock cycle of precharge_set_bank is associated with access A3, while the second clock cycle of precharge_set_bank is associated with access A4. <3> The second and third clock cycles of 801 are associated with access B3. Time segment 803 further illustrates the pipelining of 801 and 802 (precharge of B3 is asserted during the mem_en cycle of A3 and the sram bitcell access cycle of A3), as well as how the technique may keep the precharge input active for multiple cycles for a given request (in this case B3) if desired.

[0026] Further examples Each of the following non-limiting features in the following examples may exist independently or may be combined in various permutations or combinations with one or more of the other features in the following examples. In various embodiments, the present disclosure may be implemented as a processor or a method.

[0027] An embodiment of the present disclosure includes a static random access memory (SRAM) circuit including: an SRAM memory bank configured to store bits of data, the SRAM memory bank including a plurality of bit lines; and an SRAM access control circuit coupled to the plurality of bit lines of the SRAM memory bank, the SRAM access control circuit configured to precharge the plurality of bit lines to access the stored bits of data, wherein when the SRAM access control circuit is accessing the bits of data stored in the SRAM memory bank in a current cycle, the SRAM access control circuit receives and stores a precharge signal for a subsequent cycle.

[0028] In another embodiment, the present disclosure includes a method of precharging an SRAM circuit, the method including: storing bits of data in an SRAM memory bank, the SRAM memory bank including a plurality of bit lines; receiving and storing, by the SRAM access control circuit, a precharge signal for a subsequent cycle while the SRAM access control circuit is accessing the bits of data stored in the SRAM memory bank in a current cycle; and precharging, by the SRAM access control circuit, the plurality of bit lines based on the precharge signal to access the bits of data stored in the SRAM memory bank.

[0029] In one embodiment, the precharge signal causes a plurality of bit lines to precharge when the SRAM access control circuit is not accessing a bit of data stored in the SRAM memory bank in the current cycle.

[0030] In one embodiment, when the SRAM access control circuit is accessing a bit of data stored in the SRAM memory bank in the current cycle, a precharge signal is stored in the SRAM access control circuit to automatically precharge the plurality of bit lines when the current memory access is completed.

[0031] In one embodiment, when the precharge signal indicates that there is no precharge for the subsequent cycle, the SRAM access control circuit does not precharge the bit lines when the current memory access is completed.

[0032] In one embodiment, when the precharge signal indicates that there is no precharge for a subsequent cycle, the SRAM access control circuit further turns off one or more head switches that provide power to the plurality of word lines when the current memory access is completed.

[0033] In one embodiment, the precharge signal includes one or more bits.

[0034] In one embodiment, the SRAM memory bank includes multiple memory sub-banks, and the precharge signal includes a corresponding number of bits for independently precharging the multiple memory sub-banks.

[0035] In one embodiment, the number of bits is equal to the number of memory sub-banks.

[0036] In one embodiment, the SRAM access control circuit includes a number of precharge signal inputs equal to the number of memory sub-banks.

[0037] In one embodiment, the SRAM access control circuit includes a plurality of flip-flops for storing a plurality of precharge signal inputs equal to the number of the plurality of memory sub-banks.

[0038] In one embodiment, the SRAM access control circuit includes a precharge reset input for clearing the precharge of the plurality of bit lines.

[0039] In one embodiment, the precharge reset input also clears the precharge signal stored in the SRAM access control circuit.

[0040] In one embodiment, the precharge reset input also turns off one or more head switches that power multiple word lines.

[0041] The above description illustrates various embodiments, along with examples of how aspects of some embodiments may be implemented. The above examples and embodiments should not be considered the only embodiments, but are presented to illustrate the flexibility and advantages of some embodiments, as defined by the following claims. Based on the above disclosure and the following claims, other arrangements, embodiments, implementations, and equivalents may be used without departing from the scope of the present specification, as defined by the claims.< / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x> < / x>

Claims

1. 1. A static random access memory (SRAM) circuit comprising: an SRAM memory bank configured to store bits of data, the SRAM memory bank including a plurality of bit lines; an SRAM access control circuit coupled to the plurality of bit lines of the SRAM memory bank, the SRAM access control circuit configured to precharge the plurality of bit lines to access bits of the stored data; Including, 1. An SRAM circuit, wherein the SRAM access control circuit receives and stores a precharge signal for a subsequent cycle when the SRAM access control circuit is accessing a bit of data stored in the SRAM memory bank in a current cycle.

2. 2. The SRAM circuit of claim 1, wherein said precharge signal causes said plurality of bit lines to precharge when said SRAM access control circuitry is not accessing a bit of data stored in said SRAM memory bank in said current cycle.

3. 2. The SRAM circuit of claim 1, wherein the precharge signal is stored in the SRAM access control circuit when the SRAM access control circuit is accessing a bit of data stored in the SRAM memory bank in the current cycle to automatically precharge the plurality of bit lines when the current memory access is completed.

4. 2. The SRAM circuit of claim 1, wherein when the precharge signal indicates no precharge for the subsequent cycle, the SRAM access control circuit does not precharge the bit lines when the current memory access is completed.

5. 5. The SRAM circuit of claim 4, wherein when the precharge signal indicates that there is no precharge for the subsequent cycle, the SRAM access control circuitry further turns off one or more head switches that supply power to a plurality of word lines when the current memory access is completed.

6. 2. The SRAM circuit of claim 1, wherein the precharge signal comprises one or more bits.

7. 2. The SRAM circuit of claim 1, wherein the SRAM memory bank includes a plurality of memory sub-banks, and the precharge signal includes a corresponding number of bits for independently precharging the plurality of memory sub-banks.

8. 8. The SRAM circuit of claim 7, wherein the number of bits is equal to the number of the plurality of memory sub-banks.

9. 8. The SRAM circuit of claim 7, wherein said SRAM access control circuitry includes a plurality of precharge signal inputs equal to the number of said plurality of memory sub-banks.

10. 10. The SRAM circuit of claim 9, wherein said SRAM access control circuitry comprises a plurality of flip-flops for storing said plurality of precharge signal inputs equal to said number of said plurality of memory sub-banks.

11. 2. The SRAM circuit of claim 1, wherein said SRAM access control circuitry includes a precharge reset input for clearing said precharge of said plurality of bit lines.

12. 12. The SRAM circuit of claim 11, wherein the precharge reset input further clears a precharge signal stored in the SRAM access control circuit.

13. 13. The SRAM circuit of claim 12, wherein the precharge reset input further turns off one or more head switches that provide power to multiple word lines.

14. 1. A method of precharging an SRAM circuit, comprising: Storing bits of data in an SRAM memory bank, the SRAM memory bank including a plurality of bit lines; receiving and storing, by the SRAM access control circuitry, a precharge signal for a subsequent cycle while the SRAM access control circuitry is accessing a bit of data stored in the SRAM memory bank in a current cycle; precharging, by the SRAM access control circuit, the plurality of bit lines based on the precharge signal to access the stored data bits of the SRAM memory bank; A method comprising:

15. 15. The method of claim 14, wherein the precharge signal causes the plurality of bit lines to precharge when the SRAM access control circuitry is not accessing a bit of data stored in the SRAM memory bank in the current cycle.

16. 15. The method of claim 14, wherein the precharge signal is stored in the SRAM access control circuit when the SRAM access control circuit is accessing a bit of data stored in the SRAM memory bank in the current cycle to automatically precharge the plurality of bit lines when the current memory access is completed.

17. 15. The method of claim 14, wherein when the precharge signal indicates no precharge for the subsequent cycle, the SRAM access control circuit does not precharge the bit lines when the current memory access is completed.

18. 15. The method of claim 14, wherein the precharge signal comprises one or more bits.

19. 15. The method of claim 14, wherein the SRAM memory bank includes a plurality of memory sub-banks, and the precharge signal includes a corresponding number of bits for independently precharging the plurality of memory sub-banks.

20. 15. The method of claim 14, wherein the SRAM access control circuitry includes a precharge reset input for clearing the plurality of bit lines and for clearing a precharge signal stored in the SRAM access control circuitry.

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