System and method for testing non-volatile memory

Abstract

According to one embodiment, a method for characterizing a non-volatile memory includes applying a first voltage on a word line conductively coupled to a non-volatile memory cell and measuring a current through the non-volatile memory cell in response to the application of the first voltage, using a sense amplifier to compare the current through the non-volatile memory cell to a plurality of different first currents generated by an adjustable current source while applying the same first voltage to the word line, and determining a measured current based on the comparison.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This international application claims priority to U.S. Patent Application No. 18 / 069,408, filed December 21, 2022, which is incorporated herein by reference.

[0002] The present invention relates generally to electronic systems and methods, and in particular embodiments to systems and methods for testing non-volatile memory. [Background technology]

[0003] Programmable nonvolatile memory (NVM) is useful in many applications because it retains stored information even when power is removed from the memory. There are many different types of programmable nonvolatile memory, including, but not limited to, programmable read-only memory (PROM), electrically erasable read-only memory (EEPROM), and flash memory. These memory types have several charge storage methods, including, but not limited to, placing charge on a floating gate or silicon-oxide-nitride-oxide-silicon (SONOS) storage material or node. Like other types of memory, programmable NVM is typically constructed as an array of bit cells arranged in rows and columns. Each bit cell may contain one split gate or two transistors (i.e., 1T, 1.5T, or 2T cells). During programming, charge is injected into the storage node of one of the transistors. During normal operation of an NVM, bit cells are read by selecting a row of bit cells via word lines (WLs) and measuring the output current of each bit cell via a sense amplifier coupled to the bit line.

[0004] In practical memory applications, the device characteristics of bit cells may vary with respect to semiconductor process parameters and may vary randomly with respect to each other. Therefore, in some applications, the threshold of each bit cell is measured to determine read parameters, write parameters, and sense amplifier threshold currents. In addition, some bit cells may be defective and require replacement using redundant bit cells. However, given the large size of modern non-volatile memories, it can take a long time to measure and characterize each cell, resulting in increased test costs. Summary of the Invention [Means for solving the problem]

[0005] According to one embodiment, a method for characterizing a non-volatile memory includes applying a first voltage on a word line conductively coupled to a non-volatile memory cell and measuring a current through the non-volatile memory cell in response to the application of the first voltage, using a sense amplifier to compare the current through the non-volatile memory cell to a plurality of different first currents generated by an adjustable current source while applying the same first voltage to the word line, and determining a measured current based on the comparison.

[0006] According to another embodiment, a memory system includes an integrated circuit having a memory array including non-volatile memory cells, a plurality of word line drivers coupled to the memory array, a plurality of sense amplifiers coupled to the memory array and coupled to an external data bus, an adjustable current source coupled to the plurality of sense amplifiers, a first control circuit configured to set the adjustable current source to a test current and apply a first address to the memory array to select a row of non-volatile memory cells, and a second control circuit configured to read outputs of the sense amplifiers and iteratively update the test current based on the outputs of the sense amplifiers to determine a current through at least one non-volatile memory cell of the row of non-volatile memory cells.

[0007] According to a further embodiment, a method for characterizing a non-volatile memory includes the steps of operating the non-volatile memory in a test mode, including applying a row address to the non-volatile memory to select a row of non-volatile memory cells, grounding a word line coupled to the selected row of non-volatile memory cells, measuring a current in at least one non-volatile memory cell of the row of non-volatile memory cells with the word line grounded, incrementing the row address, and performing a test read of the non-volatile memory, and repeating the step of performing the test read using the incremented row address.

[0008] For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: [Brief explanation of the drawings]

[0009] [Figure 1A] FIG. 1 is a block diagram of a memory system according to one embodiment. [Figure 1B] 1 shows a diagram illustrating an exemplary read current distribution for N memory cells. [Figure 2A] 1 is a flowchart of a method according to an embodiment of the present invention. [Figure 2B] 4 is another flowchart of a method according to an embodiment of the present invention. [Figure 3A] FIG. 2 is a block diagram illustrating the operation of a sense amplifier according to one embodiment. [Figure 3B] FIG. 2 is a schematic diagram of a word line driver according to one embodiment. [Figure 3C] FIG. 1 is a schematic diagram of a conventional word line driver. [Figure 3D] FIG. 2 is a schematic diagram of a level shifter according to an embodiment. [Figure 3E] FIG. 10 is a schematic diagram of a level shifter according to another embodiment. [Figure 3F] FIG. 2 is a schematic diagram of a reference current generator according to one embodiment. [Figure 4]FIG. 2 is a timing diagram according to one embodiment. [Figure 5A] FIG. 2 illustrates an exemplary memory cell that can be used to implement a non-volatile memory array according to an embodiment of the present invention. [Figure 5B] FIG. 2 is another diagram illustrating an exemplary memory cell that can be used to implement a non-volatile memory array according to embodiments of the present invention. [Figure 5C] FIG. 10 is yet another diagram illustrating an exemplary memory cell that can be used to implement a non-volatile memory array according to embodiments of the present invention. [Figure 5D] FIG. 1 is a cross-sectional view illustrating one embodiment of an N-type SONOS transistor. [Figure 6] FIG. 1 illustrates a processing system that can be used to implement portions of the system of an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Corresponding numbers and symbols in different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly show relevant aspects of preferred embodiments and are not necessarily drawn to scale. To more clearly describe particular embodiments, figure numbers may be followed by letters indicating variations of the same structure, material, or process step.

[0011] The following detailed description provides ways to make and use presently preferred embodiments. It should be understood, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments described are merely illustrative of specific ways to make and use the invention and do not limit the scope of the invention.

[0012] In one embodiment, a nonvolatile memory array is characterized by grounding the word lines of each row of memory cells and measuring the output current of each nonvolatile memory cell. The current measurements may be performed by repeatedly comparing the output current of each memory cell to an adjustable reference current using a sense amplifier to estimate the output current of the nonvolatile memory cell. In some embodiments, these measurements may be performed quickly row by row using the nonvolatile memory's existing sense amplifiers, external data bus, and sense amplifier current reference circuitry used during normal read operations of the memory.

[0013] Grounding the word lines in a non-volatile memory array during testing allows for faster characterization of memory cells compared to conventional systems that measure memory cell thresholds by applying a variable voltage to the word lines. Conventional systems require additional time to charge and discharge the higher voltage applied to the word lines before and after each measurement. Embodiment memory systems also have a size advantage over conventional systems because the word line drivers do not need to include high-voltage circuitry to apply test voltages to the word lines. Using smaller word line drivers reduces silicon area and lowers costs.

[0014] FIG. 1A illustrates one embodiment of a memory system including an integrated circuit 100 having non-volatile memory. As shown, the integrated circuit 100 includes a memory array 104, a row decoder 102, a word line driver 103, a controller 106, sense amplifiers 112, a column decoder 110, I / O logic 114 coupled to an external data bus, a reference current generator 108, and a test controller 116. The reference current generator 108 may also be referred to as an adjustable current source. In some embodiments, the integrated circuit 100 may be coupled to an external tester 120 while the memory array 104 is being characterized. Instead of or in addition to the tester 120, the integrated circuit 100 may also include a built-in self-test (BIST) circuit 118 that performs one or more characterization functions for the memory array 104. The BIST circuit 118 and the tester 120 are shown with dashed lines to indicate that these blocks may or may not be present in some embodiments.

[0015] In various embodiments, the components of integrated circuit 100 may be located on a single monolithic semiconductor integrated circuit, such as a single semiconductor substrate, and / or on the same monolithic semiconductor integrated circuit as other disclosed system components.

[0016] As shown, memory array 104 includes an array of non-volatile memory cells 105. Each non-volatile memory cell 105 is connected to a respective word line (WL1...WLn) and a respective bit line (BL1...BLm). During normal operation of the memory, row decoder 102 decodes a row address based on address data ADDR provided at the input to I / O logic 114. The decoded row address is used to select one of the word lines (WL1...WLn) via word line driver 103, which activates a row of memory cells 105 generating a respective read current on a respective bit line (BL1...BLm). The current on each bit line is compared to a reference current generated by reference current generator 108 using sense amplifier 112. Column decoder 110 selects a column of memory array 104 to be sent to sense amplifier 112, the output of which is sent to data line DATA via I / O logic 114. Controller 106 is a memory controller that controls the operation of the memory. In some embodiments, the reference current generator 108 may be implemented using a current digital-to-analog converter (CDAC).

[0017] In various embodiments, the non-volatile memory cells 105 of the memory array 104 are measured to (1) characterize the thresholds of programmed and / or unprogrammed memory cells; (2) determine memory operating parameters such as sense amplifier thresholds and program times; and / or (3) identify non-functional memory cells that should be replaced by redundant memory cells.

[0018] As mentioned above, in various embodiments, the state of each memory cell is evaluated by determining whether the read current of each memory cell is greater than or less than a threshold current. Figure 1B shows a diagram illustrating an example distribution of read currents for N memory cells, which may represent, for example, N memory cells 105 in a row of non-volatile memory array 104.

[0019] As shown, each memory cell generates a first, lower current when the memory cell is written to a "1" state 134 and a second, higher current when the memory cell is written to a "0" state 132. In an alternative embodiment, the assignment of binary states "0" and "1" may be reversed. The current I NOM0 represents the average or nominal current of N memory cells when written to the "0" state, and the current I NOM1 represents the average or nominal current of N memory cells when written to the "1" state. Current I THRESH represents the threshold current used by the sense amplifier 112 during a read operation to determine whether a particular bit is written to a "0" state or a "1" state. For example, during a read operation, the sense amplifier determines whether the current generated by the memory cell is greater than or equal to the threshold current I THRESH is greater than the threshold current I THRESH If the value is less than 1, the memory cell 105 is determined to be written to the "1" state.

[0020] In a real memory system, the actual current I generated by each memory cell NOM0 and I NOM1 can vary during operation due to changes in operating memory parameters including, but not limited to, temperature, power supply voltage, memory cell aging, and write duration and write voltage. Therefore, the memory must maintain a nominal "0" write current I NOM0 and the threshold current I THRESH and the nominal "1" write current I NOM1 and the threshold current I THRESH There is some current margin between I MARG The current margin I MARG may be selected to ensure sufficient noise margin and accurate operation over a specified temperature range and supply voltage. This margin may be adjusted by adjusting the threshold current I to meet the given margin requirement. THRESH , and in FIG. 1B, for a "0" write bit, INOM0 -I THRESH , and I for a "1" write bit NOM1 +I MARG In various embodiments, the I NOM0 -I THRESH Write a "0" bit and I NOM0 +I THRESH A "1" write bit that produces a measured current less than I is considered to have sufficient margin. For example, an outlier measurement 136 for a "0" write bit would be considered to have sufficient margin if its associated current is less than I NOM0 -I THRESH is larger than the current margin I MARG On the other hand, the outlier measurement 138 for a "1" write bit is within the range of the associated current I NOM1 +I THRESH Because it is larger, the current margin I MARG It's outside.

[0021] In various embodiments, measurements of the current of one or more memory cells are determined by iteratively setting a current threshold for the sense amplifier 112 and reading the output of the sense amplifier 112. For example, in one embodiment, the current generated by the reference current generator is set to a first current value for comparison to a particular current threshold. The row of memory cells is then read using the first current value. The resulting read values ​​provide an indication of which memory cells generate currents above and below the first current value. For example, with reference to FIG. 1B, after the row of memory cells has been written to have a "1" value, the first current value is I NOM1 +I MARG If set to , all of the measured memory cells return a "1" value except for bit 138, which returns a "0" value indicating that its current is greater than the first current value. This information can be used, for example, to replace bit 138 with a redundant memory cell or to replace the entire row with a redundant row of memory cells.

[0022] In various embodiments, memory cells of a row of memory cells may be written to "1" values, "0" values, or a combination of "1" and "0" values ​​according to a particular pattern. For example, in one embodiment, all of the memory cells of a particular row are written to have "0" values. The reference current generated by reference current generator 108 is then continuously varied to determine one or more current levels for the written memory cells using a "linear search." For example, referring to FIG. 1B, the initial reference current is set to current I NOM0 , so that the initial measurement returns a set of measurements indicating that the memory cells in the row have current levels less than the initial reference current. During each subsequent measurement, the reference current is successively lowered so that the returned measurements indicate a mix of memory cells having currents above and below the reference current. For example, if the reference current is I NOM0 If in, I NOM0 Memory cells with a current greater than I return a value of "0" and NOM1 A memory cell having a current below 136 returns a value of "1." The current of a particular memory cell may be estimated to be between a first reference current, at which a "0" is returned, and a second reference current, at which a "1" is returned. These measurements may continue until the current of each memory cell is determined. For example, once the reference current is below the current of the outlier memory cell 136, all memory cells will return a value of "0." In an alternative embodiment, a linear search may be performed to find a memory cell with a lower current (e.g., I NOM0 -I MARG The value starts at (less than 1000 kJ / s) and can be increased continuously.

[0023] In some embodiments, the current of a subset of memory cells may be estimated, for example, by iteratively adjusting the current threshold to determine a "worst case" memory cell (e.g., memory cell 136) that is written as "0" or by determining a predetermined number of "worst case" memory cells with the lowest current, and then terminating the memory measurement.

[0024] In some embodiments of the present invention, different search techniques can be applied in addition to the linear search technique described above. For example, the current of a particular memory cell can be successively approximated using a binary search algorithm. In such embodiments in which the reference current generator 108 is implemented using a CDAC, the CDAC is initialized to an initial DAC word in which the MSB of the DAC is set to “1” and the remaining least significant bits are set to “0.” When a measurement of a particular bit indicates “0,” meaning the reference current is less than the current generated by the particular memory cell, consider the case in which all bits are written to “0.” The MSB and the second most significant bit of the CDAC are set to “1” for the next measurement. On the other hand, when a measurement of a particular bit indicates “1,” meaning the reference current is greater than the current generated by the particular memory cell, the MSB is set to “0” and the second most significant bit of the CDAC is set to “1” for the next measurement. The measurement proceeds bit by bit until all bits of the CDAC input word are used. In some embodiments, the CDAC word can be stored and modified using successive approximation registers according to well-known successive approximation techniques known in the art. In such an embodiment, the final value stored in the successive approximation register at the end of the measurement represents the estimated value of the memory cell.

[0025] In some embodiments, the measurement results of multiple memory cells may be used to determine a reference current when performing a binary search to identify one or more outlier memory cells and / or to identify and measure the current of a “worst-case” memory cell. In such embodiments, the binary search may be performed to minimize the number of bits that generate a “1” value when the bits are pre-programmed to a “0” state. For example, the current used for each successive approximation trial may be determined by comparing the number of “1” values ​​generated during two consecutive cycles to converge to a current value where a single memory cell (e.g., the outlier 136) returns a “1” value while the remaining memory cells return a “0” value. In other words, the system is configured to find the cell (or cells) with the lowest erase current.

[0026] While the above current estimation techniques are described with respect to measuring memory cells programmed to a "0" value, it should be understood that similar measurement techniques can also be used to measure memory cells programmed to a "1" value. In such an embodiment, the polarity of the measurements of the corresponding measurement sequence is reversed and adjusted to correspond to the reversed programmed polarity. For example, instead of determining the current of the outlier cell having the minimum current, the current of one or more outlier cells (e.g., cell 138) having the maximum current is determined.

[0027] Each measurement may be controlled using, for example, BIST 118, tester 120, controller 106, test controller 116, or a combination thereof. For example, one of these controllers provides a row address to row decoder 102, analyzes the resulting data output by sense amplifiers 112, and determines the next current to be generated by reference current generator 108. In embodiments in which test operations are controlled by external tester 120 during test mode, the row address of the test row may be provided via address bits ADDR, and the measured bits may be read out via data bus DATA coupled to I / O logic 114. Reference current generator 108 and the test mode operation of the embodiment may be controlled by tester 120 via control bus CTL coupled to I / O logic 114. In some embodiments, various test sequences may be controlled in part by test controller 116. For example, when tester 120 places integrated circuit 100 in a characterization test mode, test controller 116 may configure controller 106 to apply the necessary test control sequence and configure reference current generator 108 to adjust its reference current to the requested test current or series of test currents described above. In some embodiments, tester 120 may provide only the initial row address for characterization. In such embodiments, the row address may be incremented internally by test controller 116 and / or BIST 118 after each measurement for each row.

[0028] In some embodiments, tester 120 may analyze the output of each measurement iteration described above and determine the next current value to be provided by reference current generator 108. In alternative embodiments, the analysis of each measurement iteration and / or the determination of the next current value may be performed internally by BIST 118. In some embodiments, the entire characterization method may be performed internally by BIST 118, and the results of the characterization may be made externally available via I / O logic 114.

[0029] In various embodiments, the characterization results may be tabulated in various formats. In one embodiment, the characterization results may include a list of memory cell address locations and their associated current thresholds. This list may detail each memory cell in each row or subset of memory cells, such as one or more “worst-case” memory cells and their associated current thresholds. These current thresholds may be expressed in terms of CDAC input words provided to reference current generator 108 and / or converted to equivalent current thresholds and / or equivalent threshold voltage values ​​based on other physical measurements or characterization data. This conversion may be performed, for example, using a database, a look-up table, or other data conversion methods known in the art.

[0030] The memory systems described herein may be implemented in a variety of semiconductor processes, such as standard CMOS processes and / or CMOS processes modified to accommodate one or more particular types of non-volatile memory. While embodiments of the memory architecture are described herein with reference to silicon-oxide-nitride-oxide-silicon (SONOS) devices developed according to, for example, Infineon's SONOS process technology, other embodiments of the invention are not so limited and may include substantially any type of memory cell developed according to substantially any non-volatile process technology.

[0031] 2A and 2B illustrate flowcharts of methods according to embodiments of the present invention. More specifically, FIG. 2A illustrates a method 200 for characterizing a non-volatile memory array in which each memory cell under test has been written with a "0," and FIG. 2B illustrates a method 230 for characterizing a non-volatile memory array in which each memory cell under test has been written with a "1." In various embodiments, methods 200 and 230 may be performed under control of test controller 116, BIST 118, and / or tester 120, depending on the particular system implementation and its specifications.

[0032] 2A, method 200 begins with entering a "margin mode" (e.g., a mode for characterizing memory cells) in step 202. This margin mode may be entered externally via a command provided to I / O logic 114 shown in FIG. 1A via control line CTL. Next, in step 204, a first row address is provided to row decoder 102. As discussed above, this row address may be provided by tester 120, BIST 118, and / or test controller 116.

[0033] In step 206, a first initial read current reference is set, for example, by providing a first CDAC input word to the reference current generator 108. This first initial read current may correspond, for example, to a first (e.g., MSB) estimate of the binary search successive approximation.

[0034] Once the initial trim current is set, the word lines of the selected row are set to a reference voltage, such as 0V (e.g., ground voltage), and an initial measurement of the selected row is made by performing a memory read in step 212. The resulting memory output (e.g., the output of sense amplifier 112) for the selected row is analyzed to determine whether the read passes a first set of conditions. In some embodiments, a read pass is defined as a memory read that produces all "0"s for each memory cell in the row of memory cells. If a read pass is encountered in step 214, the reference current generated by reference current generator 108 is increased in step 210, and step 212 is repeated with the increased reference current. In some implementations, the reference current is increased by incrementing the digital word provided to the CDAC of reference current generator 108. On the other hand, if a read pass is not encountered in step 214 (e.g., one or more bits returned by the memory read indicate a "1"), the reference current generated by reference current generator 108 is decreased in step 208, and step 212 is repeated with the decreased reference current. The reference current may be decreased, for example, by decrementing the digital word provided to the CDAC of the reference current generator 108 .

[0035] In various embodiments, steps 212, 214, and steps 208 and / or 210 are repeated until measurements are complete in step 213. In some embodiments, measurements are complete when all bits controlling the CDACs have been toggled and the current in the memory cells has been determined (within the accuracy of the CDACs), at which point the method proceeds to step 216, where the row address is incremented. If measurements are not complete, the method proceeds to step 214, as described above. In embodiments utilizing a column decoder, such as column decoder 110 shown in FIG. 1A, the current column decoder setting may be continuously incremented in step 216 to read out the entire row before the row address is incremented.

[0036] During step 218, a determination is made as to whether the incremented row address is greater than a predetermined maximum address. If the incremented row address is not greater than the maximum row address, the method proceeds to step 212, where the row corresponding to the incremented row address is measured. On the other hand, if the incremented row address is greater than the maximum row address, margin mode is exited in step 218. The predetermined maximum address may be the maximum address of the non-volatile memory, or may be a different address in embodiments where only a subset of the memory rows is measured.

[0037] Method 230 shown in FIG. 2B is similar to method 200 shown in FIG. 2A, except that memory cells in a particular row are written to have a value of “1.” Accordingly, steps 212 and 214 are replaced with steps 232 and 234, respectively. In step 234, the word lines of the selected row are set to 0V (e.g., ground voltage), and an initial measurement of the selected row is made by performing a memory read in step 234. The memory output obtained for the selected row (e.g., the output of sense amplifier 112) is analyzed to determine whether the read passed a first set of conditions. In some embodiments, a read pass is defined as a memory read that produces all “1s” for each selected memory cell in the accessed row of memory cells. If a read pass is encountered in step 234, the reference current generated by reference current generator 108 is decreased in step 208, and step 232 is repeated with the decreased reference current. On the other hand, if no read path is encountered in step 234 (e.g., one or more bits returned by the memory read indicate a "0"), the reference current generated by reference current generator 108 is increased in step 210, and step 234 is repeated with the increased reference current. Operation of the remaining steps of method 230 proceeds as described above with respect to method 200 of FIG. 2A.

[0038] Figures 3A, 3B, 3D, 3E, and 3F illustrate circuits that may be used to implement a memory system according to embodiments of the present invention. Figure 3A illustrates an embodiment memory sensing system 300 that includes memory cells 105 corresponding to memory cells in memory array 104 shown in Figure 1A, sense amplifiers 302 corresponding to sense amplifiers included in the plurality of sense amplifiers in sense amplifier block 112 shown in Figure 1A, and reference current generator 108 corresponding to the reference current generator of Figure 1A.

[0039] The memory cell 105 may be a floating gate memory cell or a non-volatile memory cell, such as a SONOS memory, configured to generate an output current Icell that depends on the memory state of the memory cell. For example, when the memory cell 105 is in a programmed state (e.g., a "1" state), a lower bit line current Icell is generated. On the other hand, when the memory cell 105 is in an erased state or a "0" state, a higher bit line current Icell is generated. Therefore, the sense amplifier 302 can be used to determine the state of the memory cell 105 by comparing the output current Icell of the memory cell 105, provided to a sense input of the sense amplifier 302, with a reference current Isense generated by a current generator 108, provided to a reference current input of the sense amplifier 302.

[0040] In operation, the sense amplifier 302 generates a first logic state for the output signal Dout when the output current Icell of the memory cell 105 is less than the reference current Isense, and generates a second logic state when the output current Icell is greater than the reference current Isense. The first and second logic states may be referred to as "low" and "high" states, or "0" and "1" states, respectively. In some embodiments, this designation may be reversed, such that the first and second logic states are referred to as "high" and "low" states, or "1" and "0" states, respectively.

[0041] The memory cells 105 and sense amplifiers 302 may be constructed using memory cell and sense amplifier circuits known in the art. For example, the memory cells 105 may be SONOS or charge trap memory cells or floating gate memory cells, and the sense amplifiers 302 may be implemented using cross-coupled CMOS latch circuits. In alternative embodiments, other memory cell and sense amplifier circuits may be used. The reference current generator 108 may be implemented using a CDAC, such as the CDAC 360 described below with respect to FIG. 3F.

[0042] 3B illustrates an embodiment word line driver circuit 320 that can be used to implement each of the multiple word line driver circuits in the word line driver block 103 illustrated in FIG. 1A. As illustrated, the word line driver 320 includes a p-channel MOS transistor P1 coupled between a positive bias node (also referred to as a “positive supply node”) and a word line drive node WLS, and an n-channel MOS transistor N1 coupled between the word line drive node WLS and a negative bias node (also referred to as a “negative supply node”). The positive bias node and the negative bias node are coupled to positive and negative power supply circuits (e.g., positive and negative charge pumps), respectively. In some embodiments, a body connection NWELL of the p-channel MOS transistor P1 may be coupled to the positive bias node, and a body connection PWELL of the n-channel MOS transistor N1 may be coupled to the negative supply node.

[0043] Negative level shifter 322 and positive level shifter 324 provide gate drive signals to the gates of p-channel MOS transistor P1 and n-channel MOS transistor N1, respectively, based on signals received from low-voltage row control block 326. In one embodiment, low-voltage row control block 326 represents the output stage of row decoder 102 shown in FIG. 1A. During normal memory read and write operations, the positive and negative bias nodes provide the necessary voltages for word line WLS, as described below with respect to FIGS. 5A, 5B, 5C, and 5D. However, during memory cell characterization operations of the embodiments described herein, the negative bias node is set to a ground voltage such that word line WLS is grounded.

[0044] The device characterization system and method of the embodiment, which allows for word line grounding during memory cell characterization, advantageously allows for the use of physically compact word line drivers. This is in contrast to voltage-mode characterization systems and methods, which apply variable voltages to the word lines and require additional circuitry to perform memory cell characterization. A wide range of voltages is applied to the measured memory cells to determine their voltage thresholds. In some cases, devices rated to handle higher voltages are used to provide these voltages during characterization. In some embodiments, each of these devices may be composed of multiple devices connected together and occupy a large amount of silicon area. FIG. 3C shows a conventional word line driver that includes transistors P1 and N1 and level shifters 322 and 324, along with additional circuitry to support the application of a wider positive voltage range to the word line via p-channel MOS device P3. The additional circuitry further includes p-channel MOS device P2, n-channel MOS device N2, and level shifters 333 and 335, which receive input from low-voltage row control margin mode block 336. The conventional word line driver 330 includes more devices than the word line driver 320 of the embodiment. In various embodiments of the present invention, the word line drivers of the embodiments are physically smaller than conventional word line drivers used in voltage mode device characterization.

[0045] 3D and 3E illustrate level shifter circuits 332 and 334, respectively, that can be used to implement the negative level shifter circuit 322 and the positive level shifter circuit 324 of the word line driver 320 shown in FIG. 3B. FIG. 3D illustrates the negative level shifter 332 configured to convert a low-level logic signal (e.g., 0V to 1V) to a high-level logic signal having a signal swing between a negative and a positive power supply (e.g., −3V to 0 / 1V). In various embodiments, the voltage range at the output of the negative level shifter circuit 332 is sufficient to drive the gate of an n-channel MOS transistor N1 (FIG. 3B), which functions as a high-side switching transistor. The negative level shifter 332 includes a cross-coupled latch including p-channel MOS transistors P4 and P5, n-channel MOS transistors N4 and N5, and input p-channel MOS transistors P6 and P7, which function as input transistors. In operation, a low logic input IN LV is applied to the gate of p-channel MOS transistor P6, and an inverted low logic input Inb LV is applied to the gate of p-channel MOS transistor P7. The resulting current drawn by transistors P6 and P7 causes the cross-coupled latch circuit to provide a high logic signal at output node Out HV and an inverted high logic signal at OutB HV.

[0046] Referring to FIG. 3E, a positive level shifter 334 is shown configured to convert a low-level logic signal (e.g., 0V to 1V) to a high-level logic signal having a signal swing between a negative and positive power supply (e.g., 0 / 1V to 4V). In various embodiments, the voltage range at the output of the positive level shifter circuit 334 is sufficient to drive the gate of a p-channel MOS transistor P1 (FIG. 3B), which functions as a low-side switching transistor. The positive level shifter 334 includes a cross-coupled latch including p-channel MOS transistors P4 and P5, n-channel MOS transistors N4 and N5, and input n-channel MOS transistors N8 and N9, which function as input transistors. In operation, a low-level logic input IN_LV is applied to the gate of N-channel MOS transistor N8, and an inverted low-level logic input IN_LV is applied to the gate of N-channel MOS transistor N9. The resulting current drawn by transistors N8 and N9 causes the cross-coupled latch circuit to provide a high-level logic signal at output nodes Out_HV and Out_B_HV.

[0047] It should be understood that the level shifter circuits 332 and 334 shown in Figures 3D and 3E are two examples of many possible level shifter circuits that may be used to implement the level shifting function of word line driver 320. In alternative embodiments of the present invention, other level shifting circuits known in the art may be used.

[0048] 3F illustrates a CDAC circuit 360 that can be used to implement the reference current generator 108 shown in FIG. 1A. As shown, the CDAC circuit 360 is configured to provide an output current Iout based on an n-bit digital input word CDAC[n:1]. In one embodiment of the present invention, the CDAC 360 is an 8-bit CDAC. However, other bit resolutions may be used in other embodiments, depending on the particular embodiment and its specifications.

[0049] As shown, CDAC circuit 360 is implemented as a binary-weighted circuit with n binary-weighted output branches and a bias branch. The bias branch includes p-channel MOS transistors 362, 364, and 366 and a resistor RC1. A current source Iin provides a bias voltage P0_BIAS to transistor 366 in the input branch and transistors 372, 378, and 384 in the output branch. The output of resistor RC1 provides a bias voltage P1_BIAS to transistor 364 in the input branch and transistors 370, 376, and 382 in the output branch, and transistor 362 is used to match the on-resistance of select transistors 368, 374, and 380 in the output branch. As shown, transistors 362, 364, and 366 each have a relative size of one unit and are configured to receive a DC bias current Iin. The first output branch includes cascode transistor 372, current source transistor 370, and select transistor 368, which is activated when the LSB of the digital input word CDAC[n:1] is asserted. As shown, transistors 368, 370, and 372 have the same size as transistors 362, 364, and 366 in the bias branch, causing the first branch to generate a current of 1×Iin when the branch is active. The second output branch includes cascode transistor 378, current source transistor 376, and select transistor 374, which is activated when the second most significant bit of the digital input word CDAC[n:1] is asserted. As shown, transistors 374, 376, and 378 are twice the size of transistors 362, 364, and 366 in the bias branch, causing the second branch to generate a current of 2×Iin when the branch is active. The nth output branch includes a cascode transistor 384, a current source transistor 382, ​​and a select transistor 380 that is activated when the MSB of the digital input word CDAC[n:1] is asserted. As shown, transistors 380, 382, ​​and 384 are n times the size of transistors 362, 364, and 366 in the bias branch, allowing the nth branch to operate twice as fast when the branch is active. n-1Generate a current of 4 to 2 × Iin, if applicable. n-2 The additional binary weighted branch with weightings of is not shown for simplicity of explanation. In some embodiments, CDAC circuit 360 may be implemented using equally weighted segments or a combination of equally weighted and binary weighted segments, depending on the specifications of a particular embodiment. In further alternative embodiments, other CDAC circuits and architectures known in the art may also be used.

[0050] 4 shows a timing diagram illustrating the states of row address lines RADDR and data lines DATA coupled to I / O logic 114 of FIG. 1A during an embodiment memory cell characterization procedure when memory array 104 is being read. Also shown is a clock signal CLK representing the system clock of the memory system, and a control signal R_VALID, which is asserted when the first row address is written to the test memory system. At time t1, when R_VALID is asserted, the first row address A1 is written to row address lines RADDR. This causes a first measurement, represented by data word D1, to appear on data lines DATA at time t2, with each word length matching the width of the row being measured or the width of the selected column. For example, in an embodiment in which 128 sense amplifiers are coupled to the selected column and / or in an embodiment using 128 sense amplifiers coupled to a 128-bit wide row, data words D1, D2, D4, and D4 are each 128 bits wide. Five clock cycles later, the initial row address A1 is incremented to A2 and applied to row decoder 102, and the corresponding data word D2 appears on data lines DATA at time t3. This process is repeated until the read of memory 104 is complete. In embodiments utilizing a column decoder, such as column decoder 110 shown in FIG. 1A, a separate read is performed for each selected column until the entire row is read before the row address RADDR is incremented.

[0051] The timing scheme shown in FIG. 4 is advantageous because it allows a large number of measurements to be output in a small number of clock cycles, thereby increasing the speed of characterization testing and reducing the test cost per device. In contrast, conventional embodiments require a significant delay between measurements of each row of the memory array to allow for the charging and discharging of word lines by on-board charge pumps. Additionally, embodiments that provide measurement data over a wide external data bus are more efficient because the measurement data can be quickly clocked out in a faster parallel manner than using a narrower output bus or a narrower dedicated bus such as a narrow test or control bus.

[0052] It should be understood that the timing diagram of Figure 4 is merely one example of possible signal timing relationships in an embodiment characterization system. In alternative embodiments, different timing relationships may be implemented. For example, in alternative embodiments, the data line DATA may be updated every n clock cycles, where n is less than or greater than 5.

[0053] 5A, 5B, and 5C illustrate exemplary memory cells that can be used to implement memory cells 105 of non-volatile memory array 104 according to embodiments of the present invention. For example, one embodiment of a one transistor (1T) SONOS memory cell is shown in FIG. 5A, including an N-type SONOS transistor having a gate terminal, a drain terminal, and a source terminal (see FIG. 5C). The gate of the SONOS transistor is coupled to receive a SONOS word line (WLS) voltage, the drain is coupled to receive a bit line (BL) voltage, and the source is coupled to receive a source line (SL) voltage. As shown in cross section in FIG. 5C, the substrate or well of the SONOS transistor is coupled to receive a well bias voltage (P-WELL). Exemplary voltages for reading, erasing, and programming a 1T SONOS memory cell are shown in FIG. 5D and are discussed in more detail below.

[0054] One embodiment of a 2T SONOS memory cell is shown in FIG. 5B, which includes an N-type SONOS transistor and an N-type pass device (FNPASS) included to minimize leakage current during read operations. The SONOS gate is coupled to receive a SONOS word line (WLS) voltage, and the drain is coupled to receive a bit line (BL) voltage. The source of the SONOS transistor is coupled to the drain of the FNPASS device. The gate of the FNPASS device is coupled to receive a word line (WL) voltage, and the source is coupled to receive a source line (SL) voltage. The SONOS and FNPASS devices may share a common substrate connection. As with the 1T cell, a well bias voltage (P-WELL) is supplied to the substrates of the SONOS and FNPASS devices to facilitate read, erase, and program operations. Exemplary voltages for reading, erasing, and programming a 2T SONOS memory cell are shown in FIG. 5D and are discussed in more detail below.

[0055] Figure 5C is a cross-sectional view of one embodiment of an N-type SONOS transistor. While Figures 5A-5C show N-type devices, the memory architectures described herein are not so limited and may include p-type devices in other embodiments. Those skilled in the art will understand how the memory architecture can be modified to accommodate such devices.

[0056] As shown in Figure 5C, the gate of a SONOS transistor is separated from the channel by a stack of dielectric layers. The dielectric stack (often referred to as an "ONO stack") may include a thin tunneling layer (typically an oxide) above the channel, a charge trapping layer (typically a nitride) above the tunneling layer, and a blocking layer (typically an oxide) between the charge trapping layer and the gate. The charge trapping layer of a SONOS transistor is, for example, the storage node of the 1T and 2T memory cells shown in Figures 5A and 5B. The charge trapping layer can be "charged" to change the threshold voltage (Vt) of the SONOS transistor and change the value of the bit stored in the 1T or 2T memory cell (e.g., to "0" or "1"). The threshold voltage (Vt) is defined as the threshold gate-source voltage for current to flow through a SONOS transistor.

[0057] SONOS memory cells according to embodiments of the present invention can be programmed or erased by applying a voltage of appropriate polarity, magnitude, and duration between the gate terminal and the source / drain / substrate terminals of the SONOS transistor. This voltage is referred to as the gate-channel voltage. For example, a SONOS memory cell can be programmed by raising the gate-channel voltage of the SONOS transistor to a relatively high positive value (typically 7V to 12V). This causes electrons to tunnel from the channel to the ONO stack, where they are trapped in the charge-trapping nitride layer. The trapped charge creates an energy barrier between the drain and source of the transistor, which raises the threshold voltage (Vt) of the SONOS transistor. In one embodiment, a "1" bit can be stored in the memory cell by raising the threshold voltage of a programmed SONOS transistor to a substantially positive Vt. Electrons trapped in the nitride layer can be removed by applying a negative gate-channel voltage (typically -7V to -12V) to the SONOS transistor, thereby lowering the threshold voltage of the SONOS transistor and erasing the contents of the memory cell. In one embodiment, an erased SONOS transistor with a substantially negative Vt may be used to store a "0" bit in the memory cell. Once programmed or erased, the contents of a SONOS memory cell may be read by applying nominal voltages to a particular combination of word, bit, and source lines and sensing whether or not current flows through the corresponding bit line.

[0058] Exemplary bias voltage schemes for reading, erasing, and programming 1T and 2T SONOS memory cells are shown in FIG. 5D. Some of the bias voltages shown in FIG. 5D include two entries separated by a slash ( / ). When two entries are included, the first entry corresponds to a "select bias" and the second entry corresponds to a "deselect bias." In some embodiments, the non-volatile memory array 104 may be divided into multiple "blocks" and / or multiple "sectors."

[0059] When a block or sector architecture is used, the select and deselect biases shown in FIG. 5D may be applied to enabled blocks or sectors in one embodiment. In one embodiment, disabled blocks or sectors may also receive a deselect signal (typically 0V), except for the WL in a 2T cell block architecture (because the WL spans multiple blocks, the WL cannot be disabled if it is connected to an accessed memory cell in an enabled block). When the memory array is not divided into blocks or sectors, the select and deselect biases shown in FIG. 5D may be applied to the entire memory array. Some of the bias voltages shown in FIG. 5D are indicated with an asterisk (*). These bias voltages are exemplary and may be different in other embodiments of the present invention. For example, instead of shorting the SL to the BL during programming and erasure, the SL may be allowed to float.

[0060] As shown in FIG. 5D, 1T and 2T SONOS memory cells can be read by applying a bias (VLIM) to the bit line (BL) while grounding the source line (SL) and SONOS word line (WLS) of the selected memory cell. The word line (WL) of the selected 2T cell can also receive an appropriate voltage bias during a read operation. This allows current to flow (or not flow) on the bit line depending on the threshold voltage (V) of the SONOS device. As described in more detail below, the bit line current can be sensed or "read" by a sense amplifier. In one embodiment, a current value near 0 may indicate the presence of a "1" bit, while a substantially higher current value may indicate the presence of a "0" bit in the selected cell. In alternative embodiments of the present invention, the opposite may be true.

[0061] As shown in FIG. 5D, the bias (VLIM) applied to the selected BL during a read operation is limited to avoid disturbing other cells on the same BL. In one embodiment, a VLIM of approximately 1.2 V may be provided. As further shown in FIG. 5D, a power supply voltage (VPWR) is supplied to the WL of the selected 2T cell to activate the N-channel FNPASS device during a read operation. In one embodiment, a power supply voltage of approximately 2 V may be supplied to the WL of the selected 2T cell. In other embodiments, the read current may be increased by supplying a pump bias above the power supply level to the WL of the selected 2T cell. However, it should be noted that the read bias voltage shown in FIG. 5D is exemplary and should not be considered limiting of the present invention.

[0062] In some embodiments, a select / deselect bias (e.g., 1.2V / 0V) may be applied to the word lines (WL) connected to the BLs of 1T and 2T memory cells and the pass devices (FNPASS) in 2T cells. A select / deselect bias (e.g., 0V / -2V) may also be applied to the WLS lines of 1T cells to select / deselect the cells during read operations. A select / deselect bias may also be used on the WLS lines of 1T cells because they do not have pass devices. As shown in FIG. 5D, the read bias supplied to the P-well may be different for 1T and 2T cells. In one embodiment, 0V may be applied to the substrate of 2T cells. However, a slightly negative bias (e.g., -2V) may be applied to the substrate of 1T cells. The negative bias applied to the P-well results in a gate-to-channel voltage of 0V for deselected memory cells. However, it should be noted that the read bias voltages mentioned herein are exemplary and may differ in other embodiments of the present invention.

[0063] As shown in Figure 5D, 1T SONOS memory cells can be erased by applying a negative voltage (VNEG) to the SONOS word lines (WLS) and a positive voltage (VPOS) to the bit lines (BL), source lines (SL) and substrate (P-well) of the target or "selected" memory cells. The SONOS word lines (WLS) of unselected memory cells in an enabled block or sector are biased with VPOS to avoid erasing memory cells in unselected rows.

[0064] A similar bias scheme for erasing a 2T SONOS memory cell is shown in Figure 5D. However, the 2T scheme differs from the 1T scheme in that select / deselect biases are applied to the word lines (WLs) connected to the pass devices (FNPASS) in the 2T cell. In one embodiment, VPWR may be applied to the selected WLs, while 0V is applied to all deselected WLs. The select / deselect biases applied to the WLs during erase may be generated, for example, by the word line driver 103.

[0065] As shown in Figure 5D, 1T SONOS memory cells can be programmed by applying a positive voltage (VPOS) to the SONOS word lines (WLS) and a negative voltage (VNEG) to the bit lines (BL), source lines (SL) and substrate (P-well) of the selected memory cells. The SONOS word lines (WLS) of unselected memory cells in an enabled block or sector are biased with VNEG to avoid programming memory cells on unselected rows.

[0066] In some embodiments, the BL and SL of unselected memory cells may be biased (VBL) to prevent programming of memory cells that are to remain in the erased state. As described in more detail below, a VBL bias between 0V and VPWR may be used to inhibit programming of certain cells. In one embodiment, a VBL of approximately 1V may be provided.

[0067] A similar bias scheme for programming 2T SONOS memory cells is shown in Figure 5D. However, the 2T scheme differs from the 1T scheme in that a VWL bias (typically 0V to VNEG) is applied to the word lines (WL) of all 2T cells to reduce HV damage to the SONOS device during the program operation.

[0068] 5D, the SONOS memory cell may be programmed and erased by applying positive (VPOS) and negative (VNEG) voltages to the gate, drain, source, and substrate terminals of the SONOS transistor. In various embodiments, the SONOS memory cell may be programmed or erased in the manner described above before applying the characterization method of the embodiments.

[0069] The selection and biasing of memory cells during the characterization operation of the embodiment is similar to the selection and biasing of memory cells during the read operation. For example, VPWR can be applied to the WL of the selected 2T cell to activate the FNPASS device, while a ground voltage (0V) is applied to the WLS of the selected 2T cell. For 1T cells, a ground voltage (0V) is applied to the WLS of the selected 1T cell.

[0070] Referring now to FIG. 6, a block diagram of a processing system 600 according to one embodiment of the present invention is shown. Processing system 600 illustrates a general-purpose platform and typical components and functions that may be used to implement portions of the embodiments described herein, such as controller 106, test controller 116, BIST 118, and / or tester 120 described above with respect to FIG. 1A. For example, processing system 600 may be used to perform some or all of the processes used to analyze memory cell characterization results and determine reference currents to apply to a memory array under test. Processing system 600 may also be used to implement portions of the methods of the embodiments described herein with respect to FIGS. 2A and 2B.

[0071] Processing system 600 may include, for example, a central processing unit (CPU) 602 and memory 604 connected to a bus 608, and may be configured to perform the processes described above according to program instructions stored in memory 604 or other non-transitory computer-readable medium. Processing system 600 may further include, if desired, a display adapter 610 providing connection to a local display 612, and an input / output (I / O) adapter 614 providing an input / output interface for one or more input / output devices 616, such as a mouse, keyboard, flash drive, etc.

[0072] Processing system 600 may also include a network interface 618, which may be implemented using a wired link, such as a network cable, a USB interface, and / or a network adapter configured to couple to a wireless / cellular link for communicating with network 620. Network interface 618 may also include appropriate receivers and transmitters for wireless communication. Note that processing system 600 may include other components. For example, if processing system 600 is implemented externally, it may include hardware components such as a power supply, cables, a motherboard, removable storage media, a case, etc. These other components are not shown but are considered part of processing system 600. In some embodiments, processing system 600 may be implemented on a single monolithic semiconductor integrated circuit and / or the same monolithic semiconductor integrated circuit as the other disclosed system components.

[0073] Embodiments of the present invention are summarized here. Other embodiments can be seen from the entire specification and claims appended hereto.

[0074] Example 1. A method for characterizing a nonvolatile memory, the method comprising: applying a first voltage to a word line conductively coupled to a nonvolatile memory cell; and measuring a current flowing through the nonvolatile memory cell in response to the application of the first voltage, the measuring comprising: using a sense amplifier to compare the current flowing through the nonvolatile memory cell to a plurality of different first currents generated by an adjustable current source; applying the same first voltage on the word line; and determining the measured current based on the comparison.

[0075] Example 2. The method of example 1, further comprising determining whether the measured current is within a predetermined range.

[0076] Example 3. The method of example 1 or 2, further comprising replacing the non-volatile memory cell with a redundant cell when the measured current is not within a predetermined range.

[0077] Example 4. The method of any one of Examples 1 to 3, further comprising: setting a memory operating parameter based on the measured current, the memory operating parameter comprising a write duration or a write voltage.

[0078] Example 5. The method of any one of Examples 1 to 4, wherein the first voltage is a ground voltage.

[0079] Example 6. The method of any one of Examples 1 to 5, wherein measuring the current through the non-volatile memory cell comprises iteratively adjusting the current produced by the adjustable current source.

[0080] Example 7. The method of example 6, wherein iteratively adjusting the current generated by the adjustable current source comprises performing a binary search.

[0081] Example 8. The method of example 6 or 7, wherein the step of iteratively adjusting the current generated by the adjustable current source includes: increasing the current generated by the adjustable current source when the result of the comparison indicates a first comparison result; and decreasing the current generated by the adjustable current source when the result of the comparison indicates a second comparison result opposite to the first comparison result.

[0082] Example 9. The method of any one of Examples 6 to 8, wherein iteratively adjusting the adjustable current source comprises iteratively adjusting an input word provided to a current digital-to-analog converter (CDAC).

[0083] Example 10. The method of any one of Examples 1 to 9, wherein the non-volatile memory includes a plurality of non-volatile memory cells, and the sense amplifier includes a plurality of sense amplifier circuits configured to determine the memory states of the plurality of non-volatile memory cells.

[0084] Example 11. The method of example 10, further comprising providing outputs of the plurality of sense amplifier circuits to an external data bus.

[0085] Example 12. The method of example 10 or 11, wherein a plurality of nonvolatile memory cells are arranged in a row in the memory array, and the method further includes measuring current flowing through at least some of the nonvolatile memory cells in the row of the memory array.

[0086] Example 13. The method of example 12, wherein measuring current through at least some of the non-volatile memory cells of a row of the memory array includes selecting the non-volatile memory cells using a column decoder.

[0087] Example 14. A memory system including an integrated circuit including: a memory array including nonvolatile memory cells; a plurality of word line drivers coupled to the memory array; a plurality of sense amplifiers coupled to the memory array and coupled to an external data bus; an adjustable current source coupled to the plurality of sense amplifiers; a first control circuit configured to set the adjustable current source to a test current and apply a first address to the memory array to select a row of nonvolatile memory cells; and a second control circuit configured to read an output of the sense amplifiers and iteratively update the test current based on the output of the sense amplifiers to determine a current through at least one nonvolatile memory cell of the row of nonvolatile memory cells.

[0088] Example 15. The memory system of example 14, wherein the second control circuit is located on an integrated circuit.

[0089] Example 16. The memory system of example 15, wherein the second control circuit is external to the integrated circuit.

[0090] Example 17. The memory system of example 15 or 16, wherein the second control circuit is configured to read the output of the sense amplifier via an external data bus.

[0091] Example 18. The memory system of any one of Examples 14 to 17, wherein each word line driver of the plurality of word line drivers includes: a first transistor coupled between the word line and a positive supply node; and a second transistor coupled between the word line and a negative supply node, wherein the word line is only couplable to the positive supply node and the negative supply node via the first transistor and the second transistor, respectively.

[0092] Example 19. The memory system of Example 18, further including a first level shifter coupled to the first transistor and a second level shifter coupled to the second transistor, wherein the word line driver does not include any additional level shifting circuitry other than the first level shifter and the second level shifter.

[0093] Example 20. The memory system of any one of Examples 14 to 19, wherein the adjustable current source includes a current DAC.

[0094] Example 21. The memory system of any one of Examples 14 to 20, wherein the non-volatile memory cells comprise silicon-oxide-nitride-oxide-silicon (SONOS) memory cells.

[0095] Example 22. A method for characterizing a nonvolatile memory, the method comprising the steps of: operating the nonvolatile memory in a test mode, the method comprising the steps of: applying a row address to the nonvolatile memory to select a row of nonvolatile memory cells; grounding a word line coupled to the selected row of nonvolatile memory cells; measuring a current in at least one nonvolatile memory cell of the row of nonvolatile memory cells with the word line grounded; incrementing the row address; and performing a test read of the nonvolatile memory, the test read including the step of performing a test read using the incremented row address.

[0096] Example 23. The method of example 22, wherein the method further includes the steps of, after applying the row address, applying a column address to select a subset of the row of the selected non-volatile memory cells, and, after measuring the current but before incrementing the row address, incrementing the column address, and, after incrementing the column address but before incrementing the row address, repeating the steps of performing a test read using the incremented column address when the selected row of non-volatile memory cells has not yet been fully read.

[0097] Example 24. The method of example 22 or 23, further comprising determining non-functional non-volatile memory cells of the non-volatile memory based on the current measurements, or determining operational memory parameters based on the current measurements.

[0098] Example 25. The method of any one of Examples 22 to 24, wherein the step of measuring the current of the at least one nonvolatile memory cell includes the steps of applying a reference current to a sense amplifier coupled to the at least one nonvolatile memory cell to generate a sense amplifier output, modifying the reference current based on the sense amplifier output, and repeating the steps of applying the reference current and modifying the reference current to estimate the current of the at least one nonvolatile memory cell.

[0099] Example 26. The method of example 25, wherein the repeating of applying the reference current and modifying the reference current is performed according to a linear search or a binary search.

[0100] Example 27. The method of any one of Examples 22 to 26, wherein at least one nonvolatile memory cell of the row of nonvolatile memory cells includes a nonvolatile memory cell having a maximum threshold value or a minimum threshold value of the nonvolatile memory cells of the row of nonvolatile memory cells.

[0101] While the present invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art upon reference to the description. It is therefore intended that the appended claims cover any such modifications or embodiments.

Claims

1. 1. A method for characterizing a non-volatile memory, the method comprising: applying a first voltage to a word line conductively coupled to a non-volatile memory cell; measuring a current flowing through the non-volatile memory cell in response to application of the first voltage; wherein the measuring step comprises: using a sense amplifier to compare the current flowing through the non-volatile memory cell with a plurality of different first currents generated by an adjustable current source and applying the same first voltage on the word line; determining the measured current based on the comparison; and A method comprising:

2. The method further includes determining whether the measured current is within a predetermined range. The method of claim 1.

3. The method further includes replacing the non-volatile memory cell with a redundant cell when the measured current is not within the predetermined range. The method of claim 2.

4. The method further includes setting a memory operating parameter based on the measured current, the memory operating parameter including a write duration or a write voltage. The method of claim 1.

5. the first voltage is a ground voltage; The method of claim 1.

6. measuring the current through the non-volatile memory cell includes iteratively adjusting the current generated by the adjustable current source; The method of claim 1.

7. the step of iteratively adjusting the current generated by the adjustable current source includes performing a binary search. The method of claim 6.

8. The step of iteratively adjusting the current generated by the adjustable current source comprises: increasing the current generated by the adjustable current source when the comparison indicates a first comparison result; decreasing the current generated by the adjustable current source when the result of the comparison indicates a second comparison result opposite to the first comparison result; Including, The method of claim 6.

9. wherein the step of iteratively adjusting the adjustable current source comprises iteratively adjusting an input word provided to a current digital-to-analog converter (CDAC). The method of claim 6.

10. the nonvolatile memory includes a plurality of nonvolatile memory cells; the sense amplifier includes a plurality of sense amplifier circuits configured to determine memory states of the plurality of non-volatile memory cells; The method of claim 1.

11. the method further comprising providing outputs of the plurality of sense amplifier circuits to an external data bus; The method of claim 10.

12. the plurality of nonvolatile memory cells are arranged in a row in a memory array; The method further includes measuring the current flowing through at least a portion of the non-volatile memory cells of the row of the memory array. The method of claim 10.

13. measuring the current through at least some of the non-volatile memory cells of the row of the memory array includes selecting the non-volatile memory cells using a column decoder; The method of claim 12.

14. 1. A memory system comprising an integrated circuit, The integrated circuit comprises: a memory array comprising non-volatile memory cells; a plurality of word line drivers coupled to the memory array; a plurality of sense amplifiers coupled to the memory array and coupled to an external data bus; an adjustable current source coupled to the plurality of sense amplifiers; a first control circuit; a second control circuit; Equipped with The first control circuit includes: setting the adjustable current source to a test current; applying a first address to the memory array to select a row of the non-volatile memory cells; The second control circuit includes: reading the output of the sense amplifier; and iteratively updating the test current based on the output of the sense amplifier to determine a current through at least one non-volatile memory cell of the row of non-volatile memory cells. Memory system.

15. the second control circuit is disposed on the integrated circuit; 15. The memory system of claim 14.

16. the second control circuit is external to the integrated circuit; 16. The memory system of claim 15.

17. the second control circuit is configured to read the output of the sense amplifier via the external data bus; 17. The memory system of claim 16.

18. Each word line driver of the plurality of word line drivers comprises: a first transistor coupled between the word line and the positive supply node; a second transistor coupled between the word line and a negative supply node; wherein the word line is only couplable to the positive supply node and the negative supply node via the first transistor and the second transistor, respectively.

15. The memory system of claim 14.

19. The memory system includes: a first level shifter coupled to the first transistor; a second level shifter coupled to the second transistor; wherein the word line driver does not include any additional level shifting circuitry other than the first level shifter and the second level shifter.

20. The memory system of claim 18.

20. the adjustable current source comprises a current DAC; 15. The memory system of claim 14.

21. the non-volatile memory cells comprise silicon-oxide-nitride-oxide-silicon (SONOS) memory cells; 15. The memory system of claim 14.

22. 1. A method for characterizing a non-volatile memory, the method comprising: operating the nonvolatile memory in a test mode, the step of operating the nonvolatile memory in the test mode comprising: a step of performing a test read of the nonvolatile memory, the step of performing a test read of the nonvolatile memory including: applying a row address to the non-volatile memory to select a row of said non-volatile memory cells; grounding a word line coupled to a selected row of said non-volatile memory cells; measuring the current of at least one non-volatile memory cell in said row of non-volatile memory cells with said word line grounded; incrementing the row address; Including, The step of operating the nonvolatile memory in a test mode includes: repeating the step of performing the test read using the incremented row address. method.

23. The method comprises: after applying the row address, applying a column address to select a subset of the row of the selected non-volatile memory cells; incrementing the column address after measuring the current and before incrementing the row address; repeating the step of performing the test read using the incremented column address after incrementing the column address and before incrementing the row address when the selected row of non-volatile memory cells has not yet been completely read; further comprising:

23. The method of claim 22.

24. The method comprises: determining non-functional non-volatile memory cells of the non-volatile memory based on the current measurements; or determining an operational memory parameter based on the current measurement. further comprising:

23. The method of claim 22.

25. The step of measuring the current of the at least one non-volatile memory cell comprises: applying a reference current to a sense amplifier coupled to the at least one non-volatile memory cell to generate a sense amplifier output; modifying the reference current based on the sense amplifier output; repeating the steps of applying the reference current and modifying the reference current to estimate the current in the at least one non-volatile memory cell; Including, 23. The method of claim 22.

26. the steps of repeating the steps of applying the reference current and modifying the reference current are performed according to a linear search or a binary search.

26. The method of claim 25.

27. the at least one nonvolatile memory cell of the row of nonvolatile memory cells includes a nonvolatile memory cell having a maximum threshold value or a minimum threshold value of the nonvolatile memory cells of the row of nonvolatile memory cells; 23. The method of claim 22.

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