Device, system and method for injecting spurious errors into machine check architectures

Abstract

An exemplary system includes and / or represents an agent and a machine check architecture. In one example, the machine check architecture includes and / or represents at least one circuit configured to report errors via at least one reporting register. In this example, the machine check architecture includes and / or represents at least one error injection register configured to cause the circuit to inject at least one pseudo-error report into the reporting register in response to a write operation performed by the agent on at least one bit of the error injection register. Various other devices, systems, and methods are also disclosed.

Description

[Background technology]

[0001] Machine check architectures are often used to report errors to operating systems running on the processors. For example, a system on a chip (SoC) may include and / or represent various processors along with a machine check architecture that detects and / or reports errors to one or more processors. In this example, a user and / or administrator of the SoC may desire and / or need to test the effect of one or more errors on firmware, software, and / or flows running on the processors. Unfortunately, such testing may become impractical, unfeasible, and / or unscalable as the number of error detectors included in the machine check architecture expands and / or increases. Accordingly, the present disclosure identifies and addresses the need for additional and improved devices, systems, and methods for injecting pseudo errors into a machine check architecture.

[0002] The accompanying drawings illustrate several exemplary embodiments and are a part of this specification, and together with the following description, these drawings demonstrate and explain various principles of the present disclosure. [Brief explanation of the drawings]

[0003] [Figure 1] FIG. 1 is a block diagram of a portion of an example computing device capable of injecting spurious errors into a machine check architecture in accordance with one or more embodiments of the present disclosure. [Figure 2] FIG. 1 is a block diagram of an example machine check architecture that supports and / or facilitates the injection of spurious errors into the machine check architecture, in accordance with one or more embodiments of the present disclosure. [Figure 3] FIG. 1 is a block diagram of an example computing device capable of injecting spurious errors into a machine check architecture in accordance with one or more embodiments of the present disclosure. [Figure 4] FIG. 1 is a block diagram of an example computing device capable of injecting spurious errors into a machine check architecture in accordance with one or more embodiments of the present disclosure. [Figure 5] FIG. 1 is a block diagram of an example computing device capable of injecting spurious errors into a machine check architecture in accordance with one or more embodiments of the present disclosure. [Figure 6] FIG. 1 is a block diagram of an example computing device capable of injecting spurious errors into a machine check architecture in accordance with one or more embodiments of the present disclosure. [Figure 7] FIG. 1 is a block diagram of an example embodiment involving a computing system that facilitates injecting spurious errors into a machine check architecture in accordance with one or more variations of the present disclosure. [Figure 8] 1 is a flowchart of an exemplary method for injecting spurious errors into a machine check architecture, in accordance with one or more embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0004] Throughout the drawings, like reference numerals and descriptions indicate similar, but not necessarily identical, elements. While the exemplary embodiments described herein are susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and are described in detail herein. However, the exemplary embodiments described herein are not intended to be limited to the particular forms disclosed. Rather, the present disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims.

[0005] This disclosure describes various devices, systems, and methods for injecting pseudo errors into a machine check architecture. In some examples, an SoC implements a machine check architecture with error detectors that have been modified to inject pseudo errors for testing and / or validation purposes. Unfortunately, some configurations of the machine check architecture require custom logic for all of those modified error detectors. In some embodiments, such custom logic is not scalable because an SoC may include and / or implement thousands of error detectors that utilize the machine check architecture for error reporting.

[0006] To address this issue, the SoC may provide and / or implement a register accessible to privileged out-of-band agents. When a portion of this register is written, the SoC hardware (e.g., hardware blocks and / or circuits within the machine check architecture) intentionally generates a pseudo-error for injection into the logging pipeline of the machine check architecture. The SoC hardware may select and / or customize which errors to generate and / or inject into the logging pipeline of the machine check architecture to suit a particular purpose and / or to test certain functionality. By using the SoC hardware to select and / or customize for generating and / or injecting such errors, a user and / or administrator of the SoC may develop, generate, and / or establish a robust platform for testing and / or validating software and / or firmware against errors. Alternatively, the SoC hardware may write the pseudo-error directly to a register within the machine check architecture without necessarily pushing the error into the logging pipeline.

[0007] In some examples, the system includes and / or represents an agent and a machine check architecture. In one example, the machine check architecture includes and / or represents at least one circuit configured to report errors via at least one reporting register. In this example, the machine check architecture includes and / or represents at least one error injection register configured to cause the circuit to inject at least one pseudo-error report into the reporting register in response to a write operation performed by the agent to at least one bit of the error injection register.

[0008] In some examples, the circuit includes and / or represents a plurality of circuits, and the error injection register includes and / or represents a plurality of error rejection registers. In one example, the machine check architecture includes and / or represents a pipeline configured to convey error reports from the circuit to a reporting register. In this example, the error injection register is configured to cause the circuit to inject a pseudo-error report into the pipeline for transmission to the reporting register.

[0009] In some examples, the circuitry includes and / or represents one or more wires configured to communicate another pseudo-error report from an external source to the reporting register via the pipeline. In one example, the reporting register includes and / or represents a first reporting register and a second reporting register. In this example, the first reporting register is configured to receive a first copy of the pseudo-error report via a first lane of the pipeline and store the first copy of the pseudo-error report for access by the in-band processor. Additionally or alternatively, the second reporting register is configured to receive a second copy of the pseudo-error report via a second lane of the pipeline and / or store the second copy of the pseudo-error report for access by the out-of-band controller.

[0010] In some examples, the agent includes and / or represents software or firmware executing on a processor having access to the error injection register. In one example, the system includes and / or represents an integrated circuit incorporating a processor and machine check architecture. Additionally or alternatively, the agent includes and / or represents an out-of-band controller having access to the error injection register.

[0011] In some examples, the system includes and / or represents a first integrated circuit incorporating an out-of-band controller and a second integrated circuit incorporating a machine check architecture. In one example, the out-of-band controller includes and / or represents a baseboard management controller external to the second integrated circuit.

[0012] In some examples, the circuitry includes and / or represents a table configured to store a plurality of error entries and to map bits of the error injection register to particular error entries of the plurality of error entries, and in such examples, the circuitry is configured to generate a report of the injected pseudo-error based at least in part on the mapping of bits to particular error entries.

[0013] In some examples, the error injection register is further configured to cause the circuit to inject another pseudo-error report into the reporting register in response to another write operation performed by the agent on at least one other bit of the error injection register. In one example, the system includes and / or represents an out-of-band controller configured to perform a particular action in response to a particular error identified in the pseudo-error report injected into the reporting register. For example, the particular action includes and / or represents triggering an interrupt that notifies at least one other circuit of the particular error.

[0014] In some examples, the other circuitry includes and / or represents a processor located on an integrated circuit with a machine-check architecture. In such examples, the other circuitry includes and / or represents a baseboard management controller that is external to the integrated circuit with the machine-check architecture.

[0015] In some examples, the machine check architecture includes and / or represents at least one circuit configured to report errors to a reporting register and a pipeline configured to convey the error report from the circuit to the reporting register. In such examples, the machine check architecture includes and / or represents at least one error injection register configured to cause the circuit to inject at least one pseudo-error report via the pipeline into the reporting register in response to a write operation performed by an external source on at least one bit of the error injection register.

[0016] In some examples, the method includes and / or represents configuring at least one error injection register of a circuit within the machine check architecture. In such examples, the method includes and / or represents detecting a write operation performed on at least one bit of the error injection register. In one example, the method further includes and / or represents injecting at least one pseudo-error report into at least one reporting register within the machine check architecture in response to the write operation.

[0017] A detailed description of exemplary devices, systems, and / or corresponding embodiments for injecting pseudo-errors into a machine check architecture is provided below with reference to Figures 1-7. A detailed description of an exemplary method for injecting pseudo-errors into a machine check architecture is provided in connection with Figure 8.

[0018] 1 illustrates an example computing device 100 that facilitates and / or supports injecting pseudo errors into a machine check architecture. As shown in FIG. 1, example computing device 100 includes and / or represents machine check architecture 102 and agent 104. In some examples, machine check architecture 102 and agent 104 are electrically and / or communicatively coupled to machine check architecture 102. In one example, machine check architecture 102 includes and / or represents multiple circuits 108(1)-(N) and at least one reporting register 114. In this example, circuits 108(1)-(N) include and / or represent error detectors 110(1)-(N) and error injection registers 116(1)-(N), respectively. In one embodiment, error detectors 110(1)-(N) detect errors occurring in circuits 108(1)-(N), respectively, and / or report the errors to agent 104, one or more in-band processors, and / or one or more out-of-band controllers via reporting registers 114.

[0019] In some examples, machine check architecture 102 may include and / or represent circuits, devices, and / or hardware mechanisms that detect errors and / or report errors to other circuits, devices, and / or hardware mechanisms. For example, an SoC may include and / or implement machine check architecture 102 and various processors and / or central processing unit (CPU) cores. In this example, machine check architecture 102 is configured and / or programmed to monitor for hardware errors occurring in circuits 108(1)-(N), processors or CPU cores implemented on the SoC, and / or other functions or components of the SoC.

[0020] In some examples, circuits 108(1)-(N) include and / or represent hardware blocks and / or banks of machine check architecture 102. In one example, the hardware blocks and / or banks include and / or represent memory controllers and / or CPU cores. Additionally or alternatively, the hardware blocks and / or banks include and / or represent control registers and / or model-specific registers used to check, detect, and / or log various hardware and / or machine errors. Examples of such errors include, but are not limited to, memory or cache errors, buffer errors, translation errors, parity errors, system bus errors, error-correcting code (ECC) failures, error detection and correction (EDAC) failures, communication errors, input / output (I / O) errors, one or more portions thereof, combinations or variations of one or more thereof, and / or any other detectable error. Circuits 108(1)-(N) may be configured and / or programmed to generate and / or issue pseudo-error reports indicating any of these errors in response to one or more bits being written to and / or modified in error injection registers 116(1)-(N), respectively.

[0021] In some examples, agent 104 includes and / or represents a hardware-implemented device and / or circuitry capable of executing firmware, an operating system, and / or a user application. Additionally or alternatively, agent 104 includes and / or represents software and / or firmware executing on a hardware-implemented device and / or circuitry. In one example, agent 104 may include and / or represent software and / or firmware executing on an in-band processor implemented on an SoC with machine check architecture 102. In another example, agent 104 may include and / or represent an out-of-band controller that interfaces with and / or communicates with an SoC with machine check architecture 102. Additionally or alternatively, agent 104 may include and / or represent software and / or firmware executing on such an out-of-band controller.

[0022] In some examples, each of error injection registers 116(1)-(N) causes and / or instructs circuitry 108(1)-(N) to inject and / or insert one or more pseudo-error reports into reporting register 114. In one example, the injection and / or insertion of the pseudo-error reports occurs in response to a write operation performed by agent 104 on one or more of error injection registers 116(1)-(N). For example, agent 104 writes and / or modifies one or more bits in error injection register 116(1). In response to this writing and / or modification of such bits, error injection register 116(1) can cause and / or instruct error detector 110(1) and / or circuitry 108(1) to inject and / or insert the pseudo-error reports into reporting register 114. The pseudo-error report may correspond to, represent, and / or reflect a spoof error associated with a bit affected by a write operation.

[0023] In some examples, agent 104 and / or another out-of-band component can obtain, receive, and / or retrieve the pseudo-error report from reporting register 114. In such examples, agent 104 and / or another out-of-band component can process and / or consume the pseudo-error report to test whether all relevant functions and / or components of machine check architecture 102 are operating and / or functioning as expected. In one example, agent 104 and / or another out-of-band component can notify a user of computing device 100 of any functions and / or components of machine check architecture 102 that are identified, at least in part, as not operating and / or functioning as expected based on the testing. Additionally or alternatively, agent 104 and / or another out-of-band component can implement one or more corrective actions to address and / or fix any functions and / or components of machine check architecture 102 that are identified, at least in part, as not operating and / or functioning as expected based on the testing.

[0024] 2 illustrates an exemplary embodiment of machine check architecture 102 that facilitates and / or supports the injection of spurious errors. In some examples, machine check architecture 102 may include and / or represent components and / or functions that perform and / or provide similar and / or identical functions as those described above in connection with FIG. 1. As shown in FIG. 2, exemplary machine check architecture 102 includes and / or represents a pipeline 212 that conveys, transports, and / or forwards error reports 220 from circuits 108(1)-(N) to a reporting register 216.

[0025] In some examples, each of the error injection registers 116(1)-(N) can cause and / or direct circuits 108(1)-(N) to inject and / or inject pseudo-error reports into pipeline 212 for transmission to one or more reporting registers 216. In one example, each of circuits 108(1)-(N) includes and / or represents a table 210(1)-(N). In this example, each of tables 210(1)-(N) can store multiple error entries and / or map one or more bits of error injection registers 116(1)-(N) to those error entries.

[0026] For example, when agent 104 writes to at least one bit in error injection register 116(1), circuit 108(1) may refer to table 210(1) to identify which error to generate and / or which error to report to reporting register 216. In this example, the mapping may indicate and / or specify an error corresponding to and / or associated with that bit in error injection register 116(1). Continuing with this example, error detector 110(1) and / or circuit 108(1) may generate pseudo-error report 226 based at least in part on the mapping of that bit to a particular error entry in table 210(1). Additionally or alternatively, error detector 110(1) and / or circuit 108(1) may then inject and / or insert pseudo-error report 226 into pipeline 212 for transmission to reporting register 216.

[0027] Similarly, if agent 104 writes to another bit in error injection register 116(1), circuit 108(1) can refer to table 210(1) to identify which other errors to generate and / or report to reporting register 216. In this example, the mapping can indicate and / or specify another error corresponding to and / or associated with the other bit in error injection register 116(1). Continuing with this example, error detector 110(1) and / or circuit 108(1) can generate another pseudo-error report based at least in part on the mapping of the other bit to another particular error entry in table 210(1). Additionally or alternatively, error detector 110(1) and / or circuit 108(1) can then inject and / or insert another pseudo-error report specifying the other error into pipeline 212 for transmission to reporting register 216.

[0028] In some examples, error injection registers 116(1)-(N) and / or tables 210(1)-(N) may be configurable and / or programmable to facilitate testing and / or verifying certain features of machine check architecture 102. For example, agent 104 and / or another function of computing device 100 may configure and / or program error injection register 116(1) and / or table 210(1) to implement a mapping between bits in error injection register 116(1) and particular errors. In this example, agent 104 and / or another function of computing device 100 may reconfigure and / or reprogram error injection register 116(1) and / or table 210(1) dynamically and / or as needed to test and / or verify certain features of the machine check architecture.

[0029] 3 illustrates another exemplary embodiment of machine check architecture 102 that facilitates and / or supports the injection of spurious errors. In some examples, machine check architecture 102 may include and / or represent components and / or functions that perform and / or provide similar and / or identical functionality to those described above in connection with either of FIGS. 1 and 2. As shown in FIG. 3, exemplary machine check architecture 102 includes and / or represents one or more in-band reporting registers 316 and / or out-of-band reporting registers 318.

[0030] In some examples, pipeline 212 of machine check architecture 102 includes and / or represents unified lane 312, fork 314, single lane 322, and / or single lane 324. In this example, unified lane 312 conveys and / or forwards error report 220 and / or quasi-error report 326 to both in-band reporting register 316 and out-of-band reporting register 318. In one example, single lane 322 can electrically and / or communicatively couple fork 314 to in-band reporting register 316. Additionally or alternatively, single lane 324 can electrically and / or communicatively couple fork 314 to out-of-band reporting register 318.

[0031] In some examples, the consolidated lane 312 is electrically and / or communicatively coupled to the fork 314. In such examples, the consolidated lane 312 supplies and / or distributes the error reports 220 and / or the pseudo-error reports 326 to the fork 314, and the fork 314 replicates and / or copies the error reports 220 and / or the pseudo-error reports 326. For example, the fork 314 bifurcates and / or splits the consolidated lane 312 into a single lane 322 and a single lane 324. In this example, the single lane 322 carries and / or forwards one copy of the error reports 220 and / or the pseudo-error reports 326 toward the in-band reporting register 316, and the single lane 324 carries and / or forwards another copy of the error reports 220 and / or the pseudo-error reports 326 toward the out-of-band reporting register 318.

[0032] In some examples, error detectors 110(1)-(N) monitor and / or detect errors within and / or via circuits 108(1)-(N), respectively. In such examples, one or more of error detectors 110(1)-(N) generate and / or issue error reports 220 in response to detecting such errors. In one example, error detectors 110(1)-(N) can send and / or transmit error reports 220 and / or pseudo-error reports 326 via pipeline 112 to both in-band reporting register 316 and out-of-band reporting register 318. For example, error reports 220 and / or pseudo-error reports 326 can traverse and / or propagate from one or more circuits 108(1)-(N) to fork 314 via integration lane 312. In this example, the fork 314 may duplicate and / or copy the error report 220 and / or the pseudo-error report 326 for transmission to both the in-band reporting register 316 and the out-of-band reporting register 318. Thus, one copy of the error report 220 and / or the pseudo-error report 326 may traverse and / or propagate from the fork 314 to the in-band reporting register 316 via a single lane 322, and another copy of the error report 220 and / or the pseudo-error report 326 may traverse and / or propagate from the fork 314 to the out-of-band reporting register 318 via a single lane 324.

[0033] In some examples, the in-band reporting register 316 receives a copy of either the error report 220 and / or the pseudo-error report 326 and stores the copy of the error report 220 and / or the pseudo-error report 326 for access by the agent 104 and / or the in-band processor. Additionally or alternatively, the out-of-band reporting register 318 receives another copy of the error report 220 and / or the pseudo-error report 326 and stores the copy of the error report 220 and / or the pseudo-error report 326 for access by the agent 104 and / or the out-of-band controller.

[0034] 4 illustrates an exemplary embodiment of a computing device 100 that facilitates and / or supports injection of spurious errors into a machine check architecture. In some examples, computing device 100 may include and / or represent components and / or functionality that perform and / or provide similar and / or identical functions as those described above in connection with any of FIGS. 1-3. In one example, computing device 100 includes and / or represents machine check architecture 102, in-band processor 404, out-of-band controller 406, and / or external source 414. In this example, machine check architecture 102 may be electrically and / or communicatively coupled to in-band processor 404, out-of-band controller 406, and / or external source 414.

[0035] In some examples, agent 104 may include and / or represent an in-band processor 404 that implements and / or executes an operating system 408. In one example, operating system 408 may cause and / or instruct in-band processor 404 to obtain, receive, and / or retrieve copies of pseudo-error reports 326 from in-band reporting registers 316. Additionally or alternatively, agent 104 may include and / or represent software and / or firmware executing on in-band processor 404. In this example, in-band processor 404 has and / or maintains access to one or more in-band reporting registers 316. In an embodiment, in-band processor 404 and / or operating system 408 processes and / or consumes copies of pseudo-error reports 326 to test whether all relevant functions and / or components of machine check architecture 102 are operating and / or functioning as expected.

[0036] Additionally or alternatively, agent 104 may include and / or represent an out-of-band controller 406 that implements and / or executes firmware 410. In one example, firmware 410 may cause and / or instruct out-of-band controller 406 to obtain, receive, and / or retrieve copies of pseudo-error reports 326 from out-of-band reporting registers 318. In this example, out-of-band controller 406 has and / or maintains access to one or more out-of-band reporting registers 318. In some embodiments, out-of-band controller 406 and / or firmware 410 processes and / or consumes copies of pseudo-error reports 326 to test whether all relevant functions and / or components of machine check architecture 102 are operating and / or functioning as expected.

[0037] In some examples, the in-band processor 404 may include and / or represent a hardware-implemented device and / or circuitry capable of executing firmware, an operating system, and / or user applications. For example, the in-band processor 404 may include and / or represent a graphics processing unit (GPU) and / or a CPU. In this example, the in-band processor 404 may include and / or represent any of several processors (e.g., several x86 processors) implemented and / or located on an SoC. Further examples of the in-band processor 404 include, but are not limited to, a parallel acceleration processor, a tensor core, a microprocessor, a microcontroller, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an integrated circuit, a chiplet, one or more portions thereof, one or more variations or combinations thereof, and / or any other suitable in-band processor.

[0038] The in-band processor 404 may implement and / or be configured with any of a variety of different architectures and / or microarchitectures. For example, the in-band processor 404 may be implemented and / or configured as a reduced instruction set computer (RISC) architecture. In another example, the in-band processor 404 may be implemented and / or configured as a complex instruction set computer (CISC) architecture. Additional examples of such architectures and / or microarchitectures include, but are not limited to, 16-bit computer architecture, 32-bit computer architecture, 64-bit computer architecture, x86 computer architecture, advanced RISC machine (ARM) architecture, microprocessor without interlocked pipelined stage (MIPS) architecture, scalable processor architecture (SPARC), load-store architecture, portions of one or more thereof, combinations or variations of one or more thereof, and / or any other suitable architecture or microarchitecture.

[0039] In some examples, the out-of-band controller 406 may include and / or represent hardware-implemented devices and / or circuits that can control and / or modify certain hardware functions and / or components on an integrated circuit (e.g., an SoC implementing various CPU cores). In one example, the out-of-band controller 406 may include and / or represent devices and / or circuits that are on-board (e.g., on-chip) and / or internal to the SoC implementing the in-band processor 404. For example, the out-of-band controller 406 may include and / or represent a system management unit implemented on-board and / or internal to the SoC. In another example, the out-of-band controller 406 may include and / or represent a baseboard management controller implemented outside (e.g., off-chip) and / or external to the SoC implementing the in-band processor 404. Further examples of the out-of-band controller 406 include, but are not limited to, a microprocessor, a microcontroller, an FPGA, an ASIC, an integrated circuit, a chiplet, one or more portions thereof, one or more variations or combinations thereof, and / or any other suitable out-of-band controller.

[0040] In some examples, the term “out-of-band” may refer to any components, circuits, and / or processes dedicated to and / or supporting the control plane (e.g., control data and / or firmware), management plane, and / or data related to the underlying device (e.g., SoC). In contrast, the term “in-band” may refer to any components, circuits, and / or processes dedicated to and / or supporting the user plane (e.g., user data and / or user applications) executing on a processor (e.g., CPU cores of an SoC) and / or implemented by the processor. In one example, an in-band workload of an SoC may include and / or represent computing tasks performed for and / or in connection with user applications executing on the processor, and an out-of-band workload of an SoC may include and / or represent computing tasks performed for any other purpose other than being utilized and / or consumed by such user applications.

[0041] In some examples, computing device 100 and / or machine check architecture 102 are configured and / or equipped with one or more wires that can communicate pseudo-error reports from external source 414 to one or more of in-band reporting register 316 and / or out-of-band reporting register 318 via pipeline 212. Examples of external source 414 include, but are not limited to, agent 104, in-band processor 404, out-of-band controller 406, one or more portions thereof, one or more variations or combinations thereof, and / or any other suitable external source 414. Thus, although not necessarily depicted as such in FIG. 4 , external source 414 may be the same as any of the devices that obtain, receive, and / or retrieve pseudo-error reports from the reporting registers of machine check architecture 102.

[0042] FIG. 5 illustrates an exemplary embodiment of a computing device 100 that facilitates and / or supports injection of pseudo errors into a machine check architecture. In some examples, computing device 100 may include and / or represent components and / or functionality that perform and / or provide similar and / or identical functions as those described above in connection with any of FIGS. 1-4. In one example, computing device 100 includes and / or represents integrated circuit 502 and / or integrated circuit 504 communicatively coupled to each other. In this example, integrated circuit 502 includes and / or represents machine check architecture 102 and / or in-band processor 404, and integrated circuit 504 includes and / or represents out-of-band controller 406. Thus, integrated circuit 504 is off-chip from and / or external to integrated circuit 502. However, integrated circuits 502 and 504 may be located and / or applied to the same circuit board.

[0043] In some examples, the integrated circuit 502 includes and / or represents an SoC with multiple CPU cores and machine check architecture 102. In one example, the in-band processor 404 is on-chip and / or internal to the SoC, and the out-of-band controller 406 is off-chip and / or external to the SoC. In this example, the in-band processor 404 has access to copies of the pseudo-error reports 326 stored in the in-band reporting registers 316, but has limited access to copies of the pseudo-error reports 326 stored in the out-of-band reporting registers 318. For example, the in-band processor 404 may implement and / or execute an operating system 408 that acquires, receives, and / or retrieves copies of the pseudo-error reports 326 from the in-band reporting registers 316. Additionally or alternatively, the out-of-band controller 406 can access copies of the pseudo-error reports 326 stored in the out-of-band reporting registers 318, but has limited access to copies of the pseudo-error reports 326 stored in the in-band reporting registers 316.

[0044] In some examples, the in-band processor 404 and the out-of-band controller 406 can make error logging decisions independently of one another. For example, the in-band processor 404 can clear certain flags (e.g., status flags) in the in-band reporting registers 316 that remain set in the out-of-band reporting registers 318. Alternatively, the out-of-band controller 406 can clear certain flags (e.g., status flags) in the out-of-band reporting registers 318 that remain set in the in-band reporting registers 316. In either case, such flag discrepancies across the in-band reporting registers 316 and the out-of-band reporting registers 318 can cause the in-band reporting registers 316 and the out-of-band reporting registers 318 to log and / or ignore different errors from the same error report. Thus, the in-band processor 404 and the out-of-band controller 406 can have independent control and / or programmability over their respective registers in the machine check architecture 102.

[0045] FIG. 6 illustrates another exemplary embodiment of a computing device 100 that facilitates and / or supports out-of-band delivery of error reports. In some examples, computing device 100 may include and / or represent components and / or functionality that perform and / or provide similar and / or identical functions as those described above in connection with any of FIGS. 1-5. As shown in FIG. 6, exemplary computing device 100 includes and / or represents integrated circuit 502 and / or integrated circuit 504 communicatively coupled to each other. In one example, integrated circuit 502 includes and / or represents machine check architecture 102, in-band processor 404, and / or out-of-band interface 604. In this example, integrated circuit 504 includes and / or represents out-of-band controller 406 communicatively coupled to out-of-band interface 604 that facilitates access to a copy of pseudo-error report 326 stored in out-of-band reporting register 318 of out-of-band controller 406.

[0046] In some examples, the out-of-band interface 604 may include and / or represent a system management unit that obtains, receives, and / or retrieves copies of the pseudo-error reports 326 from the out-of-band reporting registers 318. Additionally or alternatively, the out-of-band controller 406 may include and / or represent a baseboard management controller that interfaces with and / or communicates with the system management unit. In one example, the baseboard management controller obtains, receives, and / or retrieves copies of the pseudo-error reports 326 from the system management unit.

[0047] In some examples, the out-of-band controller 406 and / or the out-of-band interface 604 may command and / or instruct the machine check architecture 102 to perform one or more particular actions in response to a particular error identified and / or included in the pseudo-error report 326. For example, the out-of-band controller 406 and / or the out-of-band interface 604 may be programmed and / or configured to set the out-of-band reporting register 318 to initiate and / or trigger a particular action in response to a particular error. In one example, the particular action may include and / or represent triggering an interrupt that notifies the out-of-band controller 406 of the particular error. For example, the out-of-band interface 604 may be programmed and / or configured to generate an interrupt that notifies the out-of-band controller 406 of the particular error.

[0048] Similarly, the in-band processor 404 and / or operating system 408 can command and / or instruct the machine check architecture 102 to perform one or more specific actions in response to a particular error identified and / or included in the pseudo-error report 326. For example, the in-band processor 404 and / or operating system 408 can program and / or configure the in-band reporting registers 316 to initiate and / or trigger a particular action in response to a particular error. In one example, the particular action can include and / or represent triggering an interrupt that notifies the in-band processor 404 and / or operating system 408 of the particular error. For example, the machine check architecture 102 and / or the in-band reporting registers 316 can be programmed and / or configured to generate an interrupt that notifies the in-band processor 404 and / or operating system 408 of the particular error.

[0049] Figure 7 illustrates an example embodiment 700 involving a computing system 702. In some examples, the computing system 702 may include and / or represent components and / or functionality that perform and / or provide similar and / or identical functionality as described above in connection with any of Figures 1-6. As shown in the example embodiment 700 of Figure 7, the computing system 702 includes and / or represents an SoC 706 with a machine check architecture 102 and / or a system management unit 708.

[0050] In some examples, computing system 702 includes and / or represents a baseboard management controller 710 electrically and / or communicatively coupled to system management unit 708. In one example, system management unit 708 obtains, receives, and / or retrieves a copy of the error report from an out-of-band register within machine check architecture 102. In this example, baseboard management controller 710 then obtains, receives, and / or retrieves a copy of the error report from system management unit 708 to facilitate processing and / or decision making.

[0051] 1-7 may include and / or represent one or more additional circuits, components, and / or functions not necessarily shown and / or labeled in FIGS. 1-7. For example, computing device 100 may include and / or represent additional analog and / or digital circuits, on-board logic, transistors, resistors, capacitors, diodes, inductors, switches, registers, flip-flops, connections, traces, buses, semiconductor (e.g., silicon) devices and / or structures, processing devices, storage devices, circuit boards, packages, substrates, housings, combinations or variations of one or more of these, and / or any other suitable components that facilitate and / or support the injection of spurious errors into a machine check architecture. In some embodiments, one or more of these additional circuits, components, devices, and / or functions may be inserted between and / or applied to any of the existing circuits, components, and / or devices shown in FIGS. 1-7 consistent with the purposes and / or goals provided herein. Thus, the electrical and / or communication couplings described with reference to Figures 1-7 may be direct connections without intermediate components, devices and / or nodes, or indirect connections involving one or more intermediate components, devices and / or nodes.

[0052] In some examples, the phrase "couple" and / or the term "coupling" as used herein may refer to a direct connection and / or an indirect connection. For example, a direct coupling between two components may constitute and / or represent a coupling in which the two components are directly connected to each other by a single node that provides electrical continuity from one of the two components to the other. In other words, a direct coupling may exclude and / or omit any additional components between the two components.

[0053] Additionally or alternatively, an indirect coupling between two components may constitute and / or represent a coupling in which the two components are indirectly connected to each other by multiple nodes that do not provide electrical continuity from one of the two components to the other. In other words, an indirect coupling may include and / or incorporate at least one additional component between the two components.

[0054] 8 is a flow diagram of an example method 800 for injecting spurious errors into a machine check architecture. In one example, the steps illustrated in FIG. 8 may be implemented and / or performed during the manufacture, assembly, configuration, and / or operation of a computing device and / or system. Additionally or alternatively, the steps illustrated in FIG. 8 may incorporate and / or involve various substeps and / or variations consistent with the description above in connection with FIGS. 1-7.

[0055] As shown in FIG. 8, the exemplary method 800 includes and / or involves configuring (810) at least one error injection register of a circuit within the machine check architecture. Step 810 may be performed in a variety of ways, including any of the ways described above in connection with FIGS. 1-7. For example, a portion of a computing device may configure and / or instantiate at least one error injection register of a circuit within the machine check architecture. In one example, the machine check architecture and / or circuitry of the computing device may set and / or clear certain bits of the error injection register to indicate and / or reflect a particular state (e.g., no pending pseudo errors).

[0056] The example method 800 also includes and / or involves detecting (820) a write operation performed on at least one bit of the error injection register. Step 820 may be performed in various manners, including any of the manners described above in connection with FIGS. 1-7. For example, the computing device may monitor and / or check any write operations performed on the error register. In one example, while monitoring and / or checking such write operations, an error detector of a machine check architecture may detect a write operation performed on at least one bit of the error injection register.

[0057] The example method 800 further includes and / or involves injecting (830) at least one pseudo-error report into at least one reporting register in the machine check architecture in response to the write operation. Step 830 may be implemented in various manners, including any of the manners described above in connection with FIGS. 1-7. For example, the computing device may inject and / or insert at least one pseudo-error report into at least one reporting register in the machine check architecture in response to the write operation. In one example, an error detector in the machine check architecture may generate at least one pseudo-error report and then input the pseudo-error report into a pipeline in the machine check architecture that conveys the pseudo-error report to the reporting register.

[0058] While the foregoing disclosure describes various embodiments using specific block diagrams, flowcharts, and examples, each block diagram element, flowchart step, operation, and / or component described and / or illustrated herein may be implemented individually and / or collectively using a wide variety of hardware, software, or firmware (or any combination thereof) configurations. It should be noted that any disclosure of components contained within other components should be considered exemplary in nature, as many other architectures can be implemented to achieve the same functionality. Furthermore, the various steps, events, and / or functions performed by such components should be considered exemplary in nature, as many alternatives and / or variations can be implemented to achieve the same functionality within the scope of the disclosure.

[0059] The process parameters and order of steps described and / or illustrated herein are given by way of example only and can be changed as desired. For example, although the steps illustrated and / or described herein are shown or described in a particular order, these steps do not necessarily have to be performed in the order illustrated or described. The various exemplary methods described and / or illustrated herein may omit one or more of the steps described or illustrated herein or may include additional steps in addition to those disclosed.

[0060] The foregoing description is provided to enable those skilled in the art to best utilize various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to be limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the present disclosure. The embodiments disclosed herein are to be considered in all respects as illustrative and not restrictive. In determining the scope of the present disclosure, reference should be made to the appended claims and their equivalents.

[0061] Unless otherwise specified, the terms "connected to" and "coupled to" (and their derivatives) as used in this specification and claims should be interpreted as allowing both direct and indirect connections (i.e., via other elements or components). Additionally, the terms "a" or "an" as used in this specification and claims should be interpreted as meaning "at least one of." Finally, for ease of use, the terms "including" and "having" (and their derivatives) as used in this specification and claims are interchangeable with the term "comprising," and have the same meaning.

Claims

1. 1. A system comprising: Agent and a machine check architecture; The machine check architecture comprises: at least one circuit configured to report errors via at least one reporting register; at least one error injection register configured to cause the circuit to inject at least one pseudo-error report into the reporting register in response to a write operation performed by the agent on at least one bit of the error injection register; system.

2. the circuit comprises a plurality of circuits; the error injection register comprises a plurality of error rejection registers; The system of claim 1.

3. the machine check architecture comprises a pipeline configured to convey the error report from the circuit to the reporting register; the error injection register is configured to cause the circuit to inject the pseudo-error report into the pipeline for transmission to the reporting register. The system of claim 1.

4. the circuitry comprising one or more wires configured to communicate another pseudo-error report from an external source to the reporting register via the pipeline. The system of claim 3.

5. The reporting register comprises: a first reporting register; a second reporting register; The first reporting register comprises: receiving a first copy of the quasi-error report via a first lane of the pipeline; storing the first copy of the pseudo-error report for access by an in-band processor; and The second reporting register comprises: receiving a second copy of the quasi-error report via a second lane of the pipeline; storing the second copy of the pseudo-error report for access by an out-of-band controller; configured to: The system of claim 3.

6. the agent comprises software or firmware executing on a processor that has access to the error injection register; The system of claim 1.

7. an integrated circuit incorporating said processor and said machine check architecture; The system of claim 6.

8. the agent comprises an out-of-band controller having access to the error injection register; The system of claim 1.

9. a first integrated circuit incorporating said out-of-band controller; a second integrated circuit incorporating the machine check architecture; The system of claim 8.

10. the out-of-band controller comprises a baseboard management controller external to the second integrated circuit. The system of claim 9.

11. The circuit comprises: Equipped with a table, The table is storing a plurality of error entries; mapping a bit of the error injection register to a particular error entry among the error entries; and the circuitry is configured to generate the injected pseudo-error report based at least in part on the mapping of the bits to the particular error entry. The system of claim 1.

12. the error injection register is configured to cause the circuit to inject another pseudo-error report into the reporting register in response to another write operation performed by the agent on at least one other bit of the error injection register. The system of claim 1.

13. an out-of-band controller configured to perform a particular action in response to a particular error identified in the pseudo-error report injected into the reporting register; The system of claim 1.

14. the specific action includes triggering an interrupt that notifies at least one other circuit of the specific error. The system of claim 13.

15. The other circuit is a processor located on an integrated circuit that includes the machine check architecture; or a baseboard management controller external to the integrated circuit containing the machine check architecture; At least one of 15. The system of claim 14.

16. 1. A machine check architecture, comprising: at least one circuit configured to report an error to a reporting register; a pipeline configured to convey error reports from said circuitry to said reporting register; at least one error injection register configured to, in response to a write operation performed by an external source on at least one bit of the error injection register, cause the circuit to inject at least one pseudo-error report through the pipeline to the reporting register; Machine check architecture.

17. the circuit comprises a plurality of circuits; the error injection register comprises a plurality of error rejection registers; 17. The machine check architecture of claim 16.

18. the circuitry comprising one or more wires configured to communicate another pseudo-error report from the external source to the reporting register via the pipeline; 17. The machine check architecture of claim 16.

19. The reporting register comprises: a first reporting register; a second reporting register; The first reporting register comprises: receiving a first copy of the quasi-error report via a first lane of the pipeline; storing the first copy of the pseudo-error report for access by an in-band processor; and The second reporting register comprises: receiving a second copy of the quasi-error report via a second lane of the pipeline; storing the second copy of the pseudo-error report for access by an out-of-band controller; configured to:

17. The machine check architecture of claim 16.

20. 1. A method comprising: configuring at least one error injection register of a circuit within the machine check architecture; detecting a write operation performed on at least one bit of the error injection register; injecting at least one pseudo-error report into at least one reporting register within the machine check architecture in response to the write operation. method.

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