Method for manufacturing light-emitting element, light-emitting element, and display device including light-emitting element

Abstract

A method for manufacturing a light-emitting device according to an embodiment of the present disclosure includes the steps of patterning a first semiconductor layer on a substrate, patterning a first insulating layer on a side surface of the first semiconductor layer, and forming an active layer and a second semiconductor layer on the first semiconductor layer.

Description

[Technical Field]

[0001] Various embodiments relate to methods for manufacturing light-emitting devices, light-emitting devices, and displays including light-emitting devices. [Background technology]

[0002] With the development of information technology, the importance of display devices, which are a connection medium between users and information, is increasing. Display devices include light-emitting elements that emit light. The light-emitting elements may be diodes that include a P-type semiconductor, an N-type semiconductor, and a quantum well structure disposed therebetween.

[0003] In order to manufacture a high-performance display device with high resolution, it is necessary to reduce the size of the light-emitting element and further improve the light-emitting efficiency of the light-emitting element.

[0004] It is necessary to eliminate process risks that arise in the process of manufacturing light-emitting devices. Summary of the Invention [Problem to be solved by the invention]

[0005] Various embodiments provide a method for manufacturing a light-emitting element, a light-emitting element, and a display device including the light-emitting element, which can reduce or minimize the risk of defects in the process for manufacturing the light-emitting element and improve light-emitting efficiency.

[0006] However, the embodiments of the present disclosure are not limited to those described herein. These and other embodiments will become more apparent to those skilled in the art upon review of the detailed description of the disclosure set forth below. [Means for solving the problem]

[0007] According to an embodiment, a method for manufacturing a light-emitting device may include the steps of patterning a first semiconductor layer on a substrate, patterning a first insulating layer on a side surface of the first semiconductor layer, and forming an active layer and a second semiconductor layer on the first semiconductor layer.

[0008] According to an embodiment, the step of patterning the first semiconductor layer may include the steps of: forming a base semiconductor layer on the substrate; and etching at least a portion of the base semiconductor layer using a mask that exposes an upper surface of the base semiconductor layer.

[0009] According to the embodiment, the patterning of the first semiconductor layer and the forming of the active layer and the second semiconductor layer may be performed in separate processes.

[0010] According to an embodiment, forming the active layer and the second semiconductor layer may include depositing the active layer and the second semiconductor layer, and depositing the active layer and the second semiconductor layer may include patterning the active layer and the second semiconductor layer separately.

[0011] According to an embodiment, patterning the first insulating layer may include exposing an upper surface of the first semiconductor layer through the first insulating layer.

[0012] According to an embodiment, forming the active layer and the second semiconductor layer may include growing the active layer and the second semiconductor layer on the exposed top surface of the first semiconductor layer.

[0013] According to the embodiment, the insulating layer may cover the side surfaces of the first semiconductor layer to prevent the active layer and the second semiconductor layer from growing on the side surfaces of the first semiconductor layer.

[0014] According to an embodiment, the manufacturing method may further include patterning the second insulating layer. The patterning of the second insulating layer may include disposing a first portion of the second insulating layer on the first insulating layer and disposing a second portion of the second insulating layer on side surfaces of the active layer and the second semiconductor layer.

[0015] According to an embodiment, the manufacturing method may further include patterning an electrode layer on the second semiconductor layer after patterning the second insulating layer.

[0016] According to an embodiment, the first semiconductor layer, the active layer, and the second semiconductor layer may form a semiconductor stack. The first semiconductor layer may include adjacent first semiconductor layers. The manufacturing method may further include, as steps performed at the same time as the step of forming the active layer and the second semiconductor layer, forming a lower active layer and a lower second semiconductor layer between the adjacent first semiconductor layers, and separating the semiconductor stack from the substrate. Separating the semiconductor stack may include separating the semiconductor stack along separation lines that are part of the first semiconductor layer. The separation lines may be defined at a position substantially the same as or higher than a top surface of the lower second semiconductor layer.

[0017] According to an embodiment, the manufacturing method may further include forming an additional first semiconductor layer on the first semiconductor layer.

[0018] According to an embodiment, the manufacturing method may further include forming the active layer and the second semiconductor layer on the additional first semiconductor layer. An area (or a size) of a top surface of the first semiconductor layer on which the additional first semiconductor layer is grown may be smaller than an area (or a size) of an adjacent surface between the additional first semiconductor layer and the active layer.

[0019] According to an embodiment, a light emitting device may include a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer, and an insulating layer disposed on a side surface of the semiconductor stack. The insulating layer may include a first insulating layer disposed on a side surface of the first semiconductor layer and a second insulating layer disposed on a side surface of the semiconductor stack, exposing side surfaces of the active layer and the second semiconductor layer. The second insulating layer may include a first portion that does not contact the first semiconductor layer (due to the first insulating layer interposed between the first portion and the first semiconductor layer) and a second portion that contacts the active layer and the second semiconductor layer.

[0020] According to an embodiment, the active layer may include a quantum well layer having a first side surface and a quantum barrier layer having a second side surface, and the first side surface and the second side surface may form a uniform plane.

[0021] According to an embodiment, the first side surface and the second side surface may form side surfaces that do not include recesses.

[0022] According to the embodiment, the second insulating layer may form a step in a region between the first portion and the second portion of the second insulating layer.

[0023] According to an embodiment, the insulating layer may have a first thickness in a region overlapping with the first semiconductor layer, and may have a second thickness thinner than the first thickness in a region overlapping with the active layer.

[0024] According to an embodiment, the first insulating layer may not cover the side surfaces of the active layer and the second semiconductor layer.

[0025] According to an embodiment, the active layer and the first semiconductor layer may have the same cross-sectional size.

[0026] According to an embodiment, the active layer may include an active surface facing the first semiconductor layer, and the active surface may entirely cover the first semiconductor layer and may include a portion of the active surface that is not in contact with the first semiconductor layer.

[0027] According to an embodiment, the active layer may be frustum-shaped.

[0028] According to the embodiment, the first semiconductor layer may include a body portion overlapping the first insulating layer and the second insulating layer, and a protrusion protruding from the body portion.

[0029] According to an embodiment, the light-emitting element may further include a first end adjacent to the first semiconductor layer, a second end adjacent to the second semiconductor layer, and an auxiliary semiconductor layer disposed on the first insulating layer in a region adjacent to the first end and including the same material as the second semiconductor layer.

[0030] According to an embodiment, the light-emitting element may further include a first end adjacent to the first semiconductor layer, a second end adjacent to the second semiconductor layer, an electrode layer disposed on the second semiconductor layer, and an auxiliary electrode layer disposed on the first insulating layer in a region adjacent to the first end and containing substantially the same material as the electrode layer.

[0031] An embodiment may provide a display device including a base layer and a light-emitting device layer disposed on the base layer and including the light-emitting device. The light-emitting device layer may include first and second electrodes spaced apart from each other, an anode-connected electrode electrically connected to a first end of the light-emitting device, and a cathode-connected electrode electrically connected to a second end of the light-emitting device. The light-emitting device may be aligned between the first and second electrodes. [Effects of the Invention]

[0032] Various embodiments provide a method for manufacturing a light-emitting element, a light-emitting element, and a display device including the light-emitting element, which can reduce or minimize the risk of defects in the process for manufacturing the light-emitting element and improve light-emitting efficiency. [Brief explanation of the drawings]

[0033] [Figure 1] 1 is a schematic diagram showing a light-emitting device according to a first embodiment. [Figure 2] 1 is a schematic diagram showing a light-emitting device according to a first embodiment. [Figure 3] 1 is a schematic diagram showing a light-emitting device according to a first embodiment. [Figure 4] FIG. 10 is a schematic diagram showing a light-emitting device according to a second embodiment. [Figure 5] FIG. 10 is a schematic diagram showing a light-emitting device according to a second embodiment. [Figure 6] FIG. 10 is a schematic cross-sectional view showing a light-emitting device according to a third embodiment. [Figure 7] FIG. 10 is a schematic cross-sectional view showing a light-emitting device according to a fourth embodiment. [Figure 8] FIG. 10 is a schematic cross-sectional view showing a light-emitting device according to a fifth embodiment. [Figure 9] FIG. 10 is a schematic cross-sectional view showing a light-emitting device according to a sixth embodiment. [Figure 10] FIG. 1 is a schematic plan view showing a display device according to an embodiment. [Figure 11] 1 is a schematic cross-sectional view showing a display device according to an embodiment. [Figure 12] 1 is a schematic cross-sectional view showing a connecting electrode and a light emitting device according to an embodiment. [Figure 13] 1 is a simplified flowchart illustrating a method for manufacturing a light-emitting device according to one or more embodiments. [Figure 14] 1A-1D are schematic cross-sectional views illustrating a method for manufacturing a light-emitting device according to one or more embodiments. [Figure 15] 1A-1D are schematic cross-sectional views illustrating a method for manufacturing a light-emitting device according to one or more embodiments. [Figure 16] 1A to 1C are schematic plan views illustrating a method for manufacturing a light-emitting element according to an embodiment. [Figure 17]1A to 1C are schematic plan views illustrating a method for manufacturing a light-emitting element according to an embodiment. [Figure 18] 1A to 1C are schematic plan views illustrating a method for manufacturing a light-emitting element according to an embodiment. [Figure 19] 1A-1D are schematic cross-sectional views illustrating a method for manufacturing a light-emitting device according to one or more embodiments. [Figure 20] 1A-1D are schematic cross-sectional views illustrating a method for manufacturing a light-emitting device according to one or more embodiments. [Figure 21] 1A-1D are schematic cross-sectional views illustrating a method for manufacturing a light-emitting device according to one or more embodiments. [Figure 22] 1A-1D are schematic cross-sectional views illustrating a method for manufacturing a light-emitting device according to one or more embodiments. [Figure 23] 1A-1D are schematic cross-sectional views illustrating a method for manufacturing a light-emitting device according to one or more embodiments. [Figure 24] 1A-1D are schematic cross-sectional views illustrating a method for manufacturing a light-emitting device according to one or more embodiments. [Figure 25] 1A-1D are schematic cross-sectional views illustrating a method for manufacturing a light-emitting device according to one or more embodiments. [Figure 26] 1A-1D are schematic cross-sectional views illustrating a method for manufacturing a light-emitting device according to one or more embodiments. [Figure 27] 1A-1D are schematic cross-sectional views illustrating a method for manufacturing a light-emitting device according to one or more embodiments. [Figure 28] 1A-1D are schematic cross-sectional views illustrating a method for manufacturing a light-emitting device according to one or more embodiments. [Figure 29] 10 is a schematic flowchart showing a method for manufacturing a light-emitting device according to a fifth embodiment. [Figure 30] 10A to 10C are schematic cross-sectional views showing a method for manufacturing a light-emitting device according to a fifth embodiment. [Figure 31] 10A to 10C are schematic cross-sectional views showing a method for manufacturing a light-emitting device according to a fifth embodiment. [Figure 32] 10A to 10C are schematic cross-sectional views showing a method for manufacturing a light-emitting device according to a fifth embodiment. [Figure 33] 13 is a schematic flowchart showing a method for manufacturing a light-emitting device according to a sixth embodiment. [Figure 34] 10A to 10C are schematic cross-sectional views showing a method for manufacturing a light-emitting device according to a sixth embodiment. [Figure 35] 10A to 10C are schematic cross-sectional views showing a method for manufacturing a light-emitting device according to a sixth embodiment. [Figure 36] 10A to 10C are schematic cross-sectional views showing a method for manufacturing a light-emitting device according to a sixth embodiment. [Figure 37] 10A to 10C are schematic cross-sectional views showing a method for manufacturing a light-emitting device according to a sixth embodiment. [Figure 38] 10A to 10C are schematic cross-sectional views showing a method for manufacturing a light-emitting device according to a sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0034] In the following description, for purposes of explanation, numerous specific details are presented in order to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiments" and "implementations" are interchangeable terms that refer to non-limiting examples of the devices or methods disclosed herein. However, it will be apparent that various embodiments may be practiced without these specific details or in one or more equivalent arrangements. The various embodiments are not necessarily exclusive and do not limit the disclosure. For example, specific shapes, configurations, and characteristics of the embodiments may be used or embodied in other embodiments.

[0035] Unless otherwise expressly stated, it should be understood that the described embodiments provide features of the present invention. Accordingly, unless otherwise expressly stated, features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be combined, separated, interchanged, and / or rearranged without departing from the invention.

[0036] The use of cross-hatching and / or shading in the accompanying drawings is generally provided to clarify boundaries between adjacent elements. Therefore, the presence or absence of cross-hatching or shading does not convey or indicate preferences or requirements for specific materials, material properties, dimensions, proportions, commonalities between the elements shown in the drawings, and / or characteristics, attributes, or the like of other elements, unless expressly stated. Furthermore, the sizes and relative sizes of elements in the accompanying drawings may be exaggerated for clarity and / or illustrative purposes. As embodiments may be embodied differently, certain steps may be performed in a different order than described. For example, two steps described as consecutive may be performed substantially simultaneously or in the reverse order of the steps described. Furthermore, like reference numerals refer to like elements.

[0037] When a component, such as a layer, is referred to as being "on," "connected," or "coupled" to another component or layer, it can refer to a direct connection to the component or layer, a connection to another component or layer, or the presence of an intervening component or layer. However, when a component or layer is "directly connected" to, "directly connected to," or "directly coupled" to another component or layer, there may be no intervening component or layer. Thus, the term "connected" can refer to a physical, electrical, and / or fluid connection with or without an intervening component. Furthermore, the DR1-axis, DR2-axis, and DR3-axis are not limited to the three axes of a rectangular coordinate system, such as the X-, Y-, and Z-axes, but can be interpreted in a broader sense. For example, the DR1-axis, DR2-axis, and DR3-axis can represent different directions that are perpendicular or non-perpendicular to each other. Furthermore, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, such as the X-axis, Y-axis, and Z-axis, but can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can represent directions that are perpendicular to one another or other directions that are not perpendicular to one another. For purposes of this disclosure, "at least one of A and B" can be understood to mean A only, B only, or all combinations of A and B. Also, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as X only, Y only, Z only, or combinations of two or more of X, Y, and Z. As used herein, the term "and / or" includes all combinations of one or more of the associated listed items.

[0038] In this specification, terms such as "first" and "second" may be used to describe various types of elements, but the elements should not be limited by such terms. Such terms are used to distinguish one element from another. Thus, a first element discussed below could be referred to as a second element without departing from the teachings of the present invention.

[0039] Spatially relative terms such as "beneath," "below," "under," "lower," "above," "upper," "over," "higher," and "side" (e.g., expressions such as "sidewall") may be used for descriptive purposes herein to describe the relationship of one component depicted in the figures to other components. Spatially relative terms are used to encompass not only the orientation shown in the figures, but also other orientations of the device during use, operation, and / or manufacture. For example, if the device were inverted in the figures, components depicted below other components or features would then be positioned above the other components or features. Thus, terms such as "beneath" can encompass an orientation of above and below. Additionally, the device may be oriented in other ways (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptions used herein should be interpreted accordingly.

[0040] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, singular terms are intended to include plural terms unless expressly stated to the contrary. Additionally, terms such as "comprises," "comprising," "includes," and / or "including" as used in this specification specify the presence of the stated feature, integer, step, operation, element, component, and / or group, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. Furthermore, the terms "approximately," "about," and similar terms are used herein as terms of degree and are recognized by those of ordinary skill in the art to reflect inherent variations that may be recognized in measurements, calculations, and / or provided values.

[0041] Various embodiments are described herein with reference to cross-sectional and / or exploded illustrations that are schematic illustrations of embodiments and / or intermediate structures. Consequently, variations in the shapes of the drawings due to manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments disclosed herein should not be construed as necessarily limited to the shapes of the particular illustrated regions, but should include, for example, deviations in shape due to manufacturing. In this manner, regions depicted in the drawings may be schematic in nature and are not necessarily limiting, as the shapes of the regions may not reflect the shapes of actual regions of the device.

[0042] The embodiments relate to a method for manufacturing a light emitting device, a light emitting device, and a display device including the light emitting device. Hereinafter, a method for manufacturing a light emitting device, a light emitting device, and a display device including the light emitting device according to the embodiments will be described with reference to the accompanying drawings.

[0043] The light emitting device LD according to the embodiment can be manufactured without applying an etching process to the active layer AL, thereby reducing the risk of defects during manufacturing of the light emitting device LD and improving the light emitting efficiency.

[0044] 1 to 9, a light emitting device LD according to one or more embodiments will be described.

[0045] The light emitting device LD according to the first embodiment will be described with reference to FIGS.

[0046] 1 to 3 are schematic diagrams showing a light-emitting device according to a first embodiment. Fig. 1 is a schematic cross-sectional view showing a light-emitting device LD according to the first embodiment. Fig. 2 is a schematic perspective view showing a light-emitting device LD according to the first embodiment. Fig. 3 is a schematic cross-sectional view showing an active layer AL of the light-emitting device LD according to the first embodiment.

[0047] The light emitting device LD can emit light. The light emitting device LD may include a semiconductor stack member ESS and an insulating layer INF. The semiconductor stack member ESS may include a first semiconductor layer SCL1, a second semiconductor layer SCL2, and an active layer AL disposed between the first semiconductor layer SCL1 and the second semiconductor layer SCL2. According to an embodiment, the light emitting device LD may further include an electrode layer ELL.

[0048] According to the embodiment, the first semiconductor layer SCL1, the active layer AL, and the second semiconductor layer SCL2 may be sequentially stacked along the longitudinal direction of the light emitting device LD, which extends in the direction of the length L of the light emitting device LD.

[0049] The light-emitting element LD can have various shapes. For example, the light-emitting element LD may be a columnar shape extending in one direction (for example, the longitudinal direction). According to the embodiment, the cross-sectional shape of the light-emitting element LD is not limited. For example, the cross-section of the light-emitting element LD may be circular or elliptical. For example, the cross-section of the light-emitting element LD may be an n-sided polygon (n is an integer of 3 or more).

[0050] The light emitting element LD may have a first end EP1 and a second end EP2. According to an embodiment, the first end EP1 of the light emitting element LD may be adjacent to a first semiconductor layer SCL1, and the second end EP2 may be adjacent to a second semiconductor layer SCL2. According to an embodiment, the second end EP2 may be adjacent to an electrode layer ELL.

[0051] The light emitting element LD may have various sizes. According to an embodiment, the diameter D (or width) and length L of the light emitting element LD may each have a nanoscale to a microscale. However, the embodiment is not necessarily limited thereto.

[0052] The first semiconductor layer SCL1 may include a semiconductor of a first conductivity type. The first semiconductor layer SCL1 is disposed on the active layer AL and may include a semiconductor layer of a different type from the second semiconductor layer SCL2. For example, the first semiconductor layer SCL1 may include an N-type semiconductor layer. For example, the first semiconductor layer SCL1 may include at least one selected from the group consisting of InAlGaN, GaN, AlGaN, InGaN, AlN, AlGaInP, GaAs, and InN, and may include an N-type semiconductor layer doped with a first conductivity type dopant such as Si, Ge, or Sn. However, examples are not limited thereto. The first semiconductor layer SCL1 may include various materials.

[0053] The active layer AL may be disposed between the first semiconductor layer SCL1 and the second semiconductor layer SCL2, and the position of the active layer AL may be changed in various ways depending on the type of the light emitting device LD.

[0054] The active layer AL can include a single-quantum well or a multi-quantum well structure.

[0055] The active layer AL may include a quantum well layer WL and a quantum barrier layer BL. The quantum barrier layer BL may form a quantum barrier for forming a quantum well structure, and the quantum well layer WL may form a quantum well for forming a quantum well structure. For example, the quantum barrier layer BL may include GaN, and the quantum well layer WL may include InGaN. However, embodiments are not limited thereto.

[0056] The second semiconductor layer SCL2 may include a semiconductor of a second conductivity type. The second semiconductor layer SCL2 is disposed on the active layer AL and may include a semiconductor layer of a different type from the first semiconductor layer SCL1. For example, the second semiconductor layer SCL2 may include a P-type semiconductor layer. For example, the second semiconductor layer SCL2 may include one or more semiconductor materials selected from the group consisting of InAlGaN, GaN, AlGaN, InGaN, AlN, AlGaInP, GaAs, and InN, or may include a P-type semiconductor layer doped with a second conductivity type dopant such as Ga, B, or Mg. However, examples are not limited thereto. The second semiconductor layer SCL2 may include various materials.

[0057] According to an embodiment, the active layer AL and the first semiconductor layer SCL1 may be adjacent to each other (e.g., in contact with each other). Depending on the embodiment, the area (or surface size) of a first surface of the active layer AL facing the first semiconductor layer SCL1 may be substantially the same as the area (or surface size) of one surface of the first semiconductor layer SCL1 facing the active layer AL. For example, since the active layer AL is grown on the upper surface of the first semiconductor layer SCL1 after the first semiconductor layer SCL1 is formed, the area (or surface size) of one surface of the active layer AL and the area (or surface size) of one surface of the first semiconductor layer SCL1 may be the same as each other.

[0058] According to an embodiment, the active layer AL and the second semiconductor layer SCL2 may be adjacent to each other (e.g., in contact with each other). Depending on the embodiment, the area (or surface size) of the second surface of the active layer AL facing the second semiconductor layer SCL2 and the area (or surface size) of one surface of the second semiconductor layer SCL2 facing the active layer AL may be substantially the same.

[0059] According to the embodiment, the active layer AL and the second semiconductor layer SCL2 may have a uniform cross-sectional area (or uniform cross-sectional size) along the lateral direction (or width direction), for example. For example, the active layer AL and the second semiconductor layer SCL2 may be grown on the first semiconductor layer SCL1 along the lateral direction (or width direction) to have a substantially uniform cross-sectional area (or uniform cross-sectional size).

[0060] The active layer AL may include side surfaces that have minimal curvature and are substantially uniform. For example, the quantum well layer WL may have a first side surface S1, and the quantum barrier layer BL may have a second side surface S2. For example, the first side surface S1 and the second side surface S2 may form a uniform plane.

[0061] For example, each of the first side S1 and the second side S2 may be groove-free. Depending on the embodiment, the first side S1 and the second side S2 may form sides that do not include recesses (e.g., flat, planar sides).

[0062] In this specification, the term "side" may refer to a region including a portion of the remaining region of an object (e.g., a semiconductor stack member ESS, an active layer AL, a first semiconductor layer SCL1, or a second semiconductor layer SCL2, etc.) other than the top and bottom surfaces. For example, the top and bottom surfaces of an object may refer to the surfaces corresponding to the first end EP1 or the second end EP2 of the light-emitting element LD (or the semiconductor stack member ESS). Depending on the embodiment, the side surface may refer to a portion of the outer surface of the object defined in the region between the first end EP1 and the second end EP2 of the light-emitting element LD (or the semiconductor stack member ESS).

[0063] For example, the active layer AL can be manufactured without a separate etching process, and therefore, according to the embodiment, defects are not formed in the active layer AL, thereby improving the luminous efficiency of the light emitting device LD.

[0064] When a voltage equal to or greater than a threshold voltage is applied to the first end EP1 and the second end EP2 of the light emitting element LD, electron-hole pairs can recombine with each other in the active layer AL, and the light emitting element LD can emit light. By controlling the light emission of the light emitting element LD using this principle, the light emitting element LD can be used as a light source for various devices.

[0065] The insulating layer INF may be disposed on one side of the semiconductor stack member ESS, and may enclose (or surround) at least a portion of a side surface of the active layer AL, and may further enclose (or surround) a portion of each of the first semiconductor layer SCL1 and the second semiconductor layer SCL2.

[0066] The insulating layer INF may include a first insulating layer INF1 and a second insulating layer INF2. According to an embodiment, the insulating layer INF may include an inorganic material.

[0067] According to an embodiment, the first insulating layer INF1 and the second insulating layer INF2 may contain the same inorganic material, and according to an embodiment, the first insulating layer INF1 and the second insulating layer INF2 may contain different inorganic materials.

[0068] According to an embodiment, the inorganic material may include one or more of the group of silicon oxides (SiOx), silicon nitrides (SiNx), silicon oxynitrides (SiOxNy), aluminum oxides (AlxOy), zirconium oxides (ZrxOy), hafnium oxides (HfxOy), and titanium oxides (TiOx).

[0069] The insulating layer INF may expose the first end EP1 and the second end EP2 of the light emitting element LD, which have different polarities from each other. For example, the insulating layer INF may expose the respective ends of the electrode layer ELL and the first semiconductor layer SCL1 adjacent to the first end EP1 and the second end EP2 of the light emitting element LD.

[0070] The insulating layer INF can ensure the electrical stability of the light emitting device LD. In addition, the insulating layer INF can minimize surface defects of the light emitting device LD to improve its lifespan and efficiency. When a plurality of light emitting devices LD are arranged closely to each other, the insulating layer INF can prevent short defects between the light emitting devices LD.

[0071] The first insulating layer INF1 and the second insulating layer INF2 may be formed by different processes. For example, the first insulating layer INF1 may be formed before the second insulating layer INF2 is formed. According to an embodiment, the first insulating layer INF1 may be patterned before the active layer AL and the second semiconductor layer SCL2 are formed. The second insulating layer INF2 may be patterned after the active layer AL and the second semiconductor layer SCL2 are formed.

[0072] According to an embodiment, the first insulating layer INF1 forming the inner structure of the insulating layer INF can be selectively disposed at a portion of the semiconductor stack member ESS.

[0073] For example, a step defined by the second insulating layer INF2 can be formed between an area on one side of the semiconductor stack member ESS where the first insulating layer INF1 is arranged and an area on the other side of the semiconductor stack member ESS where the first insulating layer INF1 is not arranged.

[0074] For example, since the second insulating layer INF2 is arranged on the entire side of the semiconductor stack member ESS, the second insulating layer INF2 can form a step between the area on one side of the semiconductor stack member ESS where the first insulating layer INF1 is arranged and the area on the other side of the semiconductor stack member ESS where the first insulating layer INF1 is not arranged.

[0075] According to an embodiment, the thickness of the insulating layer INF in a region corresponding to the position of the first semiconductor layer SCL1 may be thicker than the thickness of the insulating layer INF in a region corresponding to the position of the second semiconductor layer SCL2 and / or the active layer AL. For example, the insulating layer INF may have a first thickness TH1 in a region overlapping with the first semiconductor layer SCL1, and a second thickness TH2 thinner than the first thickness TH1 in a region overlapping with the active layer AL or the second semiconductor layer SCL2.

[0076] The first insulating layer INF1 may be disposed on the side surface of the first semiconductor layer SCL1. For example, the first insulating layer INF1 may cover the side surface of the first semiconductor layer SCL1, but may not cover the side surfaces of the active layer AL and the second semiconductor layer SCL2.

[0077] The first insulating layer INF1 can be manufactured after the first semiconductor layer SCL1 is formed and before the active layer AL and the second semiconductor layer SCL2 are formed, thereby determining the positions where the active layer AL and the second semiconductor layer SCL2 are to be formed.

[0078] The second insulating layer INF2 may be disposed on each side surface of the first semiconductor layer SCL1, the active layer AL, and the second semiconductor layer SCL2. The second insulating layer INF2 may be disposed on the first insulating layer INF1. For example, the second insulating layer INF2 may cover each side surface of the first semiconductor layer SCL1, the active layer AL, and the second semiconductor layer SCL2.

[0079] The second insulating layer INF2 may include a first portion P1 that overlaps with the first semiconductor layer SCL1 along the cross-sectional direction of the light-emitting element LD (or along the lateral direction in which the cross-section D (or width direction) of the light-emitting element LD extends), and the second semiconductor layer SCL2 may include a second portion P2 that overlaps with the active layer AL or the second semiconductor layer SCL2 along the cross-sectional direction of the light-emitting element LD (or along the lateral direction in which the cross-section D (or width direction) of the light-emitting element LD extends).

[0080] The first portion P1 of the second insulating layer INF2 may be prevented from contacting the first semiconductor layer SCL1 across the first insulating layer INF1, and the second portion P2 of the second insulating layer INF2 may be in contact with the active layer AL and the second semiconductor layer SCL2.

[0081] The first portion P1 of the second insulating layer INF2 may overlap the first insulating layer INF1. The first portion P1 of the second insulating layer INF2 may be disposed on the first insulating layer INF1. According to an embodiment, the first portion P1 of the second insulating layer INF2 may overlap the first semiconductor layer SCL1 and the first insulating layer INF1, but may not overlap the active layer AL and the second semiconductor layer SCL2.

[0082] The second portion P2 of the second insulating layer INF2 may not overlap with the first insulating layer INF1. The second portion P2 of the second insulating layer INF2 may be disposed on the active layer AL and the second semiconductor layer SCL2. According to an embodiment, the second portion P2 of the second insulating layer INF2 may overlap with the active layer AL and the second semiconductor layer SCL2, but may not overlap with the first semiconductor layer SCL1.

[0083] A portion of the second insulating layer INF2 may not contact the semiconductor stack member ESS, while another portion of the second insulating layer INF2 may contact the semiconductor stack member ESS. For example, a first portion P1 of the second insulating layer INF2 may be separated from the semiconductor stack member ESS by the first insulating layer INF1. A second portion P2 of the second insulating layer INF2 may contact the semiconductor stack member ESS. For example, the second portion P2 of the second insulating layer INF2 may contact the active layer AL and the second semiconductor layer SCL2.

[0084] The second portion P2 of the second insulating layer INF2 may form a contact surface with the active layer AL or the second semiconductor layer SCL2. According to an embodiment, one surface of the active layer AL facing the second insulating layer INF2 may include a generally flat surface. Referring also to FIG. 3, the active layer AL may include a first side surface S1 and a second side surface S2, which may face the second portion P2 of the second insulating layer INF2. According to an embodiment, the first side surface S1 and the second side surface S2 of the active layer AL may contact the second insulating layer INF2.

[0085] The electrode layer ELL may be disposed on the second semiconductor layer SCL2. The electrode layer ELL may be adjacent to the second end EP2.

[0086] The electrode layer ELL may be connected (e.g., electrically connected) to the second semiconductor layer SCL2. A portion of the electrode layer ELL may be exposed. For example, the insulating layer INF may expose one surface of the electrode layer ELL. The electrode layer ELL may be exposed in a region corresponding to the second end EP2. According to an embodiment, a side surface of the electrode layer ELL may also be exposed.

[0087] According to an embodiment, the electrode layer ELL may be an ohmic contact electrode, but the embodiment is not limited thereto. For example, the electrode layer ELL may be a Schottky contact electrode.

[0088] According to an embodiment, the electrode layer ELL may be substantially transparent. For example, the electrode layer ELL may include ITO (Indium Tin Oxide). This allows the electrode layer ELL to transmit emitted light. However, embodiments are not limited thereto. According to an embodiment, the electrode layer ELL may include one or more of the group consisting of chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), oxides thereof, and alloys thereof.

[0089] The structure of the light emitting device LD according to the embodiment is not limited to the above. For example, the light emitting device LD may further include a superlattice layer disposed between the first semiconductor layer SCL1 and the active layer AL and / or a strain relief layer disposed between the active layer AL and the second semiconductor layer SCL2.

[0090] According to an embodiment, the superlattice layer may have a structure in which two or more layers with different compositions are alternately stacked. For example, the superlattice layer may have a structure in which GaN layers and InGaN layers are alternately arranged. According to an embodiment, the superlattice layer may relieve (or reduce) stress between the first semiconductor layer SCL1 and the active layer AL. The electron blocking layer may block at least a portion of electrons between the active layer AL and the second semiconductor layer SCL2, thereby improving the recombination efficiency of electron-hole pairs for light emission.

[0091] According to an embodiment, the electron blocking layer may include a material having a bandgap energy larger than that of the second semiconductor layer SCL2 to prevent electron overflow. For example, the electron blocking layer may include Mg-doped AlGaN.

[0092] The light emitting device LD according to the second embodiment will be described with reference to Figures 4 and 5. The features of the light emitting device LD according to the second embodiment will be described, focusing on the differences from the first embodiment. For convenience of explanation, overlapping descriptions similar to or the same as the above embodiments may be simplified or omitted.

[0093] 4 and 5 are schematic diagrams showing a light emitting device according to a second embodiment. Fig. 4 is a schematic cross-sectional view showing a light emitting device LD according to the second embodiment. Fig. 5 is a schematic perspective view showing a light emitting device LD according to the second embodiment.

[0094] The light emitting device LD according to the second embodiment differs from the light emitting device LD according to the first embodiment in that the active layer AL and the second semiconductor layer SCL2 have larger cross-sectional areas than the first semiconductor layer SCL1.

[0095] The active layer AL may include an active surface facing the first semiconductor layer SCL1, and the first semiconductor layer SCL1 may include a semiconductor surface facing the active layer AL. For example, the active surface of the active layer AL may have an area (or surface size) larger than the semiconductor surface of the first semiconductor layer SCL1.

[0096] For example, the active surface of the active layer AL can entirely cover the semiconductor surface of the first semiconductor layer SCL1. The active surface of the active layer AL includes at least the semiconductor surface of the first semiconductor layer SCL1, and may also include a portion that is not in contact with the semiconductor surface of the first semiconductor layer SCL1.

[0097] The second semiconductor layer SCL2 may include a semiconductor surface facing the first semiconductor layer SCL1. For example, the semiconductor surface of the second semiconductor layer SCL2 may have a larger area (or surface size) than the semiconductor surface of the first semiconductor layer SCL1. According to an embodiment, the semiconductor surface of the second semiconductor layer SCL2 may have an area (or surface size) corresponding to the active surface of the active layer AL. According to an embodiment, the area of ​​one side of the electrode layer ELL may have an area (or surface size) corresponding to the active surface of the active layer AL.

[0098] According to an embodiment, the active surface of the active layer AL can overlap at least a portion of the first insulating layer INF1. For example, a portion of the active surface of the active layer AL can contact the first insulating layer INF1 (e.g., the top surface of the first insulating layer INF1 along the longitudinal direction) and can overlap a side surface of the second insulating layer INF2 along the thickness direction of the second insulating layer INF2.

[0099] For example, since the active surface of the active layer AL entirely covers the semiconductor surface of the first semiconductor layer SCL1, a stable electrical contact region can be formed between the first semiconductor layer SCL1 and the active layer AL.

[0100] The light emitting device LD according to the third embodiment will be described with reference to Fig. 6. The features of the light emitting device LD according to the third embodiment will be described, focusing on the differences from the first embodiment. For convenience of explanation, overlapping descriptions similar or identical to those of the above embodiments may be simplified or omitted.

[0101] FIG. 6 is a schematic cross-sectional view showing a light emitting device according to the third embodiment.

[0102] The light emitting device LD according to the third embodiment differs from the light emitting device LD according to the first embodiment in that the active layer AL and the second semiconductor layer SCL2 have large cross-sectional areas that are close to the second end EP2.

[0103] According to an embodiment, the active layer AL and the second semiconductor layer SCL2 may have a frustum shape such as a truncated cone, an n-sided truncated pyramid, etc. (n is a natural number of 3 or more).

[0104] For example, the active layer AL may have a larger cross-sectional area along a region adjacent to the first end EP1 to a region adjacent to the second end EP2, and the second semiconductor layer SCL2 may have a larger cross-sectional area along a region adjacent to the first end EP1 to a region adjacent to the second end EP2.

[0105] According to the embodiment, the second portion P2 of the second insulating layer INF2 may have a complementary thickness depending on the cross-sectional areas of the active layer AL and the second semiconductor layer SCL2. For example, the second portion P2 of the second insulating layer INF2 may have a thickness that increases from the first end EP1 toward the second end EP2. This allows the light emitting element LD to have a generally uniform cross-sectional area, for example, along the lateral direction (or width direction), in a region corresponding to the active layer AL and the second semiconductor layer SCL2.

[0106] The light emitting device LD according to the fourth embodiment will be described with reference to Fig. 7. The features of the light emitting device LD according to the fourth embodiment will be described, focusing on the differences from the above-mentioned embodiments. For convenience of explanation, the overlapping description similar to or the same as the above-mentioned embodiments may be simplified or omitted.

[0107] FIG. 7 is a schematic cross-sectional view showing a light emitting device according to a fourth embodiment.

[0108] The light emitting device LD according to the fourth embodiment differs from the light emitting device LD according to the above embodiments in that it further includes an auxiliary semiconductor layer RSCL.

[0109] The auxiliary semiconductor layer RSCL can be disposed on the first insulating layer INF1, similar to the first portion P1 of the second insulating layer INF2. For example, the auxiliary semiconductor layer RSCL can be disposed in the peripheral portion of the first insulating layer INF1. The auxiliary semiconductor layer RSCL can overlap the semiconductor stack member ESS along the cross-sectional direction of the light-emitting element LD.

[0110] The auxiliary semiconductor layer RSCL can be disposed on the first insulating layer INF1. For example, the auxiliary semiconductor layer RSCL and the second insulating layer INF2 may be adjacent to and in contact with each other, or may be disposed on the same layer (e.g., the first insulating layer INF1).

[0111] The auxiliary semiconductor layer RSCL may be disposed on the first insulating layer INF1 in a region adjacent to the first end EP1 of the light-emitting element LD. For example, the auxiliary semiconductor layer RSCL may be disposed on a first insulating portion of the first insulating layer INF1, and the first portion P1 of the second insulating layer INF2 may be disposed on a second insulating portion of the second insulating layer INF2. For example, the first insulating portion of the first insulating layer INF1 may be closer to the first end EP1 of the light-emitting element LD than the second insulating portion of the first insulating layer INF1, and may not overlap with the second insulating portion of the first insulating layer INF1 along the cross-sectional direction of the light-emitting element LD (or along the lateral direction extending in the direction of the cross-section D (or width) of the light-emitting element LD).

[0112] The auxiliary semiconductor layer RSCL and the second semiconductor layer SCL2 may include the same material. For example, the auxiliary semiconductor layer RSCL may include a P-type semiconductor material and one or more of the materials described above with reference to the second semiconductor layer SCL2. The auxiliary semiconductor layer RSCL and the second semiconductor layer SCL2 may be grown (or formed) by the same process. Therefore, according to the embodiment, a light emitting device LD including the auxiliary semiconductor layer RSCL can be manufactured without adding a process for manufacturing the auxiliary semiconductor layer RSCL.

[0113] The light emitting device LD according to the fifth embodiment will be described with reference to Fig. 8. The features of the light emitting device LD according to the fifth embodiment will be described, focusing on the differences from the above-mentioned embodiments. For convenience of explanation, the overlapping description similar to or the same as the above-mentioned embodiments may be simplified or omitted.

[0114] FIG. 8 is a schematic cross-sectional view showing a light emitting device according to a fifth embodiment.

[0115] The light emitting device LD according to the fifth embodiment differs from the light emitting device LD according to the above embodiments in that it further includes an auxiliary electrode layer RELL, which may be disposed at a position corresponding to the auxiliary semiconductor layer RSCL.

[0116] The auxiliary electrode layer RELL can be disposed on the first insulating layer INF1, similar to the first portion P1 of the second insulating layer INF2. For example, the auxiliary electrode layer RELL can be disposed in the peripheral portion of the first insulating layer INF1. The auxiliary electrode layer RELL can overlap with the semiconductor stack member ESS along the cross-sectional direction of the light-emitting element LD.

[0117] The auxiliary electrode layer RELL can be disposed on the first insulating layer INF1. For example, the auxiliary electrode layer RELL and the second insulating layer INF2 may be adjacent to each other, may be in contact with each other, or may be disposed on the same layer (e.g., the first insulating layer INF1).

[0118] The auxiliary electrode layer RELL may be disposed on the first insulating layer INF1 in a region adjacent to the first end EP1 of the light-emitting element LD. For example, the auxiliary electrode layer RELL may be disposed on a first insulating portion of the first insulating layer INF1, and the first portion P1 of the second insulating layer INF2 may be disposed on a second insulating portion of the second insulating layer INF2. For example, the first insulating portion of the first insulating layer INF1 may be closer to the first end EP1 of the light-emitting element LD than the second insulating portion of the first insulating layer INF1, and may not overlap with the second insulating portion of the first insulating layer INF1 along the cross-sectional direction of the light-emitting element LD (or along the lateral direction extending along the direction of the cross section D (or width) of the light-emitting element LD).

[0119] The auxiliary electrode layer RELL and the electrode layer ELL may include the same material. For example, the auxiliary electrode layer RELL may include a conductive material and may include one or more of the materials described above with reference to the electrode layer ELL. The auxiliary electrode layer RELL and the electrode layer ELL may be deposited (or formed) using the same process. Therefore, according to the embodiment, the light emitting device LD including the auxiliary electrode layer RELL can be manufactured without an additional process for manufacturing the auxiliary electrode layer RELL. According to the embodiment, the auxiliary electrode layer RELL may help the light emitting device LD to be more closely electrically connected (e.g., electrically connected) to other wirings. For example, the first end EP1 of the light emitting device LD may be connected (e.g., electrically connected) to the cathode-connecting electrode CNEC. For example, the auxiliary electrode layer RELL may help the electrical connection between the first end EP1 of the light emitting device LD and the cathode-connecting electrode CNEC.

[0120] The light emitting device LD according to the sixth embodiment will be described with reference to Fig. 9. The features of the light emitting device LD according to the sixth embodiment will be described, focusing on the differences from the first embodiment. For convenience of explanation, overlapping descriptions similar to or the same as those of the above-mentioned embodiments may be simplified or omitted.

[0121] FIG. 9 is a schematic cross-sectional view showing a light emitting device according to the sixth embodiment.

[0122] The light emitting device LD according to the sixth embodiment differs from the light emitting device LD according to the first embodiment in that the first semiconductor layer SCL1 has a protruding portion.

[0123] For example, the first semiconductor layer SCL1 may include a body portion SCL1_B and a protrusion portion SCL1_A.

[0124] The body part SCL1_B may be a part of the first semiconductor layer SCL1 and overlap the first insulating layer INF1 and the second insulating layer INF2, and may correspond to the overall structure of the first semiconductor layer SCL1 described above.

[0125] The protrusion SCL1_A may be a semiconductor layer formed (e.g., grown) on the body portion SCL1_B. The protrusion SCL1_A may have a shape in which at least a portion thereof protrudes. For example, the protrusion SCL1_A may have a conical shape with one region that protrudes sharply, but the embodiment is not limited thereto.

[0126] According to the embodiment, the active layer AL, the second semiconductor layer SCL2, and the electrode layer ELL may have shapes corresponding to the outer surface shape of the protrusion SCL1_A.

[0127] The protrusion SCL1_A may be adjacent to the active layer AL. For example, the protrusion SCL1_A may be directly adjacent to the active layer AL, and the active layer AL may include an active surface directly adjacent to the protrusion SCL1_A. For example, the adjacent area between the active layer AL and the first semiconductor layer SCL1 may be enlarged, thereby improving the light-emitting efficiency of the light-emitting element LD.

[0128] A display device DD including a light emitting device LD according to an embodiment will be described with reference to Figures 10 to 12. For convenience of explanation, overlapping descriptions similar to or the same as those of the above-described embodiment may be simplified or omitted.

[0129] FIG. 10 is a schematic plan view showing a display device according to an embodiment.

[0130] The display device DD can emit light. The display device DD includes a light-emitting element LD. According to an embodiment, the display device DD can be provided in various forms. For example, the display device DD can be applied to a smartphone, a notebook, a tablet PC (personal computer), a wearable device (e.g., a head-mounted device, a smart watch, smart glasses, etc.), a television, a vehicle infotainment system, etc., and can be applied to various other embodiments.

[0131] 10, the display device DD may include a base layer BSL and pixels PXL disposed on the base layer BSL. The display device DD may further include a driving circuit unit (e.g., a scan driver and a data driver) for driving the pixels PXL, wiring, and pads.

[0132] The display device DD may include a display area DA and a non-display area NDA. The non-display area NDA may refer to an area other than the display area DA. The non-display area NDA may surround at least a portion of the display area DA.

[0133] The base layer BSL may form a base member of the display device DD. The base layer BSL may be a rigid or flexible substrate or film. For example, the base layer BSL may be a rigid substrate made of glass or tempered glass, a flexible substrate (or thin film) made of plastic or metal, or at least one insulating layer. The material and / or physical properties of the base layer BSL are not limited. According to an embodiment, the base layer BSL may be substantially transparent. For example, substantially transparent may mean that light can be transmitted at a transmittance of at least one. In other embodiments, the base layer BSL may be translucent or opaque. The base layer BSL may also include a reflective material.

[0134] The display area DA may refer to an area where the pixels PXL are arranged, and the non-display area NDA may refer to an area where the pixels PXL are not arranged. The non-display area NDA may include driving circuits, wiring, and pads connected to the pixels PXL of the display area DA.

[0135] According to an embodiment, the pixels PXL (or sub-pixels SPX) may be arranged according to a stripe or PENTILE™ arrangement structure, etc. However, the embodiment is not limited thereto.

[0136] According to the embodiment, the pixel PXL includes a light-emitting element LD. The pixel PXL (or sub-pixel SPX) may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. At least one of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 may form one pixel unit PXU that can emit light of various colors.

[0137] For example, each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 can emit light of one color. For example, the first subpixel SPX1 may be a red pixel that emits red light (e.g., a first color), the second subpixel SPX2 may be a green pixel that emits green light (e.g., a second color), and the third subpixel SPX3 may be a blue pixel that emits blue light (e.g., a third color). The colors, types, and / or numbers of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 that constitute each pixel unit PXU are not limited to specific examples.

[0138] Fig. 11 is a schematic cross-sectional view showing a display device according to an embodiment, showing a pixel circuit layer PCL including pixel circuits and a light emitting element layer EML in which a light emitting element LD is arranged.

[0139] Referring to FIG. 11, the display device DD may include a pixel circuit layer PCL and a light emitting element layer EML.

[0140] The pixel circuit layer PCL may be a layer including a pixel circuit for driving the light emitting element LD. The pixel circuit layer PCL may include a base layer BSL, a metal layer for forming the pixel circuit, and an insulating layer disposed between the metal layers. According to an embodiment, the base layer BSL may form a base surface for supporting the display device DD.

[0141] According to an embodiment, the pixel circuit may include a thin film transistor. The pixel circuit may further include a storage capacitor. The pixel circuit is connected (e.g., electrically connected) to the light emitting element LD to provide an electrical signal for the light emitting element LD to emit light.

[0142] The light emitting element layer EML may be disposed on the pixel circuit layer PCL and may include first and second insulating pattern layers INP1 and INP2, an alignment electrode layer ELT, a first insulating layer INS1, banks BNK, a light emitting element LD, a second insulating layer INS2, and a connecting electrode layer CNE.

[0143] The first and second insulating pattern layers INP1, INP2 may be disposed on the protective layer PSV. The first and second insulating pattern layers INP1, INP2 may have various shapes. In an embodiment, the first and second insulating pattern layers INP1, INP2 may protrude in the thickness direction of the base layer BSL (e.g., in the third direction DR3).

[0144] The first and second insulating pattern layers INP1 and INP2 may have a step to be easily aligned within a light-emitting region where the light-emitting element LD is disposed. According to an embodiment, the first and second insulating pattern layers INP1 and INP2 may be partition walls (or walls). According to an embodiment, the first and second insulating pattern layers INP1 and INP2 may include at least one organic material and / or inorganic material. However, the embodiment is not limited to the examples.

[0145] The alignment electrode layer ELT may include an electrode for aligning the light emitting element LD. According to an embodiment, the alignment electrode layer ELT may include a first electrode ELTA and a second electrode ELTG. According to an embodiment, the first electrode ELTA may be a first alignment electrode, and the second electrode ELTG may be a second alignment electrode.

[0146] The alignment electrode layer ELT may be disposed on the pixel circuit layer PCL. Part of the alignment electrode layer ELT may be disposed on the first and second insulating pattern layers INP1 and INP2. The first electrode ELTA may be supplied with a first alignment signal and / or a first power supply. The second electrode ELTG may be supplied with a second alignment signal and / or a second power supply.

[0147] The first electrode ELTA may be an electrode to which an AC signal can be supplied to align the light emitting element LD. The first electrode ELTA may be an electrode to which an anode signal can be supplied to cause the light emitting element LD to emit light. The second electrode ELTG may be an electrode to which a ground signal can be supplied to align the light emitting element LD. The second electrode ELTG may be an electrode to which a cathode signal can be supplied to cause the light emitting element LD to emit light.

[0148] The first electrode ELTA (or the first alignment electrode) and the second electrode ELTG (or the second alignment electrode) may receive a first alignment signal and a second alignment signal, respectively, during a process of aligning the light emitting element LD. For example, ink containing the light emitting element LD may be supplied, and the first alignment signal may be supplied to the first electrode ELTA and the second alignment signal may be supplied to the second electrode ELTG. For example, the first alignment signal and the second alignment signal may have different waveforms, potentials, and / or phases. For example, the first alignment signal may be an AC signal, and the second alignment signal may be a ground signal. However, embodiments are not limited thereto. An electric field is formed between (or on) the first electrode ELTA and the second electrode ELTG, and the light emitting element LD may be aligned between the first electrode ELTA and the second electrode ELTG based on the electric field. For example, the light emitting element LD may be aligned (or disposed) on the first alignment electrode and the second alignment electrode by moving (or rotating) due to a force (e.g., a dielectrophoresis (DEP) force) corresponding to the electric field.

[0149] The first insulating film INS1 may be disposed on the alignment electrode layer ELT. For example, the first insulating film INS1 may cover the first electrode ELTA and the second electrode ELTG.

[0150] The bank BNK may be disposed on the first insulating film INS1. The bank BNK may form a space in which ink containing the light-emitting element LD is accommodated. For example, the ink containing the light-emitting element LD may be supplied into the space defined by the bank BNK.

[0151] According to an embodiment, the bank BNK may include an organic material such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, a polyimide resin, a polyester resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB), but the embodiment is not limited thereto.

[0152] The light emitting element LD may be disposed on the first insulating film INS1 in an area surrounded by the bank BNK. According to an embodiment, the light emitting element LD may emit light based on electrical signals (e.g., anode signals and cathode signals) provided from the anode-connected electrode CNEA and the cathode-connected electrode CNEC.

[0153] The second insulating film INS2 may be disposed on the light emitting element LD. The second insulating film INS2 may cover the active layer AL of the light emitting element LD. The second insulating film INS2 may expose at least a portion of the light emitting element LD. For example, the second insulating film INS2 may not cover the first end EP1 and the second end EP2 of the light emitting element LD, thereby exposing the first end EP1 and the second end EP2 of the light emitting element LD and allowing them to be connected (e.g., electrically connected) to the anode-connecting electrode CNEA and the cathode-connecting electrode CNEC, respectively. According to an embodiment, another portion of the second insulating film INS2 may be disposed on the bank BNK and the first insulating film INS1.

[0154] When the second insulating film INS2 is formed on the light emitting element LD after the alignment of the light emitting element LD is completed, the light emitting element LD can be prevented from moving away from the aligned position.

[0155] The second insulating film INS2 may have a single layer structure or a multi-layer structure. The second insulating film INS2 may include one or more of the following group: silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlNx), aluminum oxide (AlxOy), zirconium oxide (ZrOx), hafnium oxide (HfOx), and titanium oxide (TiOx). However, the embodiment is not limited thereto.

[0156] The anode-connecting electrode CNEA and the cathode-connecting electrode CNEC may be disposed on the first insulating layer INS1 and the second insulating layer INS2. The anode-connecting electrode CNEA may be connected (e.g., electrically connected) to a first end EP1 of the light emitting element LD. The cathode-connecting electrode CNEC may be connected (e.g., electrically connected) to a second end EP2 of the light emitting element LD.

[0157] The anode-connecting electrode CNEA may be connected (e.g., electrically connected) to the first electrode ELTA through a first contact portion CNT1 penetrating the first insulating film INS1, and the cathode-connecting electrode CNEC may be connected (e.g., electrically connected) to the second electrode ELTG through a second contact portion CNT2 penetrating the first insulating film INS1. According to the embodiment, the anode-connecting electrode CNEA may be connected (e.g., directly electrically connected) to a line of the pixel circuit layer PCL through the first contact portion CNT1. The cathode-connecting electrode CNEC may be connected (e.g., directly electrically connected) to a line of the pixel circuit layer PCL through the second contact portion CNT2.

[0158] According to an embodiment, the anode-connecting electrode CNEA and the cathode-connecting electrode CNEC may be patterned at the same time in the same process, but the embodiment is not limited thereto. After one of the anode-connecting electrode CNEA and the cathode-connecting electrode CNEC is patterned, the remaining electrode may be patterned.

[0159] Meanwhile, a structure in which the connecting electrodes CNEA and CNEC are connected (for example, electrically connected) to the light emitting element LD will be described with reference to Fig. 12. Fig. 12 is a schematic cross-sectional view showing connecting electrodes and a light emitting element according to an embodiment.

[0160] According to the embodiment, the insulating layer INF of the light emitting device LD may have a stepped portion. The connecting electrodes CNEA and CNEC disposed on the light emitting device LD may have a shape corresponding to the stepped portion. For example, a step may be defined in a region between the active layer AL and the first semiconductor layer SCL1. Accordingly, a portion of the anode connecting electrode CNEA may be curved in the region where the step is formed. According to the embodiment, a step may not be defined in a region where the first insulating layer INF1 and the second insulating layer INF2 overlap. Accordingly, a portion of the cathode connecting electrode CNEA may not be curved on the light emitting device LD.

[0161] The application field of the light emitting device LD according to the embodiment is not necessarily limited to the example. For example, the light emitting device LD may be a micro LED (light emitting diode) that can be transferred onto the base layer BSL by various transfer methods.

[0162] Next, a method for manufacturing the light emitting device LD according to an embodiment will be described with reference to Fig. 13 to Fig. 38. For convenience of explanation, overlapping explanations similar to or the same as those in the above-described embodiment may be simplified or omitted.

[0163] 13 to 28, a method for manufacturing the light-emitting element LD according to the first to fourth embodiments will be described. FIGS. 13 to 28 are schematic diagrams showing a method for manufacturing the light-emitting element according to the first to fourth embodiments. According to the embodiments, FIGS. 14 to 19 show the first to fourth embodiments, FIGS. 20 and 23 show the first embodiment, FIGS. 21 and 24 show the second embodiment, FIGS. 22 and 25 show the third embodiment, FIG. 26 shows a step of forming the electrode layer ELL according to the first to fourth embodiments based on the first embodiment, FIG. 27 shows a step of separating the light-emitting element LD according to the first to third embodiments based on the first embodiment, and FIG. 28 shows a step of separating the light-emitting element LD according to the fourth embodiment.

[0164] Fig. 13 is a schematic flow chart illustrating a method for manufacturing a light-emitting device according to one or more embodiments. Figs. 14, 15, and 19-28 are schematic cross-sectional views illustrating a method for manufacturing a light-emitting device according to one or more embodiments. Figs. 16-18 are schematic plan views illustrating a method for manufacturing a light-emitting device according to an embodiment.

[0165] Referring to FIG. 13, a method for manufacturing a light-emitting device LD according to one or more embodiments may include step S100 of patterning a first semiconductor layer on a growth substrate, step S200 of patterning a first insulating layer, step S300 of forming an active layer and a second semiconductor layer, step S400 of patterning the second insulating layer, step S500 of patterning an electrode layer, and step S600 of separating the semiconductor stack members.

[0166] Referring to Figures 13 to 15, in step S100 of patterning a first semiconductor layer on a growth substrate, an undoped semiconductor layer USCL and a base semiconductor layer BSCL may be formed (or disposed) on the growth substrate GS, and the base semiconductor layer BSCL may be etched to pattern the first semiconductor layer SCL1.

[0167] The growth substrate GS may be a base plate for growing a target material. For example, the growth substrate GS may be a wafer for epitaxial growth of a material. The growth substrate GS may be a GaAs, GaP, or InP substrate, but the material for forming the growth substrate GS is not limited to these examples.

[0168] The undoped semiconductor layer USCL is disposed on the buffer layer to reduce defects in the semiconductor layer formed on the growth substrate GS. According to an embodiment, the undoped semiconductor layer USCL may include GaN that does not contain a separate dopant, but the material for forming the undoped semiconductor layer USCL is not limited to the example.

[0169] The base semiconductor layer BSCL may be epitaxially grown on the undoped semiconductor layer USCL. The base semiconductor layer BSCL is a layer for forming the first semiconductor layer SCL1 and may include one or more of the above-described N-type semiconductor materials. According to an embodiment, the base semiconductor layer BSCL may be formed by a metal organic chemical vapor deposition (MOCVD) method, but the embodiment is not limited thereto.

[0170] In this step S100, an etching mask MAS may be formed on the base semiconductor layer BSCL, and the base semiconductor layer BSCL may be etched using the etching mask MAS, thereby patterning the first semiconductor layer SCL1. For example, multiple layers (e.g., a silicon oxide (SiOx) layer and an aluminum layer) for forming the etching mask MAS may be formed, and then the multiple layers may be patterned to manufacture the etching mask MAS. According to an embodiment, a nanoimprint process or a photolithography process may be performed, and the embodiment is not limited to the example.

[0171] In this step S100, the base semiconductor layer BSCL is etched to form an etched base semiconductor layer BSCL' and a first semiconductor layer SCL1 that is separately separated from the base semiconductor layer BSCL.

[0172] In this step S100, a dry etching process may be performed to pattern the first semiconductor layer SCL1, but the embodiment is not limited thereto. According to an embodiment, a wet etching process may also be performed.

[0173] After the first semiconductor layer SCL1 is patterned, the mask MAS may be removed by various processes, and the process is not particularly limited. For example, the mask MAS can be removed by etching using a solution containing BOE (Buffered Oxide Etchant).

[0174] Meanwhile, the cross section of the patterned first semiconductor layer SCL1 may have various shapes. The cross section of the patterned first semiconductor layer SCL1 may correspond to the cross section of the bottom surface of the light emitting element LD to be manufactured. For example, the cross section of the first semiconductor layer SCL1 may be circular (FIG. 16). In another example, the cross section of the first semiconductor layer SCL1 may be rectangular (FIG. 17). In yet another example, the cross section of the first semiconductor layer SCL1 may be hexagonal (FIG. 18). However, the embodiment is not limited thereto.

[0175] According to the embodiment, when the top surface (e.g., at least a portion of the top surface) of the base semiconductor layer BSCL is exposed, an etching process for forming the first semiconductor layer SCL1 may be performed. For example, the etching process for the first semiconductor layer SCL1 may be performed before the active layer AL and the second semiconductor layer SCL2 are etched. For example, the structures for individually defining the light emitting elements LD may be defined when the first semiconductor layer SCL1 is etched.

[0176] 13 and 19, in the step S200 of patterning the first insulating layer, the first insulating layer INF1 may be patterned on the side surface of the first semiconductor layer SCL1.

[0177] In step S200, an insulating layer may be deposited to form the first insulating layer INF1, and then the deposited insulating layer may be etched to expose the top surface of the first semiconductor layer SCL1. According to an embodiment, the insulating layer for forming the first insulating layer INF1 may be formed using a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method, but the embodiment is not limited thereto.

[0178] In this step S200, a dry etching process may be performed to pattern the first insulating layer INF1, thereby covering the side surfaces of the first semiconductor layer SCL1 with the first insulating layer INF1 and exposing the top surface of the first semiconductor layer SCL1.

[0179] 13 and 20 to 22, in step S300 of forming the active layer and the second semiconductor layer, the active layer AL and the second semiconductor layer SCL2 may be formed (or disposed) on the upper surface of the first semiconductor layer SCL1, thereby manufacturing a semiconductor stack member ESS including the first semiconductor layer SCL1, the active layer AL, and the second semiconductor layer SCL2.

[0180] In this step S300, the active layer AL and the second semiconductor layer SCL2 may be grown on the upper surface of the first semiconductor layer SCL1 exposed by the first insulating layer INF1. The active layer AL and the second semiconductor layer SCL2 may be formed by a metal organic chemical vapor deposition (MOCVD) process, but the embodiment is not limited thereto.

[0181] In this step S300, according to an embodiment, when the active layer AL and the second semiconductor layer SCL2 are formed, corresponding layers may be formed on the exposed, pre-etched base semiconductor layer BSCL'. A lower active layer AL' and a lower second semiconductor layer SCL2' may be grown in the region between the spaced-apart first semiconductor layers SCL1.

[0182] For example, the lower active layer AL′ and the lower second semiconductor layer SCL2′ may be interposed between adjacent first insulating layers INF1. The lower active layer AL′ and the lower second semiconductor layer SCL2′ may be grown on the exposed, pre-etched base semiconductor layer BSCL′.

[0183] According to an embodiment, quantum barrier layers BL and quantum well layers WL may be grown alternately to form the active layer AL. According to an embodiment, the quantum barrier layers BL and the quantum well layers WL may be grown on the exposed upper surface of the first semiconductor layer SCL1, so that an etching process for separately manufacturing the active layer AL may be conveniently omitted.

[0184] For example, the active layer AL and the second semiconductor layer SCL2 according to the embodiment can be manufactured without an etching process. For example, in the process of forming (e.g., growing) the active layer AL and the second semiconductor layer SCL2, the active layer AL and the second semiconductor layer SCL2 can be patterned separately. As described above, when the etching process is performed on the active layer AL, structural risks such as the formation of defects in the active layer AL can occur. For example, the light emitting efficiency can be reduced. However, according to the embodiment, the active layer AL is manufactured without performing an etching process, so the light emitting device LD according to the embodiment can have excellent light emitting efficiency.

[0185] In this step S300, to manufacture the light emitting device LD according to the first embodiment (e.g., FIGS. 1 to 3), the active layer AL and the second semiconductor layer SCL2 may be grown, for example, along the lateral direction (or width direction) so that their cross-sectional areas are substantially the same as the cross-sectional area (or cross-sectional size) of the first semiconductor layer SCL1 (see FIG. 20). According to the embodiment, the active layer AL and the second semiconductor layer SCL2 may be grown so that they correspond to the area (or cross-sectional size) of the exposed top surface of the first semiconductor layer SCL1.

[0186] In this step S300, to manufacture the light emitting device LD according to the second embodiment (e.g., FIGS. 4 and 5), the active layer AL and the second semiconductor layer SCL2 may be grown, for example, along the lateral direction (or width direction) so that their cross-sectional areas are larger than that of the first semiconductor layer SCL1 (see FIG. 21). In this step S300, since the active layer AL has a larger cross-sectional area than the first semiconductor layer SCL1, the active layer AL can cover the entire upper surface of the first semiconductor layer SCL1. According to the embodiment, the grown active layer AL can cover a portion of the first semiconductor layer SCL1.

[0187] In this step S300, in order to manufacture the light emitting device LD according to the third embodiment (e.g., FIG. 6), the active layer AL and the second semiconductor layer SCL2 can be grown to have a cross-sectional area that increases toward the upper side (see FIG. 22).

[0188] 13 and 23 to 25, in the step S400 of patterning the second insulating layer INF2, the second insulating layer INF2 may be patterned on the side surface of the semiconductor stack member ESS.

[0189] In step S400, an insulating layer may be deposited to form the second insulating layer INF2, and then the deposited insulating layer may be etched to expose the top surface of the second semiconductor layer SCL2. According to an embodiment, the insulating layer for forming the second insulating layer INF2 may be formed using a CVD method or an ALD method. However, the embodiment is not limited thereto.

[0190] In this step S400, a part of the second insulating layer INF2 may be in contact with the first insulating layer INF1, and another part of the second insulating layer INF2 may be in contact with the active layer AL and the second semiconductor layer SCL2.

[0191] In this step S400, a dry etching process may be performed to pattern the second insulating layer INF2, thereby covering the side surfaces of the first semiconductor layer SCL1 and the first insulating layer INF1 with the second insulating layer INF2, covering the side surfaces of the active layer AL and the second semiconductor layer SCL2 with the second insulating layer INF2, and exposing the top surface of the second semiconductor layer SCL2.

[0192] 23 may show a structure in which the second insulating layer INF2 is formed for manufacturing the light emitting device LD according to the first embodiment. For example, the second insulating layer INF2 may be formed to cover the side surfaces of the active layer AL and the second semiconductor layer SCL2, which have a substantially uniform cross-sectional area.

[0193] 24 may show a structure in which a second insulating layer INF2 is formed for manufacturing a light emitting device LD according to the second embodiment. For example, the second insulating layer INF2 may be fabricated to cover the side surfaces of the active layer AL and the second semiconductor layer SCL2, which have a cross-sectional area larger than that of the first semiconductor layer SCL1.

[0194] 25 may show a structure in which the second insulating layer INF2 is formed for manufacturing the light emitting device LD according to the third embodiment. For example, the second insulating layer INF2 may be formed to cover the side surfaces of the active layer AL and the second semiconductor layer SCL2, each having a frustum shape.

[0195] 13 and 26, in the step S500 of patterning the electrode layer, an electrode layer ELL may be patterned on the exposed upper surface of the second semiconductor layer SCL2.

[0196] In step S500, the electrode layer ELL may be formed by depositing a base electrode layer and then etching the deposited base electrode layer to pattern the electrode layer ELL. According to an embodiment, the base electrode layer may be formed using a sputtering method, although the embodiment is not limited thereto.

[0197] In this step S500, the electrode layer ELL may be connected (eg, electrically connected) to the second semiconductor layer SCL2, and the insulating layer INF may be exposed.

[0198] 13, 27, and 28, in the step S600 of separating the semiconductor stack members, the semiconductor stack members ESS spaced apart from each other may be separated to manufacture individually provided light emitting devices LD. For example, each light emitting device LD may be manufactured to include a semiconductor stack member ESS, an insulating layer INF, and an electrode layer ELL. According to an embodiment, the light emitting device LD may be manufactured to further include an auxiliary semiconductor layer RSCL.

[0199] In step S600, the light emitting elements LD may be individually separated by cutting a portion of the first semiconductor layer SCL1. For example, a line along which the semiconductor stack members ESS are individually separated may be defined within the first semiconductor layer SCL1.

[0200] In step S600, according to an embodiment, the light emitting device LD may be separated into individual pieces by applying a physical external force. For example, by applying ultrasonic waves to the light emitting device LD, the lower portion of the light emitting device LD may be separated, thereby providing the light emitting device LD individually. In another example, laser lift-off, a thermal process, or the like may be performed to separate the light emitting device LD. However, the embodiment is not limited thereto, and various processes may be applied.

[0201] According to the embodiment, the line separating the light emitting devices LD may be defined at a position corresponding to the height of the lower second semiconductor layer SCL2'. For example, the separation line defined in the first semiconductor layer SCL1 may be determined (or defined) at a position that is the same as or higher than the top surface of the lower second semiconductor layer SCL2'. This allows the outer surface of the second insulating layer INF2 to be exposed, and a structure of the insulating layer INF that can electrically isolate the light emitting devices LD can be manufactured, thereby providing the light emitting device LD according to the embodiment.

[0202] 28, the line separating the light emitting device LD may overlap with a part of the lower second semiconductor layer SCL2' according to an embodiment. For example, the light emitting device LD according to the fourth embodiment may be manufactured.

[0203] According to an embodiment, the position of the line along which the light emitting element LD is separated may be defined to overlap with a portion of the lower second semiconductor layer SCL2', and a layer containing the same material as the second semiconductor layer SCL2 may be provided on a portion of the insulating layer INF (e.g., the second insulating layer INF2) of the manufactured light emitting element LD.

[0204] For example, at least a portion of the lower second semiconductor layer SCL2' can remain on at least a portion of the lower part of the first insulating layer INF1 of the light-emitting element LD, and similar to the second insulating layer INF2, an auxiliary semiconductor layer RSCL can be manufactured that covers the first insulating layer INF1 and includes a P-type semiconductor material.

[0205] A method for manufacturing the light emitting device LD according to the fifth embodiment will be described with reference to Figures 28 to 32. For convenience of explanation, overlapping explanations similar to or the same as those in the above-mentioned embodiments may be simplified or omitted.

[0206] 29 to 32 are schematic diagrams showing a method for manufacturing a light emitting device according to the fifth embodiment.

[0207] Fig. 29 is a schematic flow chart showing a method for manufacturing a light-emitting device according to Example 5. Figs. 30 to 32 are schematic cross-sectional views showing a method for manufacturing a light-emitting device according to Example 5.

[0208] According to the embodiment, the method for manufacturing the light emitting device LD according to the fifth embodiment differs from the method for manufacturing the light emitting device LD according to one or more of the above-described embodiments in that the electrode layer ELL is manufactured before the second insulating layer INF2.

[0209] For example, referring to FIG. 29, a method for manufacturing a light-emitting element LD according to an embodiment may include step S100 of patterning a first semiconductor layer on a growth substrate, step S200 of patterning a first insulating layer, step S300 of forming an active layer and a second semiconductor layer, step S420 of patterning an electrode layer, step S520 of patterning a second insulating layer, and step S600 of separating the semiconductor stack members.

[0210] Referring to FIG. 30, in step S300 of forming the active layer and second semiconductor layer and step S420 of patterning the electrode layer, the active layer AL, the lower active layer AL', the second semiconductor layer SCL2, and the lower second semiconductor layer SCL2' can be grown on the patterned first semiconductor layer SCL1, and then the electrode layer ELL and the lower electrode layer ELL' can be patterned.

[0211] The electrode layer ELL and the lower electrode layer ELL' can be formed by the same process. For example, after depositing a base electrode for forming the electrode layer ELL and the lower electrode layer ELL', the deposited base electrode can be etched to form the electrode layer ELL and the lower electrode layer ELL'.

[0212] According to an embodiment, the lower electrode layer ELL' may be disposed on the lower second semiconductor layer SCL2', and the electrode layer ELL may be disposed on the second semiconductor layer SCL2.

[0213] Referring to FIG. 31, in the step S520 of patterning the second insulating layer, the second insulating layer INF2 may be patterned on the side surface of the semiconductor stack member ESS.

[0214] In step S520, the second insulating layer INF2 may expose the electrode layer ELL, and in some embodiments, a portion of the second insulating layer INF2 may cover the side surface of the electrode layer ELL. In some embodiments, a portion of the second insulating layer INF2 may contact a portion of the lower electrode layer ELL'.

[0215] Referring to FIG. 32, in the step S600 of separating the semiconductor stack members, the semiconductor stack members ESS spaced apart from each other can be separated to manufacture the light emitting devices LD that are individually provided.

[0216] In this step S600, the lines along which the light emitting device LD is separated may overlap with a part of the lower electrode layer ELL', For example, the light emitting device LD according to the fifth embodiment may be manufactured.

[0217] According to an embodiment, the position of the line at which the light emitting element LD is separated can be defined to overlap with a portion of the lower electrode layer ELL', and the same material as the electrode layer ELL may be provided on a portion of the insulating layer INF (e.g., the second insulating layer INF2) of the manufactured light emitting element LD.

[0218] For example, at least a portion of the lower electrode layer ELL′ can remain on at least a portion of the lower portion of the first insulating layer INF1 of the light-emitting element LD, and an auxiliary electrode layer RELL can be manufactured that covers the first insulating layer INF1 and includes a conductive material, similar to the second insulating layer INF2.

[0219] A method for manufacturing the light emitting device LD according to the sixth embodiment will be described with reference to Figures 33 to 38. For convenience of explanation, duplicated explanations similar to or the same as those of the above-mentioned embodiments may be simplified or omitted.

[0220] 33 to 38 are schematic diagrams showing a method for manufacturing a light emitting device according to the sixth embodiment.

[0221] Fig. 33 is a schematic flow chart showing a method for manufacturing a light-emitting device according to Example 6. Figs. 34 to 38 are schematic cross-sectional views showing the method for manufacturing a light-emitting device according to Example 6.

[0222] According to the embodiment, the method for manufacturing the light emitting device LD according to the sixth embodiment differs from the method for manufacturing the light emitting device LD according to one or more of the above-described embodiments in that step S250 of forming an additional first semiconductor layer is further performed.

[0223] For example, referring to FIG. 33, a method for manufacturing a light-emitting element LD according to an embodiment may include step S100 of patterning a first semiconductor layer on a growth substrate, step S200 of patterning a first insulating layer, step S250 of forming an additional first semiconductor layer, step S300 of forming an active layer and a second semiconductor layer, step S400 of patterning the second insulating layer, step S500 of patterning an electrode layer, and step S600 of separating the semiconductor stack members.

[0224] For example, in the method for manufacturing the light emitting device LD according to the embodiment, after the step S100 of patterning the first semiconductor layer and the step S200 of patterning the first insulating layer are performed, the step S250 of forming an additional first semiconductor layer may be performed.

[0225] The additional first semiconductor layer SCL1_A may be the above-mentioned protrusion SCL1_A.

[0226] 33 and 34, an additional first semiconductor layer SCL1_A may be grown on the top surface of the first semiconductor layer SCL1 where the first insulating layer INF1 is exposed.

[0227] In this step S250, since the additional first semiconductor layer SCL1_A has at least a partially protruding shape, the exposed surface of the additional first semiconductor layer SCL1_A can have an area (or surface size) larger than the area (or surface size) of the top surface of the above-mentioned patterned first semiconductor layer SCL1.

[0228] In this step S250, a lower additional first semiconductor layer ASCL' can be grown on the already-etched base semiconductor layer BSCL'.

[0229] Referring to FIGS. 33 and 35, after the additional first semiconductor layer SCL1_A is grown, the active layer AL and the second semiconductor layer SCL2 can be grown.

[0230] In this step S300, the active layer AL and the second semiconductor layer SCL2 can be grown on the exposed first additional semiconductor layer SCL1_A, thereby making the area between the active layer AL and the first additional semiconductor layer SCL1_A and the area between the active layer AL and the second semiconductor layer SCL2 larger than the area of ​​the top surface of the first semiconductor layer SCL1.

[0231] In this step S300, a lower active layer AL' and a lower second semiconductor layer SCL2' may be grown on the lower first additional semiconductor layer ASCL'.

[0232] 33 and 36, in step S400 of patterning the second insulating layer, the second insulating layer INF2 may be patterned to cover the side surfaces of the first insulating layer INF1. In step S400, the second insulating layer INF2 may cover the side surfaces of the semiconductor stack member ESS and expose the outer surface of the second semiconductor layer SCL2. For example, a portion of the second insulating layer INF2 may cover one surface of the second semiconductor layer SCL2.

[0233] 33 and 37, in the step S500 of patterning the electrode layer, an electrode layer ELL may be patterned on the exposed second semiconductor layer SCL2. In this step S500, the electrode layer ELL may have a shape corresponding to the shape of the additional first semiconductor layer SCL1_A.

[0234] 33 and 38, in the step S600 of separating the semiconductor stack, a portion of each of the first semiconductor layer SCL1 and the insulating layer INF may be cut to provide individually separated light emitting devices LD. For example, the light emitting devices LD may be separated along the separation lines. In this way, individually separated light emitting devices LD according to the sixth embodiment may be manufactured.

[0235] After completing the detailed description, those skilled in the art will recognize that many variations and modifications can be made to the embodiments without substantially departing from the principle, spirit, and scope of the disclosure. Therefore, the disclosed embodiments are not used for limiting purposes, but only in a general and technical sense.

Claims

1. patterning a first semiconductor layer on a substrate; patterning a first insulating layer on a side surface of the first semiconductor layer; forming an active layer and a second semiconductor layer on the first semiconductor layer.

2. The step of patterning the first semiconductor layer includes: forming a base semiconductor layer on the substrate; 2. The method of claim 1, further comprising: etching at least a portion of the base semiconductor layer using a mask that exposes an upper surface of the base semiconductor layer.

3. The method of claim 2 , wherein the patterning of the first semiconductor layer and the forming of the active layer and the second semiconductor layer are performed in separate processes.

4. forming the active layer and the second semiconductor layer includes depositing the active layer and the second semiconductor layer; The method of claim 2 , wherein depositing the active layer and the second semiconductor layer comprises separately patterning the active layer and the second semiconductor layer.

5. The method of claim 1 , wherein patterning the first insulating layer comprises: the first insulating layer exposing an upper surface of the first semiconductor layer.

6. 6. The method of claim 5, wherein forming the active layer and the second semiconductor layer comprises growing the active layer and the second semiconductor layer on the exposed top surface of the first semiconductor layer.

7. The method of claim 6 , wherein the first insulating layer covers the side surfaces of the first semiconductor layer so that the active layer and the second semiconductor layer do not grow on the side surfaces of the first semiconductor layer.

8. The method further includes patterning the second insulating layer; The step of patterning the second insulating layer includes:

2. The method for manufacturing a light-emitting device according to claim 1, further comprising the steps of: disposing a first portion of the second insulating layer on the first insulating layer; and disposing a second portion of the second insulating layer on side surfaces of the active layer and the second semiconductor layer.

9. The method of claim 8 , further comprising the step of patterning an electrode layer on the second semiconductor layer after patterning the second insulating layer.

10. the first semiconductor layer, the active layer, and the second semiconductor layer form a semiconductor stack member; the first semiconductor layer includes first semiconductor layers adjacent to each other, The manufacturing method further includes forming a lower active layer and a lower second semiconductor layer between the adjacent first semiconductor layers, which are steps performed at the same time as the step of forming the active layer and the second semiconductor layer, and separating the semiconductor stack member, The step of separating the semiconductor stack members includes a step of separating the semiconductor stack members individually along separation lines that are part of the first semiconductor layer, The method of claim 1 , wherein the separation line is defined at a position substantially equal to or higher than the top surface of the lower second semiconductor layer.

11. The method of claim 1 , further comprising forming an additional first semiconductor layer on the first semiconductor layer.

12. further comprising forming an active layer and a second semiconductor layer on the additional first semiconductor layer; The method for manufacturing a light-emitting device according to claim 11 , wherein an area of ​​the top surface of the first semiconductor layer on which the additional first semiconductor layer is grown is smaller than an area of ​​an adjacent surface between the additional first semiconductor layer and the active layer.

13. a semiconductor laminate member including a first semiconductor layer, a second semiconductor layer, and an active layer disposed between the first semiconductor layer and the second semiconductor layer; an insulating layer disposed on a side surface of the semiconductor laminate member, the insulating layer exposes side surfaces of the active layer and the second semiconductor layer, and includes a first insulating layer disposed on a side surface of the first semiconductor layer and a second insulating layer disposed on a side surface of the semiconductor stack member; The second insulating layer includes a first portion that is not in contact with the first semiconductor layer - due to the first insulating layer being interposed between the first portion and the first semiconductor layer - and a second portion that is in contact with the active layer and the second semiconductor layer.

14. The light emitting device according to claim 13 , wherein the active layer includes a quantum well layer having a first side surface and a quantum barrier layer having a second side surface, and the first side surface and the second side surface form a uniform plane.

15. The light-emitting device according to claim 14 , wherein the first side surface and the second side surface form a side surface that does not include a recessed portion.

16. The light-emitting device according to claim 13 , wherein the second insulating layer forms a step in a region between the first portion and the second portion of the second insulating layer.

17. The light-emitting device according to claim 16 , wherein the insulating layer has a first thickness in a region overlapping with the first semiconductor layer, and a second thickness thinner than the first thickness in a region overlapping with the active layer.

18. The light emitting device according to claim 16 , wherein the first insulating layer does not cover side surfaces of the active layer and the second semiconductor layer.

19. The light-emitting device according to claim 13 , wherein the active layer and the first semiconductor layer have the same cross-sectional size.

20. the active layer includes an active surface facing the first semiconductor layer; The light-emitting device of claim 13 , wherein the active surface entirely covers the first semiconductor layer, including a portion of the active surface that is not in contact with the first semiconductor layer.

21. The light-emitting device of claim 13 , wherein the active layer is frustum-shaped.

22. The light emitting device according to claim 13 , wherein the first semiconductor layer includes a body portion overlapping the first insulating layer and the second insulating layer, and a protrusion protruding from the body portion.

23. 14. The light-emitting element of claim 13, further comprising an auxiliary semiconductor layer disposed on the first insulating layer in a region adjacent to a first end adjacent to the first semiconductor layer, a second end adjacent to the second semiconductor layer, and the first end, the auxiliary semiconductor layer comprising substantially the same material as the second semiconductor layer.

24. 14. The light-emitting element of claim 13, further comprising: a first end adjacent to the first semiconductor layer; a second end adjacent to the second semiconductor layer; an electrode layer disposed on the second semiconductor layer; and an auxiliary electrode layer disposed on the first insulating layer in a region adjacent to the first end and containing substantially the same material as the electrode layer.

25. Base layer and a light-emitting device layer disposed on the base layer and including the light-emitting device of claim 13; The light-emitting element layer is a first electrode and a second electrode spaced apart from each other; an anode-connecting electrode electrically connected to a first end of the light emitting device and a cathode-connecting electrode electrically connected to a second end of the light emitting device; The light-emitting element is aligned between the first electrode and the second electrode.

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