Pixel-defining encapsulation barriers for RGB color patterning

Abstract

Examples disclosed herein relate to a device. The device includes a substrate, a plurality of adjacent pixel-defining layers (PDL structures) disposed on the substrate, and a plurality of subpixels. The PDL structures have a top surface coupled to adjacent sidewalls of the PDL structures. The plurality of subpixels are defined by the PDL structures. Each subpixel includes an anode, an organic light-emitting diode (OLED), a cathode, and an encapsulation layer. The organic light-emitting diode (OLED) material is disposed on the anode. The OLED material extends over the top surface of the PDL structures and past adjacent sidewalls. The cathode is disposed on the OLED material. The cathode extends over the top surface of the PDL structures and past adjacent sidewalls. The encapsulation layer is disposed over the cathode. The encapsulation layer has a first sidewall and a second sidewall.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to displays. More particularly, embodiments described herein relate to sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in displays, such as organic light emitting diode (OLED) displays. [Background technology]

[0002] Input devices, including display devices, may be used in various electronic systems. Organic light-emitting diodes (OLEDs) are light-emitting diodes (LEDs) in which a light-emitting electroluminescent layer is a film of organic compounds that emits light in response to an electric current. OLED devices are classified as bottom-emitting devices if the emitted light passes through a transparent or semitransparent bottom electrode and substrate on which the panel is fabricated. Top-emitting devices are classified based on whether the light emitted from the OLED device exits through a lid added after the device is fabricated. OLEDs are used to fabricate the display devices in many of today's electronic devices. Today's electronics manufacturers are driven to reduce the size of these display devices while simultaneously providing higher resolutions than were available just a few years ago.

[0003] OLED pixel patterning is currently based on processes that limit panel size, pixel resolution, and substrate size. Photolithography should be used to pattern the pixels, rather than utilizing fine metal masks. Current OLED pixel patterning requires lifting off the organic material after the patterning process. Lifting off the organic material introduces particle issues that significantly degrade OLED performance. Therefore, there is a need in the art for subpixel circuits and methods of forming subpixel circuits that may be utilized in displays, such as organic OLED displays. Summary of the Invention

[0004] In one embodiment, a device is provided. The device includes a substrate, a plurality of adjacent pixel-defining layer (PDL) structures disposed on the substrate, and a plurality of subpixels defined by the PDL structures. The PDL structures have a top surface coupled to adjacent sidewalls of the PDL structures. Each subpixel includes an anode, an organic light-emitting diode (OLED) material, a cathode, and an encapsulation layer. The organic light-emitting diode (OLED) material is disposed on the anode. The OLED material has first and second OLED edges extending past adjacent sidewalls above the top surface of the PDL structures. A cathode is disposed on the OLED material. The cathode has first and second cathode edges extending past adjacent sidewalls above the top surface of the PDL structures. An encapsulation layer is disposed on the cathode. The encapsulation layer has a first sidewall and a second sidewall, the first sidewall and the second sidewall extending past the first OLED edge, the second OLED edge, the first cathode edge, and the second cathode edge.

[0005] In another embodiment, a method for forming a device is provided. The method includes positioning a substrate. The substrate includes a first opening for a first subpixel defined by a plurality of adjacent pixel-defining layer (PDL) structures disposed on the substrate, and a first anode defined by the adjacent PDL structures. The method further includes depositing an OLED material, a cathode, and an encapsulation layer for the first subpixel on the substrate, forming a resist in a well of the first subpixel, removing the encapsulation layer for the first subpixel exposed by the resist for the first subpixel, and removing the OLED material and cathode for the first subpixel exposed by the resist for the first subpixel. The method includes positioning the substrate, the substrate further includes a second opening for a second subpixel defined by a plurality of PDL structures disposed on the substrate, and a second anode defined by the adjacent PDL structures. The method then further includes depositing an OLED material, a cathode, and an encapsulation layer for a second subpixel over the substrate, forming a resist in the well of the second subpixel, removing the encapsulation layer of the second subpixel exposed by the resist, removing the OLED material and cathode of the second subpixel exposed by the resist, and removing the resist of the second subpixel.

[0006] In another embodiment, a device is provided. The device includes a substrate, a plurality of adjacent pixel-defining layer (PDL) structures disposed on the substrate, and a plurality of subpixels defined by the PDL structures. The PDL structures have a top surface coupled to adjacent sidewalls of the PDL structures. Each subpixel includes an anode, an organic light-emitting diode (OLED) material, a cathode disposed on the anode, a plug, and an encapsulation layer disposed on the plug. The OLED material has first and second OLED edges extending past the adjacent sidewalls above the top surface of the PDL structure. The cathode has first and second cathode edges extending past the adjacent sidewalls above the top surface of the PDL structure. The plug is disposed on the cathode. The encapsulation layer is disposed on the plug. The encapsulation layer has first and second sidewalls. The first sidewall and the second sidewall extend past the first OLED edge, the second OLED edge, the first cathode edge, and the second cathode edge.

[0007] In another embodiment, a method for forming a device is provided. The method includes positioning a substrate. The substrate includes a first subpixel first opening defined by a plurality of adjacent pixel-defining layer (PDL) structures disposed on the substrate and a first anode defined by the adjacent PDL structures. The method further includes depositing an OLED material, a cathode, and an encapsulation layer for the first subpixel on the substrate; forming a plug in the first subpixel well, the plug having a first plug transmittance that matches or substantially matches an OLED transmittance of the OLED material of the first subpixel; removing the encapsulation layer for the first subpixel exposed by the plug; removing the OLED material and cathode for the first subpixel exposed by the plug; depositing a second encapsulation layer over the plug and the first encapsulation layer for the first subpixel; and removing a portion of the second encapsulation layer disposed over the second subpixel. The method further includes positioning a substrate including a second subpixel opening defined by a plurality of PDL structures disposed on the substrate and a second anode defined by an adjacent PDL structure, depositing an OLED material, a cathode, and an encapsulation layer for the second subpixel on the substrate, forming a plug in the well of the second subpixel, the plug having a first plug transmittance that matches or substantially matches an OLED transmittance of the OLED material of the first subpixel, removing the first encapsulation layer for the second subpixel exposed by the plug, removing the OLED material and cathode for the second subpixel exposed by the plug, depositing a second encapsulation layer over the plug and the first encapsulation layer for the second subpixel, and removing a portion of the second encapsulation layer disposed over the first subpixel.

[0008] A more particular description of the present disclosure briefly outlined above may be had by reference to embodiments, some of which are illustrated in the accompanying drawings, in a manner that allows the above-listed features of the disclosure to be understood in detail. It should be noted, however, that the accompanying drawings depict only exemplary embodiments and, therefore, should not be considered as limiting the scope of the embodiments, which may embrace other equally effective embodiments. [Brief explanation of the drawings]

[0009] [Figure 1A] FIG. 1 is a schematic cross-sectional view of a subpixel circuit having a plugless configuration, according to an embodiment. [Figure 1B] FIG. 1 is a schematic cross-sectional view of a subpixel circuit having a plug configuration, according to an embodiment. [Figure 1C] 1 is a schematic top cross-sectional view of a sub-pixel circuit having a dotted architecture, according to an embodiment. [Figure 1D] 1 is a schematic cross-sectional view of a sub-pixel circuit having a line-type architecture, according to an embodiment. [Figure 2] 1 is a flow diagram of a method for forming a sub-pixel circuit, according to an embodiment. [Figures 3A-3P] 1A-1D are schematic cross-sectional views of a substrate during a method for forming a sub-pixel circuit, according to an embodiment. [Figure 4] 1 is a flow diagram of a method for forming a sub-pixel circuit, according to an embodiment. [Figures 5A-5P] 1A-1C are schematic cross-sectional views of a substrate during a method for forming a sub-pixel circuit according to embodiments described herein. DETAILED DESCRIPTION OF THE INVENTION

[0010] For ease of understanding, where possible, identical reference numerals have been used to designate identical elements common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without additional description.

[0011] FIELD OF THE INVENTION The embodiments described herein relate generally to displays. More particularly, the embodiments described herein relate to sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in displays, such as organic light emitting diode (OLED) displays.

[0012] FIG. 1A is a schematic cross-sectional view of a subpixel circuit 100 having a plug-less configuration 101A. The cross-sectional view of FIG. 1A is taken along section line 1"-1" in FIGS. 1C and 1D. FIG. 1B is a schematic cross-sectional view of a subpixel circuit 100 having a plug configuration 101B. The cross-sectional view of FIG. 1B is taken along section line 1"-1" in FIGS. 1C and 1D.

[0013] The subpixel circuit 100 includes a substrate 102. A metal-containing layer 104 may be patterned on the substrate 102, and the metal-containing layer 104 is defined by adjacent pixel-defining layer (PDL) structures 126 disposed on the substrate 102. In one embodiment, the metal-containing layer 104 is pre-patterned on the substrate 102. For example, the substrate 102 is a pre-patterned indium tin oxide (ITO) glass substrate. The metal-containing layer 104 is configured to act as the anode for each subpixel. In one embodiment, the metal-containing layer 104 is a layer stack including a first transparent conductive oxide (TCO) layer, a second metal-containing layer disposed on the first TCO layer, and a third TCO layer disposed on the second metal-containing layer. The metal-containing layer 104 may include, but is not limited to, chromium, titanium, gold, silver, copper, aluminum, ITO, combinations thereof, or other suitable conductive materials.

[0014] The PDL structure 126 is disposed on the substrate 102. The PDL structure includes a top surface 126A bonded to two adjacent sidewalls 126B. The PDL structure 126 includes one of an organic material, an organic material having an inorganic coating disposed thereon, or an inorganic material. The organic material of the PDL structure 126 includes, but is not limited to, polyimide. The inorganic material of the PDL structure 126 includes, but is not limited to, silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiNO), magnesium fluoride (MgF), or a combination thereof. Adjacent PDL structures 126 define respective subpixels and expose the anode (i.e., the metal-containing layer 104) of each subpixel of the subpixel circuit 100.

[0015] The subpixel circuit 100 includes multiple subpixels 106, including at least a first subpixel 108A and a second subpixel 108B. While the figures show a first subpixel 108A and a second subpixel 108B, the subpixel circuit 100 of the embodiments described herein may include more than two subpixels 106, such as a third and fourth subpixel. Each subpixel 106 includes organic light-emitting diode (OLED) material 112 configured to emit white, red, green, blue, or other color light when energized. For example, the OLED material 112 of the first subpixel 108A may emit red light when energized, the OLED material of the second subpixel 108B may emit green light when energized, the OLED material of the third subpixel may emit blue light when energized, and the OLED material of the fourth and fifth subpixels may emit light of another color when energized. In one embodiment, the OLED material is different from the material of the PDL structure 126. The OLED material 112 is disposed over the PDL structure 126. In one embodiment, the OLED material 112 is disposed on the top surface 126A of the PDL structure 126. In one embodiment, the OLED material has a first end 112A and a second end 112B that extend past an end point of the metal-containing layer 104 disposed on the top surface 126A of an adjacent PDL structure 126. In another embodiment, the first end 112A of the OLED material 112 extends past a respective sidewall 126B of the PDL structure 126, and the second end 112B of the OLED material 112 extends past another respective sidewall 126B of the PDL structure 126.

[0016] A cathode 114 is disposed over the OLED material 112. In one embodiment, the cathode 114 is disposed over the OLED material 112. The cathode comprises a conductive material, such as a metal or metal alloy. For example, the cathode 114 may include, but is not limited to, chromium, titanium, aluminum, ITO, or a combination thereof. In one embodiment, the material of the cathode 114 is different from the materials of the OLED material 112 and the PDL structure 126. In one embodiment, the cathode 114 is in contact with an auxiliary cathode (not shown). In another embodiment, the cathode 114 is in contact with a bus bar (not shown) outside the active area of ​​the subpixel circuit 100. The cathode further includes a first end 114A and a second end 114B. The first end 114A and the second end 114B are disposed over the top surface 126A of an adjacent PDL structure 126. In one embodiment, the first and second ends 112A, 112B of the OLED material extend farther above the top surface 126A of the adjacent PDL structure 126 than the first and second ends 114A, 114B of the cathode. In one embodiment, the first and second ends 114A, 114B of the cathode 114 extend past an endpoint of the metal-containing layer 104. In another embodiment, the first end 114A of the cathode 114 extends past a respective sidewall 126B of the PDL structure 126, and the second end 114B of the cathode 114 extends past another respective sidewall 126B of the PDL structure 126.

[0017] Each subpixel 106 includes an encapsulation layer 116. The encapsulation layer 116 may be or correspond to a local passivation layer. The encapsulation layer 116 of each subpixel is disposed over the cathode 114 (and the OLED material 112) along with the encapsulation layer 116. The encapsulation layer 116 includes a first sidewall 116A and a second sidewall 116B. The first sidewall 116A and the second sidewall 116B of the encapsulation layer 116 extend beyond the first end 112A and the second end 112B of the OLED material 112. The first sidewall 116A and the second sidewall 116B of the encapsulation layer 116 extend beyond the first end 114A and the second end 114B of the cathode 114. The encapsulation layer 116 contacts the first end 112A, the second end 112B, the first end 114A, the second end 114B, and the top surface 126A. In one embodiment, a gap G separates the second sidewall 116B of the encapsulation layer 116 of the first pixel 108A from the first sidewall 116A of the encapsulation layer 116 of the second pixel 108B. The deposition thickness of the encapsulation layer 116 may be varied. For example, the encapsulation layer 116 may have a thickness of 0.1 μm and 2 μm. The encapsulation layer 116 comprises a non-conductive inorganic material, such as a silicon-containing material. The silicon-containing material may include a Si3N4-containing material. In one embodiment, the material of the encapsulation layer 116 is different from the materials of the cathode 114, the OLED material 112, and the PDL structure 126.

[0018] In embodiments including one or more capping layers, the capping layer is disposed between the cathode 114 and the encapsulation layer 116. For example, a first capping layer and a second capping layer are disposed between the cathode 114 and the encapsulation layer 116. Each of the embodiments described herein may include one or more capping layers disposed between the cathode 114 and the encapsulation layer 116. The first capping layer may include an organic material. The second capping layer may include an inorganic material, such as lithium fluoride. The first capping layer and the second capping layer may be deposited by vapor deposition. The unplugged configuration 101A and the plugged configuration 101B of the subpixel circuit 100 further include a global passivation layer 121. The global passivation layer 121 is disposed on the encapsulation layer 116. In one embodiment, a global passivation layer 121 is disposed on the first and second sidewalls 116A and 116B of the encapsulation layer 116 and on a portion of the top surface 126A of the PDL structure 126 within the gap G. In another embodiment, the global passivation layer 121 is disposed on the top surface 126A of the PDL structure 126 within the gap G. In another embodiment, the global passivation layer 121 may include the intermediate layer 118 and the passivation layer 120. In one embodiment, the intermediate layer 118 is disposed on the first and second sidewalls 116A and 126B of the PDL structure 126 and on a portion of the top surface 126A of the PDL structure 126 within the gap G. In another embodiment, the intermediate layer 118 is disposed on the top surface 126A of the PDL structure 126 within the gap G. In another embodiment, global passivation layer 121, intermediate layer 118, and passivation layer 120 are not in contact with OLED material 112 or cathode 114. Intermediate layer 118 may include an inkjet material, such as an acrylic material.

[0019] The plug configuration 101B includes plugs 122 disposed within the encapsulation layer 116. Each plug 122 is disposed within a respective subpixel 106 of the subpixel circuit 100. The plugs 122 may have an additional passivation layer disposed thereon. The plugs may include, but are not limited to, a photoresist, a color filter, or a photosensitive monomer. The plugs 122 have a plug transmittance that matches or substantially matches the OLED transmittance of the OLED material 112. The plugs 122 may each be the same material or may match the OLED transmittance. The plugs 122 may also be different materials that match the OLED transmittance of each of the multiple subpixels 106. The matched or substantially matched plug and OLED transmittances allow the plugs 122 to remain on the subpixels 106 without blocking light emitted from the OLED material 112. The plugs 122 can remain in place and therefore do not require a lift-off procedure for removal from the subpixel circuit 100. Because the plugs 122 remain, there is no need to place additional patterned resist material over the formed subpixels 106 in subsequent operations. Eliminating the need for a lift-off procedure for the plugs and the need for additional patterned resist material for the subpixel circuitry 100 increases slew-through.

[0020] FIG. 1C is a schematic top cross-sectional view of a subpixel circuit 100 having a dot-type architecture 101C. FIG. 1D is a schematic cross-sectional view of a subpixel circuit 100 having a line-type architecture 101D. Each of the top cross-sectional views of FIG. 1C and FIG. 1D is taken along section line 1′-1′ in FIG. 1A and FIG. 1B. The dot-type architecture 101C includes multiple pixel openings 124A with adjacent PDL structures 126. Each of the pixel openings 124A defines a subpixel 106 of the dot-type architecture 101C. The line-type architecture 101D includes multiple pixel openings 124B with adjacent PDL structures 126. Each of the pixel openings 124B defines a subpixel 106 of the line-type architecture 101D.

[0021] 2 is a flow diagram of a method 200 for forming a subpixel circuit 100 having a plug-less configuration 101 A. Figures 3A-3P are schematic cross-sectional views of a substrate 102 during a method 200 for forming a subpixel circuit 100 having a plug-less configuration 101 A.

[0022] 3A, in operation 201, the OLED material 112, cathode 114, and first encapsulation layer 116A of the first subpixel 108A are deposited on the substrate 102. The OLED material 112, cathode 114, and first encapsulation layer 116A are disposed over the PDL structure 126 and the metal-containing layer 104. In embodiments including a capping layer, the capping layer is deposited between the cathode 114 and the first encapsulation layer 116A. The capping layer may be deposited by vapor deposition. In one embodiment, the OLED material 112 and the cathode 114 are deposited using vapor deposition.

[0023] As shown in FIG. 3B , in operation 202, a resist 302 is formed in the well of the first subpixel 108A. The resist 302 is disposed on the first encapsulation layer 116A. The resist 302 has a width W1. The resist 302 is a positive resist or a negative resist. A positive resist includes a portion of the resist that, when exposed to electromagnetic radiation, becomes soluble in a resist developer that is applied after a pattern is written in the resist using electromagnetic radiation. A negative resist includes a portion of the resist that, when exposed to electromagnetic radiation, becomes insoluble in a resist developer that is applied after a pattern is written in the resist using electromagnetic radiation. The chemical composition of the resist 302 determines whether the resist is a positive resist or a negative resist. The resist 302 is patterned to form one of the pixel openings 124A of the dot-type architecture 101C or the pixel opening 124B of the line-type architecture 101D of the first subpixel 108A. The patterning is one of a photolithography, a digital lithography process or a laser ablation process.

[0024] As shown in FIG. 3C , in operation 203, the first encapsulation layer 116A exposed by the resist 302 is removed. The first encapsulation layer 116A exposed by the resist 302 may be removed by a dry etching process. As shown in FIG. 3D , in operation 204, the cathode 114 and the OLED material 112 exposed by the resist 302 are removed. The cathode 114 and the OLED material 112 exposed by the resist 302 may be removed by a dry etching process. The dry etching processes of operations 203 and 204 are anisotropic or substantially anisotropic. The width W1 of the resist 302 creates a buffer zone 303 above the PDL structure 126. Residual isotropic etching that occurs during these dry etching processes is limited to the buffer zone 303. As a result, damage to the OLED material 112 and the cathode 114 of the first subpixel 108A is limited.

[0025] As shown in Figure 3E, in operation 205, a second encapsulation layer 116B is deposited. The second encapsulation layer 116B is disposed over the resist 302 and the first encapsulation layer 116A. As shown in Figure 3F, in operation 206, a resist 304 is formed over the second encapsulation layer in the well of the first subpixel 108A. In one embodiment, the resist 304 has a width W2 that is greater than the width W1 of the resist 302. The resist 304 is a positive resist or a negative resist.

[0026] As shown in FIG. 3G , in operation 207, the second encapsulation layer 116B exposed by the resist 304 is removed. The second encapsulation layer 116B exposed by the resist 304 may be removed by a dry etching process. This dry etching process is anisotropic or substantially anisotropic. The width W2 of the resist 304 creates a buffer zone 305 above the PDL structure 126. Residual isotropic etching that occurs during this dry etching process is limited to the buffer zone 305. As a result, the second encapsulation layer 116B remains between the resist 302 and the resist 304, and a residual thickness t1 of the second encapsulation layer 116B adjacent to the first encapsulation layer 116A. The residual thickness t1 of the second encapsulation layer 116B insulates the cathode 114 and the OLED material 112 from exposure to the etchant in a subsequent etching operation. As a result, the first encapsulation layer 116A and the residual thickness t1 of the second encapsulation layer 116B provide the encapsulation layer 116 of FIG. 1A.

[0027] As shown in FIG. 3H, in operation 208, the resist 302, the optional resist 304, and the second encapsulation layer 116B between the resist 302 and the resist 304 are removed, thereby forming the first subpixel 108A.

[0028] 3I, in operation 209, the OLED material 112, cathode 114, and first encapsulation layer 116A of the second subpixel 108B are deposited on the substrate 102. The OLED material 112, cathode 114, and first encapsulation layer 116A are disposed over the PDL structure 126 and the metal-containing layer 104. In embodiments including a capping layer, the capping layer is deposited between the cathode 114 and the first encapsulation layer 116A. The capping layer may be deposited by vapor deposition. In one embodiment, the OLED material 112 and the cathode 114 are deposited using vapor deposition.

[0029] As shown in FIG. 3J, in operation 210, a resist 306 is formed in the well of the second subpixel 108B. The resist 306 is disposed on the first encapsulation layer 116A. The resist 306 has a width W3. The resist 306 is a positive resist or a negative resist. The resist 306 is patterned to form one of the pixel openings 124A of the dot-type architecture 101C or the pixel opening 124B of the line-type architecture 101D of the second subpixel 108B. This patterning is one of a photolithography, a digital lithography process, or a laser ablation process.

[0030] As shown in FIG. 3K, in operation 211, the first encapsulation layer 116A exposed by the resist 306 is removed. The first encapsulation layer 116A exposed by the resist 306 may be removed by a dry etching process. As shown in FIG. 3L, in operation 212, the cathode 114 and the OLED material 112 exposed by the resist 306 are removed. The cathode 114 and the OLED material 112 exposed by the resist 306 may be removed by a dry etching process. The dry etching processes of operations 211 and 212 are anisotropic or substantially anisotropic. The width W3 of the resist 306 creates a buffer zone 307 above the PDL structure 126. Residual isotropic etching that occurs during these dry etching processes is limited to the buffer zone 307. As a result, damage to the OLED material 112 and the cathode 114 of the second subpixel 108B is limited.

[0031] As shown in Figure 3M, in operation 213, a second encapsulation layer 116B is deposited. The second encapsulation layer 116B is disposed over the resist 306 and the first encapsulation layer 116A. As shown in Figure 3N, in operation 214, a resist 308 is formed over the second encapsulation layer in the well of the second subpixel 108B. In one embodiment, the resist 304 has a width W4 that is greater than the width W3 of the resist 306. The resist 308 is a positive resist or a negative resist.

[0032] As shown in FIG. 3O, in operation 215, the second encapsulation layer 116B exposed by the resist 308 is removed. The second encapsulation layer 116B exposed by the resist 308 may be removed by a dry etching process. This dry etching process is anisotropic or substantially anisotropic. The width W4 of the resist 308 creates a buffer zone 309 above the PDL structure 126. Residual isotropic etching that occurs during this dry etching process is limited to the buffer zone 309. As a result, the second encapsulation layer 116B remains between the resist 306 and the resist 308, and a residual thickness t2 of the second encapsulation layer 116B adjacent to the first encapsulation layer 116A. The residual thickness t2 of the second encapsulation layer 116B isolates the cathode 114 and the OLED material 112 from subsequent etching operations. As a result, first encapsulation layer 116A and residual thickness t2 of second encapsulation layer 116B provide encapsulation layer 116 of FIG. 1A.

[0033] As shown in FIG. 3P, in operation 216, resist 306, optional resist 308, and second encapsulation layer 116B between resist 306 and resist 308 are removed, thereby forming second subpixel 108B.

[0034] 4 is a flow diagram of a method 400 for forming a subpixel circuit 100 having a plug configuration 101B. Figures 5A-5P are schematic cross-sectional views of a substrate 102 during a method 400 for forming a subpixel circuit 100 having a plug configuration 101B.

[0035] 5A, in operation 401, the OLED material 112, cathode 114, and first encapsulation layer 116A of the first subpixel 108A are deposited on the substrate 102. The OLED material 112, cathode 114, and first encapsulation layer 116A are disposed over the PDL structure 126 and the metal-containing layer 104. In embodiments including a capping layer, the capping layer is deposited between the cathode 114 and the first encapsulation layer 116A. The capping layer may be deposited by vapor deposition. In one embodiment, the OLED material 112 and the cathode 114 are deposited using vapor deposition.

[0036] As shown in FIG. 5B , in operation 402, a plug 122A is formed in the well of the first subpixel 108A. The plug 122A is disposed on the first encapsulation layer 116A. The plug 122A has a width W5. The plug 122A may include, but is not limited to, a photoresist, a color filter, or a photosensitive monomer. The plug 122A has a plug transmittance that matches or substantially matches the OLED transmittance of the OLED material 112. The plugs 122A may each be the same material or may match the OLED transmittance. The plugs 122A may also be different materials that match the OLED transmittance of each of the plurality of subpixels 106. The matched or substantially matched plug and OLED transmittances allow the plug 122A to remain over the subpixel 106 without blocking light emitted from the OLED material 112. The plug 122A can remain in place and therefore does not require a lift-off procedure to remove it from the subpixel circuit 100. The plug 122A is patterned to form one of the pixel openings 124A of the dot architecture 101C or the pixel openings 124B of the line architecture 101D of the first subpixel 108A.

[0037] As shown in FIG. 5C , in operation 403, the first encapsulation layer 116A exposed by the plug 122A is removed. The first encapsulation layer 116A exposed by the plug 122A may be removed by a dry etching process. As shown in FIG. 5D , in operation 404, the cathode 114 and the OLED material 112 exposed by the plug 122A are removed. The cathode 114 and the OLED material 112 exposed by the plug 122A may be removed by a dry etching process. The dry etching processes of operations 403 and 404 are anisotropic or substantially anisotropic. The width W5 of the plug 122A creates a buffer zone 503 above the PDL structure 126. Residual isotropic etching that occurs during these dry etching processes is limited to the buffer zone 503. As a result, damage to the OLED material 112 and the cathode 114 of the first subpixel 108A is limited.

[0038] As shown in Figure 5E, in operation 405, a second encapsulation layer 116B is deposited. The second encapsulation layer 116B is disposed over the plug 122A and the first encapsulation layer 116A. As shown in Figure 5F, in operation 406, a resist 504 is formed in the well of the first subpixel 108A. In one embodiment, the resist 504 has a width W6 that is greater than the width W5 of the plug 122A. The resist 504 is a positive resist or a negative resist.

[0039] In operation 407, portions of the second encapsulation layer 116B are removed, as shown in FIG. 5H. In embodiments that do not include resist 504, the second encapsulation layer 116B disposed in the well of the first subpixel 108A is removed. In embodiments that include resist 504, the portions of the second encapsulation layer 116B exposed by resist 504 are removed, as shown in FIG. 5G. The second encapsulation layer 116B may be removed by a dry etching process, which may be anisotropic or substantially anisotropic. Width W6 of resist 504 creates a buffer zone 505 above the PDL structure 126. Residual isotropic etching during this dry etching process is limited to buffer zone 505. This leaves behind the second encapsulation layer 116B between plug 122A and resist 504, and a residual thickness t3 of the first encapsulation layer 116A and second encapsulation layer 116B adjacent to cathode 114 and OLED material 112. 1B. A residual thickness t3 of encapsulation layer 116 isolates cathode 114 and OLED material 112 from subsequent etching operations. As shown in FIG. 5H, in operation 408, resist 504 is removed, thereby forming first subpixel 108A.

[0040] As shown in FIG. 5I, in operation 409, the OLED material 112, cathode 114, and first encapsulation layer 116A of the second subpixel 108B are deposited on the substrate 102. The OLED material 112, cathode 114, and first encapsulation layer 116A are disposed over the PDL structure 126 and the metal-containing layer 104. In embodiments including a capping layer, the capping layer is deposited between the cathode 114 and the first encapsulation layer 116A. The capping layer may be deposited by vapor deposition. In one embodiment, the OLED material 112 and the cathode 114 are deposited using vapor deposition.

[0041] As shown in FIG. 5J, in operation 410, a plug 122B is formed in the well of the second subpixel 108B. The plug 122B is disposed on the first encapsulation layer 116A. The plug 122B has a width W7. The plug 122B may include, but is not limited to, a photoresist, a color filter, or a photosensitive monomer. The plug 122B has a plug transmittance that matches or substantially matches the OLED transmittance of the OLED material 112. The plugs 122B may each be the same material or may match the OLED transmittance. The plugs 122B may also be different materials that match the OLED transmittance of each of the plurality of subpixels 106. The matched or substantially matched plug and OLED transmittances allow the plug 122B to remain over the subpixel 106 without blocking light emitted from the OLED material 112. The plug 122B can remain in place and therefore does not require a lift-off procedure to remove it from the subpixel circuit 100. The plug 122B is patterned to form one of the pixel openings 124A of the dot architecture 101C or the pixel opening 124B of the line architecture 101D of the second subpixel 108B.

[0042] As shown in FIG. 5K, in operation 411, the first encapsulation layer 116A exposed by the plug 122B is removed. The first encapsulation layer 116A exposed by the plug 122B may be removed by a dry etching process. As shown in FIG. 5L, in operation 412, the cathode 114 and the OLED material 112 exposed by the plug 122B are removed. The cathode 114 and the OLED material 112 exposed by the plug 122B may be removed by a dry etching process. The dry etching processes of operations 411 and 412 are anisotropic or substantially anisotropic. The width W7 of the plug 122B creates a buffer zone 507 above the PDL structure 126. Residual isotropic etching that occurs during these dry etching processes is limited to the buffer zone 507. As a result, damage to the OLED material 112 and the cathode 114 of the second subpixel 108B is limited.

[0043] As shown in Figure 5M, in operation 413, a second encapsulation layer 116B is deposited. The second encapsulation layer 116B is disposed over the plug 122B and the first encapsulation layer 116A. As shown in Figure 5N, in operation 414, a resist 508 is formed in the well of the second subpixel 108B. In one embodiment, the resist 508 has a width W8 that is greater than the width W7 of the plug 122B. The resist 508 is a positive resist or a negative resist.

[0044] In operation 415, portions of the second encapsulation layer are removed, as shown in FIG. 5P. In embodiments that do not include resist 508, the second encapsulation layer 116B disposed in the well of second subpixel 108A is removed. In embodiments that include resist 508, the portions of second encapsulation layer 116B exposed by resist 508 are removed, as shown in FIG. 5G. The second encapsulation layer 116B may be removed by a dry etching process, which is anisotropic or substantially anisotropic. Width W8 of resist 508 creates a buffer zone 509 above PDL structure 126. Residual isotropic etching during this dry etching process is limited to buffer zone 509. This leaves behind the second encapsulation layer 116B between plug 122B and resist 508 and a residual thickness t4 of the first encapsulation layer 116A and second encapsulation layer 116B adjacent to cathode 114 and OLED material 112. 1B. A residual thickness t4 of the encapsulation layer 116 isolates the cathode 114 and the OLED material 112 from subsequent etching operations. As shown in FIG. 5P, in operation 416, the resist 508 is removed, thereby forming the second subpixel 108B.

[0045] In summary, described herein are subpixel circuits and methods for forming the subpixel circuits that may be utilized in displays such as organic light-emitting diode (OLED) displays. Adjacent PDL structures define each subpixel of the subpixel circuit using vapor deposition. Vapor deposition may be utilized to deposit the OLED material, cathode, and encapsulation layer. Resist may be deposited to condition the edges of the OLED material, the edges of the cathode, and the sidewalls of the encapsulation layer to isolate the OLED material and cathode from etchants in a subsequent etching operation. Plugs may be used to enhance the performance of the OLED display.

[0046] While the foregoing is directed to embodiments of the present disclosure, other and additional embodiments of the disclosure may be devised without departing from the basic scope thereof, the scope of which is determined by the claims that follow.

Claims

1. A substrate; a plurality of adjacent pixel definition layer (PDL) structures disposed over the substrate, the PDL structures having top surfaces bonded to adjacent sidewalls of the PDL structures; a plurality of subpixels defined by the PDL structures; each sub-pixel comprising: an anode; an organic light emitting diode (OLED) material disposed over the anode, the OLED material having first and second OLED edges extending past the adjacent sidewalls above the top surface of the PDL structure; and a cathode disposed over the OLED material, the cathode having a first cathode end and a second cathode end extending past the adjacent sidewalls above the top surface of the PDL structure; an encapsulation layer disposed over the cathode, the encapsulation layer having a first sidewall and a second sidewall, the first sidewall and the second sidewall extending past an edge of the first OLED, an edge of the second OLED, an edge of the first cathode, and an edge of the second cathode; A device comprising:

2. 10. The device of claim 1, wherein the anode comprises one or more layers comprising a transparent conductive oxide material, chromium, titanium, gold, silver, copper, aluminum, ITO, or a combination thereof.

3. an edge of the first OLED and an edge of the second OLED extend above the top surface of the PDL structure past an end of the anode; 10. The device of claim 1, wherein the first cathode end and the second cathode end extend past an end point of the anode onto the top surface of the PDL structure.

4. 2. The device of claim 1, wherein the plurality of subpixels includes a first subpixel and a second subpixel, and a gap separates the first sidewall of the encapsulation layer of the second subpixel from the second sidewall of the encapsulation layer of the first subpixel.

5. 5. The device of claim 4, further comprising a global passivation layer disposed over the encapsulation layer, the global passivation layer disposed over the first and second sidewalls of the encapsulation layer and over a portion of the top surface of the PDL structure within the gap.

6. 6. The device of claim 5, wherein the global passivation layer contacted the first and second sidewalls of the encapsulation layer and the portion of the top surface of the PDL structure within the gap.

7. 1. A method of forming a device, comprising: positioning a substrate, the substrate comprising: a first sub-pixel first opening defined by a plurality of adjacent pixel definition layer (PDL) structures disposed over the substrate; a first anode defined by the adjacent PDL structures; and positioning the depositing an OLED material, a cathode, and an encapsulation layer for the first subpixel over the substrate; forming a resist in a well of the first subpixel; removing the encapsulation layer of the first subpixel where the resist of the first subpixel is exposed; removing the OLED material and the cathode of the first subpixel exposed by the resist of the first subpixel; and positioning the substrate, the substrate comprising: a second opening of a second subpixel defined by the plurality of PDL structures disposed on the substrate; and a second anode defined by the adjacent PDL structures; and and depositing an OLED material, a cathode, and an encapsulation layer for the second subpixel over the substrate; forming a resist in a well of the second subpixel; removing the encapsulation layer of the second subpixel exposed by the resist; removing the OLED material and cathode of the second subpixel exposed by the resist; removing the resist of the second subpixel; A method comprising:

8. depositing a second encapsulation layer over the resist and the encapsulation layer of the first subpixel after removing the encapsulation layer, the OLED material, and the cathode of the first subpixel exposed by the resist of the first subpixel; removing portions of the second encapsulation layer; The method of claim 7 further comprising:

9. forming a second resist over the second encapsulation layer in the well of the first subpixel; removing portions of the second encapsulation layer exposed by the second resist; The method of claim 8 further comprising:

10. 8. The method of claim 7, further comprising removing the resist from the first subpixel before positioning the substrate and depositing the OLED material, cathode, and encapsulation layer of the second subpixel on the substrate.

11. 9. The method of claim 8, wherein the anode comprises one or more layers comprising a transparent conductive oxide material, chromium, titanium, gold, silver, copper, aluminum, ITO, or a combination thereof.

12. the PDL structure having a top surface bonded to adjacent sidewalls of the PDL structure; the OLED material having first and second OLED edges on the top surface of the PDL structure that extend past the adjacent sidewalls of the PDL structure; The method of claim 8 , wherein the cathode has a first cathode end and a second cathode end on the top surface of the PDL structure that extend past the adjacent sidewalls of the PDL structure.

13. 10. The method of claim 8, further comprising a global passivation layer disposed over the encapsulation layer, the global passivation layer contacting first and second sidewalls of the encapsulation layer and a portion of a top surface of the PDL structure within the gap.

14. removing the encapsulation layer, the OLED material, and the cathode of the second subpixel exposed by the resist of the second subpixel, and then depositing a second encapsulation layer over the resist and the encapsulation layer of the second subpixel; removing a portion of the second encapsulation layer of the second subpixel; and The method of claim 7 further comprising:

15. forming a second resist over the second encapsulation layer in the well of the first subpixel; removing portions of the second encapsulation layer exposed by the second resist; 15. The method of claim 14, further comprising:

16. 15. The method of claim 14, further comprising removing the resist from the first subpixel before positioning the substrate and depositing the OLED material, cathode, and encapsulation layer of the second subpixel on the substrate.

17. 15. The method of claim 14, wherein the anode comprises a first transparent conductive oxide (TCO) layer, a metal-containing layer disposed on the first TCO layer, and a second TCO layer disposed on the metal-containing layer.

18. the PDL structure having a top surface bonded to adjacent sidewalls of the PDL structure; the OLED material having first and second OLED edges on the top surface of the PDL structure that extend past the adjacent sidewalls of the PDL structure; The method of claim 14 , wherein the cathode has first and second cathode ends on the top surface of the PDL structure that extend past the adjacent sidewalls of the PDL structure.

19. 15. The method of claim 14, further comprising a global passivation layer disposed over the encapsulation layer, the global passivation layer contacting first and second sidewalls of the encapsulation layer and a portion of a top surface of the PDL structure within the gap.

20. A substrate; a plurality of adjacent pixel definition layer (PDL) structures disposed over the substrate, the PDL structures having top surfaces bonded to adjacent sidewalls of the PDL structures; a plurality of subpixels defined by the PDL structures; each sub-pixel comprising: an anode; an organic light emitting diode (OLED) material disposed over the anode, the OLED material having first and second OLED edges extending past the adjacent sidewalls above the top surface of the PDL structure; and a cathode disposed over the OLED material, the cathode having a first cathode end and a second cathode end extending past the adjacent sidewalls above the top surface of the PDL structure; a plug disposed above the cathode; an encapsulation layer disposed over the plug, the encapsulation layer having a first sidewall and a second sidewall, the first sidewall and the second sidewall extending past an edge of the first OLED, an edge of the second OLED, an edge of the first cathode, and an edge of the second cathode; A device comprising:

21. 21. The device of claim 20, wherein the anode comprises one or more layers comprising a transparent conductive oxide material, chromium, titanium, gold, silver, copper, aluminum, ITO, or a combination thereof.

22. an edge of the first OLED and an edge of the second OLED extend above the top surface of the PDL structure past an end of the anode; 21. The device of claim 20, wherein the first cathode end and the second cathode end extend past an end point of the anode onto the top surface of the PDL structure.

23. 21. The device of claim 20, wherein the plurality of subpixels includes a first subpixel and a second subpixel, and a gap separates the first sidewall of the encapsulation layer of the second subpixel from the second sidewall of the encapsulation layer of the first subpixel.

24. 21. The device of claim 20, further comprising a global passivation layer disposed over the encapsulation layer, the global passivation layer disposed over the first and second sidewalls of the encapsulation layer and over a portion of the top surface of the PDL structure within the gap.

25. 21. The device of claim 20, further comprising a global passivation layer disposed over the encapsulation layer, the global passivation layer contacting the first and second sidewalls of the encapsulation layer and a portion of the top surface of the PDL structure within gap G.

26. 1. A method of forming a device, comprising: positioning a substrate, the substrate comprising: a first sub-pixel first opening defined by a plurality of adjacent pixel definition layer (PDL) structures disposed over the substrate; a first anode defined by the adjacent PDL structures; and positioning the depositing an OLED material, a cathode, and an encapsulation layer for the first subpixel over the substrate; forming a plug in a well of the first subpixel, the plug having a first plug transmittance that matches or substantially matches an OLED transmittance of the OLED material of the first subpixel; removing the encapsulation layer of the first subpixel exposed by the plug of the first subpixel; removing the OLED material and the cathode of the first subpixel exposed by the plug of the first subpixel; depositing a second encapsulation layer over the plug and the first encapsulation layer of the first subpixel; removing a portion of the second encapsulation layer disposed over a second subpixel; and and positioning the substrate, the substrate comprising: a second opening of the second subpixel defined by the plurality of PDL structures disposed on the substrate; and a second anode defined by the adjacent PDL structures; and and depositing an OLED material, a cathode, and an encapsulation layer for the second subpixel over the substrate; forming a plug in the well of the second subpixel, the plug having a first plug transmittance that matches an OLED transmittance of the OLED material of the first subpixel; removing the first encapsulation layer of the second subpixel exposed by the plug of the second subpixel; removing the OLED material and cathode of the second subpixel exposed by the plug of the second subpixel; depositing a second encapsulation layer over the plug and the first encapsulation layer of the second subpixel; removing a portion of the second encapsulation layer disposed over a first subpixel; and A method comprising:

27. forming a resist over the second encapsulation layer in the well of the first subpixel; removing the portions of the second encapsulation layer exposed by the resist; removing the resist on the second encapsulation layer in the well of the first subpixel; 27. The method of claim 26, further comprising:

28. forming a second resist over the second encapsulation layer in the well of the second subpixel; removing portions of the second encapsulation layer exposed by the second resist; removing the second resist on the second encapsulation layer in the well of the second subpixel; 27. The method of claim 26, further comprising:

29. the PDL structure having a top surface bonded to adjacent sidewalls of the PDL structure; the OLED material having first and second OLED edges on the top surface of the PDL structure that extend past the adjacent sidewalls of the PDL structure; 27. The method of claim 26, wherein the cathode has first and second cathode ends on the top surface of the PDL structure that extend past the adjacent sidewalls of the PDL structure.

30. 30. The method of claim 29, further comprising a global passivation layer disposed over the encapsulation layer, the global passivation layer contacting first and second sidewalls of the encapsulation layer and a portion of a top surface of the PDL structure within the gap.

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