Programmable hybrid memory and capacitive devices in a DRAM process.

Abstract

A DRAM manufacturing process for producing semiconductor dies adapted to have both hybrid memory and power supply capacitance capabilities. DRAM arrays on a semiconductor die can be individually selected to function as either memory or auxiliary capacitance on a power distribution network that serves circuitry on one or more semiconductor dies in a three-dimensional active-on-active (AoA) stacked semiconductor die package configuration. Trench capacitors of a defective DRAM array can be repurposed to function as auxiliary capacitance on the power distribution network. The trench capacitors of the DRAM array can be dynamically reassigned as auxiliary capacitance when a power supply monitor detects that additional power supply capacitance is needed.

Description

[Technical Field]

[0001] Embodiments of the present invention relate generally to integrated circuit devices having active-on-active (AoA) stacked semiconductor dies, and more particularly to AoA stacks having dynamic random memory access (DRAM) cells to provide a combination of both memory and power network capacitance. [Background technology]

[0002] Electronic products such as tablets, computers, copiers, digital cameras, smartphones, control systems, and automated teller machines, among others, often use electronic components that utilize chip package assemblies for increased functionality and component density. Traditional chip packaging methods often utilize multiple integrated circuit (IC) dies attached to a single package substrate. The IC dies may include memory, logic, processors, or other IC devices.

[0003] Planar programmable device architectures have steadily increased power density as manufacturing nodes shrink the feature size of compute logic. This has prompted innovations in power delivery network (PDN) technology, including advances in packaging, interposers, and silicon to regulate power and reduce electrical noise. To manage electrical noise and voltage droop caused by transient power dissipation, capacitance is added at each power distribution level of the system and device; discrete capacitors are added between the board voltage regulation module (VRM) and the package (which surrounds or encapsulates the IC device); additional capacitors are added on the package next to the IC device or embedded in the shadow package of the IC device; trench capacitors embedded in chip-on-wafer-on-substrate (CoWoS) interposers; metal-insulator-metal capacitors (MIMCAPs) embedded in the top metal layer of the silicon die; and metal-oxide-semiconductor capacitors (MOSCAPs) constructed from transistors on the silicon itself. There are performance, cost, and form factor tradeoffs for various capacitance solutions, and power integrity can be a high priority for achieving efficient compute architectures.

[0004] With the realization of three-dimensional (3D) IC devices, there is a dramatic leap in computational and power density that is not matched by the ability to deliver power or off-chip memory access, both of which are limited by the planar surface area of ​​package pins for power and input / output (I / O) at the base of the semiconductor die stack. High-speed memory access (e.g., high-bandwidth memory (HBM) DRAM) is further limited by the linear edges of the device. Neither the edges nor the surfaces of planar IC devices scale when devices are stacked, which creates an imbalance between the ratio of complementary metal-oxide semiconductor (CMOS) logic to I / O for planar devices. Furthermore, computational logic is almost guaranteed to be thermally limited and / or have power integrity issues due to the higher logic density. In this context, there is an opportunity to restructure devices to balance the trade-off between memory hierarchy and power delivery in ways that were previously untenable due to the opportunity cost of the required silicon.

[0005] In architectures where compute density is maximized within a thermal envelope without fully utilizing 3D silicon area, power efficiency can be improved by minimizing the cost of data movement through an expanded memory hierarchy and increasing compute data locality. For example, the relative cost of accessing 3D-connected level 2 cache memory (L2 SRAM) is an order of magnitude lower than off-chip HBM, which shifts power consumption from data movement and I / O toward further increasing maximum compute capacity. Furthermore, there is over an order of magnitude more bandwidth between layers (to 3D-connected SRAM) than off-chip HBM. While this is an improvement over planar devices, the technology has drawbacks. SRAM consumes more static power than DRAM, has approximately 10 times lower density, is fabricated on standard CMOS processes, and offers little opportunity for improving power integrity through added capacitance.

[0006] To improve power integrity, alternative processes can be used to fabricate layers of trench capacitors with densities approximately 50-100 times higher than MOSCAPs fabricated with standard CMOS processes. This process can be inexpensive compared to logic layers, but is unlikely to be compatible with other useful resources; an entire layer must be dedicated to capacitance. There is diminishing return on adding capacitance; the capacitance required to mitigate power supply voltage droop is significantly smaller than the total layer area.

[0007] Therefore, there is a need for both improved power delivery in AoA stacks and more efficient utilization of the IC die area of ​​devices in AoA stacks. Summary of the Invention

[0008] Using an entire layer of a semiconductor die for capacitance has a lost opportunity cost in the logic area; the ideal solution is to use a small portion of one die for high-density capacitance and use the remaining portion for logic or memory. Active-on-active / 3D integration is an emerging technology in the semiconductor industry that enables high-density interconnects on a flat surface between multiple layers of silicon devices. Adding a third dimension to device design fundamentally changes the impact of architectural tradeoffs and allows for a reevaluation of memory hierarchy and power delivery methods. Embodiments disclosed herein describe the construction of 3D devices in which one or more layers are fabricated using DRAM processes, and these layers consist of multiple trench capacitors used for both memory cells and their extensions to the power delivery network (PDN). In one embodiment, trench capacitors in one layer of silicon can be used as capacitors in the PDN for CMOS logic in an adjacent layer. In one embodiment, a method is provided that enables programmable allocation of trench capacitors in at least one semiconductor die as either power capacitors or for use in memory cells. In one embodiment, a silicon recovery method is provided in which defective memory elements are identified and dynamically reassigned as capacitors. Using one or more silicon layers fabricated in a DRAM process, hybrid memory and power capacitor plane(s) can serve to improve both the memory hierarchy and power integrity characteristics of the CMOS logic layer in AoA 3D devices.

[0009] The advantage of using a DRAM process to fabricate a semiconductor die adapted to be both a hybrid memory and capacitance in power distribution is that an optimal balance of area can be dedicated to the extended memory hierarchy, and transient power effects can be explored and compensated for to maximize the computational and power efficiency of the device. Although DRAM cells use small trench capacitors to store data rather than power, some of these memory storage capacitors can be repurposed for power capacitance distributed throughout the device, while still providing much higher memory density than SRAM in a CMOS logic die, and comparable bandwidth.

[0010] Defect tolerance is another device architecture consideration that becomes more prominent in AoA products because wafer-on-wafer (WoW) hybrid bonding increases the physical dimensions of silicon by a factor equal to the number of layers, reducing the likelihood of defect-free devices. A typical strategy for defect tolerance is to include fine- or coarse-grained redundancy. For example, a fine-grained redundancy mechanism for DRAM may include additional columns within each bank and a mechanism for disabling columns with defective cells by shifting the output to select only from cells known to function. Similarly, a coarse-grained redundancy mechanism may include an entire redundant bank that can be configured to transparently replace another entire bank that did not fail. [Brief explanation of the drawings]

[0011] So that the above-mentioned features of the present invention can be understood in detail, a more particular description of the invention briefly summarized above can be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments of the invention and therefore should not be considered as limiting its scope, as the invention may admit of other equally effective embodiments. [Figure 1]1 illustrates a schematic isometric view of an adaptive computational acceleration platform (ACAP) device configuration, in accordance with one or more specific exemplary embodiments of the present disclosure. [Figure 2] 1 illustrates a schematic diagram of a 16-bit DRAM bank in a 4x4 configuration, in accordance with one or more specific exemplary embodiments of the present disclosure. [Figure 3] FIG. 1 illustrates a schematic diagram of a bank of trench capacitors connected directly to a power rail for adjacent logic, in accordance with one or more specific exemplary embodiments of the present disclosure. [Figure 4] 1 illustrates a schematic diagram of a 16-bit DRAM bank in a 4x4 configuration with capacitance enable circuitry, in accordance with one or more specific exemplary embodiments of the present disclosure. [Figure 5] 1 shows a schematic block diagram of an ACAP device with dynamic allocation of DRAM and capacitor arrays, in accordance with one or more specific example embodiments of the present disclosure.

[0012] For ease of understanding, wherever possible, identical reference numbers have been used to indicate identical elements common to the figures. It is contemplated that elements of one embodiment may be beneficially incorporated in other embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0013] Embodiments of the present disclosure generally relate to dedicating at least one silicon layer in an AoA stack to multiple trench capacitors that can be adapted for use as both DRAM memory storage and power network capacitance. The result is a computing device with improved power efficiency, both in terms of reduced off-chip data movement and reduced droop voltage. Beyond the core concept of a hybrid memory and capacitance layer, it is contemplated and within the scope of the present disclosure to add programmability to dynamically select which trench capacitors or banks of trench capacitors are connected to power and which are available for use as memory. Programmability can be used to tailor power and memory characteristics to specific applications or as a mechanism for defect tolerance and silicon recovery (reuse).

[0014] Referring to FIG. 1 , a schematic isometric view of an adaptive computational acceleration platform (ACAP) device configuration is shown in accordance with one or more specific exemplary embodiments of the present disclosure. As shown in FIG. 1 , a 3D stacked device 100 may include a four-deep stack including, for example, but not limited to, one layer of CMOS logic 102, a semiconductor fabric 106 replaced with a layer of silicon fabricated in a DRAM process, i.e., a DRAM capacitor fabric 120, a layer of input / output (I / O) 108, an interposer substrate 110, and a high-bandwidth memory (HBM) 112. The DRAM capacitor fabric 120 may comprise a portion of trench capacitors 232 used for memory and a remaining portion for power network capacitance. The DRAM capacitor fabric 120 includes a silicon layer of trench capacitors 232 that may be used for both DRAM cells and PSN capacitors, and is not limited to CMOS logic. It is contemplated and within the scope of the present disclosure that the DRAM capacitor fabric 120 may also benefit (improve) the memory and power characteristics of other semiconductor devices formed in the 3D stack.

[0015] Hybrid Memory and Capacitance Implementation In the simplest implementation, the 3D stacked ACAP device 100 can be designed with one or more layers fabricated in a DRAM process, and some of the trench capacitors can be statically assigned to a power distribution network (PDN) by hard-wiring the trench capacitors used as voltage storage capacitor(s) to power rails without the use of intervening transistors.

[0016] Referring to Figure 2, a schematic diagram of a 16-bit DRAM bank in a 4x4 configuration is shown in accordance with one or more specific exemplary embodiments of the present disclosure. Typical banks in modern DRAM products are much larger, e.g., 64k x 8k. Word lines 222 run horizontally from a selector circuit (row address demultiplexer 224) on one edge of a DRAM array 226 to select words, and bit lines 228 are routed vertically to sense amplifiers 230 on the adjacent edge to read memory contents (data) stored in trench capacitors 232.

[0017] 3, a schematic diagram of a bank of trench capacitors directly connected to a power rail for adjacent logic is shown, in accordance with one or more specific exemplary embodiments of the present disclosure. In one embodiment, trench capacitors 326 of the entire array of trench capacitors 332 (trench capacitors 232) may be directly connected to a power rail 334 for the adjacent logic circuitry, without any transistors coupled to the array of trench capacitors 326. Such a coarse-grained capacitor design is the simplest and has complete regularity for the array of trench capacitors 326. The power rail 334 may be coupled to a power distribution network (PDN) 336.

[0018] In another embodiment, the DRAM array 226 may have some of its trench capacitors 232 used for memory in a typical configuration, with some columns omitting the transistors 238 and instead wiring the trench capacitors 232 directly to bit lines 228 that connect to power via through-silicon vias (TSVs). Finer granularity may be more attractive for lowering wire resistance in the power delivery network (PDN) by delivering power directly through the Z plane with fewer X / Y dimensional jogs.

[0019] In another embodiment, an array of trench capacitors 232 independent of the bank configuration may be added within or alongside one or more of the DRAM arrays 226. For example, trench capacitors 232 located near the precharge circuitry and / or sense amplifiers 230 typically need to drive larger transient currents and may benefit significantly from the additional decoupling capacitance from nearby trench capacitors 332. This may improve timing margins and / or improve the reliability of the overall power distribution network (PDN).

[0020] Programmable capacitance / memory allocation Referring to FIG. 4, a schematic diagram of a 16-bit DRAM bank in a 4×4 configuration with capacitance enable circuitry is shown, in accordance with one or more specific exemplary embodiments of the present disclosure. Adding capacitance enable transistors 440 in series with the DRAM cell transistors 238 increases the resistance to reach the trench capacitors 232, but adds programmability so that the bank of DRAM memory (DRAM array 426) can be dynamically reconfigured to provide capacitance to the power delivery network (PDN). As shown in FIG. 4, each bit line 228 of the DRAM array 226 has a gate connection to a power rail 434, and a global signal (capacitance enable signal 442) enables coupling between the bit lines 228 and the power rail 434, pulling all word lines 222 of the DRAM array 426 high, which couples the individual trench capacitors 232 to the bit lines 228. 4, the trench capacitors 232 of the defective DRAM array 426 can be connected to the power rail 434 by turning on the capacitance enable transistor 440, thereby coupling those trench capacitors 232 to the PDN. The other trench capacitors 232 of the functional DRAM array 426a can be used as DRAM memory by turning off the capacitance enable transistor 440.

[0021] Defect Tolerance As an extension of the circuit configuration described in Figure 4, recovery of useful silicon can be maximized by adding a defect tolerance mechanism that reassigns banks of the DRAM array 426 to the capacitive network coupled to the PDN as a result of individual cells, sense amplifiers, and / or row controllers not functioning as designed. In conventional DRAM products, defects lead to "wasted" silicon that may exceed the cost of programmability to reconfigure cells unsuitable for use as memory into the PDN. The trench capacitor 232 of Figure 4 can be "repurposed" if its associated support electronics proves to be partially defective or inoperable for its intended purpose as a functional DRAM array 426.

[0022] In embodiments utilizing a 3D stack of semiconductor dies, i.e., having multiple DRAM arrays 426 on the DRAM capacitor fabric 120, multiple identical dies can be stacked together, but then individual dies can be configured / assigned to function as either conventional DRAM or as decoupling capacitance layers. This avoids the need to tape out two different dies, which can also provide a means to harvest a die that has insufficient functionality to perform as an operational DRAM. As an example, a nine-layer stack of DRAM dies (DRAM capacitor fabric 120) can be fabricated, with one layer serving as a decoupling capacitance layer for the entire DRAM stack. After fabrication, the individual stacks can be tested to determine which layers or sub-regions of layers are defective from a DRAM functionality perspective, particularly using wafer-on-wafer (WoW) bonding, where testing of known good dies cannot practically be used to match good dies with good dies. If at most one layer or sub-region of a layer is defective for DRAM operation but can be utilized as decoupling capacitance, that layer or sub-region can be configured in this manner, leaving eight remaining fully functional DRAM layers to provide the desired DRAM functionality. (If no layers or sub-regions of layers are defective, one layer can be arbitrarily selected to provide the required decoupling capacitance.)

[0023] Dynamic allocation of DRAM and capacitor arrays. Referring to FIG. 5, a schematic block diagram of an ACAP device with dynamic allocation of DRAM and capacitor arrays is shown, in accordance with one or more specific exemplary embodiments of the present disclosure. The ACAP device 100a may include multiple stacked integrated circuit dies in a WoW configuration. The WoW configuration may include an input / output die 108, a processing and control logic die 104, multiple DRAM / capacitor dies 120, a configuration selection circuit 550, a power distribution network (PDN) 552, and power quality monitoring and control 554 associated with each DRAM / capacitor die 120. The power quality monitoring and control 554 is adapted to detect when more capacitance needs to be coupled to the PDN 552 or when a particular DRAM array should be dynamically reallocated to a capacitor array. The power quality monitoring and control 554 detects when there is a power supply voltage drop or when a large data transfer occurs to improve data transfer noise immunity and data integrity during current surges that may cause a power supply voltage drop. Power quality monitoring and control 554 can communicate with configuration selection circuitry 550 via communication line 560 to relay detection of power problems and their location.

[0024] The configuration of which DRAM arrays 226 are used for DRAM operations and which are used as auxiliary PDN capacitance can also be programmed to occur before a power-intensive event occurs and / or when defective DRAM arrays are known and can be used only as auxiliary PDN capacitance. The configuration selection circuit 550 can select which of the DRAM arrays 226 are used for DRAM operations and which other DRAM arrays 226 are used as auxiliary PDN capacitance via control lines 442. The configuration selection circuit 550 can also communicate with the processing and control logic die 104 via a communication bus 556 to receive instructions regarding which DRAM arrays 226 are needed as auxiliary PDN capacitance (dynamic selection programming). The configuration selection circuit 550 can also communicate with the processing and control logic die 104 to inform it which DRAM arrays 226 can be used only for auxiliary PDN capacitance.

[0025] The allocation of DRAM elements for use as PDN capacitance can be dynamically allocated based on overall system power performance requirements. Power monitors, such as power quality monitor and control 554, can be included at various locations within the CMOS layer and device packaging to determine the power quality at those locations. These power quality monitor and control 554 can be adapted to detect when the quality of the power source is approaching an invalid state threshold trigger, indicating the need for additional capacitance coupled to the PDN. When triggered, several techniques can be used to dynamically transition memory elements. In scenarios such as a hardware-managed cache, memory elements can be invalidated and kept in that state. Alternatively, in software-managed scenarios where a memory manager (instructing the configuration selection circuit 550) is allocating memory, the contents of those memory elements can be migrated and then marked as unused. In either of these control scenarios, or other control scenarios, memory storage elements (trench capacitors 232) used as capacitance can be reclaimed when power quality monitor and control 554 indicates when a threshold for valid operating conditions is met.

[0026] While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, the scope of which is determined by the following claims.

Claims

1. 1. An integrated circuit (IC) stack comprising: a plurality of semiconductor IC dies stacked together and having circuit interconnections therebetween; at least one of the plurality of semiconductor IC dies comprises a plurality of dynamic random access memory (DRAM) arrays, each of the plurality of DRAM arrays comprising a plurality of trench capacitors and support circuitry therefor; The IC stack, wherein the plurality of trench capacitors of at least one of the plurality of DRAM arrays are adapted to couple to a power bus.

2. The IC stack of claim 1 , wherein the power bus is adapted to couple to a power distribution network (PDN) of at least one of the plurality of semiconductor IC dies.

3. The IC stack of claim 1 , wherein the plurality of trench capacitors are adapted to couple directly to the power bus.

4. The IC stack of claim 1 , wherein the plurality of trench capacitors are adapted to couple to the power bus through the support circuitry.

5. The IC stack of claim 1 , wherein the plurality of trench capacitors are adapted to couple to a plurality of power buses.

6. 10. The IC stack of claim 1, wherein the plurality of DRAM arrays that do not have trench capacitors coupled to the power bus are available for use as memory.

7. 7. The IC stack of claim 6, wherein a configuration selection circuit selects which of said plurality of DRAM arrays are used for memory and which others of said plurality of DRAM arrays have trench capacitors coupled to said power bus.

8. 8. The IC stack of claim 7, wherein the configuration selection circuitry selects which of the plurality of DRAM arrays have trench capacitors coupled to the power bus upon increased logic activity or current draw.

9. 8. The IC stack of claim 7, wherein the configuration selection circuit dynamically assigns which of the plurality of DRAM arrays are used for memory and which others of the plurality of DRAM arrays have trench capacitors coupled to the power bus.

10. 10. The IC stack of claim 9, wherein the trench capacitor is selected for coupling to the power bus when a power quality monitoring circuit detects a low power voltage or a fault in an associated DRAM array.

11. 1. A system of integrated circuit (IC) dies arranged in a three-dimensional stack configuration, comprising: an interposer base adapted to connect to an external circuit; a logic circuit IC die electrically coupled to the interposer base; at least one memory IC die comprising a plurality of dynamic random access memory (DRAM) arrays, each of the plurality of DRAM arrays comprising a plurality of trench capacitors and support circuitry therefor; at least one digital logic and processing IC die; some of the plurality of DRAM arrays are used for memory, and some others of the plurality of DRAM arrays have associated trench capacitors coupled to a power bus, the power bus adapted to couple to a power distribution network (PDN) for supplying power to the IC die.

12. 12. The system of claim 11, wherein a selection of which of the plurality of DRAM arrays are used for memory and which other of the plurality of DRAM arrays not used for memory have trench capacitors coupled to the power bus is dynamically allocated.

13. 12. The system of claim 11, wherein configuration selection circuitry is programmed to select which of the plurality of DRAM arrays are used for memory and which other of the plurality of DRAM arrays not used for memory have trench capacitors coupled to the power bus.

14. 12. The system of claim 11, wherein signals and power are coupled between the stacked ICs using through silicon vias (TSVs).

15. 1. A method for coupling capacitance to a power distribution network (PDN) in an integrated circuit (IC) stack, comprising: selecting at least one of a plurality of dynamic random access memory (DRAM) arrays for use as memory, each of the plurality of DRAM arrays comprising a plurality of trench capacitors and support circuitry therefor, the plurality of DRAM arrays being stacked together and within at least one of a plurality of semiconductor IC dies having circuit interconnections therebetween; selecting a trench capacitor not associated with the at least one of the plurality of DRAM arrays selected for use as a memory, for coupling to a power bus adapted to couple to the PDN.

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