Power semiconductor device and method for manufacturing a power semiconductor device - Patents.com

Abstract

A power semiconductor device (1) is described, comprising: a drift layer (2) of a first conductivity type; a well region (3) of a second conductivity type different from the first conductivity type; a first doped region (4) of the first conductivity type and a second doped region (5) of the second conductivity type, wherein the well region (3), the first doped region (4), and the second doped region (5) are provided on a first side of the power semiconductor device (1), the first doped region (4) and the second doped region (5) are spaced (6) from the drift layer (2) by the well region (3), the second doped region (5) is completely surrounded laterally by the first doped region (4), and the second doped region (5) comprises at least two portions (6) spaced (6) from each other laterally by the first doped region (4). Further, a method for manufacturing the power semiconductor device (1) is described.

Description

[Technical Field]

[0001] The present disclosure relates to power semiconductor devices and methods for manufacturing power semiconductor devices. [Background technology]

[0002] Power semiconductor devices are realized, for example, as metal-oxide-semiconductor field-effect transistors (MOSFETs). MOSFETs may be based on wide-bandgap materials, such as silicon carbide (SiC) materials. SiC MOSFETs rated at 650 V and 1200 V are currently commercially available. SiC MOSFETs implemented using planar and trench cell designs are being developed for automotive and transportation applications. Compared to their Si counterparts, SiC MOSFETs offer lower power density and maximum junction temperature (T ) while improving the efficiency and reducing the size of power electronic systems using such SiC MOSFETs. jmax While increased maximum junction temperature provides a useful indicator of resistance to abnormal electrical events such as unclamped inductive switching (UIS) and short circuits (SC), higher power densities often result in faster thermal transients (dT / dt), limiting the reliability of the device and metallization and / or packaging materials. Summary of the Invention [Problem to be solved by the invention]

[0003] In terms of fault handling capabilities, SiC MOSFETs still fall short of the typical industry standard values ​​exhibited by their Si counterparts. Furthermore, SiC MOSFETs with reduced cell pitch and die size exhibit reduced SC withstand time compared to previous generations. However, such SiC MOSFETs are usually associated with a strong trade-off between conduction losses and short-circuit withstand time (SCWT). [Means for solving the problem]

[0004] SUMMARY OF THE INVENTION Embodiments of the present disclosure relate to power semiconductor devices with improved efficiency. Further embodiments relate to methods for manufacturing such power semiconductor devices.

[0005] This is achieved by the subject matter of the independent claims. Further embodiments are evident from the dependent claims and the following description.

[0006] The term "power" herein and hereinafter refers to power semiconductor devices adapted to handle voltages and currents of, for example, more than 100V, such as 650V or 1200V and / or more than 10A.

[0007] The power semiconductor device is, for example, a power metal insulating semiconductor field-effect transistor (MISFET) for short. The term MISFET also includes MOSFETs with oxide as the insulating material in the gate. The power semiconductor device can also be an insulated-gate bipolar transistor (IGBT).

[0008] Exemplarily, the power MISFET comprises a wide bandgap material, which may be silicon carbide, SiC, and therefore the power semiconductor device is exemplarily embodied as a power SiC MISFET, in particular a power SiC MOSFET.

[0009] According to one embodiment, a power semiconductor device includes a drift layer of a first conductivity type. For example, the drift layer includes or consists of a semiconductor material. Illustratively, the semiconductor material is SiC. For example, the drift layer includes a first dopant that defines the first conductivity type.

[0010] The drift layer may have, for example, a major extension plane, with the lateral direction aligned parallel to the major extension plane and the vertical direction aligned perpendicular to the major extension plane.

[0011] When viewed from above, along the vertical direction, the drift layer has a polygonal shape in the lateral direction, for example, a triangular shape, a square shape, a hexagonal shape, etc. For example, the periphery of the drift layer has a polygonal shape in the lateral direction.

[0012] According to an embodiment, a power semiconductor device includes a well region of a second conductivity type different from the first conductivity type. The well region includes or consists of a semiconductor material, e.g., the same material as the semiconductor material of the drift layer. Illustratively, the well region includes a second dopant that defines the second conductivity type.

[0013] Illustratively, the first dopant is an n-type dopant such that the first conductivity type is n-type conductivity, and the second dopant is a p-type dopant such that the second conductivity type is p-type conductivity, or vice versa. For example, n-type conductivity is achieved by using phosphorus (P) and / or nitrogen (N) as the first dopant. P-type conductivity is achieved by using aluminum (Al) and / or boron (B) as the second dopant.

[0014] When viewed from above, the well region has a polygonal shape, such as a triangular, rectangular, or hexagonal shape, in the vertical direction. For example, the periphery of the well region has a polygonal shape in the horizontal direction. In particular, the well region has the same shape as the drift layer in the horizontal direction and is smaller in size than the drift layer. Furthermore, all symmetry axes of the horizontal shape, for example, all mirror axes of the horizontal shape, are the same. The symmetry axes, and therefore the mirror axes, are also merely imaginary in nature.

[0015] According to an embodiment, a power semiconductor device comprises a first doped region of a first conductivity type and a second doped region of a second conductivity type.

[0016] The first doped region and the second doped region may comprise or consist of a semiconductor material, e.g., the same semiconductor material as the drift layer. Illustratively, the first doped region comprises a first additional dopant. Illustratively, the second doped region comprises a second additional dopant. For example, the first additional dopant may be an n-type dopant and the second additional dopant may be a p-type dopant, or vice versa.

[0017] Illustratively, the additional first dopant is the same dopant as the first dopant. Furthermore, the additional second dopant is illustratively the same dopant as the second dopant.

[0018] Illustratively, the drift layer has a uniform doping concentration such that the maximum doping concentration corresponds to the average doping concentration. For example, the maximum doping concentration of the first doped region is higher than the maximum doping concentration of the drift layer. Illustratively, the maximum doping concentration of the first doped region is at least one order of magnitude or at least two orders of magnitude higher than the maximum doping concentration of the drift layer. For example, the maximum doping concentration of the drift layer is at least 1·10 14 cm -3 and is at most 1·10 17 cm -3 is.

[0019] For example, the maximum doping concentration of the second doped region is higher than the maximum doping concentration of the well region. Illustratively, the maximum doping concentration of the second doped region is at least one or two orders of magnitude higher than the maximum doping concentration of the well region.

[0020] For example, the maximum doping concentration of the first doped region is at least 1·10 16 cm -3 and is at most 1·10 21 cm -3 For example, the maximum doping concentration of the second doped region is at least 1·10 17 cm -3 and is at most 1·10 21 cm -3 is.

[0021] In particular, at least a portion of the first doped region forms a source region of the power semiconductor device, the source region being a region into which charge carriers, e.g., electrons or holes, are injected into the well region.

[0022] According to an embodiment of the power semiconductor device, the well region, the first doped region, and the second doped region are provided on a first side of the power semiconductor device.

[0023] The well region, the first doped region, and the second doped region each extend vertically from the first side to a predetermined depth, and the well region can have a first depth, the first doped region can have a second depth, and the second doped region can have a third depth.

[0024] Illustratively, the first depth is greater than the second depth and the third depth. For example, the third depth is greater than the second depth, or the second depth and the third depth are equal. For example, the second depth is at least 0.1 μm and at most 0.5 μm. For example, the third depth is at least 0.3 μm and at most 3 μm.

[0025] For example, the first main surface on the first side of the power semiconductor device is flat and extends parallel to the lateral direction. This means that the top surface of the well region, the top surface of the first doped region, and the top surface of the second doped region are all part of the first main surface.

[0026] According to an embodiment of the power semiconductor device, the first doped region and the second doped region are separated from the drift layer by a well region. The first doped region and the second doped region are illustratively incorporated into the well region. This means that the outer surfaces of the first doped region and the second doped region are covered by the well region, except for the top surfaces of the first doped region and the second doped region.

[0027] For example, the top surfaces of the first doped region and the second doped region can be electrically conductively externally contacted in at least some regions.

[0028] According to an embodiment of the power semiconductor device, the second doped region is completely surrounded laterally by the first doped region.

[0029] When viewed from above, the first doped region has a polygonal shape, such as a triangular, rectangular, or hexagonal shape, along the vertical direction. For example, the periphery of the first doped region has a polygonal shape in the horizontal direction. In particular, the first doped region has the same shape in the horizontal direction as the drift layer and / or well region, but is smaller in size.

[0030] Illustratively, the periphery of the drift layer completely surrounds the periphery of the well region in the lateral direction, e.g., the periphery of the well region completely surrounds the periphery of the first doped region in the lateral direction.

[0031] The term "the second doped region is completely surrounded laterally by the first doped region" means here and below, for example, that the second doped region is integrated into the first doped region. This means that the outer surfaces, in particular all side surfaces, of the second doped region are at least partially covered by the first doped region, except for the top and bottom surfaces of the second doped region. In particular, the side surfaces of the second doped region are at least partially in direct and immediate contact with the first doped region.

[0032] According to an embodiment of the power semiconductor device, the second doped region comprises at least two portions that are laterally separated from one another by the first doped region. In particular, each portion is completely surrounded laterally by the first doped region, which here and below means, for example, that each portion is integrated into the first doped region. This means that the outer surface of each portion, in particular all side surfaces, except for the top and bottom surfaces of each portion, are at least partially covered by the first doped region.

[0033] Illustratively, the distance between immediately adjacent portions is at least 0.1 μm and at most 1 μm. Illustratively, the distance is defined between opposing sides of immediately adjacent portions.

[0034] This means that, for example, the power semiconductor device is a three-dimensional (3D) SiC MISFET, in particular a 3D SiC MOSFET.

[0035] Such a second doped region having two portions spaced apart from each other via the first doped region leads to superior performance of such a power semiconductor device: reductions in both peak drain current density and maximum junction temperature can be realized.

[0036] Advantageously, such discontinuities restrict the current path to a narrow, high-resistivity region, which is very effective at higher junction temperatures, significantly reducing junction temperatures and improving the reliability of oxides and packaging materials.

[0037] The source region of such a power semiconductor device advantageously features a first region having discontinuous portions, each illustratively having a p+ implant profile, thereby improving the tradeoff between conduction losses and short-circuit withstand time.

[0038] According to a further embodiment of the power semiconductor device, the first doped region comprises at least two zones: a first zone and a fourth zone.

[0039] According to a further embodiment of the power semiconductor device, the second doped region is completely surrounded in the laterally direction by the first zone, and illustratively the periphery of the first zone in the laterally direction is formed by the periphery of the first doped region.

[0040] According to a further embodiment of the power semiconductor device, the fourth zone is arranged in a central region of the power semiconductor device in the lateral direction. In particular, the fourth zone is arranged in a region of a high point of symmetry, where all symmetry axes intersect each other in the lateral direction. This means that the fourth zone is completely surrounded laterally by the first zone. Furthermore, the fourth zone is illustratively arranged between laterally adjacent parts.

[0041] According to a further embodiment of the power semiconductor device, the maximum doping concentration of the first zone is different from the maximum doping concentration of the fourth zone, for example, the maximum doping concentration of the first zone is less than the maximum doping concentration of the fourth zone, or vice versa, for example, the maximum doping concentration of the first zone is at least one or two orders of magnitude less than the maximum doping concentration of the fourth zone, or vice versa.

[0042] In particular, the second doping region must be high enough for the formation of a sufficiently good ohmic contact to a contact metal layer, for example a top metal layer.

[0043] According to a further embodiment of the power semiconductor device, the second doped region comprises further portions, illustratively spaced laterally from the respective portions by the first doped region.

[0044] According to a further embodiment of the power semiconductor device, the further portion is arranged in a central region of the power semiconductor device in the lateral direction.

[0045] According to a further embodiment of the power semiconductor device, the further portion is completely surrounded laterally by the fourth zone.

[0046] When viewed from above, the further portion has a polygonal shape, such as a triangular, rectangular, or hexagonal shape, in the vertical direction. For example, the periphery of the further portion has a polygonal shape in the horizontal direction. In particular, the further portion has the same shape as the drift layer and / or well region and is smaller in size.

[0047] Furthermore, when viewed from above, the fourth zone has a polygonal shape, such as a triangular, rectangular, or hexagonal shape, in the vertical direction. For example, the periphery of the fourth zone has a polygonal shape in the horizontal direction. In particular, the fourth zone has the same shape in the horizontal direction as the drift layer and / or well region, but is smaller in size.

[0048] Illustratively, the periphery of the fourth zone completely surrounds the periphery of the further portion in the transverse direction. According to a further embodiment of the power semiconductor device, the portions are arranged at grid points of a grid, which grid is exemplarily a polygonal grid, such as a triangular grid, a square grid or a hexagonal grid.

[0049] According to a further embodiment of the power semiconductor device, the grid points are connected by grid lines of the grid and the portions extend at least partially along the grid lines, in particular at least some regions of the grid lines are free of the portions, e.g., the regions of the grid lines are free of the portions and the portions are laterally spaced apart from one another by a first region.

[0050] The grid, grid points and grid lines are merely imaginary in nature. According to a further embodiment of the power semiconductor device, the grid is a square grid or a hexagonal grid. The shape of the grid corresponds to, for example, the shape, particularly a common shape, of the drift layer, well region, first region, and / or second region. In particular, the grid is a regular grid.

[0051] According to a further embodiment of the power semiconductor device, each of the portions is arranged at at least one grid point.

[0052] According to a further embodiment of the power semiconductor device, each of the portions comprises at least two branches, and illustratively each of the portions extends along these branches, i.e. each of the portions is formed from these branches.

[0053] According to a further embodiment of the power semiconductor device, the at least two branches extend at least partially along at least two of the grid lines of the respective grid point.

[0054] According to a further embodiment of the power semiconductor device, the first doped region comprises at least four zones: a first zone, a fourth zone, a second zone, and a third zone.

[0055] According to a further embodiment of the power semiconductor device, the second doped region is completely surrounded laterally by the first zone.

[0056] According to a further embodiment of the power semiconductor device, the second zone is completely surrounded laterally by the first zone.

[0057] When viewed from above, the second zone has a polygonal shape, such as a triangular, rectangular, or hexagonal shape, along the vertical direction. For example, the periphery of the second zone has a polygonal shape in the horizontal direction. In particular, the second zone has the same shape in the horizontal direction as the first zone, but is smaller in size.

[0058] Illustratively, the perimeter of the second zone completely surrounds the perimeter of the second doped region in the lateral direction, and the perimeter of the first zone completely surrounds the perimeter of the second zone in the lateral direction.

[0059] According to a further embodiment of the power semiconductor device, the third zone is arranged laterally between the end regions of the opposing portions, in particular, the third zone is arranged laterally between the fourth zone and the second zone.

[0060] Illustratively, the maximum doping concentrations of all zones are equal to one another within manufacturing tolerance limits.

[0061] Illustratively, the maximum doping concentrations of at least two of the zones differ from one another, for example, the maximum doping concentrations of all the zones differ from one another, for example, the maximum doping concentrations of the different zones differ from one another by at most 90%, for example, by about 80%.

[0062] Illustratively, the maximum doping concentrations of the second and third zones are equal to each other, and the maximum doping concentrations of the first and fourth zones are equal to each other, but the maximum doping concentrations of the second and third zones are less than the maximum doping concentrations of the first and fourth zones.

[0063] Illustratively, the maximum doping concentrations of the first, second, and fourth zones are equal to each other, and for example, the maximum doping concentration of the third zone is less than the maximum doping concentrations of the first, second, and fourth zones.

[0064] For example, the maximum doping concentrations of the first and fourth zones are equal to each other. Illustratively, the maximum doping concentration of the third zone is less than the maximum doping concentration of the second zone. Illustratively, the maximum doping concentration of the second zone is less than the maximum doping concentrations of the first and fourth zones.

[0065] Illustratively, the maximum doping concentrations of the first, second, and fourth zones are equal to one another. Furthermore, the maximum doping concentration of each of the first, second, and fourth zones is, for example, about 20% of the maximum doping concentration of the third zone. For example, the maximum doping concentration of the third zone may be about 1·10 in such a configuration. 20 cm -3 Such a doping configuration advantageously exhibits an improved tradeoff between conduction loss and short circuit withstand time.

[0066] In particular, the presence of the lightly doped zone allows for better utilization of the electrostatic potential effect, i.e., the increased depletion region expansion, which can pinch off the total current during short-circuit operation. Furthermore, the presence of the lightly doped zone advantageously does not affect the threshold voltage of the power semiconductor device.

[0067] According to a further embodiment of the power semiconductor device, the maximum doping concentration of the further portion is different from the maximum doping concentration of the portion, e.g. the maximum doping concentration of the portion is less than the maximum doping concentration of the further portion or vice versa.

[0068] For example, the maximum doping concentration of the further portion is at least one or two orders of magnitude greater than the maximum doping concentration of the portion, or vice versa.

[0069] According to a further embodiment, a power semiconductor device comprises a semiconductor body having a first main surface on a first side and a second main surface on a second side opposite the first side.

[0070] According to a further embodiment, a power semiconductor device comprises a gate insulator disposed on the first major surface.

[0071] The gate insulator comprises an electrically insulating material, such as an electrically insulating oxide or high-k dielectric. SiO2 has a dielectric constant of 3.9, and "high-k" dielectric materials are said to have a dielectric constant k>3.9.

[0072] Advantageously, by predetermining the lateral overlap area of ​​the gate insulator and the first region, in particular the first zone, the resistance of the first region, in particular the first zone, can be predetermined, that is, the resistance of the first region, in particular the first zone, is predetermined depending on the lateral overlap area of ​​the gate insulator and the first region, in particular the first zone.

[0073] According to a further embodiment, a power semiconductor device comprises a gate electrode spaced apart from a semiconductor body by a gate insulator.

[0074] The gate electrode includes or consists of a metal. For example, the gate contact is electrically conductively externally contactable in at least some areas. Furthermore, the gate contact is illustratively integrated into the gate insulator. This means that the gate insulator covers all outer surfaces of the gate contact except for the area intended for external contact.

[0075] According to a further embodiment of the power semiconductor device, the semiconductor body comprises a drift layer, a well region, a first doped region, and a second doped region.

[0076] According to a further embodiment, the power semiconductor device includes an upper metal layer disposed on the first main surface. For example, the upper metal layer is provided on the source region, i.e., the first doped region and the second doped region on the first side. For example, the upper metal layer is provided on the first main surface.

[0077] According to a further embodiment of the power semiconductor device, the upper metal layer at least partially overlaps the first doped region and the second doped region laterally, and illustratively is in direct contact with the first doped region and the second doped region on their upper surfaces.

[0078] According to a further embodiment of the power semiconductor device, the upper metal layer at least partially overlaps laterally with at least two or all of the portions, or the upper metal layer completely overlaps laterally with the further portion.

[0079] If the top metal layer completely overlaps the further portions laterally, e.g., all portions are free of the top metal layer, then the portions are floating portions. Otherwise, if the top metal layer overlaps at least some of the portions, then these portions are, e.g., grounded portions.

[0080] Illustratively, the top metal layer at least partially overlaps the fourth zone laterally, e.g., the first zone, the second zone, and the third zone do not laterally overlap the top metal layer.

[0081] In particular, the upper metal layer laterally overlaps the fourth zone to a significant extent, where "to a significant extent" means that the upper metal layer covers at least 50% or at least 70% of the top surface of the fourth zone.

[0082] According to a further embodiment, the power semiconductor device includes a substrate layer. Illustratively, the substrate layer of a first conductivity type is disposed on a second side of the drift layer opposite the first side. For example, the maximum doping concentration of the drift layer is at least two orders of magnitude higher, illustratively five times higher, than the maximum doping concentration of the drift layer.

[0083] According to a further embodiment, the power semiconductor device includes a rear metal layer disposed on the second main surface. For example, the rear metal layer is provided on the second main surface of the drift layer on the second side. For example, the rear metal layer completely covers the second main surface.

[0084] The upper metal layer and / or the rear metal layer may, for example, comprise or consist of a metal, for example, the upper metal layer and / or the rear metal layer may be an electrode that can be electrically conductively contacted externally.

[0085] According to a further embodiment of the power semiconductor device, the substrate layer is arranged between the back metal layer and the drift layer.

[0086] Further embodiments relate to methods for manufacturing power semiconductor devices, in particular the power semiconductor devices described herein above. Accordingly, features described in relation to the method are also applicable to the power semiconductor device and vice versa.

[0087] According to one embodiment of the method, a drift layer of a first conductivity type is provided. In particular, the drift layer is an epitaxial semiconductor layer. For example, the substrate of the drift layer is epitaxially grown. The substrate is further doped with a first dopant.

[0088] According to an embodiment of the method, a well region of a second conductivity type different from the first conductivity type is formed on the first side. Exemplarily, the well region is formed in the drift layer, i.e., the substrate, by a doping process. For example, a second dopant is introduced into the drift layer. Exemplarily, the well region is generated due to the introduction of the second dopant into the drift layer.

[0089] According to an embodiment of the method, a first doped region of a first conductivity type and a second doped region of a second conductivity type are fabricated on the first side surface. Illustratively, a source region comprising the first doped region and the second doped region is fabricated in the drift layer by a further doping process.

[0090] For example, the source region is created by introducing at least one of an additional first dopant or an additional second dopant into the drift layer. The term "at least one of an additional first dopant or an additional second dopant is introduced" is intended to encompass cases where an additional first dopant is introduced, or an additional second dopant is introduced, or an additional first dopant and an additional second dopant are introduced.

[0091] The first dopant, the further first dopant, the second dopant, and / or the further second dopant are incorporated into the drift layer by, for example, an ion implantation process.

[0092] According to an embodiment of the method, a mask is used to generate the at least one first doped region such that an interface between the at least one first doped region and the at least one second doped region is established, in particular the mask is an implantation mask configured to limit an implantation area of ​​the further first dopant.

[0093] According to a further embodiment of the method, a further mask is used to generate the at least one second doped region, in particular a further implantation mask configured to limit an implantation region of the further second dopant.

[0094] In such a method, no process modifications are required compared to fabricating conventional SiC MISFETs, and advantageously, no extra masks are required to create the second doped region portion. Thus, advantageously, only the implantation masks for the first and second dopants need to be redrawn.

[0095] According to a further embodiment of the method, a self-aligned process is used to generate the at least one second doped region, which allows the interface to be particularly easily and precisely defined.

[0096] The accompanying figures are included to provide a further understanding. In the figures, elements of the same structure and / or function may be referred to by the same reference numerals. It should be understood that the embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale. [Brief explanation of the drawings]

[0097] [Figure 1] 1 shows an exemplary schematic diagram of a power semiconductor device according to the prior art; [Figure 2] 1 shows an exemplary schematic diagram of a power semiconductor device according to the prior art; [Figure 3] 1 shows an exemplary schematic diagram of a power semiconductor device according to the prior art; [Figure 4] 1 shows an exemplary schematic diagram of a power semiconductor device according to the prior art; [Figure 5] 1 illustrates a schematic top view of a power semiconductor device according to an exemplary embodiment; [Figure 6] 1 illustrates a schematic top view of a power semiconductor device according to an exemplary embodiment; [Figure 7] 1 illustrates a schematic top view of a power semiconductor device according to an exemplary embodiment; [Figure 8] 1 illustrates a schematic top view of a power semiconductor device according to an exemplary embodiment; [Figure 9] 1 illustrates a schematic top view of a power semiconductor device according to an exemplary embodiment; [Figure 10] 1 illustrates a schematic top view of a power semiconductor device according to an exemplary embodiment; [Figure 11] 1 illustrates a schematic top view of a power semiconductor device according to an exemplary embodiment; [Figure 12] 1 illustrates a schematic top view of a power semiconductor device according to an exemplary embodiment; [Figure 13] 1 illustrates a schematic top view of a power semiconductor device according to an exemplary embodiment; [Figure 14] 1 illustrates, among other things, an exemplary diagram of simulated performance data for a power semiconductor device in accordance with an exemplary embodiment. [Figure 15] 1 illustrates, among other things, an exemplary diagram of simulated performance data for a power semiconductor device in accordance with an exemplary embodiment. [Figure 16] 1 illustrates, among other things, an exemplary diagram of simulated performance data for a power semiconductor device in accordance with an exemplary embodiment. [Figure 17] 1 illustrates, among other things, an exemplary diagram of simulated performance data for a power semiconductor device in accordance with an exemplary embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0098] 1 and 2 comprises a rear metal layer 9, a substrate layer 10, and a drift layer 2, which are stacked vertically on top of each other in the order shown. Drift layer 2, and in particular substrate layer 10, comprises a semiconductor material formed from SiC.

[0099] The prior art power semiconductor device further comprises two well regions 3 of a second conductivity type different from the first conductivity type on a first side of the drift layer 2. The well regions 3 are laterally spaced apart from each other by the drift layer 2.

[0100] For example, the first conductivity type is n-type conductivity, and the second conductivity type is p-type conductivity. The well region 3s is created in the drift layer 2, for example, by a doping process. For example, a second dopant is introduced into the drift layer 2, thereby creating the well region 3 to a first depth.

[0101] Each well region 3 comprises a first doped region 4 of a first conductivity type and a second doped region 5 of a second conductivity type.

[0102] The top surface of the well region 3, the top surface of the first doped region 4, the top surface of the second doped region 5 and the top surface of the drift layer 2 are arranged in a common plane, i.e., in a first major surface.

[0103] The upper metal layer 8 is disposed on the first major surface and covers, for example, completely, an upper surface of the second doped region 5 and at least a part of an upper surface of the first doped region 4. Furthermore, a gate insulator 11 is disposed on an upper surface between the upper metal layers 8 disposed in different well regions 3. This means that the gate insulator 11 covers, for example, completely, an upper surface of the drift layer 2, an upper surface of the well region 3, for example, completely, and at least a part of an upper surface of the first doped region 4. A gate electrode 12 is disposed on the gate insulator 11 on a first side facing away from the drift layer 2. The gate electrode 12 laterally overlaps, for example, completely, the drift layer 2 and at least partially overlaps the well region 3.

[0104] 3 is a top view along a vertical direction that is perpendicular to the lateral direction, which extends along the main extension plane of the drift layer 2.

[0105] The top metal layer 8 is depicted as a hatched area (line) in FIG. 3 and the following FIGS. 4-13, and the gate insulator 11 is depicted as a shaded area (dot) in FIG. 3 and the following FIGS. 4-13.

[0106] In particular, the prior art power semiconductor device according to FIG. 3 has a standard stripe topology, in which the well region 3 and the first doped region 4 and the second doped region 5 extend in the main extension direction.

[0107] The prior art power semiconductor devices according to Figures 4 and 5 are top views along the vertical direction, respectively. Compared with Figure 3, the prior art power semiconductor device according to Figure 4 has an array-based cell topology, and the prior art power semiconductor device according to Figure 5 has a hexagonal cell topology.

[0108] 6 has a drift layer 2, a well region 3, a first doped region 4, and a second doped region 5. According to this exemplary embodiment, the second doped region 5 comprises at least two portions 6, a first portion and a second portion, which are laterally spaced apart from each other by the first doped region 4.

[0109] The periphery of the drift layer 2, the periphery of the well region 3, and the periphery of the first doped region 4 each have a rectangular shape in the lateral direction. Furthermore, all axes of symmetry, such as all mirror axes, of the lateral shapes of the drift layer 2, the well region 3, and the first region are the same.

[0110] The outer periphery of the drift layer 2 completely surrounds the outer periphery of the well region 3 in the lateral direction. The outer periphery of the well region 3 completely surrounds the outer periphery of the first doped region 4 in the lateral direction.

[0111] The first doped region 4 comprises a first zone N1, a second zone N2, two third zones N3, and a fourth zone N4. The periphery of the first zone N1 is represented by the periphery of the first doped region 4. Furthermore, the periphery of the second zone N2 also has a rectangular shape in the transverse direction. The periphery of the first zone N1 completely surrounds the periphery of the second zone N2 in the transverse direction. Furthermore, the periphery of the second zone N2 completely surrounds the first doped region 4, as well as the third zone N3 and the fourth zone N4 in the transverse direction.

[0112] The first and second portions of portion 6 of second doped region 5 are located at grid points 13 of a grid, which is a rectangular grid of grid points 13 of size 2x2. The grid points 13 are connected by grid lines of the grid. Grid points 13 and grid lines 14 are of a virtual nature and are depicted in FIG. 6 merely for better understanding.

[0113] Each portion 6 is located at two immediately adjacent grid points 13. These two immediately adjacent grid points 13 are connected by one of the grid lines 14 along which the respective portion 6 extends completely, forming a branch of the portion 6.

[0114] Furthermore, each of the portions 6 comprises two further branches extending perpendicularly to the branch connecting two directly adjacent grid points 13, in that each of the two further branches extends partly along a grid line connecting two directly adjacent grid points 13 of different portions 6. The first doped region 4, in particular the third zone N3, is arranged laterally between the directly adjacent further branches of the directly adjacent different portions 6.

[0115] The fourth zone N4 is arranged in the central region of the power semiconductor device 1 in the lateral direction, in particular in the region of the high symmetry point, where the axes of symmetry of the shapes all intersect each other in the lateral direction, that is, the fourth zone N4 is arranged between directly opposite branches of directly adjacent different parts 6.

[0116] The upper metal layer 8 extends between the directly opposing branches of the directly adjacent different portions 6. The upper metal layer 8 covers the directly opposing branches of the directly adjacent different portions 6 as well as the fourth region.

[0117] In contrast to the power semiconductor device 1 of FIG. 6, the power semiconductor device 1 according to the exemplary embodiment of FIG. 7 has a second doped region 5 comprising four portions 6. Each portion 6 is arranged at one grid point 13. Furthermore, each portion 6 comprises two branches, which extend partially along two grid lines 14 of the corresponding grid point 13. Opposite branches of different directly adjacent portions 6 are laterally spaced apart from each other. This means that the first doped region 4, in particular the third zone N3, is arranged between two directly adjacent branches of laterally different directly adjacent portions 6.

[0118] 7 has four upper metal layers 8. Each upper metal layer 8 completely covers one of the portions 6 laterally. Each upper metal layer 8 has a laterally rectangular shape such that each metal layer 8 also laterally covers the portion 6 of the fourth zone N4.

[0119] The power semiconductor device 1 according to the exemplary embodiment of Figure 8 has, in contrast to the power semiconductor device 1 of Figure 6, an additional portion 7 of the power semiconductor device. The additional portion 7 is arranged in a central region of the power semiconductor device 1 in the lateral direction.

[0120] The further portion 7 is completely surrounded laterally by the fourth zone N4, such that the further portion 7 is spaced apart from the respective portion 6 by the first doped region 4, in particular by the fourth zone N4.

[0121] The upper metal layer 8 according to Figure 8 does not cover the branches of the portion 6, in contrast to Figure 6. In Figure 8, the upper metal layer 8 completely covers the further portion 7 laterally and partially covers the fourth zone N4 laterally.

[0122] The power semiconductor device 1 according to the exemplary embodiment of FIG. 9, in contrast to the power semiconductor device 1 of FIG. 7, has a further portion 7 and an upper metal layer 8 similar to FIG.

[0123] In contrast to the power semiconductor device 1 of FIG. 9, the power semiconductor device 1 according to the exemplary embodiment of FIG. 10 has eight portions 6. The grid has nine grid points 13 evenly distributed along the rows and columns, i.e., in a 3×3 matrix. A further portion 7 is arranged at the central grid point 13. Each portion 6 is arranged at one of the grid points arranged around the central grid point 13.

[0124] In contrast to the power semiconductor device 1 of FIG. 9, the power semiconductor device 1 according to the exemplary embodiment of FIG. 11 has portions 6, each of which has a triangular shape in the transverse direction. Each triangular shape in the transverse direction is in particular a right-angled triangle. The orthogonal angle of each right-angled triangle faces one corner of the shape of the first doped region 4.

[0125] Compared to the power semiconductor device 1 of FIG. 8, the power semiconductor device 1 according to the exemplary embodiment of FIG. 12 has a drift layer 2, a well region 3, a first doped region 4, and a second doped region 5, each of which has a hexagonal outer surface.

[0126] Each portion 6 is arranged on three grid points 13 of a hexagonal grid, i.e. a grid having a size of six grid points 13 .

[0127] Compared to the power semiconductor device 1 of FIG. 9, the power semiconductor device 1 according to the exemplary embodiment of FIG. 13 has a drift layer 2, a well region 3, a first doped region 4, and a second doped region 5, each of which has a hexagonal outer surface.

[0128] Due to the hexagonal shape, the branches have angles with each other that are different from right angles. Ampere (A / cm 2 ) units of drain current density I DS is depicted on the y-axis of the diagrams according to Figures 14, 15 and 16. Furthermore, the drain voltage V D is plotted on the x-axis of Figure 14. The top three IV curves correspond to prior art SiC MOSFETs.

[0129] The two lowest I-V curves correspond to a power semiconductor device 1 that is a SiC MISFET according to an exemplary embodiment, in particular the power semiconductor device 1 according to FIG. 7. The upper curve of the two lowest I-V curves corresponds to a distance between directly adjacent portions 6 of 0.4 μm. The lower curve of the two lowest I-V curves corresponds to a distance between directly adjacent portions 6 of 0.6 μm.

[0130] The values ​​in the diagram in Figure 14 are for a gate-source voltage V of 15V. GS and simulated at a temperature of 300K.

[0131] Gate voltage V in volts (V) G are plotted on the x-axis of Figure 15. The top I-V curve corresponds to the prior art, e.g., a SiC MOSFET according to Figure 3. The bottom I-V curve corresponds to a power semiconductor device 1 according to Figure 7 with a distance between directly adjacent portions 6 of 0.6 μm.

[0132] Time t in microseconds (μs) is plotted on the x-axis of Figure 16. The top I-V curve corresponds to a SiC MOSFET according to the prior art, e.g., Figure 3. The two bottom I-V curves correspond to the power semiconductor device 1 already described in connection with Figure 14.

[0133] The maximum junction temperature T in Kelvin (K) is plotted on the y-axis of the diagram according to Fig. 17. Furthermore, the time t in microseconds (µs) is plotted on the x-axis of Fig. 17. The top I-V curve corresponds to the prior art, e.g., a SiC MOSFET according to Fig. 3. The two bottom I-V curves correspond to the power semiconductor device 1 already described in connection with Fig. 14.

[0134] The difference D1 shown in FIG. 14 is about 7%, and the difference D2 is about 12%. Furthermore, the difference D3 shown in FIG. 16 is about 52%, and the difference D4 shown in FIG. 17 is about 25%. As can be observed, the presence of the discontinuity 6 restricts the current path to a narrow high-resistance region, which is very effective at higher junction temperatures. This makes it possible to significantly reduce the junction temperature and improve the reliability of the oxide and packaging material. [Explanation of symbols]

[0135] Reference sign 1. Power semiconductor devices 2 Drift layer 3. Well Area 4. First doped region 5 Second doped region 6 parts 7 Further Parts 8 Upper metal layer 9 Rear metal layer 10 substrate layers 11 Gate insulator 12 gate electrode 13 grid points 14 Grid Lines N1 1st Zone N2 Second Zone N3 Third Zone N4 4th Zone I DS Drain Current Density V D Drain Voltage V G Gate voltage T temperature t time D1~D4 difference

Claims

1. A power semiconductor device (1), a drift layer (2) of the first conductivity type, a well region (3) of a second conductivity type different from said first conductivity type; a first doped region (4) of said first conductivity type and a second doped region (5) of said second conductivity type; Equipped with - the well region (3), the first doped region (4) and the second doped region (5) are provided on a first side of the power semiconductor device (1); - the first doped region (4) and the second doped region (5) are spaced (6) from the drift layer (2) by the well region (3), - said second doped region (5) is completely surrounded laterally by said first doped region (4); - said second doped region (5) comprises at least two portions (6) laterally spaced apart (6) from one another by said first doped region (4); - said second doped region (5) comprises a further portion (7), - the further part (7) is arranged in a central region of the power semiconductor device (1) in a lateral direction, Power semiconductor device (1).

2. - said first doped region (4) comprises at least two zones: a first zone (N1) and a fourth zone (N4); - said second doped region (5) is completely surrounded laterally by said first zone (N1); - the fourth zone (N4) is arranged in a central region of the power semiconductor device (1) in a lateral direction, the maximum doping concentration of said first zone (N1) is different from the maximum doping concentration of said fourth zone (N4); A power semiconductor device (1) according to claim 1.

3. - said further portion (7) is completely surrounded laterally by said fourth zone (N4); A power semiconductor device (1) according to claims 1 and 2.

4. - said portions (6) are placed at grid points (13) of a grid, A power semiconductor device (1) according to any one of claims 1 to 3.

5. - said grid points (13) are connected by grid lines (14) of said grid, said portions (6) extending at least partly along said grid lines (14); - the grid is a square grid or the grid is a hexagonal grid, A power semiconductor device (1) according to claim 4.

6. - each of said portions (6) is located at at least one grid point, - each of said portions (6) comprises at least two branches, - said at least two branches extend at least partially along at least two of said grid lines (14) of said respective grid point; A power semiconductor device (1) according to any one of claims 4 or 5.

7. - said first doped region (4) comprises at least four zones: said first zone (N1), said fourth zone (N4), a second zone (N2) and a third zone (N3); - said second doped region (5) is completely surrounded laterally by said first zone (N1); - said second zone (N2) is completely surrounded laterally by said first zone (N1); - said third zone (N3) is arranged laterally between the end regions of said parts (6) facing each other, A power semiconductor device (1) according to any one of claims 2 to 6.

8. the maximum doping concentration of said further portion (7) is different from the maximum doping concentration of said portion (6), A power semiconductor device (1) according to any one of claims 1 to 7.

9. a semiconductor body having a first main surface on said first side and a second main surface on a second side opposite said first side; a gate insulator (11) arranged on said first major surface; a gate electrode (12) separated from said semiconductor body by said gate insulator (11); Equipped with the semiconductor body comprises the drift layer (2), the well region (3), the first doped region (4) and the second doped region (5), A power semiconductor device (1) according to any one of claims 1 to 8.

10. an upper metal layer (8) disposed on said first main surface; Furthermore, - said upper metal layer (8) at least partially overlaps laterally with said first doped region (4) and said second doped region (5); A power semiconductor device (1) according to claim 9.

11. said upper metal layer (8) at least partially laterally overlaps at least two or all of said portions (6), or said upper metal layer (8) completely laterally overlaps said further portion (7); A power semiconductor device (1) according to claim 10.

12. a substrate layer (10), a rear metal layer (9) disposed on said second main face; Furthermore, - said substrate layer (10) is arranged between said rear metal layer (9) and said drift layer (2); A power semiconductor device (1) according to any one of claims 9 to 11.

13. demonstrating a drift layer (1) of a first conductivity type; - making at least one well region (2) of a second conductivity type different from said first conductivity type on a first side; - creating a first doped region (3) of said first conductivity type and a second doped region (4) of said second conductivity type on said first side; Including, a mask is used to generate said at least one first doped region (3) so that an interface between said at least one first doped region (3) and said at least one second doped region (4) is established; A method for manufacturing a power semiconductor device (20).

14. a further mask is used to generate said at least one second doped region (4), or a self-aligned process is used to generate said at least one second doped region (4); A method for manufacturing a power semiconductor device (20) according to claim 13.

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