Circuit board and semiconductor package including same

Abstract

A semiconductor package according to an embodiment includes an insulating layer, an electrode portion disposed on the insulating layer, and a protective layer disposed on the electrode portion, wherein the protective layer includes a first region disposed around an upper surface of the protective layer and a second region excluding the first region, and a step is provided between the upper surface of the first region and the upper surface of the second region.

Description

[Technical Field]

[0001] The embodiments relate to a circuit board and a semiconductor package including the same. [Background technology]

[0002] As the performance of electrical / electronic products continues to improve, technologies for mounting more packages onto a board with limited size are being proposed and researched. However, because a typical package is based on mounting a single semiconductor chip, there is a limit to how much performance can be achieved.

[0003] A typical package substrate has a configuration in which a processor package in which a processor chip is disposed and a memory package in which a memory chip is mounted are connected as a single unit. This package substrate has the advantages of reducing the chip mounting area by manufacturing the processor chip and the memory chip in a single integrated package and enabling high-speed signals to be transmitted through a short path.

[0004] Due to these advantages, the above-mentioned package substrate is widely used in mobile devices and the like.

[0005] On the other hand, recently, the size of packages has increased due to the high specifications of electronic devices such as mobile devices and the adoption of HBM (High Bandwidth Memory), and as a result, package substrates including interposers are mainly used.

[0006] That is, the semiconductor package includes a package substrate, a semiconductor device disposed on the package substrate, and a memory substrate disposed on the package substrate. The memory substrate may be connected via a separate interposer, or alternatively, the memory substrate may be directly coupled to the package substrate.

[0007] The package substrate also has a mounting pad connected to the semiconductor element and a first insulating layer (for example, a solder resist or a protective layer) having an opening vertically overlapping an upper surface of the mounting pad.

[0008] Meanwhile, the number of terminals on semiconductor devices is gradually increasing due to recent trends such as 5G, Internet of Things (IOT), improved image quality, and increased communication speed, etc. Accordingly, the number of mounting pads included in the package substrate and the number of openings in the first insulating layer are also increasing.

[0009] However, there is a problem that the minimum size of the opening that can be formed in the first insulating layer is limited, and therefore, it is not possible to arrange all of the mounting pads connected to the terminals of the semiconductor device within the limited space, which results in a decrease in circuit integration density and an increase in overall size in conventional semiconductor packages.

[0010] Therefore, there is a need for a semiconductor package including a first insulating layer with a new structure that can reduce the size of the semiconductor package and arrange all mounting pads connected to the terminals of the semiconductor element in a limited space.

[0011] (Patent Document 1) Korean Patent Publication No. 10-2016-0138753 Summary of the Invention [Problem to be solved by the invention]

[0012] The embodiments provide a circuit board with a new structure and a semiconductor package including the same.

[0013] Furthermore, the embodiments provide a circuit board capable of stably protecting conductive joints and a semiconductor package including the same.

[0014] Furthermore, the embodiments provide a circuit board capable of preventing the diffusion of connection members and a semiconductor package including the same.

[0015] Furthermore, the embodiments provide a circuit board capable of improving the molding processability of a semiconductor device and a semiconductor package including the same.

[0016] Furthermore, the embodiments provide a circuit board including a protective layer with a new open structure and a semiconductor package including the same.

[0017] Furthermore, the embodiments provide a circuit board capable of improving circuit integration and a semiconductor package including the same.

[0018] Furthermore, the embodiments provide a circuit board and a semiconductor package including the same with improved physical reliability and electrical reliability.

[0019] Furthermore, the embodiments provide a circuit board that can be slimmed down and made compact, and a semiconductor package including the same.

[0020] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the technical field to which the proposed embodiments pertain from the following description. [Means for solving the problem]

[0021] A circuit board according to an embodiment includes an insulating layer, an electrode portion disposed on the insulating layer, a protective layer disposed on the electrode portion, and a semiconductor element disposed on the protective layer, wherein the protective layer includes a first region that vertically overlaps the semiconductor element and a second region that is disposed outside the first region and does not vertically overlap the semiconductor element, and a step is provided between the top surface of the first region and the top surface of the second region.

[0022] Furthermore, the top surface of the first region is located lower than the top surface of the second region.

[0023] The second region is provided along the circumferential direction of the upper surface of the protective layer, and the first region is provided inside the second region.

[0024] Furthermore, the upper surface of the second region of the protective layer is located higher than the lower surface of the semiconductor element and lower than the upper surface of the semiconductor element.

[0025] The protective layer also includes a first protective layer disposed on the insulating layer and including a through hole that vertically overlaps the semiconductor element, and a second protective layer disposed inside the through hole of the first protective layer and spaced apart from the first protective layer.

[0026] The first protective layer includes the first region and the second region, and an upper surface of the second protective layer is disposed on the same plane as an upper surface of the first region of the first protective layer.

[0027] The first protective layer includes the first region and the second region, and the top surface of the second protective layer is located lower than the top surfaces of the first and second regions of the first protective layer.

[0028] The semiconductor package further includes a conductive coupling portion that penetrates at least a portion of the second region of the first protective layer, the conductive coupling portion being disposed on a first electrode of the electrode portion that does not vertically overlap with the semiconductor element, the second region of the first protective layer including a first opening that vertically overlaps with the conductive coupling portion, and the second region of the first protective layer being configured to entirely surround a side surface of the conductive coupling portion.

[0029] Furthermore, the upper surface of the conductive coupling portion is positioned higher than the lower surface of the semiconductor element and lower than the upper surface of the semiconductor element.

[0030] The inner side surface of the through hole of the first protective layer includes a protruding surface that protrudes toward the second protective layer.

[0031] The outer surface of the second protective layer includes a protruding surface that protrudes toward the first protective layer.

[0032] Furthermore, the horizontal distance between the inner surface of the through hole of the first protective layer and the outer surface of the second protective layer includes different intervals along the inner surface of the through hole.

[0033] Furthermore, a separation region is formed between the inner surface of the through hole of the first protective layer and the outer surface of the second protective layer, the separation region vertically overlapping the through hole but not vertically overlapping the second protective layer.

[0034] The semiconductor device also includes first and second semiconductor devices spaced apart in a horizontal direction.

[0035] The semiconductor package further includes connecting members embedded in the insulating layer and vertically overlapping portions of the first semiconductor chip and the second semiconductor chip, respectively.

[0036] The semiconductor package further includes an external substrate disposed on the conductive coupling portion.

[0037] The semiconductor package further includes a molding layer disposed on the semiconductor element, the lower surface of the molding layer having a step corresponding to the step of the first and second regions of the protective layer. [Effects of the Invention]

[0038] The embodiment can simplify the manufacturing process of the semiconductor package, can improve the product yield, and can improve the physical reliability and / or electrical reliability of the semiconductor package.

[0039] That is, the semiconductor package of the embodiment includes an insulating layer and a protective layer disposed on the insulating layer. The upper surface of the protective layer has a step. Specifically, the protective layer includes a first region vertically overlapping a semiconductor device and a second region excluding the first region, and the upper surfaces of the first region and the second region have a step. Preferably, the upper surface of the first region is located lower than the upper surface of the second region. Therefore, the step between the first region and the second region of the protective layer of the embodiment can function as a dam during a process of applying a connecting portion, such as solder, to mount the semiconductor device. For example, the step between the first region and the second region of the protective layer can guide the seating position so that the connecting portion moves to a specified position. This allows the connecting portion to be seated in an accurate position, thereby simplifying the manufacturing process. Furthermore, the step between the first region and the second region of the protective layer of the embodiment can prevent the connecting portion from moving outside the semiconductor package, thereby reducing product manufacturing costs. Furthermore, the embodiment can facilitate the manufacturing process of semiconductor packages, and can further improve product yield.

[0040] In addition, the second region of the protective layer of the embodiment is provided to surround the periphery of the conductive coupling portion. Preferably, the second region of the protective layer of the embodiment is provided to entirely surround the side surface of the conductive coupling portion. This eliminates the need to form a separate molding member to surround the side surface of the conductive coupling portion, thereby simplifying the manufacturing process.

[0041] Furthermore, in the embodiment, the side surfaces of the conductive coupling part are entirely covered with a protective layer, which minimizes stress acting on the conductive coupling part, thereby resolving the reliability issue of cracks occurring at the interface between the conductive coupling part and the electrode part due to stress concentration on the conductive coupling part.

[0042] For example, in the prior art, a portion of a side surface of a conductive coupling part is covered with a protective layer, and the remaining portion is covered with a molding member. The protective layer and the molding member contain different insulating materials, and therefore have different thermal expansion coefficients. Therefore, one of the protective layer and the molding member may expand or contract more than the other. Therefore, different stresses may act on the side of the conductive coupling part that contacts the molding member and the side of the conductive coupling part that contacts the protective layer, which may reduce the physical reliability of the conductive coupling part.

[0043] According to another conventional technique, the entire side of the conductive coupling part may be in contact with the molding member. In this case, the molding member is laminated after mounting the semiconductor device on the substrate. Therefore, the entire top and side of the conductive coupling part may be exposed during the semiconductor device mounting process. Therefore, physical impact may be applied to the conductive coupling part during the semiconductor device mounting process, which may cause the conductive coupling part to peel off from the electrode part. Furthermore, foreign matter may accumulate on the top surface of the conductive coupling part during the semiconductor device mounting process, which may reduce the electrical reliability of the conductive coupling part.

[0044] In contrast, in the embodiment, a protective layer is provided to entirely surround the side surface of the conductive coupling portion, so that the expansion or contraction of the protective layer can apply uniform stress to the entire area of ​​the conductive coupling portion, thereby resolving the physical reliability issue of the conductive coupling portion peeling off from the electrode portion.

[0045] Furthermore, the embodiment can stably protect the conductive joint from impacts applied during the process of mounting a semiconductor element, thereby improving the physical reliability and / or electrical reliability of the conductive joint.

[0046] In addition, the protective layer of the embodiment includes first and second regions, a first protective layer having a through hole, and a second protective layer provided inside the through hole of the first protective layer. In this case, the first protective layer includes a protruding surface protruding inward toward the second protective layer. For example, the outer surface of the second protective layer includes a protruding surface protruding toward the first protective layer. Therefore, in the embodiment, the horizontal separation distance or spacing between the inner surface of the through hole of the first protective layer and the outer surface of the second protective layer may include different separation distances or spacings along the inner surface of the through hole. For example, the separation distance may include a first separation distance and a second separation distance. The first separation distance and the second separation distance may be different from each other. For example, the first separation distance may be greater than the second separation distance.

[0047] In this embodiment, the second electrodes and traces of the electrode units may be densely arranged in a first separation region corresponding to the first separation distance, with a density higher than that of a second separation region corresponding to the second separation distance. For example, the spacing between the second electrodes and / or traces arranged in the first separation region may be smaller than the spacing between the second electrodes and / or traces arranged in the second separation region. This means that the density of the electrode units in the first separation region is higher than the density of the electrode units in the second separation region.

[0048] In this case, the second electrodes and traces can be arranged with the same integration density in the first and second separation regions, but in this case, the distance between the second electrodes to be connected to each other increases, which can lead to increased signal transmission loss. Furthermore, if the second electrodes and traces are arranged with the same integration density in the first and second separation regions, the second electrodes, which cause mutual signal interference, must be spaced farther apart, which can increase the overall area of ​​the separation region. Furthermore, if the overall area of ​​the separation region increases, the number of electrodes and traces not protected by the first and second protective layers increases, which can cause problems with physical and electrical reliability.

[0049] Alternatively, after arranging the first electrodes and traces with different integration densities in the first and second isolation regions, the isolation regions can all be configured to have the same isolation distance along the inner surface of the first protective layer. However, in this case, the area of ​​the electrodes and traces that are not covered by the first or second protective layer increases, which can cause problems such as the electrodes or traces being peeled off due to thermal stress, etc.

[0050] Therefore, in the embodiment, the separation region has different first and second separation distances along the inner surface of the first protective layer and the outer surface of the second protective layer. Therefore, the embodiment has different circuit integration levels in the separation region, thereby minimizing signal transmission loss due to a reduction in signal transmission distance and improving signal transmission characteristics. Furthermore, in the embodiment, the separation distance in a region of the separation region with a relatively low circuit integration level is made smaller than the separation distance in a region of a high circuit integration level. This minimizes reliability issues caused by traces not being covered by the first or second protective layer in a separation region with a small separation distance. This further improves the electrical and physical reliability of the semiconductor package. [Brief explanation of the drawings]

[0051] [Figure 1] 1 is a cross-sectional view showing a semiconductor package according to a first embodiment. [Figure 2] FIG. 10 is a cross-sectional view showing a semiconductor package according to a second embodiment. [Figure 3] FIG. 10 is a cross-sectional view showing a semiconductor package according to a third embodiment. [Figure 4] FIG. 2 is a plan view of a first protective layer according to the first embodiment. [Figure 5] FIG. 4 is a plan view of a second protective layer according to the embodiment. [Figure 6] FIG. 10 is a plan view showing a state in which a second protective layer is disposed in a through hole of a first protective layer according to an example. [Figure 7]FIG. 7 is a cross-sectional view of one embodiment taken along the AA' direction in FIG. 6. [Figure 8] 8 is a cross-sectional view showing a state in which a semiconductor element is arranged in the semiconductor package of FIG. 7. [Figure 9] FIG. 7 is a cross-sectional view of another embodiment taken along the AA' direction in FIG. 6. [Figure 10] FIG. 10 is a plan view of a first protective layer according to a second embodiment. [Figure 11] 11 is a cross-sectional view showing a state in which a semiconductor element is disposed in a semiconductor package including the first protective layer of FIG. 10. FIG. [Figure 12] FIG. 7 is an enlarged view of an area B in FIG. 6. [Figure 13] 2 is a plan view showing a first electrode portion provided in region A of FIG. 1. FIG. [Figure 14] 14 is a plan view showing a state in which first and second protective layers are disposed on the first electrode portion of FIG. 13. FIG. [Figure 15] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an embodiment in the order of steps. [Figure 16] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an embodiment in the order of steps. [Figure 17] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an embodiment in the order of steps. [Figure 18] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an embodiment in the order of steps. [Figure 19] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an embodiment in the order of steps. [Figure 20] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an embodiment in the order of steps. [Figure 21] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an embodiment in the order of steps. [Figure 22] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an embodiment in the order of steps. [Figure 23]1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an embodiment in the order of steps. [Figure 24] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an embodiment in the order of steps. [Figure 25] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an embodiment in the order of steps. [Figure 26] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an embodiment in the order of steps. [Figure 27] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an embodiment in the order of steps. [Figure 28] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an embodiment in the order of steps. [Figure 29] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an embodiment in the order of steps. [Figure 30] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an embodiment in the order of steps. [Figure 31] 1A to 1C are cross-sectional views for explaining a method for manufacturing a semiconductor package according to an embodiment in the order of steps. DETAILED DESCRIPTION OF THE INVENTION

[0052] Hereinafter, the embodiments disclosed herein will be described in detail with reference to the accompanying drawings. Identical or similar components are designated by the same reference numerals, regardless of their reference numerals, and redundant descriptions will be omitted. The suffixes "module" and "section" used in the following description are used solely for the convenience of drafting the specification and do not have any distinguishing meanings or functions. Furthermore, when describing the embodiments disclosed herein, if a detailed description of related publicly known technology is deemed to obscure the gist of the embodiments disclosed herein, that detailed description will be omitted. Furthermore, the accompanying drawings are intended to facilitate understanding of the embodiments disclosed herein, and the technical concepts disclosed herein should not be limited by the accompanying drawings. It should be understood that the accompanying drawings include all modifications, equivalents, and alternatives within the spirit and scope of the present invention.

[0053] Terms including ordinal numbers such as first, second, etc. may be used to describe various components, but the components are not limited by the terms. The terms are used only to distinguish one component from another.

[0054] When a component is referred to as being "coupled" or "connected" to another component, it should be understood that it may be directly coupled or connected to the other component, but that there may be other components in between. Conversely, when a component is referred to as being "directly coupled" or "directly connected" to another component, it should be understood that there are no other components in between.

[0055] The singular expression includes the plural expression unless the context clearly indicates otherwise.

[0056] In this application, the use of terms such as "comprises" or "having" is intended to specify the presence of features, numbers, steps, operations, components, parts, or combinations thereof described herein, and should be understood as not precluding the possible presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0057] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0058] -Electronic Devices-

[0059] Before describing the embodiments, an electronic device to which the semiconductor package of the embodiments can be applied will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiments. Various chips may be mounted in the semiconductor package.

[0060] The semiconductor device may include active and / or passive devices. The active device may be a semiconductor chip in the form of an integrated circuit (IC) in which hundreds to millions of devices are integrated into a single chip. The semiconductor device may be a logic chip, a memory chip, or the like. The logic chip may be a central processor (CPU), a graphics processor (GPU), or the like. For example, the logic chip may be an application processor (AP) chip including at least one of a central processor (CPU), a graphics processor (GPU), a digital signal processor, a cryptographic processor, a microprocessor, or a microcontroller, or may be an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a chipset including a specific combination of the above.

[0061] The memory chips may be stacked memories such as HBM, and may include volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, and the like.

[0062] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0063] Furthermore, the electronic device may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automobile, etc. However, it is not limited to these, and it may also be any other electronic device that processes data.

[0064] -Semiconductor Package-

[0065] A semiconductor package according to an embodiment will be described below.

[0066] FIG. 1 is a cross-sectional view showing a semiconductor package according to a first embodiment, FIG. 2 is a cross-sectional view showing a semiconductor package according to a second embodiment, and FIG. 3 is a cross-sectional view showing a semiconductor package according to a third embodiment.

[0067] The schematic structure of the semiconductor package of the embodiment will be described below with reference to FIGS.

[0068] Meanwhile, the structure of the protective layer provided in the semiconductor package will be specifically described with reference to FIG. 4 and subsequent drawings.

[0069] 1, a semiconductor package includes a substrate 100. The substrate 100 may refer to, but is not limited to, a package substrate.

[0070] The substrate 100 may provide a space in which at least one semiconductor device is mounted, or may provide a space to which at least one external substrate is coupled.

[0071] The substrate 100 may provide a space to which a first external substrate is coupled, which may refer to a main board included in an electronic device.

[0072] The substrate 100 may provide a space to which a second external substrate is coupled. The second external substrate may be an interposer. For example, the second external substrate may be an interposer that electrically connects a semiconductor device and the substrate 100. The interposer may be either an active interposer or a passive interposer.

[0073] The substrate 100 includes an insulating layer 110 .

[0074] The insulating layer 110 can include an organic material that does not include a reinforcing member, which has excellent processability and allows the substrate to be slimmed down and the electrode portion of the substrate to be miniaturized. For example, the insulating layer 110 of the substrate can be made of Ajinomoto Build-up Film (ABF), a product sold by Ajinomoto Co., Inc., or can be made of FR-4, BT (Bismaleimide Triazine), PID (Photo Imageable Dielectric resin), BT, etc.

[0075] The insulating layer 110 may be provided in multiple layers. The insulating layer 110 may be provided in an inner layer of the substrate 100. Being provided in an inner layer may mean that another insulating layer (e.g., a protective layer) may be disposed on at least one of the top and bottom of the insulating layer 110.

[0076] When the insulating layer 110 is formed of multiple layers, each of the multiple layers of the insulating layer 110 may be formed of the same insulating material, but is not limited to this, and at least one layer may be formed of an insulating material different from that of the other layers.

[0077] On the other hand, if multiple layers of the insulating layer 110 are made of the same insulating material, the interfaces between the multiple layers of the insulating layer 110 may not be easily distinguished. In this case, the distinction between the layers may be achieved by the electrode portions 120 and 130 disposed within the insulating layer 110.

[0078] The electrode units 120 and 130 include first electrode units 120 provided at the interfaces between multiple layers. The electrode units 120 and 130 also include second electrode units 130 provided between the first electrode units 120 arranged on different layers. The second electrode units 130 may be referred to as via electrodes.

[0079] The horizontal width of the first electrode unit 120 is different from the horizontal width of the second electrode unit 130. Therefore, the difference between the widths of the first electrode unit 120 and the second electrode unit 130 can be used to perform inter-layer division. Furthermore, the slope of the side surface of the first electrode unit 120 can be different from the slope of the side surface of the second electrode unit 130. Therefore, the difference between the slope of the side surface of the first electrode unit 120 and the slope of the side surface of the second electrode unit 130 can be used to perform inter-layer division.

[0080] On the other hand, even if the layers of the insulating layer 110 each contain the same insulating material, the interfaces between them can be distinct.

[0081] Through the stacked structure of the insulating layer 110, the substrate 100 of the embodiment can efficiently electrically connect at least one semiconductor device and / or a secondary substrate to the main substrate.

[0082] Meanwhile, at least one of the layers of the insulating layer 110 may include a reinforcing member. In one embodiment, the reinforcing member may be glass fiber. In another embodiment, the reinforcing member may be a glass core primer (GCP).

[0083] The reinforcing member is distinguished from the filler. For example, the reinforcing member may include a reinforcing substance extending horizontally within the insulating layer 110, which has a different meaning from inorganic fillers spaced apart from each other. For example, the horizontal length or width of the reinforcing member may be different from the horizontal length or width of the filler. For example, the reinforcing member may be arranged in the insulating layer 110 with a curved shape, such that the horizontal width of the reinforcing member may be greater than the horizontal width of the insulating layer 110.

[0084] In the embodiment, the rigidity of the substrate 100 can be improved by including a reinforcing member in at least one of the layers of the insulating layer 110. Exemplarily, the reinforcing member can prevent the substrate 100 from warping significantly in a specific direction. Therefore, the reinforcing member can prevent the insulating layer 110 from warping during the manufacturing process of the substrate 100, thereby improving the positional accuracy of the first electrode unit 120 and the second electrode unit 130. Furthermore, as the rigidity of the substrate 100 is ensured, a semiconductor device can be stably bonded to the substrate 100, thereby improving the operational characteristics of the semiconductor device. Furthermore, as the rigidity of the substrate 100 is ensured, the connecting member 500 (see FIG. 3 ) can be stably embedded in the circuit board. Therefore, the substrate 100 of the embodiment can stably support the connecting member 500, thereby minimizing thermal stress transmitted to the connecting member 500. Therefore, the embodiment can improve the signal transmission characteristics of the connecting member 500. Furthermore, electronic products and / or servers to which the semiconductor package of the embodiment is applied can be made to operate stably, thereby improving the reliability of the products.

[0085] When the insulating layer 110 is provided in multiple layers, each of the multiple layers can have a thickness in the range of 10 μm to 40 μm. Preferably, each of the multiple layers of the insulating layer 110 can have a thickness in the range of 15 μm to 35 μm. More preferably, each of the multiple layers of the insulating layer 110 can have a thickness in the range of 18 μm to 32 μm.

[0086] The thickness of each of the insulating layers 110 corresponds to the distance between the first electrode units 120 arranged on different layers in the vertical direction of the substrate. That is, the thickness may refer to the length from the top to the bottom of the substrate 100 or from the bottom to the top, or may refer to the length of the substrate in the vertical direction. Here, the top may refer to the highest position in the vertical direction of each component, and the bottom may refer to the lowest position in the vertical direction of each component. Furthermore, these positions may be referred to inversely.

[0087] If the thickness of each layer of the insulating layer 110 is less than 10 μm, the warpage characteristics of the substrate 100 may be reduced, which may result in the substrate 100 warping significantly in a specific direction. If the thickness of each layer of the insulating layer 110 is less than 10 μm, the electrode units 120 and 130 may not be stably protected, which may result in reduced physical and / or electrical reliability. Furthermore, if the thickness of each layer of the insulating layer 110 exceeds 40 μm, the overall thickness of the substrate 100 increases, which may result in an increased thickness of the semiconductor package. Furthermore, if the thickness of each layer of the insulating layer 110 exceeds 40 μm, it may be difficult to miniaturize the electrode units 120 and 130.

[0088] The substrate 100 includes an electrode portion. The electrode portion may perform, but is not limited to, a function of transmitting an electrical signal through the substrate 100. For example, the electrode portions 120 and 130 may include a dummy electrode for improving rigidity or a heat dissipation electrode for improving heat dissipation characteristics.

[0089] The electrode portion includes a first electrode portion 120 disposed on the surface of the insulating layer 110. The first electrode portion 120 is provided on the upper surface and / or the lower surface of the insulating layer 110. When the insulating layer 110 is provided in multiple layers, the first electrode portion 120 may be provided at each of the interfaces between the multiple layers of the insulating layer 110.

[0090] In addition, at least a portion of the first electrode unit 120 arranged on the uppermost or lowermost side of the insulating layer 110 may be disposed within the insulating layer 110. Exemplarily, as shown in FIG. 1 , at least a portion of the first electrode unit 120 arranged on the uppermost side of the insulating layer 110 may be embedded within the insulating layer 110. Here, being embedded may mean that at least a portion of the side surface of the first electrode unit 120 arranged on the uppermost side of the insulating layer 110 is covered by the insulating layer 110.

[0091] That is, a recess may be formed on the top surface of the insulating layer 110, and the first electrode unit 120 disposed on the top may have an ETS (Embedded Trace Substrate) structure disposed in the recess of the insulating layer 110. The ETS structure is advantageous for miniaturization compared to electrodes having a typical protruding structure. Accordingly, in the embodiment, the first electrode unit 120 disposed on the top side of the substrate 100 has an ETS structure, thereby enabling miniaturization. Here, the first electrode unit 120 disposed on the top side includes an electrode connected to a terminal of a semiconductor device and an external substrate. Therefore, in the embodiment, the electrodes of the first electrode unit 120 can be formed corresponding to the size and pitch of the terminals provided on the semiconductor device. As a result, the embodiment can improve circuit integration. Furthermore, the embodiment can minimize the transmission distance of a signal transmitted through the semiconductor device, thereby minimizing signal transmission loss.

[0092] The first electrode unit 120 may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). The first electrode unit 120 may also be formed of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn), which has excellent bonding strength. Preferably, the first electrode unit 120 may be formed of copper (Cu), which has high conductivity and is relatively inexpensive.

[0093] The first electrode unit 120 may have a thickness in the range of 7 μm to 20 μm. For example, the first electrode unit 120 may have a thickness in the range of 9 μm to 17 μm. For example, the first electrode unit 120 may have a thickness in the range of 10 μm to 13 μm. If the thickness of the first electrode unit 120 is less than 7 μm, the resistance of the first electrode unit 120 increases, and the allowable current of the transmittable signal may decrease. If the thickness of the first electrode unit 120 exceeds 20 μm, the thickness of the insulating layer 110 increases accordingly, which may make it difficult to thin the semiconductor package. If the thickness of the first electrode unit 120 exceeds 20 μm, it may make it difficult to miniaturize the first electrode unit 120.

[0094] The first electrode unit 120 includes a plurality of electrodes. Specifically, the first electrode unit 120 disposed on the insulating layer 110 includes a plurality of electrodes.

[0095] For example, the first electrode unit 120 disposed on the insulating layer 110 includes a first electrode 123, a second electrode 121, a third electrode 122, and a fourth electrode .

[0096] First electrode 123, second electrode 121, third electrode 122, and fourth electrode 124 are obtained by dividing first electrode section 120, which is arranged on the same plane, according to its arrangement position and / or function.

[0097] The second electrode 121, the third electrode 122, and the fourth electrode 124 of the first electrode unit 120 refer to electrodes connected to the terminal 225 of the semiconductor element 220. In this case, the semiconductor element 220 includes the terminal 225 provided on the lower surface. For example, the terminal 225 of the semiconductor element 220 may include first to third terminals. The second terminal of the semiconductor element 200 may be disposed in a peripheral region of the lower surface of the semiconductor element 200. The third terminal of the semiconductor element 200 may be disposed in the center of the lower surface of the semiconductor element 200. The first terminal of the semiconductor element 200 may be disposed between the second terminal and the third terminal of the semiconductor element.

[0098] The second electrode 121 of the first electrode unit 120 is connected to a first terminal of the semiconductor device 220. The third electrode 122 of the first electrode unit 120 is connected to a second terminal of the semiconductor device 220. The fourth electrode 124 of the first electrode unit 120 is connected to a third terminal of the semiconductor device 220. At least one of the second electrode 121, the third electrode 122, and the fourth electrode 124 may have a width or shape different from at least one of the other electrodes. For example, the terminals 225 of the semiconductor device 220 may have different sizes or pitches depending on their positions. Thus, the second electrode 121, the third electrode 122, and the fourth electrode 124 may have widths or shapes corresponding to the sizes or pitches of the terminals 225 of the semiconductor device 220. As a result, the embodiment may improve the integration density of the first electrode unit 120.

[0099] In addition, the first electrode 123 of the first electrode unit 120 is an electrode connected to the external substrate 300. The external substrate 300 may be a substrate on which the semiconductor device 420 is disposed, or an interposer connected to a substrate on which the semiconductor device 420 is mounted.

[0100] The first electrode 123 of the first electrode unit 120 may have a width greater than the second electrode 121, the third electrode 122, and the fourth electrode .

[0101] The electrode unit of the substrate 100 further includes a second electrode unit 130. The second electrode unit 130 penetrates at least a portion of the insulating layer 110. The second electrode unit 130 is provided between the plurality of first electrode units 120 provided on different layers. The second electrode unit 130 electrically connects the plurality of first electrode units 120 provided on different layers in the vertical direction.

[0102] The second electrode unit 130 may be formed by filling a through-hole that penetrates at least a portion of the insulating layer 110 with a conductive material.

[0103] The metal material forming the second electrode unit 130 may be any one selected from the group consisting of copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). In addition, the conductive material may be filled by any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, ink-jetting, and dispensing.

[0104] The semiconductor package includes a protective layer disposed on at least one of the upper and lower sides of the insulating layer 110. Exemplarily, the semiconductor package includes an upper protective layer 140 disposed on the insulating layer 110. The semiconductor package also includes a lower protective layer 150 disposed below the insulating layer 110.

[0105] The upper protective layer 140 and the lower protective layer 150 may function to protect the insulating layer 110. The upper protective layer 140 and the lower protective layer 150 may be resist layers. Preferably, the upper protective layer 140 and the lower protective layer 150 may be solder resist layers including an organic polymer material. For example, the upper protective layer 140 and the lower protective layer 150 may include an epoxy acrylate resin. In particular, the upper protective layer 140 and the lower protective layer 150 may include a resin, a hardener, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, etc. However, the embodiment is not limited thereto, and the upper protective layer 140 and the lower protective layer 150 may be any one of a photo solder resist layer, a coverlay, and a polymer material.

[0106] The upper protective layer 140 includes a first protective layer 141 having a through hole 141T1 and a second protective layer 142 disposed inside the through hole 141T1 of the first protective layer 141. The through hole 141T1 provided in the first protective layer 141 refers to the region where the semiconductor element 220 is disposed. Therefore, the second protective layer 142 refers to the upper protective layer 140 disposed in a region vertically overlapping the semiconductor element 220, and the first protective layer 141 refers to the protective layer surrounding the second protective layer 142. That is, the first protective layer 141 and the second protective layer 142 may be distinguished by their positions on the insulating layer 110. The first protective layer 141 and the second protective layer 142 may represent a single component separated by their positions, or may represent separate or distinct components. Here, separating a single layer by their positions may mean that the first protective layer 141 and the second protective layer 142 are made of the same material.

[0107] At this time, the upper surface of the first protective layer 141 of the upper protective layer 140 has a step.

[0108] For example, the first protective layer 141 includes a first region 141R1 (see FIG. 4) and a second region 141R2 (see FIG. 4). The first region 141R1 of the first protective layer 141 refers to an inner region of the upper surface of the first protective layer 141. The inner region may refer to a region adjacent to the through-hole 141T of the first protective layer 141 and surrounding the periphery of the through-hole 141T. The inner region may also refer to a region vertically overlapping with the semiconductor element 220. For example, the semiconductor element 200 disposed on the substrate 100 vertically overlaps with a portion of the first protective layer 141 and the entire second protective layer 142. The first region 141R1 of the first protective layer 141 may refer to a partial region of the entire region of the first protective layer 141 that vertically overlaps with the semiconductor element 220.

[0109] The second region 141R2 of the first protective layer 141 refers to a region other than the first region 141R1. The second region 141R2 of the first protective layer 141 may refer to a peripheral region of the upper surface of the first protective layer 141. The peripheral region refers to a region adjacent to the edge or frame of the upper surface of the first protective layer 141. In addition, the peripheral region refers to a region that does not vertically overlap with the semiconductor element 220 disposed on the substrate.

[0110] There is a step between the top surface 141R1 of the first region of the first protective layer 141 and the top surface of the second region 141R2 of the first protective layer 141. The height of the top surface of the first region 141R1 of the first protective layer 141 is different from the height of the top surface of the second region 141R2. For example, the top surface of the first region 141R1 is located lower than the top surface of the second region 141R2.

[0111] The upper surface of the second protective layer 142 has a step with the upper surface of the first protective layer 141. For example, the upper surface of the second protective layer 142 has a step with the upper surface of the second region 141R2 of the first protective layer 141. The upper surface of the second protective layer 142 is located lower than the upper surface of the second region 141R2 of the first protective layer 141.

[0112] In addition, in one example, the upper surface of the second protective layer 142 does not have a step with the upper surface of the first region 141R1 of the first protective layer 141. For example, the upper surface of the second protective layer 142 may be located on the same plane as the upper surface of the first region 141R1 of the first protective layer 141.

[0113] In another example, the upper surface of the second protective layer 142 has a step with respect to the upper surface of the first region 141R1 of the first protective layer 141. For example, the upper surface of the second protective layer 142 may be located lower than the upper surface of the first region 141R1 of the first protective layer 141.

[0114] Through this, the embodiment can improve the physical reliability of the conductive coupling portion 160 provided on the substrate 100.

[0115] That is, the semiconductor package includes a conductive coupling part 160. The conductive coupling part 160 is disposed on the first electrode 123 of the first electrode part 120 disposed on the insulating layer 110. The conductive coupling part 160 may refer to an electrode that electrically connects the external substrate 300 and the first electrode 123. The conductive coupling part 160 may be referred to as a post bumper.

[0116] The conductive coupling portion 160 penetrates at least a portion of the second region 141R2 of the upper protective layer 140.

[0117] Therefore, the second region 141R2 of the first protective layer 141 surrounds the side of the conductive coupling part 160. In addition, the second region 141R2 of the first protective layer 141 can stably protect the conductive coupling part 160 from various factors that may occur during the manufacturing process of a semiconductor package. For example, in this embodiment, the side of the conductive coupling part 160 is entirely covered with the second region 141R2 of the first protective layer 141, thereby minimizing stress acting on the conductive coupling part 160 compared to conventional techniques in which the side of the conductive coupling part 160 is covered with multiple insulating members made of different materials.

[0118] In addition, the second region 141R2 of the first protective layer 141 has a step with the first region 141R1 and the second protective layer 142 of the first protective layer 141, thereby facilitating the mounting process of the semiconductor device 220. For example, the step between the top surfaces of the first region 141R1 and the second region 141R2 of the first protective layer 141 surrounds the periphery of the semiconductor device 220 at a position horizontally spaced apart from the semiconductor device 220 by a predetermined distance. The step between the top surfaces of the first region 141R1 and the second region 141R2 of the first protective layer 141 does not overlap with the semiconductor device 220 in the vertical direction. Therefore, the step between the top surfaces of the first region 141R1 and the second region 141R2 of the first protective layer 141 can define a molding region of the semiconductor device 220, thereby facilitating the molding process of the semiconductor device 220.

[0119] Furthermore, the embodiment can improve the bonding strength with the semiconductor element.

[0120] The first protective layer 141 includes a plurality of open areas. For example, the first protective layer 141 includes an upper surface and a lower surface opposite the upper surface. The first protective layer 141 includes a plurality of open areas that are spaced apart from one another and penetrate the upper and lower surfaces of the first protective layer 141. The plurality of open areas of the first protective layer 141 are divided into through holes and openings. The division into through holes and openings can be performed based on the size, shape, and number of exposed electrodes.

[0121] For example, the first protective layer 141 includes a through-hole 141T1 (see FIG. 4). The first protective layer 141 also includes a first opening 141T2 (see FIG. 4) and a second opening 141T3 (see FIG. 4) that are spaced apart from the through-hole 141T1.

[0122] The planar shape of the through hole 141T1 in the first protective layer 141 may be different from the planar shapes of the first opening 141T2 and the second opening 141T3 in the first protective layer 141. The planar shape of the through hole 141T1 in the first protective layer 141 may correspond to the planar shape of the semiconductor element 220. For example, the planar shape of the through hole 141T1 in the first protective layer 141 may be, but is not limited to, a quadrangle.

[0123] The first opening 141T2 and the second opening 141T3 of the first protective layer 141 may have planar shapes corresponding to the planar shapes of the first electrode 123 and the third electrode 122 of the first electrode unit 120. For example, the planar shapes of the first opening 141T2 and the second opening 141T3 of the first protective layer 141 may be, but are not limited to, circular.

[0124] The size of the through hole 141T1 of the first protective layer 141 is larger than the sizes of the first opening 141T2 and the second opening 141T3 of the first protective layer 141. The size may refer to the planar area, or alternatively, may refer to the width in the first horizontal direction and / or the second horizontal direction. The size of the through hole 141T1 of the first protective layer 141 is determined by the size of the semiconductor element 220. In addition, the sizes of the first opening 141T2 and the second opening 141T3 of the first protective layer 141 are determined by the size of the conductive coupling portion 160 and the size of the third electrode 122.

[0125] Furthermore, the through holes 141T1 of the first protective layer 141 vertically overlap with the semiconductor element 220 mounted on the substrate 100. The through holes 141T1 of the first protective layer 141 vertically overlap with a plurality of electrodes of the first electrode unit 120 arranged on the insulating layer 110 that vertically overlap with the semiconductor element 220.

[0126] In addition, the first opening 141T2 of the first protective layer 141 vertically overlaps the third electrode 122 of the first electrode unit 120 of the substrate 100. For example, the first opening 141T2 of the first protective layer 141 may partially overlap the upper surface of one third electrode 122 in the vertical direction. In addition, the second opening 141T3 of the first protective layer 141 vertically overlaps the first electrode 123. Preferably, the second opening 141T3 of the first protective layer 141 vertically overlaps the conductive coupling part 160 provided on the first electrode 123. For example, the second opening 141T3 of the first protective layer 141 may partially overlap the upper surface of the conductive coupling part 160 in the vertical direction.

[0127] The first opening 141T2 may refer to the area where the terminal 225 of the semiconductor element 220 and the electrode of the first electrode unit 120 are connected, or may refer to the area where metal is disposed on the electrode to connect the terminal 225 of the semiconductor element 220 and the electrode of the first electrode unit 120.

[0128] In addition, the second opening 141T3 may refer to the area where the external substrate 300 and the conductive coupling portion 160 are coupled, or may refer to the area where metal is disposed on the conductive coupling portion 160 for coupling the external substrate 300 and the conductive coupling portion 160.

[0129] Furthermore, the second protective layer 142 is disposed inside the through-hole 141T1 of the first protective layer 141. For example, the second protective layer 142 is disposed in a region that vertically overlaps with the through-hole 141T1 of the first protective layer 141 on the upper surface of the insulating layer 110. For example, the second protective layer 142 can be disposed in a region that vertically overlaps with the semiconductor element 220.

[0130] The second protective layer 142 includes an opening 142T. The opening 142T of the second protective layer 142 vertically overlaps with the fourth electrode 124 of the first electrode unit 120. For example, the opening 142T of the second protective layer 142 may partially overlap with the upper surface of the fourth electrode 124 in the vertical direction.

[0131] In this case, the area of ​​the second protective layer 142 is smaller than the area of ​​the through hole 141T1 of the first protective layer 141. As a result, when the second protective layer 142 is disposed inside the through hole 141T1 of the first protective layer 141, a separation area SA (see FIG. 6) is provided between the inner surface of the through hole 141T1 of the first protective layer 141 and the outer surface of the second protective layer 142. The separation area SA refers to a region that vertically overlaps with the through hole 141T1 of the first protective layer 141 but does not vertically overlap with the second protective layer 142. At least a portion of the second electrode 121 of the first electrode unit 120 of the substrate 100 may vertically overlap with the separation area SA.

[0132] The specific structures of the first protective layer 141 and the second protective layer 142 of the upper protective layer 140 will be described in further detail below.

[0133] Meanwhile, the lower protective layer 150 may include an opening. The opening of the lower protective layer 150 may vertically overlap the electrode of the first electrode unit 120 disposed on the lower surface of the insulating layer 110 of the substrate 100. The lower protective layer 150 may include only an opening without including the through-hole provided in the first protective layer 141 of the upper protective layer 140, but is not limited thereto.

[0134] In addition, the lower surface of the lower protective layer 150 may not have a step. However, the embodiment is not limited thereto. For example, the lower surface of the lower protective layer 150 may have a step corresponding to the step provided on the upper surface of the upper protective layer 140 described below.

[0135] Meanwhile, the semiconductor package includes a conductive coupling part 160. The conductive coupling part 160 is disposed on the first electrode 123 of the first electrode part 120 disposed on the insulating layer 110. The conductive coupling part 160 is an electrode that electrically connects the external substrate 300 and the first electrode 123. The conductive coupling part 160 may be referred to as a post bumper.

[0136] The conductive coupling portion 160 penetrates the upper protective layer 140. For example, the conductive coupling portion 160 penetrates at least a partial region of the first protective layer 141 of the upper protective layer 140.

[0137] The conductive coupling part 160 vertically overlaps the second opening 141T3 of the first protective layer 141. Therefore, the side surfaces of the conductive coupling part 160 are surrounded by the first protective layer 141. A portion of the upper surface of the conductive coupling part 160 is covered by the first protective layer 141. In addition, at least a portion of the upper surface of the conductive coupling part 160 vertically overlaps the second opening 141T3 of the first protective layer 141 and does not contact the first protective layer 141.

[0138] The conductive coupling part 160 may be provided to reduce the volume of the second connection part 240 for coupling with the external substrate 300 while spacing the external substrate 300 from the substrate 100 at a predetermined distance.

[0139] The semiconductor package also includes a first connection portion 210. For example, the first connection portion 210 is disposed on an electrode of the first electrode portion 120 that is connected to a terminal 225 of the semiconductor element 220. Specifically, the first connection portion 210 is disposed on the second electrode 121, the third electrode 122, and the fourth electrode 124 of the first electrode portion 120 that is disposed on the insulating layer 110.

[0140] The first connection portion 210 is disposed in the first opening 141T2 of the first protective layer 141, the opening 141T2 of the second protective layer 142, and the separation area SA between the first protective layer 141 and the second protective layer 142, respectively.

[0141] The first connection part 210 may refer to a metal that electrically connects a plurality of components using at least one bonding method of wire bonding, solder bonding, and direct metal bonding. Since the first connection part 210 has a function of electrically connecting a plurality of components, when direct metal bonding is used, the semiconductor package may be understood as the electrically connected part, not the solder or wire.

[0142] The wire bonding method may refer to electrically connecting multiple components using a conductive wire such as gold (Au). The solder bonding method may refer to electrically connecting multiple components using a material including at least one of Sn, Ag, and Cu. The direct inter-metal bonding method may refer to directly bonding multiple components through recrystallization by applying heat and pressure between the multiple components without using materials such as solder, wire, or conductive adhesive. In this case, the first connection portion 210 may refer to a metal layer formed between the multiple components through recrystallization.

[0143] For example, the first connecting unit 210 may bond the plurality of components to each other using a thermal compression bonding method. The thermal compression bonding method may refer to a method of directly bonding the plurality of components to each other by applying heat and pressure to the first connecting unit 210.

[0144] The semiconductor package of the embodiment includes a semiconductor element 220 disposed on a first connection portion 210. A terminal 225 is provided on a bottom surface of the semiconductor element 220. The terminal 225 of the semiconductor element 220 is electrically connected to the second electrode 121, the third electrode 122, and the fourth electrode 124 of the first electrode unit 120 via the first connection portion 210.

[0145] The semiconductor package may include an underfill 230. The underfill 230 is disposed on the substrate 100. The underfill 230 is disposed on the substrate 100 to cover the periphery of the semiconductor element 220. The underfill 230 may be disposed on a portion of the upper surface of the first protective layer 141, a portion of the upper surface of the second protective layer 142, a portion of the open area of ​​the first protective layer 141, and a portion of the open area of ​​the second protective layer 142.

[0146] The semiconductor package includes a second connecting portion 240. The second connecting portion 240 is disposed on the conductive coupling portion 160. For example, the second connecting portion 240 is disposed in the second opening 141T3 of the first protective layer 141 that overlaps the conductive coupling portion 160 in the vertical direction.

[0147] In this case, the upper surface of the second connecting portion 240 is located higher than the upper surface of the semiconductor device 220. In addition, the lower surface of the second connecting portion 240 is located lower than the upper surface of the semiconductor device 220 but higher than the lower surface of the semiconductor device 220. That is, the upper surface of the conductive coupling portion 160 coupled to the second connecting portion 240 is located lower than the upper surface of the semiconductor device 220. In addition, the lower surface of the conductive coupling portion 160 is located higher than the lower surface of the semiconductor device 220. Thus, the embodiment may prevent the semiconductor device 220 from being damaged during a bonding process of the external substrate 300 disposed on the second connecting portion 240. Furthermore, the embodiment may reduce the volume of the second connecting portion 240 by using the conductive coupling portion 160. Thus, the embodiment may ensure the rigidity of the conductive coupling portion 160 and the second connecting portion 240. Therefore, the embodiment may improve the physical reliability and / or electrical reliability of the semiconductor package. Furthermore, the embodiment allows the external substrate 300 to be stably coupled onto the conductive coupling portion 160 and the second connection portion 240 .

[0148] 1 may have a package-on-package structure, i.e., the semiconductor package may have a structure in which a plurality of packages are arranged vertically and electrically connected along the vertical direction, but is not limited thereto.

[0149] The semiconductor package includes a molding layer 250 .

[0150] The molding layer 250 is disposed between the substrate 100 and the external substrate 300. The molding layer 250 is disposed on the upper protective layer 140. The molding layer 250 molds the second connecting portion 240, the underfill 230, and the semiconductor element 220.

[0151] The molding layer 250 is disposed on the first protective layer 141 and the second protective layer 142 of the upper protective layer 140. At this time, the upper surface of the first protective layer 141 of the upper protective layer 140 has a step. As a result, the lower surface of the molding layer 250 has a step corresponding to the step of the upper surface of the upper protective layer 140.

[0152] The semiconductor package includes a third connecting portion 260.

[0153] The third connection portion 260 is disposed on the lower surface of the first electrode portion 120, which is disposed on the lower surface of the insulating layer 110. For example, the third connection portion 260 may be disposed in an opening in the lower protective layer 150. The third connection portion 260 may be, but is not limited to, a solder for connecting the semiconductor package of the embodiment to another external board (e.g., a main board of an electronic device).

[0154] The semiconductor package includes an external substrate 300. The external substrate 300 may refer to another substrate coupled to the substrate 100. For example, the semiconductor device 220 disposed on the substrate 100 may be a logic chip such as a CPU or GPU, and the external substrate 300 may refer to a memory substrate on which a memory chip connected to the logic chip is disposed. The external substrate 300 may also be an interposer that connects the substrate 100 to a memory substrate on which a semiconductor device 420 corresponding to the memory chip is disposed.

[0155] The external substrate 300 may include an insulating layer 310, a circuit layer 320, and a through electrode 330. The semiconductor package may include an upper insulating layer 340 disposed on the upper surface of the external substrate 300 and a lower insulating layer 350 disposed on the lower surface of the external substrate 300.

[0156] The semiconductor package includes a fourth connection portion 410 and a semiconductor element 420. The semiconductor element 420 may be mounted on the external substrate 300 via the fourth connection portion 410. The semiconductor element 420 may be, but is not limited to, a memory chip.

[0157] Meanwhile, referring to FIG. 2, the semiconductor package of the second embodiment may differ from the semiconductor package of the first embodiment in the structure of the substrate 100.

[0158] For example, the semiconductor package of the first embodiment includes a coreless substrate, and the semiconductor package of the second embodiment of FIG. 2 includes a core substrate.

[0159] 2, the substrate 100 includes an insulating layer 110. The insulating layer 110 has a multi-layer structure. The insulating layer 110 includes a first insulating layer 111 including a reinforcing member. The reinforcing member provided in the first insulating layer 111 may be glass fiber.

[0160] The insulating layer 110 includes a second insulating layer 112 disposed above and below the first insulating layer 111. Unlike the first insulating layer 111, the second insulating layer 112 may not include a reinforcing member. For example, the second insulating layer 112 may be, but is not limited to, an ABF.

[0161] Furthermore, the semiconductor package of the second embodiment has a structure in which the first electrode portion 120 arranged on the uppermost side of the insulating layer 110 protrudes above the insulating layer 110 .

[0162] 3, the semiconductor package includes a connecting member 500 embedded in an insulating layer 110. The connecting member 500 is disposed in the insulating layer 110 of the substrate 100, and horizontally connects a plurality of semiconductor elements mounted on the substrate 100 therethrough. In this case, the insulating layer 110 may have a cavity 110C, and the connecting member 500 may be embedded in the cavity 110C of the insulating layer 110.

[0163] The connecting member 500 has a high-density electrode pattern. The connecting member 500 can be an organic bridge or an inorganic bridge.

[0164] The connecting member 500 includes a connecting electrode 510. The connecting electrode 510 may refer to an electrode disposed on the uppermost side of the connecting member 500, or may refer to an electrode connected to an electrode of the first electrode unit 120 of the substrate 100.

[0165] A fourth connection portion 520 is disposed between the connecting electrode 510 of the connecting member 500 and the electrode of the first electrode portion 120 of the substrate 100. The fourth connection portion 520 electrically couples the connecting electrode 510 of the connecting member 500 and the electrode of the first electrode portion 120 of the substrate 100.

[0166] Furthermore, a plurality of semiconductor elements are mounted on the electrodes of the first electrode unit 120. For example, a first semiconductor element 220 and a second semiconductor element 270 are coupled to the electrodes of the first electrode unit 120. The first semiconductor element 220 and the second semiconductor element 270 are arranged horizontally spaced apart on the substrate 100. The first semiconductor element 220 includes a first terminal 225, and the second semiconductor element 270 includes a second terminal 275. Furthermore, at least a portion of the first terminal 225 of the first semiconductor element 220 and at least a portion of the second terminal 275 of the second semiconductor element 270 overlap with the connecting member 500 in the horizontal direction. Therefore, at least a portion of the first terminal 225 of the first semiconductor element 220 and at least a portion of the second terminal 275 of the second semiconductor element 270 are electrically connected to each other via the connecting member 500.

[0167] Meanwhile, the second connection part 240 is disposed on the conductive coupling part 160, and the third semiconductor element 280 is coupled to the second connection part 240. The third semiconductor element 280 includes a plurality of terminals 285. Some of the plurality of terminals of the third semiconductor element 280 are coupled to the conductive coupling part 160 via the second connection part 240. In addition, some of the plurality of terminals of the third semiconductor element 280 are electrically coupled to the first semiconductor element 220 via the fifth connection part 241. In addition, some of the remaining plurality of terminals of the third semiconductor element 280 are coupled to the second semiconductor element 270 via the sixth connection part 242.

[0168] At this time, the third semiconductor device 280 may be supplied with a power signal and / or power via the conductive coupling part 160. In addition, the third semiconductor device 280 may transmit and receive communication signals to and from the first and second semiconductor devices 220 and 270 via the fifth connecting part 241 and the sixth connecting part 242, or may electrically connect the first and second semiconductor devices 220 and 270 horizontally.

[0169] The semiconductor package of the third embodiment supplies a power signal and / or power to the third semiconductor element 280 through the conductive coupling portion 160, thereby providing sufficient power for driving the third semiconductor element 280, smoothly controlling the power supply operation, and suppressing noise by reducing interference between signals when connecting the first to third semiconductor elements 220, 270, and 280.

[0170] The electrode structure of the first electrode unit 120 of the substrate 100 of the embodiment, and the step structure and open structure of the upper protective layer 140 will be specifically described below.

[0171] Figure 4 is a plan view of a first protective layer according to the first embodiment, Figure 5 is a plan view of a second protective layer according to the embodiment, Figure 6 is a plan view showing the state in which the second protective layer is arranged in the through hole of the first protective layer according to the embodiment, Figure 7 is a cross-sectional view of one embodiment taken along the A-A' direction of Figure 6, Figure 8 is a cross-sectional view showing the state in which a semiconductor element is arranged in the semiconductor package of Figure 7, Figure 9 is a cross-sectional view of another embodiment taken along the A-A' direction of Figure 6, Figure 10 is a plan view of a first protective layer according to the second embodiment, Figure 11 is a cross-sectional view showing the state in which a semiconductor element is arranged in a semiconductor package including the first protective layer of Figure 10, and Figure 12 is an enlarged view of area B of Figure 6.

[0172] 4, 5 and 6, the first protective layer 141 is disposed on the insulating layer 110. As shown in FIG.

[0173] The first protective layer 141 includes an open region. The first protective layer 141 includes a plurality of through-hole type open regions that penetrate the upper surface and the lower surface.

[0174] The first protective layer 141 includes a through-hole 141T1 that vertically overlaps with the semiconductor element 220 mounted on the insulating layer 110. The shape and size of the through-hole 141T1 of the first protective layer 141 can correspond to the shape and size of the semiconductor element 220, but are not limited to this.

[0175] The planar area of ​​the through hole 141T1 of the first protective layer 141 can correspond to the planar area of ​​the semiconductor element 220. For example, the planar area of ​​the through hole 141T1 of the first protective layer 141 may be 60% or more, 70% or more, or 80% or more of the planar area of ​​the semiconductor element 220. Furthermore, the planar area of ​​the through hole 141T1 of the first protective layer 141 is smaller than the planar area of ​​the semiconductor element 220. Therefore, at least a portion of the upper surface of the first protective layer 141 overlaps with the semiconductor element 220 in the vertical direction.

[0176] The upper surface of the first protective layer 141 has a step along the horizontal direction in the region where the through-hole 141T1 is provided. That is, the upper surface of the first protective layer 141 includes inner corners 141P and 141C that correspond to the through-hole 141T1. The inner corners 141P and 141C have a step along the horizontal direction. For example, the inner corners 141P and 141C can be divided into a protruding surface 141P and a concave surface 141C that have a step along the horizontal direction.

[0177] In one embodiment, the protruding surface 141P and the concave surface 141C may be provided on the upper surface of the first protective layer 141 connected to the inner surface of the through hole 141T1 or on the corners of the inner surface of the through hole 141T.

[0178] The inner surface of the through hole 141T1 of the first protective layer 141 has a step in the horizontal direction. For example, the inner surface of the through hole 141T1 of the first protective layer 141 includes a protruding surface 141P that protrudes in a direction away from the inner surface. For example, the inner surface of the through hole 141T1 of the first protective layer 141 includes a concave surface 141C that is recessed toward the inside of the first protective layer 141.

[0179] In this case, the outer surface of the first protective layer 141 does not have a step in the horizontal direction. Therefore, the step on the inner surface of the through hole 141T1 of the first protective layer 141 may mean that the horizontal distance between the outer surface and the inner surface of the corresponding first protective layer 141 varies along the periphery of the inner surface of the first protective layer 141.

[0180] Furthermore, although the protruding surface 141P and the concave surface 141C have been described as protruding or recessing horizontally along the circumferential direction of the inner surface of the through-hole 141T1 of the first protective layer 141, the present invention is not limited to this.

[0181] Furthermore, the through-holes 141T1 of the first protective layer 141 vertically overlap the semiconductor element 220. Therefore, the through-holes 141T of the first protective layer 141 vertically overlap the electrodes of the first electrode unit 120 of the substrate 100 that are connected to the terminals 225 of the semiconductor element 220.

[0182] For example, the first electrode unit 120 disposed on the insulating layer 110 includes a plurality of first electrodes 123, a plurality of second electrodes 121, a plurality of third electrodes 122, and a plurality of fourth electrodes 124. Furthermore, the through-hole 141T1 provided in the first protective layer 141 overlaps in the vertical direction with the plurality of second electrodes 121 and the plurality of fourth electrodes 124. The through-hole 141T1 of the first protective layer 141 means one hole, and thus the through-hole 141T1 overlaps in the vertical direction in common with the plurality of second electrodes, the plurality of fourth electrodes, and traces disposed between the plurality of second electrodes and the plurality of fourth electrodes.

[0183] The first protective layer 141 includes a plurality of openings.

[0184] The first protective layer 141 includes a plurality of first openings 141T2 and a plurality of second openings 141T3. The first openings 141T2, the second openings 141T3, and the through-holes 141T1 are substantially identical in that they penetrate the first protective layer 141, but may be distinguished from one another by at least one of their positions, sizes, and shapes.

[0185] The first protective layer 141 includes a plurality of first openings 141T2. The plurality of first openings 141T2 may penetrate the first protective layer 141 in an area adjacent to the through-hole 141T1. The first openings 141T2 are not connected to the through-hole 141T1. For example, the first openings 141T2 may penetrate the first protective layer 141 at a position spaced apart from the through-hole 141T1. However, the embodiment is not limited thereto. For example, a plurality of first openings 141T2 may be provided, and any one of the plurality of first openings may be connected to the through-hole 141T1.

[0186] The first openings 141T2 may be provided adjacent to a plurality of inner surfaces constituting the through hole 141T1 of the first protective layer 141. For example, the first openings 141T2 may be provided adjacent to each of the first to fourth inner surfaces of the first through hole 141T1 of the first protective layer 141. The size and / or shape of the first openings 141T2 may correspond to the size and / or shape of the third electrode 122 of the substrate 100.

[0187] In this case, the first opening 141T2 may partially overlap the upper surface of the third electrode 122 in the vertical direction. For example, a portion of the upper surface of the third electrode 122 may vertically overlap the first opening 141T2 of the first protective layer 141, and the remaining portion may be covered by the first protective layer 141. For example, the first opening 141T2 of the first protective layer 141 may be an SMD (Solder Mask Defined) type opening, but is not limited to this. For example, the first opening 141T2 of the first protective layer 141 may be an NSMD (Non-solder Mask Defined) type opening.

[0188] The first protective layer 141 may further include a second opening 141T3. The second opening 141T3 of the first protective layer 141 may penetrate the first protective layer 141 at a position spaced apart from the through-hole 141T1 and the first opening 141T2.

[0189] Preferably, the second opening 141T3 of the first protective layer 141 may be provided in an outer region of the top surface of the first protective layer 141.

[0190] For example, the second opening 141T3 of the first protective layer 141 may be provided in a peripheral region of the upper surface of the first protective layer 141. Preferably, the second opening 141T3 of the first protective layer 141 is provided in a region that vertically overlaps with the conductive coupling portion 160.

[0191] The second opening 141T3 of the first protective layer 141 may be larger in width than the first opening 141T2. For example, the width of the third electrode 122 of the first electrode unit 120 may be smaller than the width of the first electrode 123. Furthermore, the width of the conductive coupling portion 160 disposed on the first electrode 123 may be larger than the width of the third electrode 122. Therefore, the width of the second opening 141T3 of the first protective layer 141 may be larger than the width of the first opening 141T2 of the first protective layer 141.

[0192] The through hole 141T1 of the first protective layer 141 can be said to be an area where the second protective layer 142, the semiconductor element 220, and the first connecting portion 210 are disposed. The first opening 141T2 of the first protective layer 141 can be said to be an area where the first connecting portion 210 is disposed. The second opening 141T3 of the first protective layer 141 can be said to be an area where the second connecting portion 240 is disposed.

[0193] The second protective layer 142 also includes a plurality of openings 142T. The plurality of openings 142T of the second protective layer 142 vertically overlap with the through holes 141T1 of the first protective layer 141. The plurality of openings 142T of the second protective layer 142 vertically overlap with the plurality of fourth electrodes 124 of the first electrode unit 120 disposed on the insulating layer 110, respectively.

[0194] The opening 142T of the second protective layer 142 may partially overlap the upper surface of the fourth electrode 124 in the vertical direction. For example, a portion of the upper surface of the fourth electrode 124 may vertically overlap the opening 142T of the second protective layer 142, and the remaining portion may be covered by the second protective layer 142. For example, the opening 142T of the second protective layer 142 may be an SMD (Solder Mask Defined) type opening, but is not limited to this. For example, the opening 142T of the second protective layer 142 may be an NSMD (Non-solder Mask Defined) type opening.

[0195] 7 and 8, the upper surface of the second protective layer 142 in one embodiment is located on the same plane as a part of the upper surface of the first protective layer 141. For example, the upper surface of the second protective layer 142 is located on the same plane as the upper surface of the first region 141R1 of the first protective layer 141.

[0196] 9, the upper surface of the second protective layer 142 in another embodiment is located lower than the upper surface of the first region 141R1 of the first protective layer 141. For example, a step SH2 may be provided between the upper surface of the second protective layer 142 and the upper surface of the first region 141R1 of the first protective layer 141, but is not limited to this.

[0197] That is, the second protective layer 142 may be disposed only in the regions between the plurality of fourth electrodes 124 on the insulating layer 110. For example, the second protective layer 142 may not vertically overlap the plurality of electrodes disposed on the upper surface of the insulating layer 110 of the substrate 100.

[0198] The outer surface of the second protective layer 142 may include at least one of a protruding surface 142P and a concave surface 142C. For example, if the outer surface of the second protective layer 142 includes the protruding surface 142P, the remaining outer surface excluding the protruding surface 142P may also be considered a concave surface. For example, if the outer surface of the second protective layer 142 includes a concave surface, the remaining outer surface excluding the concave surface 142C may also be considered a protruding surface.

[0199] The outer surface of the second protective layer 142 can face the inner surface of the first protective layer 141 in the horizontal direction.

[0200] In this case, a portion of the protruding surface 141P on the inner surface of the first protective layer 141 may overlap horizontally with a portion of the protruding surface 142P on the outer surface of the second protective layer 142, and the remaining portion may overlap horizontally with a portion of the concave surface 142C on the outer surface of the second protective layer 142.

[0201] In addition, a portion of the concave surface 141C on the inner surface of the first protective layer 141 may overlap horizontally with a portion of the protruding surface 142P on the outer surface of the second protective layer 142, and the remaining portion may overlap horizontally with a portion of the concave surface 142C on the outer surface of the second protective layer 142.

[0202] The plane area of ​​the through-hole 141T1 of the first protective layer 141 is larger than the plane area of ​​the second protective layer 142. The first protective layer 141 does not come into contact with the second protective layer 142.

[0203] Therefore, when the second protective layer 142 is positioned inside the through hole 141T1 of the first protective layer 141, a separation area SA is provided between the inner surface constituting the through hole 141T1 of the first protective layer 141 and the outer surface of the second protective layer 142.

[0204] The separation region SA may refer to a region of the first protective layer 141 that does not vertically overlap the second protective layer 142 across the entire region of the through hole 141T1. Thus, the separation region SA may be formed in a closed loop shape between the inner surface of the first protective layer 141 and the outer surface of the second protective layer 142. This prevents electrical shorts between the first electrode unit 120 located in an area adjacent to the separation region SA and serves as an alignment key for positioning the semiconductor device, thereby improving process yield. Furthermore, the first protective layer 141 and the second protective layer 142 may have a structure that is physically separated from each other, thereby controlling the stress applied to the substrate 100 and thereby improving the mechanical reliability of the semiconductor device package.

[0205] Furthermore, the upper surface of the first protective layer 141 has a step. For example, the upper surface of the first protective layer 141 has a step in the vertical direction. For example, the upper surface of one region of the first protective layer 141 is located higher than the upper surface of another region of the first protective layer 141.

[0206] 4, 7, and 8, the first protective layer 141 includes a first region 141R1 and a second region 141R2. The first region 141R1 of the first protective layer 141 is an inner region of the upper surface of the first protective layer 141 that vertically overlaps the semiconductor element 220, and the second region 141R2 of the first protective layer 141 is a region other than the first region 141R1. Exemplarily, the second region 141R2 of the first protective layer 141 may be a peripheral region adjacent to the frame or edge of the upper surface of the first protective layer 141.

[0207] The peripheral region refers to a region provided along the circumferential direction of the upper surface of the first protective layer 141 and adjacent to the periphery of the upper surface. The inner region refers to a region other than the peripheral region. For example, the peripheral region may be a region adjacent to the periphery of the upper surface of the first protective layer 141, and the inner region may refer to a region adjacent to the inner surface of the through hole 141T1.

[0208] For example, the first protective layer 141 includes a second opening 141T3 and a second region 141R2 that is a peripheral region on the top surface of the first protective layer 141. The first protective layer 141 also includes a first opening 141T2 and a first region 141R1 that is an inner region of the first region 141R1 of the first protective layer 141.

[0209] In this case, the second region 141R2 of the first protective layer 141 is provided to surround the periphery of the conductive coupling part 160 disposed on the first electrode 123. The second region 141R2 of the first protective layer 141 has a first height. For example, the upper surface of the second region 141R2 of the first protective layer 141 is positioned higher than the upper surface of the conductive coupling part 160.

[0210] That is, the side surfaces of the conductive coupling part 160 in the embodiment are entirely covered with the first protective layer 141. As a result, the embodiment does not need to form a separate molding member to enclose the side surfaces of the conductive coupling part 160, thereby simplifying the manufacturing process.

[0211] Furthermore, in this embodiment, the entire side surface of the conductive coupling part 160 is covered with the first protective layer 141. This minimizes stress acting on the conductive coupling part 160, thereby resolving the reliability problem of cracks occurring at the interface between the conductive coupling part 160 and the first electrode 123 due to stress concentration on the conductive coupling part 160.

[0212] For example, in the prior art, a portion of a side of a conductive coupling part is covered with a protective layer, and the remaining portion is covered with a molding member. The protective layer and the molding member contain different insulating materials, and therefore have different thermal expansion coefficients. Therefore, one of the protective layer and the molding member may expand or contract more than the other. Therefore, different stresses may act on the side of the conductive coupling part that contacts the molding member and the side of the conductive coupling part that contacts the protective layer, which may reduce the physical reliability of the conductive coupling part.

[0213] According to another conventional technique, the entire side of the conductive coupling part may be in contact with the molding member. In this case, the molding member is laminated after mounting the semiconductor device on the substrate. Therefore, the entire top and side of the conductive coupling part may be exposed during the process of mounting the semiconductor device. Therefore, during the process of mounting the semiconductor device, physical impact may be applied to the conductive coupling part, which may cause the conductive coupling part to peel off from the first electrode part 120. Furthermore, during the process of mounting the semiconductor device, foreign matter may accumulate on the top surface of the conductive coupling part, which may reduce the electrical reliability of the conductive coupling part.

[0214] In contrast, in the embodiment, the second region 141R2 of the first protective layer 141 is provided to entirely surround the side of the conductive coupling part 160. As a result, in the embodiment, uniform stress can be applied to the entire region of the conductive coupling part 160 due to expansion or contraction of the first protective layer 141, thereby resolving the physical reliability problem of the conductive coupling part 160 peeling off from the first electrode 123.

[0215] Furthermore, in the embodiment, the conductive coupling part 160 can be stably protected from impacts applied during the process of mounting the semiconductor element, thereby improving the physical reliability and / or electrical reliability of the conductive coupling part 160.

[0216] The second region 141R2 of the first protective layer 141 is provided along the circumferential direction of the upper surface of the first protective layer 141. The second region 141R1 of the first protective layer 141 is provided inside the second region 141R2. In this case, the first region 141R1 of the first protective layer 141 has a height lower than the second region 141R2.

[0217] Therefore, the second region 141R2 of the first protective layer 141 surrounds the outside of the first region 141R1 and has a height higher than the first region 141R1. Preferably, a first step SH1 (see FIG. 7) is provided between the upper surfaces of the first region 141R1 and the second region 141R2 of the first protective layer 141.

[0218] As a result, the second region 141R2 of the first protective layer 141 may function as a dam in a process of applying the first connecting portion 210 in a semiconductor device mounting process. For example, the first connecting portion 210 is applied within the first opening 141T2 provided in the first region 141R1 of the first protective layer 141. In this case, the second region 141R2 of the first protective layer 141 may have a dam structure surrounding the first region 141R1 and having a height greater than that of the first region 141R1. Therefore, the second region 141R2 of the first protective layer 141 may facilitate the first connecting portion 210 being seated at a desired position during the process of applying the first connecting portion 210 within the first opening 141T2. As a result, the embodiment may facilitate a semiconductor package manufacturing process and further improve product yield.

[0219] The second region 141R2 of the first protective layer 141 can also function as a dam that prevents the underfill 230 disposed around the semiconductor element 220 disposed in the first region 141R1 from overflowing.

[0220] Furthermore, the fact that the upper surfaces of the first region 141R1 and the second region 141R2 of the first protective layer 141 have steps means that the first region 141R1 and the second region 141R2 have different thicknesses.

[0221] For example, the thickness of the first region 141R1 of the first protective layer 141 is smaller than the thickness of the second region 141R2.

[0222] In this case, the difference in thickness may mean, but is not limited to, that the number of layers in the first region 141R1 of the first protective layer 141 is smaller than the number of layers in the second region 141R2 of the first protective layer 141. For example, the first protective layer 141 may have a layer structure of one layer in the first region 141R1 and a layer structure of two or more layers in the second region 141R2.

[0223] Furthermore, although the first protective layer 141 has been described as including the first region 141R1 and the second region 141R2, the present invention is not limited to this.

[0224] For example, referring to FIGS. 10 and 11, the top surface of the first protective layer 141 may have at least two or more steps.

[0225] For example, the first protective layer 141 includes a first region 141R1 and a second region 141R2. The first protective layer 141 further includes a third region 141R3 between the first region 141R1 and the second region 141R2. The third region 141R3 of the first protective layer 141 has a step with the first region 141R1 and the second region 141R2. For example, the first protective layer 141 may include a first step SH1-1 between the first region 141R1 and the third region 141R3 and a second step SH1-2 between the second region 141R2 and the third region 141R3. For example, the top surface of the third region 141R3 of the first protective layer 141 is located higher than the top surface of the first region 141R1. In addition, the top surface of the third region 141R3 of the first protective layer 141 is positioned lower than the top surface of the second region 141R2. This allows the underfill 230 to be formed only in desired locations, thereby reducing the volume of the underfill 230 and, therefore, the manufacturing cost. Furthermore, the embodiment may include a first step SH1-1 adjacent to the region where the semiconductor element 220 is disposed, which can serve as an alignment mark for mounting the semiconductor element 220 in a desired location. This allows the embodiment to further simplify the mounting process of the semiconductor element 220 and, therefore, further improve the process yield.

[0226] 12, the horizontal separation distance between the first protective layer 141 and the second protective layer 142 may include at least two different first and second separation distances along the periphery of the outer surface of the second protective layer 142. The separation distance may refer to a first horizontal separation distance between the outer surface of the second protective layer 142 and the inner surface of the first protective layer 141 along the periphery of the outer surface of the second protective layer 142 and / or a second horizontal separation distance perpendicular to the first horizontal direction. The first horizontal direction may refer to any one of the horizontal direction, the x-axis direction, and the width direction. The second horizontal direction may refer to any one of the vertical direction, the y-axis direction, and the longitudinal direction perpendicular to the first horizontal direction.

[0227] That is, the horizontal distance between the inner surface of the through-hole 141T1 of the first protective layer 141 and the outer surface of the second protective layer 142 may include different intervals along the inner surface of the through-hole 141T1.

[0228] In this case, the separation distance and the interval may have the same meaning.

[0229] For example, as shown in Fig. 12, the separation distance may include a first separation distance HL1 and a second separation distance HL2, and may further include a third separation distance HL3.

[0230] Specifically, the inner surface of the first protective layer 141 that defines the through-hole 141T1 includes a protruding surface 141P and a concave surface 141C. The outer surface of the second protective layer 142 may also include a protruding surface 142P and a concave surface 142C.

[0231] The first separation distance HL1, the second separation distance HL2, and the third separation distance HL3 may be different from each other.

[0232] For example, the first separation distance HL1 may be greater than the second separation distance HL2, and the second separation distance HL2 may be greater than the third separation distance HL3. For example, among the first separation distance HL1, the second separation distance HL2, and the third separation distance HL3, the first separation distance HL1 may be the greatest and the third separation distance HL3 may be the smallest.

[0233] The first separation distance HL1 may refer to the horizontal distance between the regions of the separation area SA where the concave surface 141C on the inner surface of the first protective layer 141 and the concave surface 142C on the outer surface of the second protective layer 142 face each other horizontally.

[0234] In addition, the second separation distance HL2 may refer to the horizontal distance between the separation area SA and the area where the protruding surface 141P on the inner surface of the first protective layer 141 and the concave surface 142C on the outer surface of the second protective layer 142 face each other horizontally.

[0235] In addition, the third separation distance HL3 may refer to the horizontal distance between the separation area SA and the area where the concave surface 141C on the inner surface of the first protective layer 141 and the protruding surface 142P on the outer surface of the second protective layer 142 face each other horizontally.

[0236] At this time, the first separation distance HL1, the second separation distance HL2, and the third separation distance HL3 of the separation area SA may be different from one another depending on the arrangement structure of the second electrode 121 arranged in the separation area SA.

[0237] For example, in a first separation region of the separation region SA (e.g., a region corresponding to the first separation distance HL1), more second electrodes 121 may be arranged than in other separation regions, or traces connected to the second electrodes 121 may be concentrated.

[0238] Also, in a second separation region of the separation region SA (for example, a region corresponding to the second separation distance HL2), the second electrodes 121 and / or traces may be arranged with a lower density than in the first separation region.

[0239] Here, the integration density may refer to the ratio of an area occupied by the electrodes or traces of the first electrode unit 120 to a certain area. For example, a relatively high ratio of an area occupied by the electrodes or traces to a certain unit area of ​​the insulating layer 110 may indicate a high integration density.

[0240] Additionally, the second electrodes 121 and / or traces may be arranged in a third separation region of the separation region SA (eg, a region corresponding to the third separation distance HL3) with a lower density than the first and second separation regions.

[0241] In other words, the separation distance between the first electrodes and / or traces located in the first separation region may be smaller than the separation distance between the first electrodes and / or traces located in the second separation region and the third separation region.

[0242] That is, in the embodiment, first electrodes or traces that require no mutual signal interference or a short mutual signal transmission distance are concentrated in the first separation region. Also, in the embodiment, second electrodes and / or traces that require a certain separation distance due to mutual signal interference are placed in the second separation region or the third separation region. As a result, the embodiment can improve the electrical reliability of the semiconductor package and thereby improve the electrical signal characteristics.

[0243] In this case, the second electrodes 121 and traces can be arranged with the same integration density in the first to third separation regions, but in this case, the distance between the second electrodes to be connected to each other may increase, which may result in increased signal transmission loss. Furthermore, if the second electrodes 121 and traces are arranged with the same integration density in the first to third separation regions, the second electrodes, which cause mutual signal interference, must be spaced farther apart, which may increase the overall area of ​​the separation region SA. In this case, if the overall area of ​​the separation region SA increases, the number of electrodes and traces not protected by the first protective layer 141 and the second protective layer 142 may increase, which may cause problems with physical reliability and electrical reliability.

[0244] In addition, after arranging the second electrodes 121 and traces with different integration densities in the first to third isolation regions, the isolation distances of the isolation regions SA may all be configured to be the same along the inner surface of the first protective layer 141. However, in this case, the area of ​​the electrodes and traces that are not covered by the first protective layer 141 or the second protective layer 142 increases, which may cause problems such as the electrodes or traces being peeled off due to thermal stress, etc.

[0245] Therefore, in the embodiment, the separation region SA has different first and second separation distances along the inner surface of the first protective layer 141 and the outer surface of the second protective layer 142. Therefore, the embodiment has different circuit integration levels in the separation region SA, thereby minimizing signal transmission loss due to a reduction in signal transmission distance and improving signal transmission characteristics. Furthermore, in the embodiment, the separation distance in the separation region SA where the circuit integration level is relatively low is made smaller than the separation distance in the separation region SA where the circuit integration level is high. This minimizes reliability issues caused by traces not being covered by the first protective layer 141 or the second protective layer 142 in the separation region where the separation distance is small. This further improves the electrical and physical reliability of the semiconductor package.

[0246] In the above description, the upper protective layer 140 is described as being divided into the first protective layer 141 and the second protective layer 142, but is not limited thereto. For example, the upper protective layer 140 may refer to a single structure including a first opening corresponding to the isolation region SA, a second opening corresponding to the first opening 141T2 of the first protective layer 141, a third opening corresponding to the second opening 141T3 of the first protective layer 141, and a fourth opening corresponding to the opening 142T of the second protective layer 142.

[0247] FIG. 13 is a plan view showing the first electrode portion provided in region A of FIG. 1, and FIG. 14 is a plan view showing the state in which first and second protective layers are arranged on the first electrode portion of FIG. 13.

[0248] 13, the first electrode unit 120 of the substrate 100 includes a second electrode 121, a third electrode 122, and a fourth electrode 124. The first electrode unit 120 of the substrate 100 also includes a trace connected to at least one of the second electrode 121, the third electrode 122, and the fourth electrode 124.

[0249] The second electrode 121, the third electrode 122, and the fourth electrode 124 each represent a pad connected to a terminal 225 of a semiconductor device 220 mounted on the substrate 100. In addition, the first electrode 123 of the first electrode unit 120 is an electrode connected to an external substrate 300 via a conductive coupling part 160.

[0250] In this case, the terminals 225 of the semiconductor element 220 are disposed on the lower surface of the semiconductor element 220. The lower surface of the semiconductor element 220 may be divided into a plurality of regions. For example, the lower surface of the semiconductor element 220 may be divided into an inner region, an outer region, and an intermediate region therebetween. The terminals 225 of the semiconductor element 220 are disposed in the inner region, the outer region, and the intermediate region, respectively. The second electrode 121 of the first electrode unit 120 of the substrate 100 is connected to a terminal disposed in the intermediate region of the semiconductor element 220. The third electrode 122 of the first electrode unit 120 of the substrate 100 is connected to a terminal disposed in the outer region of the semiconductor element 220. The fourth electrode 124 of the first electrode unit 120 of the substrate 100 is connected to a terminal disposed in the inner region of the semiconductor element 220. In this case, at least one of the second electrode 121, the third electrode 122, and the fourth electrode 124 may have a width or shape different from at least one of the others. For example, the size and pitch of the terminals 225 of the semiconductor element 220 may vary depending on the arrangement position, so that the second electrode 121, the third electrode 122, and the fourth electrode 124 can have widths or shapes corresponding to the size and pitch of the terminals 225 of the semiconductor element 220.

[0251] For example, the second electrode 121 may have a different shape from the third electrode 122 and the fourth electrode 124. The second electrode 121 is connected to a terminal having a relatively small pitch and size among the terminals 225 of the semiconductor element 220. As a result, the plane area of ​​the second electrode 121 may be smaller than the plane areas of the third electrode 122 and the fourth electrode 124.

[0252] In this case, the second electrode 121 may include curved portions having a specific radius of curvature around the upper surface and straight portions connecting the curved portions. For example, the upper surface of the second electrode 121 may include a plurality of curved portions facing each other and a plurality of straight portions connecting the plurality of curved portions. For example, the plane of the second electrode 121 may have an elliptical shape, but is not limited thereto.

[0253] In this case, the width W1 of the second electrode 121 in the first horizontal direction may be smaller than the width W2 of the third electrode 122 in the first horizontal direction and the width W3 of the fourth electrode 124 in the first horizontal direction.

[0254] Furthermore, the first horizontal width W2 of the third electrode 122 and the first horizontal width W3 of the fourth electrode 124 may be the same as or different from each other. For example, the first horizontal width W2 of the third electrode 122 may be smaller than the first horizontal width W3 of the fourth electrode 124, but is not limited to this. The third electrode 122 and the fourth electrode 124 have a different shape from the second electrode 121. For example, the third electrode 122 and the fourth electrode 124 may have a circular shape.

[0255] Furthermore, the widths of second electrode 121, third electrode 122, and fourth electrode 124 in a second horizontal direction perpendicular to the first horizontal direction may be the same.

[0256] In this case, the second electrode 121 may have a circular shape with the same width in the first horizontal direction and the second horizontal direction, but in this case, the first connection portion 210 may overflow during the process of mounting the semiconductor element 220, which may cause an electrical short. That is, when the mounting process of the semiconductor element 220 is performed with the first connection portion 210 in place, pressure is applied to the first connection portion 210, causing the first connection portion 210 to expand in the horizontal direction. In this case, if the width of the second electrode 121 in the second horizontal direction is the same as the width W1 in the first horizontal direction, the expansion of the first connection portion 210 may cause a problem of contact with adjacent traces or electrodes.

[0257] Therefore, in the embodiment, the second electrode 121 has an elliptical shape with different widths in the first horizontal direction and the second horizontal direction. As a result, in the embodiment, the second electrode 121 has a shape that extends long in a direction where there is a relatively large pitch margin. As a result, in the embodiment, the first connection portion 210 extends in a direction where the risk of an electrical short circuit in the circuit is relatively low, thereby remarkably solving the problem of an electrical short circuit.

[0258] In addition, the width W1 in the first horizontal direction of the second electrode 121 disposed in the isolation region SA is smaller than the size of the opening that can be formed (or is dependent on the process capability) through the exposure and development process of the first protective layer 141 or the second protective layer 142. As a result, when openings that vertically overlap the respective second electrodes are formed after the first protective layer 141 or the second protective layer 142 is disposed in the isolation region SA, the top surface of at least one first electrode may not vertically overlap the opening depending on the process capability and process deviation of the shape of the opening, which may result in an electrical reliability issue in that the first electrode cannot be electrically connected to the semiconductor device 220.

[0259] Therefore, in the embodiment, the first protective layer 141 and the second protective layer 142 are not disposed in the separation area SA, and in order to minimize the area of ​​the separation area, the inner surface of the through hole 141T1 of the first protective layer 141 has a horizontal step, or the outer surface of the second protective layer 142 has a horizontal step. As a result, the embodiment can improve the electrical reliability and physical reliability of the semiconductor package.

[0260] Referring to FIG. 14, the first electrode portion 120 of the substrate 100 of the embodiment includes a second electrode 121 and a first trace arranged in the separation area SA between the first protective layer 141 and the second protective layer 142.

[0261] The first electrode unit 120 of the substrate 100 is also disposed adjacent to the isolated region SA and includes a third electrode 122 disposed in a region R1 that overlaps the first opening 141T2 of the first protective layer 141 in the vertical direction.

[0262] The first electrode portion 120 of the substrate 100 also includes a fourth electrode 124 disposed in a region R2 that overlaps with the opening 142T of the second protective layer 142 in the vertical direction.

[0263] Therefore, the embodiment includes the through-hole 141T1, the first opening 141T2, the second opening 141T3, and the opening 142T in the second protective layer 142, thereby allowing the second electrode 121, the third electrode 122, and the fourth electrode 124 to have different circuit integration levels depending on their positions. Therefore, the embodiment increases the circuit integration level in a specific region, thereby reducing the signal transmission distance between multiple electrodes, thereby minimizing signal transmission loss and improving signal transmission characteristics. Furthermore, the embodiment may reduce the separation distance between regions with relatively low circuit integration levels among the separated regions compared to regions with high circuit integration levels, thereby minimizing reliability issues caused by traces not being covered by the first or second protective layer in the separated regions with small separation distances. This further improves the electrical and physical reliability of the semiconductor package.

[0264] The embodiment can simplify the manufacturing process of the semiconductor package, can improve the product yield, and can improve the physical reliability and / or electrical reliability of the semiconductor package.

[0265] That is, the semiconductor package of the embodiment includes an insulating layer and a protective layer disposed on the insulating layer. The upper surface of the protective layer has a step. Specifically, the protective layer includes a first region vertically overlapping the semiconductor device and a second region excluding the first region, and the upper surfaces of the first region and the second region have a step. Preferably, the upper surface of the first region is located lower than the upper surface of the second region. Therefore, the step between the first region and the second region of the protective layer of the embodiment can function as a dam during a process of applying a connecting portion, such as solder, to mount the semiconductor device. For example, the step between the first region and the second region of the protective layer can guide the seating position so that the connecting portion moves to a specified position. This allows the connecting portion to be seated in an accurate position, thereby simplifying the manufacturing process. Furthermore, the embodiment uses the step between the first region and the second region of the protective layer to prevent the connecting portion from moving outside the semiconductor package, thereby reducing product manufacturing costs. Furthermore, the embodiment can facilitate the manufacturing process of semiconductor packages, and can further improve product yield.

[0266] In addition, the second region of the protective layer of the embodiment is provided to surround the periphery of the conductive coupling portion. Preferably, the second region of the protective layer of the embodiment is provided to entirely surround the side surface of the conductive coupling portion. This eliminates the need to form a separate molding member to surround the side surface of the conductive coupling portion, thereby simplifying the manufacturing process.

[0267] Furthermore, in the embodiment, the side surfaces of the conductive coupling part are entirely covered with a protective layer, which minimizes stress acting on the conductive coupling part, thereby resolving the reliability issue of cracks occurring at the interface between the conductive coupling part and the electrode part due to stress concentration on the conductive coupling part.

[0268] For example, in the prior art, a portion of a side of a conductive coupling part is covered with a protective layer, and the remaining portion is covered with a molding member. The protective layer and the molding member contain different insulating materials, and therefore have different thermal expansion coefficients. Therefore, one of the protective layer and the molding member may expand or contract more than the other. Therefore, different stresses may act on the side of the conductive coupling part that contacts the molding member and the side of the conductive coupling part that contacts the protective layer, which may reduce the physical reliability of the conductive coupling part.

[0269] According to another conventional technique, the entire side of the conductive coupling part may be in contact with the molding member. In this case, the molding member is laminated after mounting the semiconductor device on the substrate. Therefore, the entire top and side of the conductive coupling part may be exposed during the semiconductor device mounting process. Therefore, during the semiconductor device mounting process, physical impact may be applied to the conductive coupling part, which may cause the conductive coupling part to peel off from the electrode part. Furthermore, during the semiconductor device mounting process, foreign matter may accumulate on the top surface of the conductive coupling part, which may reduce the electrical reliability of the conductive coupling part.

[0270] In contrast, in the embodiment, the protective layer is provided to entirely surround the side surface of the conductive coupling portion, so that the expansion or contraction of the protective layer can apply uniform stress to the entire area of ​​the conductive coupling portion, thereby resolving the physical reliability issue of the conductive coupling portion peeling off from the electrode portion.

[0271] Furthermore, the embodiment can stably protect the conductive joint from impacts applied during the process of mounting a semiconductor element, thereby improving the physical reliability and / or electrical reliability of the conductive joint.

[0272] In addition, the protective layer of the embodiment includes first and second regions, a first protective layer having a through hole, and a second protective layer provided inside the through hole of the first protective layer. In this case, the first protective layer includes a protruding surface protruding inward toward the second protective layer. For example, the outer surface of the second protective layer includes a protruding surface protruding toward the first protective layer. Therefore, in the embodiment, the horizontal separation distance or gap between the inner surface of the through hole of the first protective layer and the outer surface of the second protective layer may include different separation distances or gaps along the inner surface of the through hole. For example, the separation distance may include a first separation distance and a second separation distance. The first separation distance and the second separation distance may be different from each other. For example, the first separation distance may be greater than the second separation distance.

[0273] In this embodiment, the second electrodes and traces of the electrode units may be densely arranged in a first separation region corresponding to the first separation distance, with a density higher than that of a second separation region corresponding to the second separation distance. For example, the spacing between the second electrodes and / or traces arranged in the first separation region may be smaller than the spacing between the second electrodes and / or traces arranged in the second separation region. This means that the density of the electrode units in the first separation region is higher than the density of the electrode units in the second separation region.

[0274] In this case, the second electrodes and traces can be arranged with the same density in the first and second separation regions, but in this case, the distance between the second electrodes to be connected to each other increases, which can lead to increased signal transmission loss. Furthermore, when the second electrodes and traces are arranged with the same density in the first and second separation regions, the second electrodes, which cause mutual signal interference, must be spaced farther apart, which can increase the overall area of ​​the separation region. Furthermore, when the overall area of ​​the separation region increases, the number of electrodes and traces not protected by the first and second protective layers increases, which can cause physical and electrical reliability problems.

[0275] Alternatively, after arranging the first electrodes and traces with different integration densities in the first and second isolation regions, the isolation distances of the isolation regions may all be configured to be the same along the inner surface of the first protective layer. However, in this case, the area of ​​the electrodes and traces that are not covered by the first or second protective layer increases, which may cause problems such as the electrodes or traces being peeled off due to thermal stress, etc.

[0276] Therefore, in the embodiment, the separation region SA has different first and second separation distances along the inner surface of the first protective layer and the outer surface of the second protective layer. Therefore, the embodiment allows the separation regions to have different circuit integration densities, thereby minimizing signal transmission loss due to a reduction in signal transmission distance and improving signal transmission characteristics. Furthermore, in the embodiment, the separation distance in a region of the separation region with a relatively low circuit integration density is made smaller than the separation distance in a region of a high circuit integration density. This minimizes reliability issues caused by traces not being covered by the first or second protective layer in a separation region with a small separation distance. This further improves the electrical and physical reliability of the semiconductor package.

[0277] 15 to 31 are cross-sectional views for explaining the manufacturing method of the semiconductor package according to the embodiment in the order of steps.

[0278] 1 will be described below in the order of steps with reference to Figures 15 to 31. Meanwhile, semiconductor packages of second and third embodiments can also be manufactured based on the manufacturing steps described below.

[0279] Referring to FIG. 15 , an embodiment provides a base material for manufacturing a substrate 100. For example, the embodiment provides a carrier board for manufacturing a substrate 100 having an ETS structure. The carrier board includes a carrier insulating layer CB1 and a carrier metal layer CB2 disposed on at least one surface of the carrier insulating layer CB1. Although FIG. 15 illustrates the carrier metal layer CB2 being disposed only on the lower surface of the carrier insulating layer CB1, this is not limiting. For example, the carrier metal layer CB2 may also be disposed on the upper surface of the carrier insulating layer CB1. This allows the embodiment to simultaneously manufacture multiple substrates 100 using carrier metal layers CB2 disposed on both sides of the carrier insulating layer CB1.

[0280] 16, in this embodiment, a carrier metal layer CB2 disposed on at least one surface of a carrier insulating layer CB1 is used as a seed layer, and a part of the first electrode portion 120 of the substrate 100 is formed on the lower surface of the carrier metal layer CB2. For example, in this embodiment, a process is performed to form an electrode 120a, which is an electrode portion disposed on the uppermost side of the substrate 100, on the lower surface of the carrier metal layer CB2.

[0281] Next, referring to FIG. 17, in an embodiment, once the electrode 120a is formed, the process of laminating the insulating layer 110, the process of forming the through hole, the process of forming the first electrode portion 120, and the process of forming the second electrode portion 130 can be performed at least once to form the substrate 100.

[0282] 18 , an embodiment may perform a process of removing the carrier board. For example, an embodiment may perform a process of separating the carrier insulating layer CB1 and the carrier metal layer CB2. Next, an embodiment may perform a process of removing the carrier metal layer CB2 disposed on the substrate 100 by etching. However, the embodiment is not limited thereto. For example, the carrier metal layer CB2 may be used as a seed layer for the conductive bonding portion 160. Therefore, the carrier metal layer CB2 may be removed by etching after the conductive bonding portion 160 is formed.

[0283] 19, in an embodiment, a process of laminating a first dry film DF1 on an insulating layer 110 may be performed. The first dry film DF1 includes an opening that vertically overlaps with a first electrode 121 that is disposed on the outer side of the electrodes 120a of the first electrode unit 120. Then, in an embodiment, a process of forming a conductive coupling part 160 that fills the opening of the first dry film DF1 on the first electrode 121 may be performed.

[0284] 20 , the embodiment may perform a process of removing the first dry film DF1. Thereafter, the embodiment may perform a process of removing the seed layer used for electroplating the conductive bonding portion 160. The seed layer may be, but is not limited to, a carrier metal layer CB2.

[0285] 21, in an embodiment, a process may be performed to form a first layer 141a of a first protective layer 141 of an upper protective layer 140 on a substrate 100. To this end, in an embodiment, a process may be performed in which an insulating material is applied to entirely cover the upper surface of the substrate 100, and the applied insulating material is removed by exposure and development to form a through hole 141T1 and a first opening 141T2 in the first protective layer 141.

[0286] Correspondingly, in the embodiment, a step of forming a lower protective layer 150 on the lower part of the substrate 100 can be performed.

[0287] 22 , the embodiment may perform a step of forming a second protective layer 142 inside the through-hole 141T1 of the first layer 141a of the first protective layer 141 on the substrate 100. At this time, in the step of forming the second protective layer 142, a separation area SA and an opening 142T in the second protective layer 142 may be formed between the second protective layer 142 and the first protective layer 141.

[0288] Meanwhile, in the above description, the process of forming the first layer 141a and the second protective layer 142 of the first protective layer 141 is performed step by step, but the present invention is not limited to this.

[0289] For example, as shown in FIG. 23, an embodiment may perform a process of forming an insulating material 140R to form a first layer 141a and a second protective layer 142 of a first protective layer 141 on a substrate 100.

[0290] Next, as shown in FIG. 24, the embodiment may also perform a process of removing the insulating material 140R by exposure and development to form the isolation region SA, the first opening 141T2 in the first protective layer 141, and the opening 142T in the second protective layer 142.

[0291] 25, the embodiment performs a process of forming a second dry film DF2 on the first layer 141a and the second protective layer 142 of the first protective layer 141. The second dry film DF2 may be formed on the remaining area of ​​the first protective layer 141 except for the peripheral area of ​​the first layer 141a.

[0292] 26, in this embodiment, a process of laminating a second layer 141b of the first protective layer 141 on the peripheral region of the first layer 141a of the first protective layer 141 and the conductive coupling portion 160 that are not covered by the second dry film DF2 may be performed. The second layer 141b of the first protective layer 141 may be provided to cover the conductive coupling portion 160. Thus, the first protective layer 141 may be provided with the first layer 141a and the second layer 141b. In this case, the area of ​​the second layer 141b of the first protective layer 141 is smaller than the area of ​​the first layer 141a. As a result, the first protective layer 141 may include an area provided with one layer and an area provided with two layers.

[0293] 27, the embodiment may perform a process of removing the second dry film DF2. Thereafter, the embodiment may perform a process of exposing and developing the first protective layer 141 to form a second opening 141T3 in an area vertically overlapping with the conductive coupling portion 160.

[0294] Thus, the first protective layer 141 may have a step on its upper surface while having the through-hole 141T1, the first opening 141T2, and the second opening 141T3.

[0295] Next, as shown in FIG. 28 , an embodiment may perform a process of arranging a first connection portion 210 on the substrate 100. For example, an embodiment may perform a process of arranging the first connection portion 210 on the second electrode 121 that vertically overlaps the isolation region SA, the third electrode 122 that vertically overlaps the first opening 141T2 of the first protective layer 141, and the fourth electrode 124 that vertically overlaps the opening 142T of the second protective layer 142. Also, an embodiment may perform a process of mounting a semiconductor element 220 on the first connection portion 210. As a result, the terminals 225 of the semiconductor element 220 may be electrically connected to the second electrode 121, the third electrode 122, and the fourth electrode 124, respectively, via the first connection portion 210. At this time, the semiconductor element 220 has a structure disposed on the second protective layer 142. Furthermore, at least a portion of the semiconductor element 220 may have a structure disposed on the first protective layer 141. 28 shows a single semiconductor device mounted on the substrate, but is not limited thereto. For example, a plurality of semiconductor devices may be mounted on the substrate spaced apart from one another in the horizontal direction. In this case, a connecting member 500 for connecting the plurality of semiconductor devices horizontally may be provided within the substrate.

[0296] 29, the embodiment may perform a process of forming an underfill 230 that covers the periphery of the semiconductor element 220 mounted on the substrate 100. At this time, the underfill 230 may be formed at a specified position through the step between the first region 141R1 and the second region 141R2 of the first protective layer 141.

[0297] 30, the embodiment may perform a process of forming a second connection portion 240 on the conductive coupling portion 160 that vertically overlaps with the second opening 141T3 of the first protective layer 141. Also, the embodiment may perform a process of forming a third connection portion 260 in the opening of the lower protective layer 150 disposed on the lower surface of the substrate 100.

[0298] 31 , in the embodiment, a process of forming a molding layer 250 that molds the upper part of the first protective layer 141, the upper part of the second protective layer 142, the second connecting portion 240, the semiconductor element 220, and the underfill 230 may be performed. In this case, in the embodiment, the process of forming the underfill 230 may be omitted. As a result, in the embodiment, the process up to the process of molding the semiconductor element 220 using the molding layer 250 may be performed. In addition, in the embodiment, a process of attaching an external substrate 300 on which a semiconductor element 420 is mounted onto the second connecting portion 240 may be performed.

[0299] Meanwhile, when a semiconductor package having the above-described inventive features is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, a semiconductor package having the features of the present invention can safely protect a semiconductor chip from external moisture and contaminants, and can solve problems such as leakage current, electrical shorts between terminals, and electrical open circuits in terminals supplying power to the semiconductor chip. Furthermore, when performing a signal transmission function, it can solve noise problems. As a result, a semiconductor package having the above-described inventive features can maintain stable functionality in IT devices or home appliances, and the entire product and the semiconductor package to which the present invention is applied can achieve functional integration or technical interrelationship with each other.

[0300] When a semiconductor package having the above-described features of the present invention is used in a transportation device such as a vehicle, it can solve the problem of distortion of signals transmitted to the transportation device, safely protect the semiconductor chip that controls the transportation device from the outside, and solve the problems of leakage current, electrical short circuits between terminals, and electrical open circuits of terminals supplying power to the semiconductor chip, thereby further improving the stability of the transportation device. Therefore, the transportation device and the semiconductor package to which the present invention is applied can be functionally integrated or technically linked to each other.

[0301] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person skilled in the art to which the embodiment belongs. Therefore, content related to such combinations and modifications should be interpreted as being included in the scope of the embodiments.

[0302] The above description focuses on the embodiments, but these are merely illustrative and do not limit the embodiments. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically illustrated in the embodiments can be modified and implemented. Differences related to such modifications and applications should be construed as being included within the scope of the embodiments defined in the appended claims.

Claims

1. an insulating layer; an electrode portion disposed on the insulating layer; a protective layer disposed on the electrode portion; a semiconductor element disposed on the protective layer; The protective layer is a first region vertically overlapping the semiconductor element; a second region disposed outside the first region and not overlapping the semiconductor element in a vertical direction; a step is provided between an upper surface of the first region and an upper surface of the second region; Semiconductor package.

2. The semiconductor package according to claim 1 , wherein an upper surface of the first region is located lower than an upper surface of the second region.

3. the second region is provided along a circumferential direction of the upper surface of the protective layer, The semiconductor package according to claim 1 , wherein the first region is provided inside the second region.

4. The semiconductor package according to claim 1 , wherein an upper surface of the second region of the protective layer is positioned higher than a lower surface of the semiconductor element and lower than an upper surface of the semiconductor element.

5. The protective layer is a first protective layer disposed on the insulating layer and including a through hole vertically overlapping the semiconductor element; The semiconductor package according to claim 1 , further comprising: a second protective layer disposed inside the through hole of the first protective layer and spaced apart from the first protective layer.

6. the first protective layer includes the first region and the second region, The semiconductor package according to claim 5 , wherein an upper surface of the second protective layer is disposed flush with an upper surface of the first region of the first protective layer.

7. the first protective layer includes the first region and the second region, The semiconductor package according to claim 5 , wherein an upper surface of the second protective layer is located lower than upper surfaces of the first and second regions of the first protective layer.

8. a conductive coupling portion that penetrates at least a portion of the second region of the first protective layer; The conductive coupling portion is the electrode portion is disposed on a first electrode that does not overlap the semiconductor element in a vertical direction, the second region of the first protective layer includes a first opening that vertically overlaps the conductive coupling portion; The semiconductor package according to claim 5 , wherein the second region of the first protective layer is provided to entirely surround a side surface of the conductive coupling portion.

9. The semiconductor package according to claim 8 , wherein an upper surface of the conductive coupling portion is positioned higher than a lower surface of the semiconductor element and lower than an upper surface of the semiconductor element.

10. The semiconductor package according to claim 5 , wherein an inner side surface of the through hole in the first protective layer includes a protruding surface that protrudes toward the second protective layer.

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