Microelectronic devices and related memory devices and electronic systems

Abstract

The microelectronic device includes a memory array region of memory cells, each of which includes a vertical stack structure spaced vertically from one another and including a conductive structure extending horizontally through the vertical stack of memory cells. The staircase region is horizontally located between two of the horizontally adjacent memory array regions and includes a first staircase structure extending horizontally from the vertical stack structure of a first of the two memory array regions and a second staircase structure extending horizontally from the vertical stack structure of a second of the two memory array regions. A lateral conductive contact provides a conductive path between a first step of the first staircase structure and a second step of the second staircase structure. Related microelectronic devices, memory devices, and electronic systems are also described.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims the benefit under 35 U.S.C. §119(e) of U.S. Provisional Patent Application No. 63 / 479,894, filed January 13, 2023, the disclosure of which is incorporated herein by this reference in its entirety.

[0002] The present disclosure, in various embodiments, relates generally to the field of microelectronic device design and fabrication. More particularly, the present disclosure relates to methods of microelectronic devices including lateral conductive contacts extending between stair structures operatively coupled to vertically stacked memory cells, and to related memory devices and electronic systems. [Background technology]

[0003] Microelectronic device designers often desire to increase the level of integration or density of features within a microelectronic device by reducing the size of individual features and by decreasing the separation distance between adjacent features. Furthermore, microelectronic device designers often desire to design architectures that are not only compact, but also offer performance advantages as well as simplified design.

[0004] An example of a microelectronic device is a memory device. Memory devices are commonly provided as internal integrated circuits within computers or other electronic devices. Many types of memory devices exist, including, but not limited to, volatile memory devices such as dynamic random access memory (DRAM) devices and nonvolatile memory devices such as NAND flash memory devices. A typical memory cell of a DRAM device includes one access device, such as a transistor, and one memory storage structure, such as a capacitor. Modern applications for semiconductor devices can use a significant amount of memory cells arranged in memory arrays representing rows and columns of memory cells. The memory cells may be electrically accessed through digit lines (e.g., bit lines, data lines) and word lines (e.g., access lines) arranged along the rows and columns of memory cells in the memory array. A memory array can be two-dimensional (2D), representing a single deck (e.g., single tier, single level) of memory cells, or three-dimensional (3D), representing multiple decks (e.g., multiple levels, multiple tiers) of memory cells.

[0005] As memory cell size has decreased, the density and complexity of memory arrays has increased. The increased density of memory cells within a memory array has also increased the density of conductive interconnect structures configured to facilitate operation of the memory cells. For example, the spacing between adjacent conductive interconnect structures has decreased with the increased density of memory cells within a memory array. However, the increased density of conductive interconnect structures presents challenges in properly forming the conductive interconnect structures in electrical communication with the memory cells. Furthermore, as the density of memory cells has increased, the amount of area occupied by electrical interconnects between components of the memory cells has increased. Summary of the Invention

[0006] In some embodiments, the microelectronic device comprises a memory array region, each comprising a vertical stack of memory cells comprising a vertical stack of access devices and a vertical stack of capacitors horizontally adjacent to the vertical stack of access devices, The memory array region further comprises vertical stack structures comprising conductive structures vertically spaced apart from one another and extending horizontally through the vertical stack of memory cells, the conductive structures adjacent to the access devices of the vertical stack of access devices. The staircase region is located horizontally between two of the memory array regions that are horizontally adjacent to each other, and includes: a first staircase structure extending horizontally from the vertical stack structure of a first of the two memory array regions and comprising a first step at a horizontal edge of the conductive structure of the vertical stack structure of the first of the two memory array regions; a second staircase structure extending horizontally from the vertical stack structure of a second of the two memory array regions and comprising a second step at a horizontal edge of the conductive structure of the vertical stack structure of the first of the two memory array regions; and a lateral conductive contact providing a conductive path between the first step of the first staircase structure and the second step of the second staircase structure.

[0007] In an additional embodiment, a microelectronic device comprises a memory array bank comprising a first memory array and a second memory array, the first memory array and the second memory array each comprising a vertical stack of dynamic random access memory (DRAM) cells, each DRAM cell comprising a storage device horizontally adjacent to an access device, and a vertical stack structure comprising vertically spaced apart conductive structures extending horizontally through the vertical stack of DRAM cells, the conductive structures of the vertical stack structure adjacent to a DRAM cell of the vertical stack of DRAM cells. The microelectronic device further comprises a horizontal staircase region between the first memory array and the second memory array. The staircase region comprises a first staircase structure extending horizontally from the vertical stack structure of the first memory array, a second staircase structure extending horizontally from the vertical stack structure of the second memory array, and lateral conductive contacts extending horizontally from the first staircase structure to the second staircase structure, each lateral conductive contact operably coupled to one step of the first staircase structure and one step of the second staircase structure.

[0008] In a further embodiment, a memory device comprises: a first memory array region comprising a first vertical stack of first dynamic random access memory (DRAM) cells, each of the first DRAM cells comprising a storage device of the vertical stack of storage devices and a horizontally adjacent access device of the vertical stack of access devices; a first vertical stack structure comprising vertically spaced apart first conductive structures extending horizontally through the first memory array region and terminating in a first staircase structure in a staircase region horizontally adjacent to the first memory array region; a second memory array region comprising a second vertical stack of second DRAM cells; a second vertical stack structure comprising vertically spaced apart second conductive structures extending horizontally through the second memory array region and terminating in a second staircase structure in the staircase region; and a lateral conductive contact electrically connecting a step of the first staircase structure to a step of the second staircase structure. [Brief explanation of the drawings]

[0009] [Figure 1A] 1 is a schematic partial top view of a microelectronic device according to an embodiment of the disclosure. [Figure 1B] 1 is a schematic partial cross-sectional view of a microelectronic device according to an embodiment of the disclosure. [Figure 1C] 1 is a schematic partial cross-sectional view of a microelectronic device according to an embodiment of the disclosure. [Figure 1D] FIG. 2 is a schematic partial top view of a portion of the staircase region of the microelectronic device of FIGS. 1A-1C. [Figure 1E] FIG. 2 is a schematic partial perspective view of a portion of the microelectronic device of FIGS. 1A-1C. [Figure 1F] FIG. 2 is a schematic partial perspective view of a portion of the microelectronic device of FIGS. 1A-1C. [Figure 1G] FIG. 2 is a schematic partial perspective view of a portion of the microelectronic device of FIGS. 1A-1C. [Figure 1H] 1A-1C are schematic diagrams illustrating electrical connections between horizontally adjacent stair structures of the microelectronic devices of FIGS. [Figure 2A] 1 is a schematic partial top view of a microelectronic device according to an embodiment of the disclosure. [Figure 2B] 2B is a schematic partial cross-sectional view of the microelectronic device of FIG. 2A taken through section line BB of FIG. 2A. [Figure 2C] 2B is a partial top view of an enlarged portion of the staircase region of the microelectronic device of FIG. 2A. [Figure 2D] 2B is a schematic partial perspective view of a portion of the microelectronic device of FIG. 2A. [Figure 2E] 2B is a schematic partial perspective view of a portion of the microelectronic device of FIG. 2A. [Figure 2F] 2B is a schematic partial perspective view of a portion of the microelectronic device of FIG. 2A. [Figure 2G] 1B is a schematic diagram illustrating the electrical connections between horizontally adjacent stair structures of the microelectronic device of FIG. 1A. [Figure 3A] 1 is a schematic top view of a microelectronic device according to an embodiment of the disclosure. [Figure 3B] 3B is a schematic top view of a portion of the staircase region of the microelectronic device of FIG. 3A. FIG. [Figure 4] 1 is a schematic top view of a portion of a staircase region of a microelectronic device according to an embodiment of the disclosure. [Figure 5] 10A-10C are schematic top views illustrating a portion of a staircase region of a microelectronic device according to additional embodiments of the disclosure. [Figure 6] 1 is a schematic block diagram of an electronic system according to an embodiment of the disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0010] The illustrations included herein are not intended to be actual diagrams of any particular system, microelectronic structure, microelectronic device, or integrated circuit thereof, but merely idealized representations used to describe embodiments of the present specification. Elements and features common between the figures may retain the same numerical designation, except that for ease of description below, the reference numeral may begin with the number of the drawing in which the element is introduced or most fully described.

[0011] The following description provides specific details, such as material types, material thicknesses, and processing conditions, to provide a complete description of the embodiments described herein. However, those skilled in the art will understand that the embodiments disclosed herein may be practiced without the use of these specific details. Indeed, the embodiments may be practiced in conjunction with conventional fabrication techniques used in the semiconductor industry. Furthermore, the description provided herein does not form a complete process flow for manufacturing a microelectronic device (e.g., semiconductor device, memory device), device, or electronic system, or a complete microelectronic device, device, or electronic system. The structures described below do not form a complete microelectronic device, device, or electronic system. Only the process acts and structures necessary to understand the embodiments described herein are described in detail below. Additional acts to form a complete microelectronic device, device, or electronic system from the structure may be performed by conventional techniques.

[0012] According to embodiments described herein, a microelectronic device includes an array region, each array region comprising a vertical stack of memory cells and a vertical stack structure comprising vertically spaced apart conductive structures extending horizontally through the array region. The vertical stack of memory cells comprises a respective vertical stack of storage devices, each storage device in contact with an access device in the vertical stack of access devices. The vertical stack structure terminates horizontally as a staircase structure in a staircase region horizontally adjacent the array region. Each of the array regions is horizontally bordered by at least one staircase region. In some embodiments, each array region includes a staircase structure extending horizontally from a different array region. The steps of the staircase structure are individually contacted by a conductive contact structure. The conductive contact structures of horizontally adjacent staircase structures extending horizontally from different array regions are in contact with a lateral conductive contact to electrically connect to and provide a conductive path between the conductive contact structures of the horizontally adjacent staircase structures. The lateral conductive contact extends horizontally between the staircase structures in the staircase region.

[0013] 1A-1C are simplified partial top view (FIG. 1A) and partial cross-sectional view (FIGS. 1B and 1C) of a microelectronic device 100 (e.g., a memory device such as a 3D DRAM memory device) according to an embodiment of the disclosure. From the description provided below, it will be readily apparent to those skilled in the art that the structures and microelectronic devices described herein with reference to FIGS. 1A-1C may be used in a variety of devices and electronic systems. Microelectronic device 100 may also be referred to herein as a die or a wafer.

[0014] FIG. 1A is a schematic partial top view of microelectronic device 100; FIG. 1B is a schematic partial cross-sectional view of microelectronic device 100 taken through section line BB of FIG. 1A; and FIG. 1C is a schematic partial cross-sectional view of microelectronic device 100 taken through section line CC of FIG. 1A.

[0015] 1A , a microelectronic device 100 includes array regions 102 (also referred to herein as “memory array regions”) that are horizontally adjacent to each other (e.g., in the X direction) and an array bank 101 (also referred to herein as “memory array bank”) that includes staircase regions 103 that are horizontally adjacent to the array regions 102 (e.g., in the X direction). In some embodiments, at least a portion of the staircase regions 103 are horizontally (e.g., in the X direction) interposed between horizontally (e.g., in the X direction) adjacent array regions 102, and at least a portion of the array regions 102 are horizontally (e.g., in the X direction) interposed between horizontally (e.g., in the X direction) adjacent staircase regions 103.

[0016] The stair region 103 may include a stair structure 174 that includes a conductive contact structure 176 coupled thereto. The conductive contact structure 176 may electrically connect one or more components of the microelectronic device 100 to circuitry of a second microelectronic device or to one or more additional components (e.g., sub-word line drivers).

[0017] In some embodiments, each of the staircase regions 103 exhibits approximately the same horizontal size (e.g., horizontal area in the XY plane) as each of the other staircase regions 103 of the staircase region 103. In other embodiments, at least some of the staircase regions 103 have a different horizontal size than the other staircase regions 103 of the staircase region 103.

[0018] 1A and 1B, the array region 102 of the array bank 101 individually includes vertical (e.g., Z-direction) stacks of memory cells 120 overlying the base structure 110. Each vertical stack of memory cells 120 includes a vertical stack of access devices 130 and a vertical stack of storage devices 150. A storage device 150 of a vertical stack of storage devices 150 is coupled to an access device 130 of a vertical stack of access devices 130. A vertical stack of access devices 130 may be horizontally adjacent (e.g., X-direction) to a vertical stack of storage devices 150. The vertical stacks of memory cells 120 may individually include vertically (e.g., Z-direction) spaced-apart levels of memory cells 120, each memory cell 120 including a storage device 150 horizontally adjacent to an access device 130.

[0019] 1A , each array region 102 may include subarrays 105, one of which is shown in box 105. Each subarray 105 includes, for example, two horizontally adjacent (e.g., in the Y direction) rows of vertical stacks of memory cells 120. In some embodiments, a conductive plate structure 142 is horizontally interposed between the two horizontally adjacent rows of vertical stacks of memory cells 120.

[0020] Global digit lines 108 (also called "conductive lines," "global bit lines," or "bit lines") extend horizontally (e.g., in the Y direction) through the array region 102 and overlap vertical stacks of memory cells 120 vertically (e.g., in the Z direction).

[0021] The global digit lines 108 may individually be formed of or include a conductive material such as, for example, one or more of a metal (e.g., tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold), a metal alloy, a metal-containing material (e.g., a metal nitride, a metal silicide, a metal carbide, a metal oxide), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrOx), ruthenium oxide (RuOx), a material including at least one of alloys thereof, a conductively doped semiconductor material (e.g., conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.), polysilicon, or other material exhibiting electrical conductivity. In some embodiments, the global digit lines 108 individually include tungsten. In another embodiment, the global digit lines 108 individually comprise copper.

[0022] The vertical stacks of memory cells 120 may individually include vertically (e.g., in the Z direction) spaced-apart levels of memory cells 120. Individual memory cells 120 may include storage devices 150 horizontally (e.g., in the Y direction) adjacent to access devices 130. While FIG. 1A illustrates that each of the array regions 102 includes sixty-four (64) vertical stacks of memory cells 120 (e.g., eight (8) rows and eight (8) columns of vertical stacks of memory cells 120), the disclosure is not so limited. Individual array regions 102 may include, for example, more than sixty-four (64) vertical stacks of memory cells 120. Similarly, while FIG. 1A illustrates that each subarray 105 includes sixteen (16) vertical stacks of memory cells 120, the disclosure is not so limited. Individual subarrays 105 may include, for example, more than sixteen (16) vertical stacks of memory cells 120 or fewer than sixteen (16) vertical stacks of memory cells 120.

[0023] The first base structure 110 may comprise a conventional silicon substrate (e.g., a conventional silicon wafer) or another bulk substrate comprising a semiconducting material. As used herein, the term “bulk substrate” refers to and includes not only silicon substrates, but also silicon-on-insulator (SOI) substrates, such as silicon-on-sapphire (SOS) and silicon-on-glass (SOG) substrates, epitaxial layers of silicon on a base semiconducting foundation, and other substrates formed of or including one or more semiconducting materials (e.g., one or more of silicon materials, such as monocrystalline silicon or polycrystalline silicon, silicon germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide). In some embodiments, the first base structure 110 comprises a silicon wafer.

[0024] In some embodiments, first base structure 110 includes different layers, structures, devices, and / or regions formed therein and / or thereon, and in some embodiments, first base structure 110 includes complementary metal-oxide-semiconductor (CMOS) circuits and devices configured to implement the operation of the vertical stack of memory cells 120 of microelectronic device 100.

[0025] 1B , the first base structure 110 may be electrically insulated from the vertical stack of memory cells 120 by a first insulating material 112 interposed vertically (e.g., in the Z direction) between the first base structure 110 and the vertical stack of memory cells 120. The first insulating material 112 may be formed of or include an insulating material such as, for example, one or more of an oxide material (e.g., silicon dioxide (SiO), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, titanium dioxide (TiO), hafnium oxide (HfO), zirconium dioxide (ZrO), hafnium dioxide (HfO), tantalum dioxide (TaO), magnesium oxide (MgO), aluminum oxide (AlO), or a combination thereof) and amorphous carbon. In some embodiments, the first insulating material 112 includes silicon dioxide.

[0026] Each access device 130 in the vertical stack of access devices 130 individually includes a channel region 134 including a channel material 116 that is in contact with at least a portion of a horizontally (e.g., in the Y direction) adjacent storage device 150 (e.g., the first electrode 152 of the horizontally adjacent storage device 150).

[0027] Channel material 116 may be formed of or include, for example, a semiconductive material (e.g., silicon). In some embodiments, channel material 116 includes silicon, such as epitaxially grown silicon. In some embodiments, channel material 116 includes a semiconductive material (e.g., polysilicon) doped with at least one N-type dopant or at least one P-type dopant. In some embodiments, at least some portions of channel material 116 are doped with one of at least one N-type dopant (e.g., arsenic ions, phosphorus ions, and antimony ions) and at least one P-type dopant (e.g., boron ions), and at least other portions of channel material 116 are doped with the other of at least one N-type dopant and at least one P-type dopant to form channel region 134.

[0028] Each of the access devices 130 may be individually operably coupled to one or more conductive structures 132 ( FIGS. 1A-1C ) (also referred to herein as “first conductive lines,” “access lines,” or “word lines”). Referring to FIG. 1C , the conductive structures 132 that overlap each other vertically (e.g., in the Z direction) and are within each other's horizontal boundaries (e.g., in the X direction, Y direction) may form a vertical stack structure 135 including conductive structures 132 spaced apart in the vertical direction (e.g., in the Z direction). The vertical stack structure 135 comprises levels of conductive structures 132 spaced apart in the vertical direction (e.g., in the Z direction) from each other.

[0029] 1A , each of the vertical stack structures 135 of conductive structures 132 extends horizontally (e.g., in the X direction) through the subarray 105 and terminates in a staircase structure 174 located in the staircase region 103 horizontally (e.g., in the X direction) adjacent to the array region 102 through which the vertical stack structure 135 extends horizontally. In some embodiments, each subarray 105 includes two vertical stack structures 135 that extend horizontally (e.g., in the X direction) through each subarray 105 and intersect the vertical stack of access devices 130.

[0030] The conductive structures 132 may extend horizontally (e.g., in the X direction; FIG. 1A ) through the subarray 105 (e.g., through a vertical stack of memory cells 120) as lines (e.g., word lines), and each may be configured to be operably coupled to an adjacent access device 130 in the vertical direction (e.g., in the Z direction) (e.g., the channel region 134 of the adjacent access device 130). In other words, the conductive structures 132 may be configured to be operably coupled to vertically adjacent access devices 130. Referring to FIG. 1C , the access devices 130 may be individually located vertically (e.g., in the Z direction) between predetermined portions of the conductive structures 132. In some embodiments, the access devices 130 are individually located vertically (e.g., in the Z direction) within the vertical boundaries of the conductive structures 132. The conductive structures 132 are individually adjacent to the memory cells 120 and are configured to be in electrical communication to provide voltages to the memory cells 120, such as by the access devices 130. In some embodiments, the conductive structure 132 is separated from the access device 130 by a dielectric material 140 .

[0031] The conductive structures 132 may individually be formed of or include a conductive material such as, for example, one or more of a metal (e.g., tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold), a metal alloy, a metal-containing material (e.g., a metal nitride, a metal silicide, a metal carbide, a metal oxide), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrOx), ruthenium oxide (RuOx), a material including at least one of alloys thereof, a conductively doped semiconductor material (e.g., conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.), polysilicon, or other material exhibiting electrical conductivity. In some embodiments, the conductive structures 132 individually include tungsten. In other embodiments, the conductive structures 132 individually include copper.

[0032] The conductive structures 132 may be individually configured to provide a sufficient voltage to the channel region 134 immediately vertically (e.g., in the Z direction) adjacent to the respective access device 130 to electrically couple the storage device 150 horizontally (e.g., in the Y direction) adjacent to and coupled to the access device 130, for example, to a conductive pillar structure (e.g., a conductive pillar structure 160, also referred to as a “local digit line”) extending vertically (e.g., in the Z direction) through or adjacent to the vertical stack of access devices 130 of a vertical stack of memory cells 120. In other words, each conductive structure 132 may individually comprise a gate structure configured to provide a sufficient voltage to the channel region 134 vertically (e.g., in the Z direction) adjacent to the conductive structure 132 to electrically couple the access device 130, including the channel region 134, to the horizontally (e.g., in the Y direction) adjacent storage device 150.

[0033] A vertical stack structure 135 including vertically spaced apart conductive structures 132 may intersect a vertical stack of memory cells 120 of a subarray 105, such as a vertical stack of access devices 130 of a vertical stack of memory cells 120. Each of the conductive structures 132 of the vertical stack structure 135 may intersect a level (e.g., a tier) of memory cells 120 of the vertical stack of memory cells 120. Each conductive structure 132 may intersect and comprise a portion of multiple vertical stacks of access devices 130 (e.g., gates of access devices 130).

[0034] 1A , each vertical stack structure 135 extends through and intersects several vertical stacks of access devices 130 of a vertical stack of memory cells 120. In some embodiments, each vertical stack structure 135 extends through adjacent vertical stacks of memory cells 120 in a horizontal direction (e.g., in the X direction). In some embodiments, the vertical stack structures 135 extending in a first horizontal direction (e.g., in the X direction) are spaced apart from each other in a second horizontal direction (e.g., in the Y direction).

[0035] 1A and 1B show that the conductive structures 132 of the vertical stack structure 135 individually intersect and form a predetermined portion of eight (8) vertical stacks of memory cells 120. In other embodiments, the conductive structures 132 of the vertical stack structure 135 individually intersect and form a predetermined portion of fewer than eight (8) vertical stacks of memory cells 120, such as four (4) vertical stacks of memory cells 120, five (5) vertical stacks of memory cells 120, or six (6) vertical stacks of memory cells 120. In other embodiments, the conductive structures 132 of the vertical stack structure 135 individually intersect and form a predetermined portion of more than eight (8) vertical stacks of memory cells 120, more than ten (10) vertical stacks of memory cells 120, more than twelve (12) vertical stacks of memory cells 120, more than sixteen (16) vertical stacks of memory cells 120, or more than twenty (20) vertical stacks of memory cells 120.

[0036] In some embodiments, vertically (e.g., in the Z direction) adjacent conductive structures 132 between vertically (e.g., in the Z direction) adjacent access devices 130 are spaced from each other by a second insulating material 119.

[0037] The second insulating material 119 may be formed of or include an insulating material that is different from and has an etch selectivity with respect to the channel material 116. In some embodiments, the second insulating material 119 is formed of or includes one or more of the materials described above with reference to the first insulating material 112. In some embodiments, the second insulating material 119 is formed of or includes an oxide material (e.g., silicon dioxide).

[0038] 1B and 1C in combination, each of the access devices 130 is surrounded by a dielectric material 140, which may be referred to herein as a "gate dielectric material." The channel region 134 is separated from the conductive structure 132 by the dielectric material 140. In other words, the conductive structure 132 is separated from the access device 130 by the dielectric material 140. In some embodiments, the portion of the conductive structure 132 that is directly vertically (e.g., in the Z direction) adjacent to and located within the horizontal (e.g., X-direction, Y-direction) boundary of the dielectric material 140 may be referred to as a "gate electrode."

[0039] 1C , each of the access devices 130 is substantially surrounded by a dielectric material 140, which in turn is substantially surrounded by conductive structures 132. In some such embodiments, the access devices 130 may individually comprise so-called “gate all around” access devices (e.g., gate-all around transistors) because each of the access devices 130 is individually substantially surrounded by one of the conductive structures 132.

[0040] Dielectric material 140 may be formed of or include an insulating material. By way of non-limiting example, dielectric material 140 may include one or more of phosphosilicate glass, borosilicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass, silicon dioxide, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, a nitride material (e.g., silicon nitride (Si3N4)), an oxynitride (e.g., silicon oxynitride), another gate dielectric material, a dielectric carbonitride material (e.g., silicon carbonitride (SiCN)), or a dielectric carboxynitride material (e.g., silicon carboxynitride (SiOCN)).

[0041] 1C, in some embodiments, dielectric material 140 is located on the surface of conductive structure 132 and also between conductive structure 132 and second insulating material 119. The portion of dielectric material 140 on the surface of second insulating material 119 may not be referred to as a "gate dielectric."

[0042] 1B , vertically (e.g., in the Z direction) adjacent access devices 130 are spaced from one another by a third insulating material 137. In some embodiments, the third insulating material 137 surrounds at least a portion of the dielectric material 140. The third insulating material 137 may be formed of or include an insulating material. In some embodiments, the third insulating material 137 includes silicon nitride.

[0043] 1A and 1B, in some embodiments, the storage device 150 is in contact with a conductive plate structure 142. The conductive plate structure 142 may be formed of or include a conductive material, such as one or more of the materials of the electrodes (e.g., second electrode 154) of the storage device 150. In some embodiments, the conductive plate structure 142 includes substantially the same material composition as the electrodes of the storage device 150. In other embodiments, the conductive plate structure 142 includes a different material composition than the electrodes of the storage device 150. The conductive plate structure 142 may be referred to herein as a "conductive plate" or a "ground structure." The conductive plate structure 142 extends horizontally (e.g., in the X direction) as a conductive plate. In some embodiments, and with reference to FIG. 1A, the conductive plate structure 142 extends horizontally in substantially the same direction as the conductive structure 132 and is substantially parallel thereto. The conductive plate structures 142 may be horizontally (eg, in the Y direction) between vertical stacks of memory cells 120, such as between vertical stacks of storage devices 150.

[0044] A vertical stack of storage devices 150 overlaps the base structure 110 in a vertical direction (e.g., in the Z direction). Each storage device 150 includes a first electrode 152 (also referred to herein as an “outer electrode,” “first electrode plate,” or “first node structure”), a second electrode 154 (also referred to herein as an “inner electrode,” “second electrode plate,” or “second node structure”), and a dielectric material 156 between the first electrode 152 and the second electrode 154. In some such embodiments, the storage devices 150 individually comprise capacitors. However, the disclosure is not so limited, and in other embodiments, storage device 150 may individually comprise other structures, such as, for example, phase change memory (PCM), resistance random-access memory (RRAM), conductive-bridging RAM, or another structure for storing logic states.

[0045] At least a portion of each storage device 150 contacts a horizontally (e.g., in the X direction) adjacent access device 130. In some embodiments, the first electrode 152 of each storage device 150 contacts (and directly contacts) the horizontally adjacent access device 130.

[0046] The first electrode 152 may be formed of or include a conductive material such as, for example, one or more of a metal (e.g., tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold), a metal alloy, a metal-containing material (e.g., a metal nitride, a metal silicide, a metal carbide, a metal oxide), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrOx), ruthenium oxide (RuOx), a material including at least one of alloys thereof, a conductively doped semiconductor material (e.g., conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.), polysilicon, or other material exhibiting electrical conductivity. In some embodiments, the first electrode 152 includes titanium nitride.

[0047] The second electrode 154 may be formed of or include a conductive material. In some embodiments, the second electrode 154 includes one or more of the materials described above with reference to the first electrode 152. In some embodiments, the second electrode 154 includes substantially the same material composition as the first electrode 152.

[0048] The dielectric material 156 may be formed of or include one or more of silicon dioxide (SiO), silicon nitride (SiN), polyimide, titanium dioxide (TiO), tantalum oxide (TaO), aluminum oxide (AlO), oxide-nitride-oxide materials (e.g., silicon dioxide-silicon nitride-silicon dioxide), strontium titanate (SrTiO) (STO), barium titanate (BaTiO), hafnium oxide (HfO), zirconium oxide (ZrO), ferroelectric materials (e.g., ferroelectric hafnium oxide, ferroelectric zirconium oxide, lead zirconate titanate (PZT)), and high-k dielectric materials.

[0049] The second electrode 154 may be in contact with one of the conductive plate structures 142 of the vertical stack of memory cells 120. In some embodiments, the second electrode 154 is substantially integral with the conductive plate structure 142. Referring to FIG. 1B , in some embodiments, second electrodes 154 ( FIG. 1B ) of horizontally (e.g., in the X-direction) adjacent vertical stacks of the storage device contact the same conductive plate structure 142. In some embodiments, the conductive plate structures 142 are individually formed of a conductive material, such as one or more of the materials of the second electrode 154. In some embodiments, the conductive plate structure 142 comprises substantially the same material composition as the second electrode 154. In other embodiments, the conductive plate structure 142 comprises a different material composition than the second electrode 154.

[0050] 1A and 1B, the microelectronic device 100 may include conductive pillar structures 160 extending vertically (e.g., in the Z direction) through the microelectronic device 100. The conductive pillar structures 160 may be referred to herein as “digit lines,” “second conductive lines,” “digit line pillar structures,” “local digit lines,” or “vertical digit lines.” The conductive pillar structures 160 may be electrically coupled to access devices 130 to facilitate operation of the memory cells 120 of the vertical stack of memory cells 120. In other words, each conductive pillar structure 160 extends vertically directly horizontally (e.g., in the Y direction) adjacent to and in contact with an access device 130 of the vertical stack of memory cells 120. In some embodiments, each vertical stack of memory cells 120 includes one of the conductive pillar structures that extends vertically (e.g., in the Z direction) and horizontally (e.g., in the Y direction) adjacent to the vertical stack of memory cells 120 (e.g., proximate the vertical stack of access devices 130 of the memory cells 120). As described above, application of a voltage to the conductive structure 132 vertically (e.g., in the Z direction) adjacent to the channel material 116 of the channel region 134 of the vertically adjacent access device 130 may induce a current through the channel region 134 to electrically connect the conductive pillar structure 160 to the storage device 150 horizontally (e.g., in the Y direction) adjacent to the access device 130.

[0051] In some embodiments, the conductive pillar structures 160 in horizontally (e.g., in the Y direction) adjacent vertical stack structures 135 at least partially overlap each other horizontally (e.g., in the X direction). In some embodiments, the conductive pillar structures 160 in horizontally (e.g., in the Y direction) adjacent vertical stack structures 135 are horizontally (e.g., in the X direction) aligned with each other. In other embodiments, the conductive pillar structures 160 in horizontally (e.g., in the Y direction) adjacent vertical stack structures 135 are horizontally (e.g., in the X direction) offset from each other.

[0052] In some embodiments, horizontally (e.g., in the Y direction) adjacent conductive pillar structures 160 of a vertical stack of memory cells 120 are connected to each other through a conductive portion 161 ( FIG. 1B ) located in a vertically (e.g., in the Z direction) lower portion of the microelectronic device 100 (e.g., directly above the first insulating material 112). In embodiments in which a conductive pillar structure 160 abuts a conductive portion 161 that electrically connects to a horizontally (e.g., in the Y direction) adjacent conductive pillar structure 160, the conductive pillar structure 160 may exhibit a U-shape and may be referred to as a “U-shaped conductive pillar structure” or a “U-shaped local digit line.”

[0053] In other embodiments, the conductive pillar structures 160 in contact with horizontally (e.g., in the Y direction) adjacent vertical stacks of memory cells 120 (e.g., vertical stacks of access devices 130) are electrically insulated from one another (e.g., do not include a conductive portion 161 extending horizontally (e.g., in the Y direction) between the horizontally adjacent conductive pillar structures 160). In some embodiments in which the microelectronic device 100 does not include a conductive portion 161, the horizontally (e.g., in the Y direction) adjacent conductive pillar structures 160 may be insulated from one another and may be referred to as "I-shaped conductive pillar structures" or "I-shaped local digit lines."

[0054] The conductive pillar structures 160 may individually be formed of or include one or more of a conductive material, such as a metal (e.g., tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold), a metal alloy, a metal-containing material (e.g., a metal nitride, a metal silicide, a metal carbide, a metal oxide), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrOx), ruthenium oxide (RuOx), a material including at least one of alloys thereof, a conductively doped semiconductor material (e.g., conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc.), polysilicon, or other material exhibiting electrical conductivity. In some embodiments, the conductive pillar structures 160 include tungsten.

[0055] 1A and 1B , in some embodiments, semiconductive material 170 vertically (e.g., in the Z direction) overlies the vertical stack of memory cells 120. In some embodiments, semiconductive material 170 comprises silicon. In some embodiments, semiconductive material 170 comprises single-crystal silicon. As described in further detail herein, semiconductive material 170 may be used to form one or more control logic devices of microelectronic device 100 to facilitate control operation of the memory cells 120 in the vertical stack of memory cells 120.

[0056] Transistor structures 185 may be located within the semiconductive material 170. The transistor structures 185 may each individually include conductively doped regions 188, each of which includes a source region 188A and a drain region 188B (collectively referred to herein as "conductively doped regions 188"). A channel region of the transistor structures 185 may be laterally interposed between the conductively doped regions 188. In some embodiments, the conductively doped regions 188 of each transistor structure 185 individually include one or more semiconductive materials doped with at least one conductivity-enhancing species, such as at least one N-type dopant (e.g., one or more of arsenic, phosphorus, antimony, and bismuth) or at least one P-type dopant (e.g., one or more of boron, aluminum, and gallium). In some embodiments, conductively doped region 188 comprises conductively doped silicon.

[0057] The transistor structure 185 includes additional transistors comprising a multiplexer 185A and a so-called “bleeder” transistor 185B (also referred to as a “leaker transistor”). The multiplexer 185A is horizontally adjacent (e.g., in the Y direction) to the conductive pillar structure 160, and the bleeder transistor 185B is horizontally adjacent (e.g., in the Y direction) to the conductive plate structure 142. The multiplexer 185A and the bleeder transistor 185B each comprise a gate structure 182 that vertically overlies the semiconductive material 170 and extends horizontally between conductively doped regions 188. The gate structure 182 of the multiplexer 185A comprises a multiplexer gate, and the gate structure 182 of the bleeder transistor 185B comprises a bleeder gate.

[0058] 1B, source region 188A is shown with a dashed line to indicate that source region 188A lies in a different plane than the plane of FIG. 1B. For example, source region 188A is offset horizontally (e.g., in the X direction, the Y direction) from drain region 188B. In some embodiments, drain region 188B of multiplexer 185A and drain region 188B of bleeder transistor 185B are aligned horizontally (e.g., in the X direction) with global digit line 108, which overlaps vertically (in the Z direction).

[0059] In some embodiments, each multiplexer 185A is horizontally adjacent (e.g., in the X direction or the Y direction) to one of the bleeder transistors 185B. In some embodiments, two bleeder transistors 185B are horizontally interposed (e.g., in the Y direction) between horizontally adjacent multiplexers 185A. In some embodiments, the conductive plate structure 142 is located between horizontally adjacent conductive pillar structures 160 (e.g., in the Y direction). Two multiplexers 185A may be horizontally interposed (e.g., in the Y direction) between the conductive plate structures 160, and two bleeder transistors 185B may be horizontally interposed between the multiplexers 185A. In some such embodiments, the multiplexers 185A are located closer to the conductive pillar structures 160 than the bleeder transistors 185B, and the bleeder transistors 185B are closer to the conductive pillar structures 142 than the multiplexers 185A.

[0060] In some embodiments, the source region 188A of the multiplexer 185A is shared with the horizontally adjacent bleeder transistor 185B. In other words, each multiplexer 185A has a source region 188A that is shared with the source region 188A of the horizontally adjacent bleeder transistor 185B. In other words, the source region 188A of the multiplexer 185A has the source region 188A of the bleeder transistor 185B. The multiplexer 185A and the horizontally adjacent bleeder transistor 185B may be referred to as "shared source" transistors.

[0061] In some embodiments, each of the source region 188A and the drain region 188B is in individual contact with a first conductive interconnect structure 192. The first conductive interconnect structure 192 in contact with the source region 188A and the conductive pillar structure 160 may electrically connect the source region 188A of the multiplexer 185A to the conductive pillar structure 160 by way of the routing structure 172. The first conductive interconnect structure 192 in contact with the drain region 188B of the multiplexer 185A may electrically connect the drain region 188B of the multiplexer 185A to the global digit line 108. In some embodiments, the first conductive interconnect structure 192 electrically connecting the multiplexer 185A to the global digit line 108 may be referred to as a “global digit line contact structure.”

[0062] In some embodiments, a first conductive interconnect structure 192 in contact with the drain region 188B of the bleeder transistor 185B and in contact with the conductive plate structure 142 electrically connects the bleeder transistor 185B to the conductive plate structure 142 by way of the routing structure 172.

[0063] The multiplexer 185A may be configured to selectively place a vertical stack of memory cells 120 into electrical communication with the global digit line 108 by way of a first conductive interconnect structure 192 electrically connecting the multiplexer 185A to the global digit line 108. By non-limiting example, a select voltage may be applied to the gate structure 182 of the multiplexer 185A to electrically connect the global digit line 108 to the vertical stack of memory cells 120 coupled to the multiplexer 185A. Application of the select voltage to the gate structure 182 of the multiplexer 185A may place the conductive pillar structures 160 of the selected vertical stack of memory cells 120 into electrical communication with the global digit line 108, which is in electrical communication with the conductive pillar structures 160. Thus, the conductive pillar structures 160 (e.g., local digit lines) of each vertical stack of memory cells 120 may be selectively coupled to the global digit line 108 by a multiplexer 185A between the conductive pillar structures 160 and the global digit line 108.

[0064] Each global digit line 108 may be configured to be selectively coupled to two or more of the conductive pillar structures 160 by a multiplexer 185A coupled to the global digit line 108. Each of the conductive pillar structures 160 is configured in electrical communication with the global digit line 108 and one of the multiplexers 185A by a first conductive interconnect structure 192 in contact with the global digit line 108 and the multiplexer 185A in electrical communication with the conductive pillar structure 160. In some embodiments, each global digit line 108 is configured in selective electrical communication with four (4) of the conductive pillar structures 160, each one of the conductive pillar structures 160 being coupled to a vertical stack of memory cells 120. In other embodiments, each of the global digit lines 108 is configured to be in selective electrical communication with eight (8) of the conductive pillar structures 160 or sixteen (16) of the conductive pillar structures 160. In use and operation, application of a voltage to the gate structure 182 of the multiplexer 185A induces a current in the channel region of the multiplexer 185A, electrically connecting the global digit line 108 (e.g., via the first conductive interconnect structure 192, the routing structure 172, and the drain region 188B of the multiplexer 185A) to the conductive pillar structure 160 (e.g., via the source region 188A of the multiplexer 185A, the first conductive interconnect structure 192 in contact with the source region 188A, and the routing structure 172). Thus, in some embodiments, the multiplexers 185A are individually configured to receive signals (e.g., select signals) from the multiplexer drivers and provide signals to bit lines (e.g., conductive pillar structures 160 (FIG. 1B)) to selectively access desired memory cells 120 in the array bank 101 to perform one or more control operations on the memory cells 120.

[0065] The bleeder transistors 185B may be individually configured to provide a bias voltage to the conductive pillar structures 160 to which the bleeder transistors 185B are coupled. In some embodiments, the conductive plate structures 142 coupled to the bleeder transistors 185B are configured to receive a voltage, such as a drain voltage Vdd or a voltage supply Vss, during use and operation. During use and operation, the bleeder transistors 185B are configured to provide a negative voltage to the conductive pillar structures 160 of unselected (e.g., inactive) vertical stacks of memory cells 120. In other words, the bleeder transistors 185B are configured to electrically connect the unselected conductive pillar structures 160 to their respective conductive plate structures 142 (e.g., ground structures, cell plates), which may be coupled to a negative voltage. In some embodiments, each vertical stack of memory cells 120 includes at least one (e.g., one) multiplexer 185A and at least one (e.g., one) bleeder transistor 185B.

[0066] The gate structure 182, the first conductive interconnect structure 192, and the routing structure 172 may individually be formed of or include a conductive material such as one or more of tungsten, copper, and aluminum.

[0067] The gate structure 182, the first conductive interconnect structure 192, and the routing structure 172 may be individually formed of a fourth insulating material 180. The fourth insulating material 180 may include one or more of the materials described above with reference to the first insulating material 112. In some embodiments, the fourth insulating material 180 includes silicon dioxide.

[0068] 1A and 1C collectively, the conductive structures 132 of the vertical stack structure 135 may terminate horizontally (e.g., in the X direction) with a stair structure 174 located at a horizontal (e.g., X direction) terminal portion (e.g., end) of the vertical stack structure 135. The stair structure 174 may be located within a stair region 103 that is horizontally (e.g., in the X direction) adjacent to the array region 102. Thus, the vertical stack structure 135 may include a portion that extends horizontally (e.g., in the X direction) through the array region 102 and a portion (e.g., stair structure 174) that extends horizontally (e.g., in the X direction) from the array region 102 into the stair region 103. While the stair structure 174 is shown in FIG. 1A , it will be understood that the stair structure 174 is located below a vertically (e.g., Z direction) upper surface of the microelectronic device 100. 1C , vertically (e.g., in the Z direction) taller conductive structures 132 may have smaller horizontal (e.g., X-direction) dimensions than vertically lower conductive structures 132, such that the horizontal (e.g., X-direction) edges of the conductive structures 132 at least partially define steps 175 of the staircase structure 174. In some embodiments, memory cells 120 of a vertical stack of memory cells 120 that are vertically (e.g., in the Z direction) taller than other memory cells 120 are intersected by conductive structures 132 that have smaller horizontal (e.g., X-direction) dimensions than the conductive structures 132 of vertically lower memory cells 120 in the vertical stack of memory cells 120.

[0069] In some embodiments, each vertical stack structure 135 may include one staircase structure 174 at only one horizontal (e.g., X-direction) end of the vertical stack structure 135. In some embodiments, each subarray 105 includes two vertical stack structures 135 of conductive structures 132 spaced horizontally (e.g., Y-direction) from each other. In some embodiments, the staircase structures 174 of the vertical stack structures 135 of conductive structures 132 of the same subarray 105 may be located at opposite horizontal (e.g., X-direction) ends of the microelectronic device 100. In some such embodiments, half of the vertical (e.g., Z-direction) stack structures 135 of the conductive structure 132 include a staircase structure 174 at a first horizontal (e.g., X-direction) end of the respective vertical stack structure 135, while the other vertical stack structures 135 of the conductive structure 132 each include a staircase structure 174 at a second horizontal (e.g., X-direction) end opposite the first horizontal end of each other vertical stack structure 135. In some embodiments, horizontally (e.g., Y-direction) adjacent vertical stack structures 135 of horizontally (e.g., Y-direction) adjacent subarrays 105 may be located at the same horizontal (e.g., X-direction) end of their respective subarrays 105.

[0070] 1A , in some embodiments, the stair structures 174 overlap each other horizontally (e.g., in the X direction). In some embodiments, at least a portion of an individual stair structure 174 does not overlap at least a portion of another stair structure 174 horizontally (e.g., in the X direction). In some embodiments, the stair structures 174 extending horizontally from the stack structures 135 of a subarray 105 are horizontally offset from each other in a first horizontal direction (e.g., in the X direction) and a second horizontal direction (e.g., in the Y direction). For example, referring to FIG. 1A , in some embodiments, a first staircase structure 174 extending horizontally (e.g., in the X direction) from the subarray 105 extends horizontally (e.g., in the X direction) into a first staircase region 103, and a second staircase structure 174 extending horizontally (e.g., in the X direction) from the subarray 105 extends horizontally (e.g., in the X direction) into a second staircase region 103 that is horizontally (e.g., in the X direction) adjacent to the first staircase region 103.

[0071] The quantity of steps 175 may correspond to the quantity of levels of memory cells 120 in the vertical stack. In some embodiments, the quantity of steps 175 in the staircase structure 174 is equal to the number of levels of memory cells 120 in the vertical stack of memory cells 120. Although FIGS. 1A and 1C show the staircase structures 174 individually comprising a particular number of steps 175 (e.g., eight (8)), the disclosure is not so limited. In other embodiments, the staircase structures 174 individually include a quantity of steps 175 ranging from thirty-two (32) steps 175 to two hundred fifty-six (256) steps 175. In some embodiments, the staircase structures 174 individually include sixty-four (64) steps 175. In other embodiments, the staircase structures 174 individually include more than ninety-six (96) steps 175. In some such embodiments, the individual vertical stacks of memory cells 120 in the microelectronic device 100 include a corresponding quantity of memory cells 120. In other embodiments, the stair structure 174 individually includes a different number of steps 175, such as fewer than sixty-four (64) steps 175 (e.g., sixty (60) or fewer steps 175, fifty (50) or fewer steps 175, less than about forty (40) steps 175, thirty (30) or fewer steps 175, twenty (20) or fewer steps 175, ten (10) or fewer steps 175), or more than sixty-four (64) steps 175 (e.g., seventy (70) or more steps 175, one hundred (100) or more steps 175, one hundred twenty-eight (128) or more steps 175, two hundred fifty-six (256) or more steps 175).

[0072] In some embodiments, the staircase structures 174 individually include the same amount of steps 175. In some embodiments, each step of each staircase structure 174 may be vertically (e.g., in the Z direction) offset from a vertically adjacent step 175 of the staircase structure 174 by one level (e.g., one tier) of vertically alternating conductive structures 132 and vertically (e.g., in the Z direction) intervening dielectric material 140 and second insulating material 119. In some such embodiments, all of the conductive structures 132 of a vertical stack structure 135 include a step 175 at a horizontal (e.g., X direction) end of the staircase structure 174 of the vertical stack structure 135.

[0073] 1A and 1C , the conductive contact structures 176 may contact individual conductive structures 132 at the steps 175. For example, the conductive contact structures 176 may individually physically contact (e.g., land on) predetermined portions of the upper surfaces of the conductive structures 132 that at least partially define the treads of the steps 175. Thus, each step 175 may contact a conductive contact structure 176 at a horizontal (e.g., X-direction) end of the stair structure 174.

[0074] The lateral conductive contacts 190 may vertically overlap and individually contact the conductive contact structures 176. Each of the conductive contact structures 176 may individually contact one of the lateral conductive contacts 190. The lateral conductive contacts 190 may be formed within the fourth insulating material 180.

[0075] The conductive contact structures 176 and the lateral conductive contacts 190 may individually be formed of or include a conductive material, such as one or more of the materials described above with reference to the conductive pillar structures 160. In some embodiments, the conductive contact structures 176 and the lateral conductive contacts 190 individually include substantially the same material composition as the conductive pillar structures 160. In other embodiments, the conductive contact structures 176 and the lateral conductive contacts 190 individually include a different material composition than the conductive pillar structures 160. In some embodiments, the conductive contact structures 176 and the lateral conductive contacts 190 individually include tungsten.

[0076] 1C , the fifth insulating material 159 may vertically (e.g., in the Z direction) overlie the stair structure 174. The fifth insulating material 159 may be formed of or include an insulating material such as one or more of the materials described above with reference to the first insulating material 112. In some embodiments, the fifth insulating material 159 includes silicon dioxide.

[0077] Referring to FIG. 1A , the lateral conductive contact 190 may extend horizontally (e.g., in the Y direction) between the conductive contact structures 176 of horizontally adjacent staircase structures 174. FIG. 1D is an enlarged portion of one of the staircase regions 103, showing the staircase structures 174 of the vertical stack structures 135 and a portion of the vertical stack structures 135 extending horizontally (e.g., in the X direction) from the array region 102 horizontally adjacent (e.g., in the X direction) to the staircase region 103 into the staircase region 103. FIG. 1E is a simplified perspective view showing box E of FIG. 1A but without the lateral conductive contact 190 or the conductive contact structures 176. FIG. 1F is a simplified perspective view showing the same view of FIG. 1E but including the conductive contact structures 176 but without the lateral conductive contact 190. FIG. 1G is a simplified perspective view showing the same view of FIG. 1E with the conductive contact structures 176 and the lateral conductive contact 190. The lateral conductive contacts 190 are shown with dashed lines in Figure 1G for clarity and ease of understanding the relative location of the lateral conductive contacts 190 with respect to the conductive contact structures 176 and the staircase structures 174. For clarity and ease of understanding the illustration, Figures 1D-1G do not show other components of the microelectronic device 100, such as the vertical stack of memory cells 102 within the array region 102.

[0078] 1A, 1C, and 1E-1G, and as described above, the horizontal (e.g., X-direction) dimension of the conductive structures 132 may decrease with increasing vertical (e.g., Z-direction) height of the steps 175 vertically above the base structure 110. In some embodiments, the steps 175 of the staircase structure 174 descend horizontally (e.g., X-direction) and vertically (e.g., Z-direction) outward from the array region 102 through which the vertical stack structures 135 extend.

[0079] Each stair structure 174 may exhibit a positive slope or a negative slope. In some embodiments, an imaginary line extending from the top of each half of the stair structure to the bottom of the stair structure 174 may have a positive slope, and another imaginary line extending from the top of the other half of the stair structure 174 to the bottom of the stair structure 174 may have a negative slope. For example, with reference to FIG. 1E , stair structure 174A may have a positive slope and stair structure 174B may have a negative slope. In some embodiments, the positive slope and the negative slope have the same magnitude (e.g., a positive slope may be X and a negative slope may be −X, where X is a number corresponding to the change in the vertical (e.g., Z) dimension of stair structure 174A divided by the change in the horizontal (e.g., X) dimension).

[0080] 1A , the positive X-direction may be defined as extending to the right in the view of FIG. 1A , and the negative X-direction may be defined as the direction opposite the positive X-direction (e.g., extending to the left in the view of FIG. 1A ). In some embodiments, stair structures 174 operably coupled to vertical stack structures 135 of the same subarray 105 (e.g., including conductive structures 132 extending horizontally (e.g., in the X-direction) through the same subarray 105) are located in different stair regions 103 and exhibit different slopes. For example, each subarray 105 may be operably coupled to one stair structure 174 having a positive slope and one stair structure 174 having a negative slope.

[0081] In some embodiments, at least some of the stair structures 174 exhibit the same slope (i.e., descend in the same horizontal direction (e.g., X direction)) as the nearest stair structure 174 in the horizontal direction (e.g., Y direction) (other than the terminal stair structure 174 in the horizontal direction (e.g., Y direction)). Within a particular stair region 103, stair structures 174 exhibiting the same slope (e.g., the same negative slope or the same positive slope) may extend horizontally (e.g., X direction) from the same array region 102, and stair structures 174 exhibiting a different slope (e.g., an opposite slope) may extend horizontally (e.g., X direction) from a different array region 102. In some embodiments, each stair structure 174 may be disposed next to the nearest stair structure 174 in the horizontal direction (e.g., Y direction) that includes conductive structures 132 extending horizontally (e.g., X direction) through the same array region 102 as the conductive structures 132 of the stair structure 174. The stair structure 174 on the horizontal side of the stair structure 174 opposite the nearest stair structure 174 in the horizontal direction (e.g., in the Y direction) may include a conductive structure 132 that extends horizontally (e.g., in the X direction) through the array region 102 different from the conductive structure 132 of the stair structure 174.

[0082] In some embodiments, each stair structure 174 is horizontally (e.g., in the Y direction) interposed between another stair structure 174 exhibiting the same slope as the stair structure 174 and an additional stair structure 174 exhibiting a different (e.g., opposite) slope than the stair structure 174.

[0083] 1A and 1G , a conductive pathway connects a lateral conductive contact 190 to a predetermined portion of the conductive structure 132 that defines the step 175 by a conductive contact structure 176. In some embodiments, the conductive pathway extends from each lateral conductive contact 190 through each conductive structure 132 in each step 175 of the first staircase structure 174 by a conductive contact structure 176 that overlaps vertically (e.g., in the Z direction) and horizontally (e.g., in the X direction or Y direction) with a portion of the conductive structure 132 that defines the step 175. The conductive pathway also operably couples a conductive structure 132 of the first staircase structure 174 to another individual conductive structure 132 in each step 175 of another staircase structure 174 by another conductive contact structure 176 that overlaps vertically (e.g., in the Z direction) and horizontally (e.g., in the X direction or Y direction) with a portion of another conductive structure 132 that defines the other step 175. The lateral conductive contacts 190 may each individually exhibit substantially the same horizontal (eg, Y-direction) length as one another.

[0084] 1A and 1D-1G collectively, steps 175 of horizontally (e.g., Y-direction) adjacent staircase structures 174 may overlap (e.g., substantially horizontally aligned) with each other horizontally (e.g., X-direction). In some such embodiments, lateral conductive contacts 190 extend horizontally (e.g., Y-direction) between horizontally (e.g., Y-direction) adjacent staircase structures 174. In some embodiments, the highest vertically (e.g., Z-direction) step 175 of a first staircase structure 174 that shares a lateral conductive contact 190 with a second staircase structure 174 is substantially laterally (e.g., X-direction) aligned with the lowest vertically (e.g., Z-direction) step 175 of the second staircase structure 174. The second highest vertically (e.g., Z-direction) step 175 of the first staircase structure 174 may be substantially laterally (e.g., X-direction) aligned with the second lowest vertically (e.g., Z-direction) step 175 of the second staircase structure 174. The lateral (e.g., X-direction) alignment of the steps 175 of the first stair structure 174 and the second stair structure 174 continues such that the vertically (e.g., Z-direction) lowest step 175 of the first stair structure 174 is substantially laterally (e.g., X-direction) aligned with the vertically (e.g., Z-direction) highest step 175 of the second stair structure 174.

[0085] Thus, if each stair structure 174 includes n steps 175, the nth step 175 of an individual stair structure 174 may comprise the highest step 175 that is closest horizontally (e.g., in the X direction) to the array region 102 from which the stair structure 174 extends, and the 1st step 175 may comprise the lowest step 175 that is furthest horizontally (e.g., in the X direction) from the array region 102 from which the stair structure 174 extends. In some embodiments, the conductive pathway operably couples the n-th step 175 of one of the staircase structures 174 to the 1-th step 175 of another of the staircase structures 174 by a first lateral conductive contact 190 of the lateral conductive contacts 190; the conductive pathway operably couples the n-1-th step 175 of one of the staircase structures 174 to the 2-th step 175 of another of the staircase structures 174 by a second lateral conductive contact 190 of the lateral conductive contacts 190; A third lateral conductive contact 190 of the conductive contacts 190 operably couples the n-2th step 175 of one of the stair structures 174 to the third step 175 of another of the stair structures 174; the conductive path between the step 175 of one of the stair structures 174 and the step 175 of another of the stair structures 174 continues until the first step 175 of one of the stair structures 174 is operably coupled to the nth step 175 of another of the stair structures 174.

[0086] In some embodiments, the conductive pathways operatively couple the steps 175 of each staircase structure 174 in electrical communication with the steps 175 of another staircase structure 174 that exhibits a different (e.g., opposite) slope than the staircase structure 174 by means of lateral conductive contacts 190. In some embodiments, two of the staircase structures 174 extending horizontally (e.g., in the X direction) from two different array regions 102 are configured to be in electrical communication with each other by a group of lateral conductive contacts 190 extending horizontally (e.g., in the Y direction) through one of the staircase regions 103 interposed horizontally (e.g., in the X direction) between the two different array regions 102. In some embodiments, the conductive structures 132 of the steps 175 of some staircase structures 174 that exhibit the same slope as each other may individually extend horizontally (e.g., in the X direction) outward from the vertical stack structures 135 that extend horizontally (e.g., in the X direction) within the first array region 102, and may be individually configured to be in electrical communication with the conductive structures 132 of the steps 175 of another staircase structure 174 that exhibits a different slope and extends horizontally (e.g., in the X direction) outward from the vertical stack structures 135 within a second array region 102 that is horizontally (e.g., in the X direction) adjacent to the first array region 102. In some embodiments, the step 175 of each staircase structure 174 defined by the edge of each vertical stack structure 135 extending horizontally (e.g., in the X direction) through the first array region 102 is configured to be in electrical communication with the step 175 of the horizontally (e.g., in the X direction, Y direction) nearest staircase structure 174 defined by the edge of another vertical stack structure 135 extending horizontally (e.g., in the X direction) through the second array region 102 by a lateral conductive contact 190.

[0087] In some embodiments, within each stair region 103, the stair structures 174 are interleaved with one another (e.g., offset from one another in the Y direction). In some such embodiments, pairs of stair structures 174 that are in electrical communication with the same group of lateral conductive contacts 190 are offset from one another in the horizontal direction (e.g., in the Y direction). In other words, pairs of stair structures 174 that share conductive paths between conductive structures 132 by the same group of lateral conductive contacts 190 are offset from one another in the horizontal direction (e.g., in the Y direction).

[0088] Referring to FIG. 1G, the conductive path between the conductive structure 132 defining the first step 175 of the first staircase structure 174 and the conductive structure 132 defining the nth step 175 of the second conductive staircase structure 174 is shown with dotted lines to show how horizontally (e.g., in the Y direction) adjacent staircase structures 174 of horizontally adjacent array regions 102 are electrically connected by lateral conductive contacts 190.

[0089] With continued reference to FIG. 1G, in some embodiments, the lateral conductive contacts 190 individually exhibit substantially the same vertical (eg, Z-direction) position as one another.

[0090] FIG. 1H is a schematic diagram illustrating electrical connections between horizontally adjacent (e.g., Y-direction) staircase structures 174 of horizontally adjacent (e.g., X-direction) subarrays 105 of an array region 102. In the view of FIG. 1H, the Y-direction is into and out of the page. Accordingly, a first staircase structure 174 (e.g., the left staircase structure 174) is shown with a dashed line to indicate that the first staircase structure 174 is located in a different plane than the second staircase structure 174. FIG. 1H shows only a portion of the conductive structures 132 for simplicity and ease of understanding. Referring to FIG. 1H, the conductive structures 132A, 132B, 132C that partially define the first staircase structure 174 share a conductive path with the conductive structures 132A, 132B, 132C that partially define the second staircase structure 174 by means of lateral conductive contacts 190. FIG. 1H illustrates how the conductive structures 132A, 132B, 132C that partially define the first staircase structure 174 individually share their respective conductive paths with (e.g., are in individual electrical communication with) the corresponding conductive structures 132A, 132B, 132C that partially define the second staircase structure 174 based on the vertical (e.g., Z-direction) heights of the conductive structures 132A, 132B, 132C of the two staircase structures 174.

[0091] 1E-1H , the conductive structures 132 of the vertically (e.g., Z-direction) lowest steps 175 (e.g., vertically lowest halves of the steps 175) of the staircase structures 174 extending from horizontally (e.g., X-direction) adjacent array regions 102 may overlap each other horizontally (e.g., X-direction). In other words, the conductive structures of the vertically (e.g., X-direction) lowest steps 175 of the staircase structures 174 extending from horizontally (e.g., X-direction) adjacent array regions 102 may be located within each other's horizontal (e.g., X-direction) boundaries. In some embodiments, the conductive structures 132 of the vertically (e.g., Z-direction) highest steps 175 (e.g., vertically highest halves of the steps 175) of the staircase structures 174 extending from horizontally (e.g., X-direction) adjacent array regions 102 may not overlap each other horizontally (e.g., X-direction). In other words, the conductive structures 132 of the vertically highest steps 175 of the staircase structures 174 extending from horizontally (e.g., in the X direction) adjacent array regions 102 may be located outside their horizontal (e.g., X direction) boundaries.

[0092] Forming the microelectronic device 100 to include a staircase region 103 including a staircase structure 174 extending horizontally (e.g., in the positive X direction) outward from the first array region 102 electrically connected by lateral conductive contacts 190 to a staircase structure 174 extending horizontally (e.g., in the negative X direction) outward from the second array region 102 facilitates reducing the area of ​​the microelectronic device 100 occupied by conductive interconnects and conductive routing for the steps 175 of the staircase structure 174 (e.g., for electrically connecting the conductive structure 132 to one or more devices, such as for providing an access voltage to the access device 130).

[0093] The lateral conductive contacts 190 may each be individually configured to be in electrical communication with one or more other devices. In some embodiments, the lateral conductive contacts 190 may each be individually configured to be in electrical communication with a sub-word line driver device. In some such embodiments, the lateral conductive contacts 190 and the conductive structures 132 that partially define the steps 175 of the staircase structure 174 that are coupled to each other by the conductive contact structures 176 are configured to be in electrical communication with the same sub-word line driver.

[0094] Electrically connecting the conductive structures 132 defining the relatively vertically (e.g., in the Z direction) tall steps 175 of the first staircase structure 174 to the conductive structures 132 defining the relatively vertically (e.g., in the Z direction) shorter steps 175 of the second staircase structure 174 facilitates forming the conductive structures 132 to present the same load (e.g., the same word line load) during use and operation of the microelectronic device 100. For example, during access of the memory cells 120 electrically connected to the conductive structures 132, the conductive structures 132 may each individually present substantially the same load due to the electrical connection extending between the first staircase structure 174 and the second staircase structure 174.

[0095] Although the microelectronic device of FIGS. 1A-1H is described and shown as having a stair region 103 including stair structures 174 with particular orientations relative to one another, the disclosure is not so limited. In additional embodiments, microelectronic device 100 may be formed to have a configuration different from that described above with reference to FIGS. 1A-1G. Microelectronic device 100 may be formed to exhibit a configuration such as, for example, one of the configurations shown in FIGS. 2A-2F, 3A and 3B, 4, and 5, and described in further detail below. It will be readily apparent to those skilled in the art from the description provided below that the structures and devices described herein may be included in larger structures, devices, and systems.

[0096] Before referring to FIG. 2A , it will be understood that throughout FIGS. 2A-5 and the associated description, features (e.g., regions, materials, structures, devices) that are functionally similar to features described above (e.g., materials, structures, devices described above) will be referenced with like reference numerals incremented by 100. To avoid repetition, not all features shown in FIGS. 2A-5 will be described in detail herein. Rather, unless otherwise stated below, it will be understood that one or more features of FIGS. 2A-5 designated by reference numerals that are increments of 100 of the reference numerals of features described above with reference to one or more of FIGS. 1A-1H are substantially similar to, and have substantially the same advantages as, the above-described features. Furthermore, unless otherwise stated below, it will be understood that one or more features of Figures 3A-5 designated by reference numerals that are increments of 100 from the reference numerals of features described above with reference to the preceding one or more of Figures 2A-4 are substantially similar to the above-described features and have substantially the same advantages. By way of non-limiting example, unless otherwise stated below, it will be understood that the features designated by reference numerals 290, 390, 490, and 590 in Figures 2A-2G, 3A and 3B, 4, and 5, respectively, are substantially similar to and have substantially the same advantages as lateral conductive contact 190 described herein above with reference to Figures 1A-1H. Additionally, for clarity and ease of understanding the drawings and associated description, some features (e.g., structures, materials, regions, devices) described above with reference to one or more of Figures 1A-1H are not shown in Figures 2A-2G, 3A and 3B, 4, and 5. However, unless otherwise stated below, it will be understood that any feature of microelectronic device 100 described above with reference to Figures 1A-1H may be included in any of the different configurations described hereinafter with reference to Figures 2A-2G, 3A and 3B, 4, and 5.As a non-limiting example, features substantially similar to the channel material 116 described above with reference to Figures 1B and 1C may be included in different configurations described below with reference to Figures 2A-2G, 3A and 3B, 4, and 5.

[0097] FIG. 2A is a schematic partial top view of a microelectronic device 200 according to an embodiment of the disclosure. FIG. 2B is a schematic partial cross-sectional view of the microelectronic device 200 of FIG. 2A taken through section line BB. FIG. 2C is an enlarged portion of a portion of one of the staircase regions 203, showing a vertical stack structure 235 of conductive structures 232 extending horizontally (e.g., in the X direction) within the staircase region 203 and terminating in a respective staircase structure 274. FIG. 2D is a schematic perspective view showing box D of FIG. 2A but without the lateral conductive contact 290 or the conductive contact structure 276. FIG. 2E is a schematic perspective view showing the same view of FIG. 2D but including the conductive contact structure 276 and without the lateral conductive contact 290. FIG. 2F is a schematic perspective view showing the same view of FIG. 2D but including the conductive contact structure 276 and the lateral conductive contact 290. For clarity and ease of understanding, lateral conductive contact 290 is shown with dashed lines in Figure 2F to indicate the relative location of lateral conductive contact 290 with respect to conductive contact structure 276 and staircase structure 274. For clarity and ease of understanding, Figures 2C-2F do not show other components of microelectronic device 100, such as the vertical stack of memory cells 120 in array region 202. Figure 2G is a schematic diagram illustrating the electrical connection between horizontally adjacent staircase structures of the microelectronic device of Figure 2A.

[0098] 2A , a microelectronic device 200 includes array regions 202 spaced apart horizontally (e.g., in the X direction) from one another. The array regions 202 are substantially similar to the array regions 102 described above with reference to FIGS. 1A and 1B . Staircase regions 203, including odd staircase regions 203A and even staircase regions 203B (collectively referred to as “staircase regions 203”), are horizontally adjacent (e.g., in the X direction) to the array regions 202. In some embodiments, the staircase regions 203 are interposed horizontally (e.g., in the X direction) between horizontally adjacent array regions 202.

[0099] Horizontally (e.g., in the X direction) adjacent array regions 202 may be horizontally (e.g., in the Y direction) offset from one another. For example, referring to FIG. 2A , each conductive plate structure 242 in an array region 202 may be horizontally (e.g., in the Y direction) offset from the conductive plate structures 242 of the horizontally (e.g., in the X direction) adjacent array region 202. In some embodiments, the subarrays 205 of horizontally (e.g., in the X direction) adjacent array regions 202 are horizontally (e.g., in the Y direction) offset from one another by approximately half the pitch of the subarrays 205 (e.g., in the Y direction). In some embodiments, the conductive plate structures 242 of a first array region 202 are horizontally (e.g., in the Y direction) interposed between the vertical stack structures 235 (and associated staircase structures 274 in the staircase region 203) of a second horizontally (e.g., in the X direction) adjacent array region 202. For example, in some embodiments, the conductive plate structures 242 in a first array region 202 may be horizontally (e.g., in the Y direction) between the first vertical stack structures 235 of the first subarray 205 and the second vertical stack structures 235 of the second subarray 205 of the second array region 202 that are horizontally (e.g., in the X direction) adjacent to the first subarray 205. In some embodiments, the conductive plate structures 242 in each array region 202 are horizontally (e.g., in the Y direction) aligned with the conductive pillar structures 260 of the horizontally (e.g., in the X direction) adjacent array region 202.

[0100] In some embodiments, the subarrays 205 of every other array region 202 (e.g., in the X direction) are horizontally aligned (e.g., in the Y direction) with one another. For example, the conductive plate structures 242 of every other array region 202 of an array region 202 are horizontally aligned (e.g., in the Y direction) with one another.

[0101] 2A-2F , vertical stack structures 235 including conductive structures 232 extend horizontally (e.g., in the X direction) through array region 202, as described above with reference to vertical stack structures 135, and terminate in staircase regions 203 horizontally (e.g., in the X direction) adjacent to array region 202 through which each individual vertical stack structure 235 extends horizontally. In some embodiments, each vertical stack structure 235 terminates horizontally (e.g., in the X direction) in a staircase structure 274 at each horizontal (e.g., X direction) end of the vertical stack structure 235. In some such embodiments, each vertical stack structure 235 includes two staircase structures 274 (e.g., one staircase structure 274 at each horizontal end of the vertical stack structure 235).

[0102] 2B , in some embodiments, vertically (e.g., in the Z direction) adjacent steps 275 of staircase structures 274 on a first horizontal (e.g., X direction) side of a vertical stack structure 235 may be vertically (e.g., in the Z direction) offset by two levels (e.g., two tiers) of vertically alternating conductive structures 232 and vertically intervening dielectric material 240 and second insulating material 219. In some such embodiments, the steps 275 of each staircase structure 274 are formed by every other conductive structure 232 of the vertical stack structure 235, and the steps 275 of staircase structures 274 at horizontally (e.g., X direction) opposite ends of the same vertical stack structure 235 may be defined by conductive structures 232 that are vertically (e.g., in the Z direction) spaced apart from each other by one level of vertically intervening conductive structures 232 and vertically intervening dielectric material 240 and second insulating material 219. For example, and referring to FIG. 2B , the step 275 of a first staircase structure 274 of the vertical stack structure 235 is offset vertically (e.g., in the Z direction) from the step 275 of a second staircase structure 274 of the vertical stack structure 235 that is located at an opposite horizontal (e.g., X direction) end of the vertical stack structure 235 relative to the first staircase structure 274.

[0103] In some embodiments, every other conductive structure 232 of a staircase structure 274 may include a conductive contact structure 276 in contact with the conductive structure 232. In other words, every other conductive structure 232 of a staircase structure 274 may be in individual contact with a conductive contact structure 276. In some such embodiments, each vertical stack structure 235 may include one staircase structure 274 at each horizontal (e.g., X-direction) end of the vertical stack structure 235, and each conductive structure 232 of a first staircase structure 274 at a first horizontal end of the vertical stack structure 235 that is not in contact with a conductive contact structure 276 (e.g., the vertically lower conductive structure 232 of a pair of conductive structures 232 defining a step 275) may be in individual contact with a conductive contact structure 276 of a second staircase structure 274 at a second, opposing horizontal end of the vertical stack structure 235.

[0104] In some embodiments, every other stair region 203 of the stair region 203 comprises an odd stair region 203A, and the other stair region 203 comprises an even stair region 203B. In other words, the even stair regions 203B may be horizontally (e.g., in the X direction) interposed between horizontally (e.g., in the X direction) adjacent odd stair regions 203A, and the odd stair regions 203A may be horizontally (e.g., in the X direction) interposed between horizontally (e.g., in the X direction) adjacent even stair regions 203A. The steps 275 of the stair structure 274 in the odd stair region 203A may comprise odd steps 275, and the steps 275 of the stair structure 274 in the even stair region 203B may comprise even steps 275. In some embodiments, the steps 275 in the odd staircase region 203A are vertically aligned (e.g., in the Z direction) with each other and are vertically offset (e.g., in the Z direction) from the steps 275 in the even staircase region 203B by vertically alternating conductive structures 232 and one level of vertically intervening dielectric material 240 and second insulating material 219.

[0105] As described above with reference to stair structure 174, each of stair structures 274 may exhibit a positive slope or a negative slope. In some embodiments, an imaginary line extending from the top of each half of stair structure 274 to the bottom of stair structure 274 may have a positive slope, and another imaginary line extending from the top of the other half of stair structure 274 to the bottom of stair structure 274 may have a negative slope. For example, with reference to FIG. 2D , stair structure 274A may have a positive slope and stair structure 274B may have a negative slope. In some embodiments, the positive slope and negative slope have the same magnitude (e.g., a positive slope may be X and a negative slope may be −X, where X is a number corresponding to the change in the vertical (e.g., Z) dimension of stair structure 274 divided by the change in the horizontal (e.g., X) dimension).

[0106] 2A and 2D-2F , a pair of staircase structures 274 in a first staircase region 203 extending horizontally (e.g., in the positive X direction) outward from a first array region 202 and horizontally (e.g., in the X direction) adjacent to the first array region 202 may exhibit the same slope as each other (e.g., the same positive slope), and an additional pair of staircase structures 274 extending horizontally (e.g., in the negative X direction) outward from a second adjacent array region 202 and in the first staircase region 203 may exhibit the same slope as each other and a different slope (e.g., the same negative slope) from the pair of staircase structures 274. Furthermore, a further pair of staircase structures 274 extending horizontally (e.g., in the negative X direction) outward from the first array region 202 in a second staircase region 203 on an opposite side of the first array region 202 to the first staircase region 203 may have a different slope from the pair of staircase structures 274. In some embodiments, the additional pair of stair structures 274 and the further pair of stair structures 274 have substantially the same slope as each other.

[0107] The stair structures 274 extending horizontally (e.g., in the positive X direction) from the vertical stack structures 235 of the array region 202 into the individual stair regions 203 may exhibit substantially the same slope as one another. In some embodiments, the individual stair structures 274 in the individual stair regions 203 are horizontally (e.g., in the Y direction) between additional stair structures 274 exhibiting the same slope as the stair structure 274 and further stair structures 274 exhibiting a different (e.g., opposite) slope than the stair structure 274.

[0108] 2A, 2C, and 2F, lateral conductive contacts 290 may extend horizontally (e.g., in the Y direction) between conductive contact structures 276 that contact respective conductive structures 232 of horizontally (e.g., in the Y direction) adjacent stair structures 274 that extend horizontally (e.g., in the X direction) from different array regions 202. Referring to FIG. 2F, lateral conductive contacts 290 share a conductive path with conductive structures 232 that define steps 275 with conductive contact structures 276. In some embodiments, each lateral conductive contact 290 shares a conductive path with (e.g., is in electrical communication with) the conductive structure 232 defining one step 275 of the first staircase structure 274 by way of a conductive contact structure 276 in contact with the conductive structure 232 defining the step 275, and shares a conductive path with another conductive structure 232 of another step 275 of the second staircase structure 274 that extends from a different array region 202 than the first staircase structure 274 by way of a conductive contact structure 276 in contact with another step 275. In some embodiments, each lateral conductive contact 290 shares a conductive path with (e.g., is in electrical communication with) the conductive structure 232 defining the first step 275 of the first staircase structure 274 and the conductive structure 232 defining the second step 275 of the second staircase structure 274 that has a different height than the first step 275.

[0109] In Figure 2F, the electrical connection between the conductive structure 232 of the vertically (e.g., in the Z direction) highest step 275 of the first staircase structure 274 and the conductive structure 232 of the vertically (e.g., in the Z direction) lowest step 275 of the horizontally (e.g., in the Y direction) adjacent second staircase structure 274 by the lateral conductive contact 290 is shown by a dashed line.

[0110] 2A, 2C, 2D, and 2E, in some embodiments, the steps 275 of horizontally (e.g., in the Y direction) adjacent stair structures 274 within each stair region 203 are aligned horizontally (e.g., in the X direction). Lateral conductive contacts 290 may extend horizontally (e.g., in the Y direction) between horizontally (e.g., in the Y direction) adjacent stair structures 274.

[0111] In some embodiments, each of the lateral conductive contacts 290 has substantially the same horizontal (eg, Y-direction) length as one another and is located at substantially the same vertical (eg, Z-direction) elevation as one another.

[0112] In some embodiments, the vertically (e.g., in the Z direction) highest step 275 of a first staircase structure 274 that shares a lateral conductive contact 290 with a second staircase structure 274 is aligned laterally (e.g., in the X direction) with the vertically (e.g., in the Z direction) lowest step 275 of the second staircase structure 274. The second vertically (e.g., in the Z direction) highest step 275 of the first staircase structure 274 is aligned laterally (e.g., in the X direction) with the second vertically (e.g., in the Z direction) lowest step 275 of the second staircase structure 274. The lateral (e.g., X-direction) alignment of the steps 175 of the first stair structure 274 and the second stair structure 274 continues as described above with reference to the horizontal alignment of the steps 175 of the stair structure 174 (Figures 1A and 1D-1G), such that the vertically (e.g., Z-direction) lowest step 275 of the first stair structure 274 is horizontally (e.g., X-direction) aligned with the vertically (e.g., Z-direction) highest step 275 of the second stair structure 274.

[0113] FIG. 2G is a schematic diagram illustrating electrical connections between conductive structures 232 defining horizontally (e.g., in the Y direction) adjacent staircase structures 274 of horizontally (e.g., in the X direction) adjacent subarrays 205. In the view of FIG. 2G, the Y direction is into and out of the page. In FIG. 2G, a first staircase structure 274 (e.g., the left staircase structure 274) is shown with dashed lines to indicate that the first staircase structure 274 lies in a different plane than the second staircase structure 274. The conductive structures 232A, 232B, 232C, and 232D defining steps 275 of the first staircase structure 274 share conductive paths with the conductive structures 232A, 232B, 232C, and 232D defining corresponding horizontally (e.g., in the X direction) aligned steps 275 of the second staircase structure 274 by means of lateral conductive contacts 290. FIG. 2G shows how the conductive structures 232A, 232B, 232C, 232D of the first staircase structure 274 individually share conductive paths with (e.g., electrically communicate with) the corresponding conductive structures 232A, 232B, 232C, 232D of the second staircase structure 274 based on the vertical (e.g., Z-direction) height of the conductive structures 232A, 232B, 232C, 232D of each staircase structure 274.

[0114] In some embodiments, arranging the staircase region 203 to include odd staircase structures 274 and even staircase structures 274, forming the staircase structures 274 to individually include either even steps 275 or odd steps 275, and forming lateral conductive contacts 290 between the staircase structures 274 in different subarrays 205 of different array regions 202 facilitates reducing the horizontal (e.g., X-direction) dimension of the staircase region 203. Thus, the arrangement of the staircase region 203 in the microelectronic device 200 reduces the area occupied by the staircase structures 274 and the staircase region 203, which may facilitate an increased density of vertical stacks of memory cells 220 compared to conventional microelectronic devices.

[0115] Referring again to FIG. 2A, the array area 202 may include an additional area 292 for placing one or more passive devices, such as a charge pump or a passive capacitor device.

[0116] Figure 3A is a schematic top view of a microelectronic device 300 according to an embodiment of the disclosure. Figure 3B is a schematic top view showing a portion of a staircase region 303 of the microelectronic device 300 of Figure 3A. The microelectronic device 300 may be substantially similar to the microelectronic device 200 of Figures 2A-2G, except that the staircase region 303 may be different from the staircase region 203.

[0117] 3A , the staircase regions 303 may be horizontally (e.g., in the X direction) interposed between some of the horizontally (e.g., in the X direction) adjacent array regions 302, or may not be horizontally (e.g., in the X direction) interposed between other horizontally (e.g., in the X direction) adjacent array regions 302. In some embodiments, an array region 302 is individually horizontally (e.g., in the X direction) adjacent to another array region 302 on a first horizontally (e.g., in the X direction) side of the array region 302 and a staircase region 303 on a second, opposing horizontally (e.g., in the X direction) side of the array region 302. In some such embodiments, an array region 302 may be individually horizontally (e.g., in the X direction) adjacent to one staircase region 303 and one additional array region 302.

[0118] The staircase regions 303 may each individually include a staircase structure 374 extending horizontally (e.g., in the X direction) within the staircase region 303 extending from the vertical stack structure 335 of the respective array region 302. Each staircase structure 374 may be operatively coupled to and extend from the vertical stack structure 335 of conductive structures 332 that extends horizontally (e.g., in the X direction) through the array region 302. In some embodiments, a portion of the stair structure 374 in the stair region 303 (e.g., half of the stair structure 374) is operably coupled to a vertical stack structure 335 extending horizontally (e.g., in the X direction) in a first array region 302 that is horizontally (e.g., in the X direction) adjacent to the stair region 303, and another stair structure 374 in the stair region 303 (e.g., the other half of the stair structure 374) is operably coupled to a vertical stack structure 335 extending horizontally (e.g., in the X direction) in a second array region 302 that is horizontally (e.g., in the X direction) adjacent to the stair region 303 opposite the first array region 302.

[0119] In some embodiments, each staircase structure 374 is horizontally (e.g., in the Y direction) between a first staircase structure 374 that connects to vertical stack structures 335 from the same array region 302 (and different subarrays 305) and is horizontally (e.g., in the Y direction) adjacent to the staircase structure 374 in a first direction, and a second staircase structure 374 that connects to vertical stack structures 335 extending horizontally from a different array region 302 (and different subarrays 305) and is horizontally (e.g., in the Y direction) adjacent to the staircase structure 374 in a second direction.

[0120] FIG. 3B is an enlarged view of a portion of the staircase region 303 shown in box A in FIG. 3A. FIG. 3B shows conductive contact structures 376 vertically (e.g., in the Z direction) overlying steps 375, illustrating the relative positions of the conductive contact structures 376 on the steps 375 as well as the relative positions of the lateral conductive contacts 390. For clarity and ease of understanding, FIG. 3B does not show certain portions of the array region 302, such as the vertical stack of memory cells (e.g., memory cells 120, 220). For example, within the array region 302, FIG. 3B shows only the vertical stack structure 335 of conductive structures 332 to illustrate the relationship between the vertical stack structure 335 and the staircase structure 374 in the staircase region 303.

[0121] 3A and 3B , each of the steps 375 of the staircase structure 374 in the staircase region 303 is horizontally aligned (e.g., in the X direction) with one another. For example, the steps 375 of the staircase structure 374 may be horizontally aligned (e.g., in the X direction) with the conductive structures 332 of the horizontally (e.g., in the X direction) adjacent array regions 302 that define the vertically (e.g., in the Z direction) lowest steps 375 of the staircase structure 374 connected to the horizontally adjacent array regions 302.

[0122] 3A and 3B , each of the steps 375 of the staircase structures 374 in a staircase region 303 is horizontally aligned (e.g., in the X direction) with one another. For example, the vertically (e.g., in the Z direction) highest steps 375 of the staircase structures 374 connected to vertical stack structures 335 extending horizontally (e.g., in the X direction) from the same array region 302 may be horizontally aligned (e.g., in the X direction) with one another and horizontally (e.g., in the X direction) with the vertically (e.g., in the Z direction) lowest step 375 of the staircase structures 374 connected to vertical stack structures 335 extending horizontally (e.g., in the X direction) from horizontally adjacent array regions 302.

[0123] Similarly, in some embodiments, at least some of the lateral conductive contacts 390 are horizontally aligned (e.g., in the X direction) with one another and are horizontally offset (e.g., in the X direction) from other lateral conductive contacts 390. In some embodiments, about half of the lateral conductive contacts 390 are horizontally offset (e.g., in the X direction) from about the other half of the lateral conductive contacts 390. About the other half of the lateral conductive contacts 390 may be horizontally aligned (e.g., in the X direction) with one another.

[0124] In some embodiments, the conductive contact structures 376 are individually offset laterally (e.g., in the X direction) from the lateral center (e.g., in the X direction) of the step 375 that they vertically (e.g., in the Z direction) overlie and electrically connect to the conductive structures 332. In some embodiments, the conductive contact structures 376 in contact with the conductive structures 332 defining the first staircase structure 374 may be positioned further horizontally (e.g., in the X direction) from the horizontal (e.g., in the X direction) edge of the vertically (e.g., in the Z direction) adjacent higher step 375 than from the horizontal (e.g., in the X direction) edge of the vertically (e.g., in the Z direction) adjacent lower step 375. The conductive contact structures 376 in contact with the conductive structures 332 of the first staircase structure 374 share a conductive path with (e.g., are in electrical communication with) the conductive contact structures 376 of the conductive structures 332 of the second staircase structure 374 via lateral conductive contacts 390. The conductive contact structures 376 of the second staircase structure 374 may be individually located closer horizontally (e.g., in the X direction) to the horizontal (e.g., X direction) edge of the vertically (e.g., Z direction) adjacent higher step 375 than to the horizontal (e.g., X direction) edge of the vertically (e.g., Z direction) adjacent lower step 375.

[0125] 3A and 3B , lateral conductive contacts 390 extend horizontally (e.g., in the Y direction) from the steps 375. The lateral conductive contacts 390 may be electrically connected to conductive structures 332 extending horizontally (e.g., in the X direction) from different array regions 302 and electrically connected to conductive contact structures 376 operably coupled to different staircase structures 374. Each lateral conductive contact 390 may extend horizontally (e.g., in the Y direction) from a first step 375 of a staircase structure 374 to a second step 375 of an adjacent staircase structure 374 that has a different vertical (e.g., Z direction) height than the first step 375. In some embodiments, a vertically (e.g., Z direction) higher step 375 shares a conductive path (is in electrical communication with) a vertically (e.g., Z direction) lower step 375 of another staircase structure 374 by way of the lateral conductive contact 390. In other words, the vertically taller steps 375 of each staircase structure 374 are in electrical communication with the vertically (e.g., Z-direction) shorter steps 375 of other staircase structures 374 by the lateral conductive contacts 390. In some embodiments, the vertically (e.g., Z-direction) taller steps 375 of a first staircase structure 374 are in electrical communication with the vertically (e.g., Z-direction) shorter steps 375 of a second staircase structure 374 compared to the steps 375 of the first staircase structure 374 having a height that is smaller than the height of the steps 375 of the first staircase structure 374.

[0126] In some embodiments, the lateral conductive contacts 390 extend horizontally (e.g., in the Y direction) between horizontally (e.g., in the Y direction) adjacent stair structures 374 that are coupled to vertical stack structures 335 that extend horizontally (e.g., in the X direction) from different array regions 302. The lateral conductive contacts 390 may extend horizontally from each stair structure 374 to the horizontally (e.g., in the Y direction) nearest stair structure 374 that is coupled to a different array region 302.

[0127] In some embodiments, lateral conductive contacts 390 extending horizontally (e.g., in the Y direction) from a first staircase structure 374 coupled to a subarray 305 within the array region 302 are offset horizontally (e.g., in the X direction, Y direction) from lateral conductive contacts 390 extending horizontally (e.g., in the Y direction) from a second staircase structure 374 coupled to the same subarray 305 in the array region 302.

[0128] Forming the microelectronic device 100 to include the staircase structure 374 and the lateral conductive contact 390 facilitates reducing the area of ​​the microelectronic device 100 occupied by the staircase region 303 and the staircase structure 374, thereby increasing the density of the memory cells 120.

[0129] 4 is a schematic top view of a portion of a microelectronic device 400 according to an embodiment of the disclosure. Microelectronic device 400 may be substantially similar to microelectronic device 300 of FIGS. 3A and 3B, except that microelectronic device 400 may include one or more staircase regions 403 that are different from one or more of staircase regions 303. Staircase regions 403 may replace one or more of staircase regions 303 of microelectronic device 300 of FIG. 3A.

[0130] In some embodiments, the stair structure 474 and the steps 475 may be horizontally aligned with one another (e.g., in the X direction), as described above with reference to the stair structure 374 (Figures 3A, 3B) and the steps 375 (Figures 3A, 3B).

[0131] 4 , some of the lateral conductive contacts 490 extend horizontally (e.g., in the Y direction) from the staircase region 474 to a staircase region 474 that is immediately horizontally (e.g., in the Y direction) adjacent to the staircase region 474. Other lateral conductive contacts 490 extend horizontally (e.g., in the Y direction) from the staircase region 474 to a staircase region 474 that is distal from the staircase region 474 relative to the other staircase regions 474. In some embodiments, the lateral conductive contacts 490 include a first group of lateral conductive contacts 490 that have a larger dimension (e.g., length) horizontally (e.g., in the Y direction) than the lateral conductive contacts 490 of a second group of lateral conductive contacts 490.

[0132] 4 facilitates activation of conductive pillar structures 360 ( FIG. 3A ) in an array region 302 through which the vertical stack structure 335 extends horizontally (e.g., in the X-direction) without activating undesired conductive pillar structures 360 in other array regions 302. In some embodiments, each of the conductive pillar structures 360 in a particular array region 302 includes only one corresponding conductive pillar structure 360 ​​in an adjacent array region 302 and is simultaneously activated by placing a voltage on one or more of the lateral conductive contacts 490 shared by the steps 475 of the staircase structure 474 of the respective conductive pillar structure 360. Such an arrangement facilitates reducing the complexity of multiplexers coupled to the conductive pillar structures 360.

[0133] 5 is a simplified top view of a portion of a microelectronic device 500 according to an embodiment of the disclosure. Microelectronic device 500 may be substantially similar to microelectronic device 300 of FIGS. 3A and 3B, except that microelectronic device 400 may include one or more staircase regions 503 that are different from one or more of staircase regions 303.

[0134] In some embodiments, the stair structure 574 and the steps 575 may be horizontally aligned with one another (e.g., in the X direction), as described above with reference to the stair structure 374 (Figures 3A, 3B) and the steps 375 (Figures 3A, 3B).

[0135] 5 , each of the lateral conductive contacts 590 extending horizontally (e.g., in the Y direction) from an individual stair structure 574 extends horizontally to an additional stair structure 574 spaced apart by an additional stair structure 574. In other words, the conductive contact structures 576 coupled to every other one of the stair structures 574 (e.g., in the Y direction) are configured to be in electrical communication with each other via the lateral conductive contacts 590. In some embodiments, each of the lateral conductive contacts 590 is electrically connected to the conductive contact structures 576 coupled to every other one of the stair structures 574.

[0136] In some embodiments, arranging the lateral conductive contacts 590 so that they extend horizontally (e.g., in the Y direction) to conductive contact structures 576 coupled to every other staircase structure 574 facilitates forming the lateral conductive contacts 590 to exhibit substantially similar lengths. In some embodiments, each of the lateral conductive contacts 590 has approximately the same length. In some embodiments, each of the lateral conductive contacts 590 exhibits approximately the same resistivity.

[0137] 1A-5 are described and shown as including subarrays 105, 205, 305 that include memory cells 120, 220, 320 having particular configurations, the disclosure is not so limited. In other embodiments, the subarrays 105, 205, 305 may differ from the subarrays described above. For example, although the conductive structures 132, 232, 332, 432, 532 (e.g., word lines) configured to be in electrical communication with the memory cells 120, 220, 320 (e.g., in electrical communication with the access devices 130, 230, 330) are described and shown as extending horizontally (e.g., in the Y direction) through the array regions 102, 202, 302 and terminating in stair structures 174, 274, 374, 474, 574, and the conductive pillar structures 160, 260, 360 (e.g., local digit lines) are configured to extend vertically (e.g., in the Z direction) and be in electrical communication with the access devices 130, 230, 330, the disclosure is not so limited. In other embodiments, the word lines are configured to extend vertically (e.g., in the Z direction) through the vertical stack of memory cells 120, 220, 320 and be in electrical communication with the memory cells 120, 220, 320 (e.g., in electrical communication with the access devices 130, 230, 330), and the local digit lines are configured to extend horizontally (e.g., in the Y direction) through the array region, terminate at staircase structures and be in electrical communication with the memory cells 120, 220, 320 (e.g., in electrical communication with the access devices 130, 230, 330).

[0138] Thus, according to some embodiments, a microelectronic device comprises a memory array region each comprising a vertical stack of memory cells comprising a vertical stack of access devices and a vertical stack of capacitors horizontally adjacent to the vertical stack of access devices, the memory array region further comprising vertical stack structures vertically spaced apart from one another and comprising conductive structures extending horizontally through the vertical stack of memory cells, the conductive structures adjacent to the access devices of the vertical stack of access devices. The staircase region lies horizontally between two of the horizontally adjacent memory array regions and comprises a first staircase structure extending horizontally from the vertical stack structure of a first of the two memory array regions and comprising a first step at a horizontal edge of the conductive structure of the vertical stack structure of the first of the two memory array regions, a second staircase structure extending horizontally from the vertical stack structure of a second of the two memory array regions of the memory array regions and comprising a second step at a horizontal edge of the conductive structure of the vertical stack structure of the first of the two memory array regions, and a lateral conductive contact providing a conductive path between the first step of the first staircase structure and the second step of the second staircase structure.

[0139] According to yet an additional embodiment of the disclosure, a microelectronic device comprises a memory array bank comprising a first memory array and a second memory array, each of which comprises a vertical stack of dynamic random access memory (DRAM) cells, each DRAM cell comprising a storage device horizontally adjacent to an access device, and a vertical stack structure comprising vertically spaced apart conductive structures extending horizontally through the vertical stack of DRAM cells, the conductive structures of the vertical stack structure adjacent to a DRAM cell of the vertical stack of DRAM cells. The microelectronic device further comprises a horizontal staircase region between the first memory array and the second memory array. The staircase region comprises a first staircase structure extending horizontally from the vertical stack structure of the first memory array, a second staircase structure extending horizontally from the vertical stack structure of the second memory array, and lateral conductive contacts extending horizontally from the first staircase structure to the second staircase structure, each lateral conductive contact operably coupled to one step of the first staircase structure and one step of the second staircase structure.

[0140] Further, according to some embodiments of the disclosure, a memory device comprises: a first memory array region comprising a first vertical stack of first dynamic random access memory (DRAM) cells, each of the first DRAM cells comprising a storage device of the vertical stack of storage devices and a horizontally adjacent access device of the vertical stack of access devices; a first vertical stack structure comprising vertically spaced apart first conductive structures extending horizontally through the first memory array region and terminating in a first staircase structure in a staircase region horizontally adjacent to the first memory array region; a second memory array region comprising a second vertical stack of second DRAM cells; a second vertical stack structure comprising vertically spaced apart second conductive structures extending horizontally through the second memory array region and terminating in a second staircase structure in the staircase region; and a lateral conductive contact electrically connecting a step of the first staircase structure to a step of the second staircase structure.

[0141] Structures, assemblies, and devices according to the disclosed embodiments may be included in the disclosed electronic systems. For example, FIG. 6 is a block diagram of an exemplary electronic system 600 according to the disclosed embodiments. The electronic system 600 may comprise, for example, a computer or computer hardware component, a server or other networking hardware component, a mobile phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet such as an iPad® or SURFACE® tablet, an e-book, a navigation device, etc. The electronic system 600 includes at least one memory device 602. The memory device 602 may include, for example, one or more microelectronic device embodiments described hereinabove with reference to FIGS. 1A-5. The electronic system 600 may further include at least one electronic signal processor device 604 (often referred to as a “microprocessor”). The electronic signal processor device 604 may optionally include one or more microelectronic device embodiments described hereinabove with reference to FIGS. 1A-5. Although memory device 602 and electronic signal processor device 604 are shown as two (2) separate devices in Figure 6, in further embodiments, a single (e.g., only one) memory / processor device having the functionality of memory device 602 and electronic signal processor device 604 is included in electronic system 600. In such embodiments, the memory / processor device may include one or more of the microelectronic devices described hereinabove with reference to Figures 1A-5. Electronic system 600 may further include one or more input devices 606 for inputting information into electronic system 600 by a user, such as, for example, a mouse or other pointing device, a keyboard, a touchpad, buttons, or a control panel.Electronic system 600 may further include one or more output devices 608 for outputting information (e.g., visual or audio output) to a user, such as, for example, one or more of a monitor, a display, a printer, an audio output jack, and a speaker. In some embodiments, input device(s) 606 and output device(s) 608 may comprise a single touchscreen device that can be used to both input information into electronic system 600 and output visual information to a user. Input device(s) 606 and output device(s) 608 may be in electrical communication with one or more of memory device 602 and electronic signal processor device 604.

[0142] Thus, according to a disclosed embodiment, an electronic system includes an input device, an output device, a processor device operatively coupled to the input device and the output device, and a memory device operatively coupled to the processor device, the memory device including: a first array region including a vertical stack of memory cells, each memory cell including a capacitor device and an access device coupled to the capacitor device; a first vertical stack of first conductive structures vertically spaced apart from one another and extending horizontally through the first array region in a first horizontal direction, the first conductive structures terminating horizontally in a staircase structure in a staircase region horizontally adjacent to the first array region; a second array region comprising an additional vertical stack of memory cells; a second vertical stack of second conductive structures vertically spaced from one another and extending horizontally in a first horizontal direction through the second array region, the second conductive structures terminating horizontally at a second stair structure in the stair region; and a lateral conductive contact extending horizontally in the second horizontal direction between the first stair structure and the second stair structure and operably coupled to a step of the first stair structure and a step of the second stair structure.

[0143] Additional non-limiting exemplary embodiments of the disclosure are described below.

[0144] Embodiment 1: A microelectronic device comprising: memory array regions and horizontal staircase regions between two of said memory array regions horizontally adjacent to one another, each memory array region comprising: vertical stacks of memory cells, each memory array region comprising a vertical stack of access devices and a vertical stack of capacitors horizontally adjacent to the vertical stack of access devices; and vertical stack structures vertically spaced from one another and extending horizontally through the vertical stack of memory cells, each vertical stack structure comprising conductive structures adjacent to memory cells of the vertical stack of memory cells; and the staircase regions between a first of the two memory array regions and a second of the two memory array regions. a first staircase structure extending horizontally from the vertical stack structure in the memory array region and comprising a first step at a horizontal edge of a conductive structure of the vertical stack structure in a first one of two memory array regions of the memory array regions; a second staircase structure extending horizontally from the vertical stack structure in a second one of the two memory array regions of the memory array regions and comprising a second step at a horizontal edge of the conductive structure of the vertical stack structure in the first one of the two memory array regions of the memory array regions; and a lateral conductive contact providing a conductive path between the first step of the first staircase structure and the second step of the second staircase structure.

[0145] Embodiment 2: A microelectronic device as described in embodiment 1, wherein the vertically highest first step of the first staircase structure shares a conductive path with the vertically lowest second step of the second staircase structure by one of the lateral conductive contacts.

[0146] Embodiment 3: A microelectronic device as described in embodiment 1 or 2, wherein the vertical stack structure of a first memory array area of ​​two memory array areas extends in a first horizontal direction, and the first staircase structure is horizontally adjacent to the second staircase structure in a second horizontal direction perpendicular to the first horizontal direction.

[0147] Embodiment 4: A microelectronic device as described in embodiment 3, wherein the first step of the first staircase structure horizontally overlaps the second step of the second staircase structure in a first horizontal direction.

[0148] Embodiment 5: A microelectronic device as described in embodiment 4, wherein the highest first step among the first steps of the first staircase structure is substantially aligned in the first horizontal direction with the lowest second step among the second steps of the second staircase structure, and the highest second step among the second steps of the second staircase structure is substantially aligned in the first horizontal direction with the lowest first step among the first steps of the first staircase structure.

[0149] Embodiment 6: A microelectronic device as described in embodiment 1 or 2, wherein the first step of the first staircase structure comprises every other conductive structure of the conductive structures of the vertical stack structure of a first memory array region of two memory array regions.

[0150] Embodiment 7: The microelectronic device of embodiment 6, further comprising an additional staircase region comprising an additional staircase structure extending horizontally from the vertical stack structure of a first memory array region of the two memory array regions and the vertical stack structure of a second memory array region of the two memory array regions, wherein the additional staircase region is horizontally spaced apart from the staircase region by one memory array region of the two memory array regions.

[0151] Embodiment 8: A microelectronic device as described in embodiment 1 or 2, wherein a vertical stack of memory cells in a first memory array region of the memory array regions is horizontally aligned with a vertical stack of memory cells in a second memory array region of the memory array regions.

[0152] Embodiment 9: A microelectronic device as described in embodiment 1 or 2, wherein the vertical stack of memory cells in a first memory array region among the memory array regions is horizontally offset from the vertical stack of memory cells in a second memory array region among the memory array regions in the horizontal direction in which the lateral conductive contacts extend.

[0153] Embodiment 10: A microelectronic device as described in any one of embodiments 1 to 9, wherein the conductive structure of the vertical stack structure of a first memory array area of ​​the two memory array areas comprises a word line configured to be in electrical communication with an access device of the first memory array area of ​​the two memory array areas of the memory array areas.

[0154] Embodiment 11: A microelectronic device as described in any one of embodiments 1 to 9, wherein the conductive structure of the vertical stack structure of a first memory array area of ​​the two memory array areas comprises a digit line that vertically overlaps an access device of the first memory array area of ​​the two memory array areas of the memory array areas.

[0155] Embodiment 12: A microelectronic device comprising: a memory array bank comprising a first memory array and a second memory array; and a horizontal staircase region between the first memory array and the second memory array, the first memory array and the second memory array being vertical stacks of dynamic random access memory (DRAM) cells, each DRAM cell comprising a storage device horizontally adjacent to an access device; and a vertical stack structure comprising vertically spaced apart conductive structures extending horizontally through the vertical stack of DRAM cells, the vertical stack a microelectronic device, wherein the conductive structures of the structure individually comprise vertical stack structures adjacent to DRAM cells of the vertical stack of DRAM cells, and the staircase region comprises a first staircase structure extending horizontally from the vertical stack structures of the first memory array, a second staircase structure extending horizontally from the vertical stack structures of the second memory array, and lateral conductive contacts extending horizontally from the first staircase structure to the second staircase structure, each lateral conductive contact operably coupled to one step of the first staircase structure and one step of the second staircase structure.

[0156] Embodiment 13: The microelectronic device of embodiment 12, further comprising vertically extending word lines, each vertically extending word line extending vertically along a side of an access device of a vertical stack of DRAM cells.

[0157] Embodiment 14: A microelectronic device as described in embodiment 12 or 13, wherein the lower half of the step of the first staircase structure horizontally overlaps the lower half of the step of the second staircase structure.

[0158] Embodiment 15: A microelectronic device described in any one of embodiments 12 to 14, further comprising a further lateral conductive contact extending horizontally between a third staircase structure extending from the further vertical stack structure of the first memory array and a fourth staircase structure extending horizontally from the further vertical stack structure of the second memory array.

[0159] Embodiment 16: A memory device comprising: a first memory array region comprising a first vertical stack of first dynamic random access memory (DRAM) cells, each of the first DRAM cells comprising a storage device of the vertical stack of storage devices and a horizontally adjacent access device of the vertical stack of access devices; a first vertical stack structure comprising vertically spaced apart first conductive structures extending horizontally through the first memory array region and terminating in a first staircase structure in a staircase region horizontally adjacent to the first memory array region; a second memory array region comprising a second vertical stack of second DRAM cells; a second vertical stack structure comprising vertically spaced apart second conductive structures extending horizontally through the second memory array region and terminating in a second staircase structure in the staircase region; and a lateral conductive contact electrically connecting a step of the first staircase structure to a step of the second staircase structure.

[0160] Embodiment 17: The memory device of embodiment 16, wherein the staircase region is horizontally interposed between the first memory array region and the second memory array region.

[0161] Embodiment 18: A memory device as described in embodiment 16 or 17, wherein the first memory array region is horizontally spaced from the second memory array region in a first horizontal direction, and the lateral conductive contacts extend horizontally in a second horizontal direction that is perpendicular to the first horizontal direction.

[0162] Embodiment 19: The memory device of any one of embodiments 16 to 18, wherein the first DRAM cell is horizontally offset from the second DRAM cell in a first horizontal direction and in a second horizontal direction.

[0163] Embodiment 20: A memory device described in any one of embodiments 16 to 19, further comprising conductive contact structures in individual contact with the steps of the first staircase structure and the steps of the second staircase structure, and the lateral conductive contacts contact the conductive contact structures.

[0164] The materials described herein may be formed by conventional techniques, including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). Alternatively, the materials may be grown in situ. Depending on the particular material being formed, techniques for depositing or growing the material may be selected by one of ordinary skill in the art. Material removal may be achieved by any suitable technique, including, but not limited to, etching, abrasive planarization (e.g., chemical-mechanical planarization), or other known methods, unless the context dictates otherwise.

[0165] As used herein, the term "configured" refers to one or more of the size, shape, material composition, orientation, and arrangement of at least one structure and at least one device that facilitates one or more operations of the structure and device in a predetermined manner.

[0166] As used herein, the terms “longitudinal,” “vertical,” “lateral,” and “horizontal” refer to a major plane of a substrate (e.g., a base material, structure, or configuration) in or on which one or more structures and / or features are formed, and are not necessarily defined by the Earth's gravitational field. A “lateral” or “horizontal” direction is a direction substantially parallel to the major plane of the substrate, while a “longitudinal” or “vertical” direction is a direction substantially perpendicular to the major plane of the substrate. The major plane of the substrate is defined by a surface of the substrate having a relatively large area compared to other surfaces of the substrate. With reference to a figure, a “horizontal” or “lateral” direction may be perpendicular to the indicated “Z” axis, parallel to the indicated “X” axis, and / or parallel to the indicated “Y” axis, and a “vertical” or “longitudinal” direction may be parallel to the indicated “Z” axis, perpendicular to the indicated “X” axis, or perpendicular to the indicated “Y” axis.

[0167] As used herein, the term "substantially" with respect to a given parameter, characteristic, or condition means and includes the extent to which one of ordinary skill in the art would understand that the given parameter, characteristic, or condition is met with some variance, such as within an acceptable tolerance. By way of example, depending on the particular parameter, characteristic, or condition that is substantially met, the parameter, characteristic, or condition may be at least 90.0 percent met, at least 95.0 percent met, at least 99.0 percent met, at least 99.9% met, or even 100.0 percent met.

[0168] As used herein, "about" or "approximately" in reference to a numerical value for a particular parameter includes the numerical value and a degree of variation from the numerical value that one skilled in the art would understand to be within an acceptable tolerance for the particular parameter. For example, "about" or "approximately" in reference to a numerical value may include additional numerical values ​​in the range of 90.0% to 110.0% of the numerical value, such as within 95.0% to 105.0% of the numerical value, within 97.5% to 102.5% of the numerical value, within 99.0% to 101.0% of the numerical value, within 99.5% to 100.5% of the numerical value, within 99.5% to 100.5% of the numerical value, and within 99.9% to 100.1% of the numerical value.

[0169] As used herein, spatially relative terms such as "beneath," "below," "lower," "bottom," "above," "upper," "top," "front," "rear," "left," and "right" may be used for ease of description to describe the relationship of one element or feature illustrated in the figures to another element(s) or feature(s). Unless otherwise specified, spatially relative terms are intended to encompass different orientations of the material in addition to the orientation shown in the figures. For example, if the material in the figures were inverted, an element described as "below" or "beneath" or "under" or "at the bottom of" the other element or feature would then be oriented "above" or "on top" of the other element or feature. Thus, the term "below" can encompass both an orientation of above and below, depending on the context in which the term is used, as would be apparent to one skilled in the art. Materials may be oriented in other ways (e.g., rotated 90 degrees, flipped, inverted) and the spatially relative descriptors used herein may be interpreted accordingly.

[0170] As used herein, features (e.g., regions, materials, structures, devices) described as "neigboring" one another refer to and include features of the disclosed entity(ies) that are located in closest proximity (e.g., nearest) to one another. Additional features (e.g., additional regions, additional materials, additional structures, additional devices) that do not correspond to the disclosed entity(ies) of the "neighboring" feature may be disposed between the "neighboring" features. In other words, "neighboring" features may be positioned directly adjacent to one another such that no other features intervene between the "neighboring" features, or "neighboring" features may be positioned indirectly adjacent to one another such that at least one feature having an entity other than that connected to at least one "neighboring" feature is positioned between the "neighboring" features. Thus, features described as "vertically neighboring" one another refer to and include features of the disclosed entity(ies) that are located in closest vertical proximity (e.g., nearest vertically) to one another. Additionally, features described as "horizontally neighboring" one another mean and include features of the disclosed entity(ies) that are located in closest horizontal proximity (e.g., horizontally closest) to one another.

[0171] As used herein, the term "memory device" means and includes, but is not necessarily limited to, a microelectronic device that exhibits memory functionality. In other words, and by way of example only, the term "memory device" means and includes not only conventional memory (e.g., conventional volatile memory such as conventional DRAM, conventional non-volatile memory such as conventional NAND memory), but also application specific integrated circuits (ASICs) (e.g., systems on a chip (SoCs)), microelectronic devices that combine logic and memory, and graphics processing units (GPUs) that incorporate memory.

[0172] As used herein, "conductive material" refers to a metal (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)), alloys (Co-based alloys, Fe-based alloys, Ni-based alloys, Fe- and Ni-based alloys, Co- and and Ni-based alloys, Fe- and Co-based alloys, Co- and Ni-based alloys, Al-based alloys, Cu-based alloys, magnesium (Mg)-based alloys, Ti-based alloys, steel, low-carbon steel, stainless steel), conductive metal-containing materials (e.g., conductive metal nitrides, conductive metal silicides, conductive metal carbides, conductive metal oxides), and conductively doped semiconductor materials (e.g., conductively doped polysilicon, conductively doped germanium (Ge), conductively doped silicon germanium (SiGe)). Furthermore, "conductive structure" means and includes a structure formed of and comprising a conductive material.

[0173] As used herein, "insulating material" means and includes electrically insulating materials such as one or more of at least one dielectric oxide material (e.g., one or more of silicon oxide (SiOx), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, aluminum oxide (AlOx), hafnium oxide (HfOx), niobium oxide (NbOx), titanium oxide (TiOx), zirconium oxide (ZrOx), tantalum oxide (TaOx), and magnesium oxide (MgOx)), at least one dielectric nitride material (e.g., silicon nitride (SiNy)), at least one dielectric oxynitride material (e.g., silicon oxynitride (SiOxNy)), and at least one dielectric carboxynitride material (e.g., silicon carboxynitride (SiOxCzNy)). As used herein, a formula including one or more of "x," "y," and "z" (e.g., SiOx, AlOx, HfOx, NbOx, TiOx, SiNy, SiOxNy, SiOxCzNy) describes a material that includes an average ratio of "x" atoms of one element, "y" atoms of another element, and "z" atoms of an additional element (if present) for every atom of another element (e.g., Si, Al, Hf, Nb, Ti). Because formulas represent relative atomic ratios and not strict chemical structures, insulating materials may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x," "y," and "z" (if present) may be integers or non-integers. As used herein, the term "non-stoichiometric compound" means and includes a chemical compound having an elemental composition that cannot be expressed in a clearly defined ratio of whole numbers and that defies the law of definite proportions. Additionally, "insulative structure" means and includes a structure formed of and including an insulating material.

[0174] As used herein, "semiconductor material" or "semiconductive material" refers to a material having a conductivity between that of insulating materials and that of conductive materials. For example, a semiconductor material may have a conductivity between about 10-8 siemens per centimeter (S / cm) and about 104 S / cm (106 S / cm) at room temperature. Examples of semiconductor materials include elements found in Group IV of the periodic table of elements, such as silicon (Si), germanium (Ge), and carbon (C). Other examples of semiconductor materials include, without limitation, compound semiconductor materials such as binary compound semiconductor materials (e.g., gallium arsenide (GaAs)), ternary compound semiconductor materials (e.g., AlGaAs), and quaternary compound semiconductor materials (e.g., GaXIn1-XAsYP1-Y). Compound semiconductor materials may include, without limitation, combinations of elements from groups III and V of the periodic table of elements (III-V semiconductor materials) or elements from groups II and VI of the periodic table of elements (II-VI semiconductor materials). Further examples of semiconductor materials include oxide semiconductor materials, such as zinc tin oxide (ZnxSnyO, commonly referred to as "ZTO"), indium zinc oxide (InxZnyO, commonly referred to as "IZO"), zinc oxide (ZnxO), indium gallium zinc oxide (InxGayZnzO, commonly referred to as "IGZO"), indium gallium silicon oxide (InxGaySizO, commonly referred to as "IGSO"), indium tungsten oxide (InxWyO, commonly referred to as "IWO"), indium oxide (InxO), tin oxide (SnxO), titanium oxide (TixO), oxynitride, and the like. Zinc (ZnxONz), magnesium zinc oxide (MgxZnyO), zirconium indium zinc oxide (ZrxInyZnzO), hafnium indium zinc oxide (HfxInyZnzO), indium zinc tin oxide (SnxInyZnzO), aluminum tin indium zinc oxide (AlxSnyInzZnaO), silicon indium zinc oxide (SixInyZnzO), aluminum zinc tin oxide (AlxZnySnzO), gallium zinc tin oxide (GaxZnySnzO), zirconium zinc tin oxide (ZrxZnySnzO), and other similar materials.

[0175] As used herein, the term "in electrical communication," when used with respect to a first component or structure relative to a second component or structure, means and includes that, in use and operation, the first component or structure is configured to be electrically connected to the second component. As a non-limiting example, when a first component is in electrical communication with a second component, in use and operation, electrons flow between the first and second components, such as in response to receiving an input voltage (e.g., to the first component). The first component may be in electrical communication with the second component without directly contacting the second component, or may be in electrical communication with the second component by directly contacting the second component.

[0176] While certain illustrative embodiments have been described in connection with the Figures, those skilled in the art will recognize and understand that the embodiments encompassed by the disclosure are not limited to the embodiments explicitly shown and described herein. Rather, many additions, deletions, and modifications to the embodiments described herein, such as those hereinafter claimed, including legal equivalents, may be made without departing from the scope of the embodiments encompassed by the disclosure. Furthermore, features from one disclosed embodiment may be combined with features of another disclosed embodiment while still falling within the scope of the disclosure.

Claims

1. memory array area and a horizontal staircase region between two of the memory array regions adjacent to each other in the horizontal direction; Each one is equipped with The memory array area includes: A vertical stack of memory cells, a vertical stack of access devices; and a vertical stack of capacitors horizontally adjacent said vertical stack of access devices a vertical stack of memory cells comprising: a vertical stack structure comprising conductive structures vertically spaced apart from one another and extending horizontally through the vertical stack of memory cells, the conductive structures adjacent to a memory cell of the vertical stack of memory cells; The staircase area is a first staircase structure extending horizontally from the vertical stack structure in a first memory array region of the two memory array regions and comprising a first step at a horizontal edge of the conductive structure of the vertical stack structure in the first memory array region of the two memory array regions of the memory array regions; a second staircase structure extending horizontally from the vertical stack structure in a second one of the two memory array regions and comprising a second step at a horizontal edge of the conductive structure of the vertical stack structure in the first one of the two memory array regions; and a lateral conductive contact providing a conductive path between the first step of the first staircase structure and the second step of the second staircase structure; A microelectronic device comprising:

2. 2. The microelectronic device of claim 1, wherein a vertically highest first step of the first steps of the first staircase structure shares a conductive path with a vertically lowest second step of the second steps of the second staircase structure by one of the lateral conductive contacts.

3. the vertical stack structure of the first one of the two memory array areas extends in a first horizontal direction; The microelectronic device of claim 1 , wherein the first staircase structure is horizontally adjacent to the second staircase structure in a second horizontal direction that is orthogonal to the first horizontal direction.

4. The microelectronic device of claim 3 , wherein the first step of the first staircase structure horizontally overlaps the second step of the second staircase structure in the first horizontal direction.

5. a highest first step of the first steps of the first staircase structure is substantially aligned with a lowest second step of the second steps of the second staircase structure in the first horizontal direction; 5. The microelectronic device of claim 4, wherein a highest one of the second steps of the second staircase structure is substantially aligned with a lowest one of the first steps of the first staircase structure in the first horizontal direction.

6. 2. The microelectronic device of claim 1, wherein the first step of the first staircase structure comprises every other conductive structure of the conductive structures of the vertical stack structure of the first memory array region of the two memory array regions.

7. 7. The microelectronic device of claim 6, further comprising a further staircase region comprising a further staircase structure extending horizontally from the vertical stack structure of the first memory array region of the two memory array regions and the vertical stack structure of the second memory array region of the two memory array regions, wherein the further staircase region is horizontally spaced apart from the staircase region by the one memory array region of the two memory array regions.

8. 2. The microelectronic device of claim 1, wherein the vertical stacks of memory cells in a first one of the memory array regions are horizontally aligned with the vertical stacks of memory cells in a second one of the memory array regions.

9. 2. The microelectronic device of claim 1, wherein the vertical stack of memory cells in a first memory array region of the memory array regions is horizontally offset from the vertical stack of memory cells in a second memory array region of the memory array regions in a horizontal direction in which the lateral conductive contact extends.

10. 10. The microelectronic device of claim 1, wherein the conductive structures of the vertically stacked structures of the first of the two memory array areas comprise word lines configured to be in electrical communication with access devices of the first of the two memory array areas.

11. 10. The microelectronic device of claim 1, wherein the conductive structure of the vertically stacked structure of the first one of the two memory array areas comprises a digit line that vertically overlaps the access device of the first one of the two memory array areas of the memory array areas.

12. a memory array bank comprising a first memory array and a second memory array; a horizontal staircase region between the first memory array and the second memory array; Equipped with The first memory array and the second memory array a vertical stack of dynamic random access memory (DRAM) cells, each DRAM cell comprising a storage device horizontally adjacent to an access device; and a vertical stack structure comprising vertically spaced apart conductive structures extending horizontally through the vertical stack of DRAM cells, the conductive structures of the vertical stack structure being adjacent to a DRAM cell of the vertical stack of DRAM cells; Each one is equipped with The staircase area is a first staircase structure extending horizontally from the vertical stack structure of the first memory array; a second staircase structure extending horizontally from the vertical stack structure of the second memory array; and lateral conductive contacts extending horizontally from the first staircase structure to the second staircase structure, each lateral conductive contact being operably coupled to one step of the first staircase structure and one step of the second staircase structure; A microelectronic device comprising:

13. 13. The microelectronic device of claim 12, further comprising vertically extending word lines, each vertically extending word line extending vertically along a side of an access device of a vertical stack of DRAM cells of the vertical stack of DRAM cells.

14. 14. The microelectronic device of claim 12 or 13, wherein a lower half of the step of the first staircase structure horizontally overlaps a lower half of the step of the second staircase structure.

15. 14. The microelectronic device of claim 12 or 13, further comprising a further lateral conductive contact extending horizontally between a third staircase structure extending from the further vertical stack structure of the first memory array and a fourth staircase structure extending horizontally from the further vertical stack structure of the second memory array.

16. a first memory array region comprising a first vertical stack of first dynamic random access memory (DRAM) cells, each of the first DRAM cells comprising a storage device of the vertical stack of storage devices and a horizontally adjacent access device of the vertical stack of access devices; a first vertical stack structure comprising vertically spaced apart first conductive structures extending horizontally through the first memory array region and terminating in a first staircase structure in a staircase region horizontally adjacent the first memory array region; a second memory array area comprising a second vertical stack of second DRAM cells; a second vertical stack structure comprising vertically spaced second conductive structures extending horizontally through the second memory array region and terminating in a second staircase structure in the staircase region; a lateral conductive contact electrically connecting a step of the first staircase structure to a step of the second staircase structure; A memory device comprising:

17. 17. The memory device of claim 16, wherein the staircase region is horizontally interposed between the first memory array region and the second memory array region.

18. the first memory array region is horizontally spaced from the second memory array region in a first horizontal direction; 17. The memory device of claim 16, wherein the lateral conductive contacts extend horizontally in a second horizontal direction orthogonal to the first horizontal direction.

19. 19. The memory device of claim 16, wherein the first DRAM cell is horizontally offset from the second DRAM cell in a first horizontal direction and in a second horizontal direction.

20. 19. The memory device of claim 16, further comprising conductive contact structures in contact with the steps of the first staircase structure and the steps of the second staircase structure, respectively, and the lateral conductive contacts contact the conductive contact structures.

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