Phase-locked loop (PLL) including digitally controlled oscillator (DCO) gain calibration circuit and related method

Abstract

The interface between clock domains in an integrated circuit (IC) depends on the synchronization of the phase-locked loops (PLLs) that generate the clocks in the different domains and how each PLL responds to the jitter of a shared reference clock. The well-controlled, identical bandwidth (and loop dynamics) of these PLLs ensures that the reference jitter contribution is identical or even negligible. As a key component determining digital PLL bandwidth, the digitally controlled oscillator (DCO) can vary in gain due to process, temperature, and power supply IR drop between chips or modules. A calibration circuit provides gain correction factors to achieve the DCO's nominal gain and the desired / target PLL loop bandwidth. In some examples, the calibration circuit for each PLL determines the gain correction factor that results in a common jitter response for the PLLs and stores the gain correction factor in the calibration circuit.

Description

[Technical Field]

[0001] Disclosure Areas TECHNICAL FIELD

[0001] The technology of this disclosure relates generally to phase-locked loops (PLLs), and more particularly to jitter response in PLLs. [Background technology]

[0002] background

[0002] An integrated circuit (IC) may contain multiple clock domains that communicate with each other. Each clock domain is a group of circuits that receive the same clock. Communication between circuits in different clock domains relies on synchronization of their respective clocks. Each clock domain may have its own phase-locked loop (PLL) to provide a clock to the circuits within that clock domain. The PLL includes a voltage-controlled oscillator (VCO) or a digitally controlled oscillator (DCO) that oscillates at a frequency corresponding to a reference clock. If the output clock generated by the PLL is not synchronized with the reference clock, the time difference is detected and used to generate a control signal to adjust the frequency of the output clock. In a PLL that includes a DCO, the control signal is a digital value generated by comparing a feedback signal based on the output clock with the reference clock. Immediately after powering up the PLL, there is a time difference between the feedback signal and the reference clock. This time difference gradually decreases until the PLL is locked (i.e., synchronized). However, variations in the reference clock, such as jitter, can disrupt the PLL's output clock edges. The way a PLL responds to reference jitter can vary depending on the loop bandwidth. If PLLs in different clock domains of an IC receive the same reference clock but respond differently to jitter in the reference clock, the jitter can cause timing problems, resulting in performance degradation or communication failure. Summary of the Invention [Means for solving the problem]

[0003] overview

[0003] Exemplary aspects disclosed herein include a phase-locked loop (PLL) including a digitally controlled oscillator (DCO) gain calibration circuit. Related methods for DCO gain calibration are also disclosed. Synchronization of clocks in different clock domains of an integrated circuit (IC) is important for high-performance interfaces between these clock domains. A PLL can achieve synchronization between clock domains by generating the domain clocks based on the same reference clock. However, jitter in the reference clock signal can disrupt synchronization if the PLLs do not respond to jitter in the same way. In the exemplary PLL disclosed herein, a calibration circuit provides a gain correction factor to achieve a nominal gain in the output clock generator for a desired loop bandwidth. In this manner, PLLs in different clock domains can be calibrated to have similar jitter responses. When the loop bandwidths of all PLLs in an IC are calibrated to the desired loop bandwidth, they respond similarly to jitter in the reference clock, maintaining negligible relative timing uncertainty while also maintaining a high-performance interface. The PLL feedback loop detects the time difference between the reference clock and a feedback signal based on the output clock. A PLL includes an output clock generator that adjusts the output clock to reduce the time difference. The gain of the output clock generator, determined in part by the DCO, is one factor that determines how the output clock generator responds to reference clock jitter. The DCO gain, and therefore the output clock generator gain, can vary from PLL to PLL due to differences in manufacturing process and circuit environment. A calibration circuit can be employed to determine and provide a gain correction factor that adjusts the gain of the output clock generator to a nominal gain corresponding to the desired loop bandwidth of the PLL.

[0004] In one exemplary aspect, a PLL is disclosed that includes a delta detector configured to receive a reference clock and a feedback signal and generate a delta value indicative of a time difference between the reference clock and the feedback signal, and a divider circuit configured to receive an output clock and generate the feedback signal based on the output clock. The PLL includes an output clock generator configured to receive the delta value, generate a control signal based on the delta value, and generate the output clock signal based on the control signal. The PLL also includes a calibration circuit configured to provide a gain correction factor to the output clock generator, the output clock generator being further configured to adjust its gain in response to the gain correction factor.

[0005] In another exemplary aspect, a method for generating an output clock in a phase-locked loop is disclosed. The method includes receiving a reference clock and a feedback signal at a delta detector, generating a delta value at the delta detector indicating a time difference between the reference clock and the feedback signal, receiving an output clock at a divider circuit, and generating the feedback signal based on the output clock. The method further includes receiving the delta value at an output clock generator, generating a control signal based on the delta value, and generating the output clock based on the control signal. The method also includes providing a gain correction factor to the output clock generator by a calibration circuit, and adjusting a gain of the output clock generator in response to the gain correction factor.

[0006] In another exemplary aspect, an IC is disclosed. The IC includes logic circuits arranged in multiple clock domains, each clock domain including multiple PLLs configured to generate a clock that is provided to the logic circuits in the corresponding clock domain. Each PLL in the IC includes a delta detector configured to receive a reference clock and a feedback signal and generate a delta value indicative of a time difference between the reference clock and the feedback signal, and a divider circuit configured to receive an output clock and generate the feedback signal based on the output clock. The PLL includes an output clock generator configured to receive the delta value, generate a control signal based on the delta value, and generate the output clock signal based on the control signal. The PLL also includes a calibration circuit configured to provide a gain correction factor to the output clock generator, the output clock generator being further configured to adjust its gain in response to the gain correction factor.

[0007] BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate several aspects of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. [Brief explanation of the drawings]

[0008] [Figure 1A] FIG. 1 is a block diagram of a phase-locked loop (PLL) configured for two-point injection. [Figure 1B]

[0009] FIG. 1B is a diagram of a signal injected into the PLL of FIG. 1A. [Figure 1C] FIG. 1 is a diagram of an output signal modulated with an output clock based on an injected signal. [Figure 2]

[0010] 1 is a first example of an exemplary PLL that includes a calibration circuit configured to provide a gain correction factor to adjust an output clock generator to a nominal gain corresponding to a desired PLL loop bandwidth. [Figure 3]

[0011] 1 is a flowchart of a method for generating an output clock in a PLL, including providing a gain correction factor to adjust the output clock generator to a nominal gain. [Figure 4]

[0012] 1 is a second example of an exemplary PLL that includes a calibration circuit configured to provide a gain correction factor to adjust the output clock generator to a nominal gain corresponding to a desired PLL loop bandwidth. [Figure 5]

[0013] 3 is an example of the PLL of FIG. 2 configured to determine and store gain correction factors for multiple frequencies of an output clock generator within the PLL. [Figure 6]

[0014] 5 is an example of the PLL of FIG. 4 configured to determine and store gain correction factors for multiple frequencies of an output clock generator within the PLL. [Figure 7]

[0015] FIG. 1 is a block diagram of an exemplary processor-based system including multiple devices coupled via a system bus, the processor-based system including at least one integrated circuit (IC) including multiple clock domains, each of which includes a PLL including a calibration circuit configured to provide a gain correction factor to adjust an output clock generator to a nominal gain and normalize the jitter response across the IC. DETAILED DESCRIPTION OF THE INVENTION

[0009] Detailed Description

[0016] Some exemplary aspects of the present disclosure are described with reference to the drawings. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0010]

[0017] Exemplary aspects disclosed herein include a phase-locked loop (PLL) including a digitally controlled oscillator (DCO) gain calibration circuit. Related methods for DCO gain calibration are also disclosed. Synchronization of clocks in different clock domains of an integrated circuit (IC) is important for high-performance interfaces between these clock domains. A PLL can achieve synchronization between clock domains by generating the domain clocks based on the same reference clock. However, jitter in the reference clock signal can disrupt synchronization if the PLLs do not respond to jitter in the same way. In the exemplary PLL disclosed herein, a calibration circuit provides a gain correction factor to achieve a nominal gain in the output clock generator for a desired loop bandwidth. In this manner, PLLs in different clock domains can be calibrated to have similar jitter responses. When the loop bandwidths of all PLLs in an IC are calibrated to the desired loop bandwidth, they respond similarly to jitter in the reference clock, maintaining negligible relative timing uncertainty while also maintaining a high-performance interface. The PLL feedback loop detects the time difference between the reference clock and a feedback signal based on the output clock. A PLL includes an output clock generator that adjusts the output clock to reduce the time difference. The gain of the output clock generator, determined in part by the DCO, is one factor that determines how the output clock generator responds to reference clock jitter. The DCO gain, and therefore the output clock generator gain, can vary from PLL to PLL due to differences in manufacturing process and circuit environment. A calibration circuit can be employed to determine and provide a gain correction factor that adjusts the gain of the output clock generator to a nominal gain corresponding to the desired loop bandwidth of the PLL.

[0011]

[0018] FIG. 1A is a block diagram of a phase-locked loop (PLL) 100 that is referenced in the following discussion regarding the two-point injection employed in the calibration circuit 202 of the PLL 200 of FIG.

[0012]

[0019] The PLL 100 includes a delta detector 102, an output clock generator 104, and a divider circuit 106. The delta detector 102 receives a reference clock CLK_REF and a feedback signal FB from the divider circuit 106. The reference clock CLK_REF is received from an external source, such as a crystal-controlled oscillator, and generates a reference frequency F REF The feedback signal FB oscillates at the reference frequency F of the reference clock CLK_REF. REF A frequency F that is the same as or very close to FB The delta detector 102 determines a delta time DT, which is the time difference between the reference clock CLK_REF and the feedback signal FB. The delta time DT is quantified in digital form as a delta value DV (e.g., a binary number) generated by the delta detector 102.

[0013]

[0020] The output clock generator 104 receives the delta value DV and generates the output clock CLK_OUT based on the delta value DV, which includes the phase difference and frequency difference information between CLK_REF and CLK_OUT, resulting in a reference frequency F REF Output clock frequency F that is a multiple (e.g., integer multiple N) of OUT The divider circuit 106 can generate the output clock CLK_OUT at an output clock frequency F OUT receives the output clock CLK_OUT at REF A feedback signal FB is generated.

[0014]

[0021] More specifically, the delta detector 102 includes a phase frequency detector (PFD) 108 and a time-to-digital converter (TDC) 110. The PFD 108 receives the reference clock CLK_REF and the feedback signal FB, detects a delta time DT, and indicates the delta time DT as the time difference between the start signal STRT and the stop signal STOP, which is provided to the TDC 110. For example, the delta time DT may be the time between the rising edge (e.g., in voltage) of the start signal STRT and the rising edge of the stop signal STOP. The TDC 110 digitally quantifies the delta time DT as a binary value, which is provided to the output clock generator 104 as a delta value DV. The delta value DV can be positive or negative depending on whether the feedback signal FB leads or lags the reference clock CLK_REF.

[0015]

[0022] The output clock generator 104 includes a digital low-pass filter (DLF) 112 and a digitally controlled oscillator (DCO) 114 that generates the output clock CLK_OUT. The DLF 112 receives a delta value DV from the TDC 110, filters out high-frequency noise, and provides a control signal DCO_CTL to the DCO 114. The DCO 114 adjusts the frequency of the output clock CLK_OUT based on the control signal DCO_CTL.

[0016]

[0023] As described above, the PLL 100 is configured for two-point injection. In this regard, the output clock generator 104 also includes a first summer 116 between the DLF 112 and the DCO 114. A second summer 118 is coupled between the divider circuit 106 and the delta detector 102. The locations of the first summer 116 and the second summer 118 are selected to provide an all-pass transfer function for the injection signal 120. From the first summer 116 to the output clock CLK_OUT, only the DCO 114 is present in the feedforward path, resulting in a high-pass transfer function that boosts high-frequency inputs above a first "corner" frequency. From the second summer 118 to the output clock CLK_OUT, the PLL 100 has a low-pass transfer function that filters out high-frequency inputs above a second "corner" frequency. Adding the injection signal 120 to the feedback signal FB at the second summer 118 and the injection signal 120' to the control signal DCO_CTL at the first summer 116 combines high-pass and low-pass filtering of the loop, producing an all-pass transfer function if the first and second corner frequencies are aligned at the same frequency. The injection signal 120' is a weighted version of the injection signal 120, multiplied by the coefficient required for injection at the first summer 116.

[0017]

[0024] The injection signal 120 may be added to the output clock CLK_OUT. This may include, for example, adding a function N(z) (see FIG. 1B) in a second adder 118 and adding a weighted version of the function N(z) (W×N(z)) to the control signal DCO_CTL in a first adder. The coefficient W is used in the first adder 116 to account for differences in the injection points. In a transmitter, two-point injection can be used to modulate a carrier signal (e.g., CLK_OUT) by adding the injection signal 120 (N(z)) as the data signal to be transmitted. The injection signal 120 with the function N(z) can be added (e.g., by modulating) N(z) at the output clock CLK_OUT. OUT (See FIG. 1C.) The output signal N(z)OUT The relationship between the weighting factor W and the gain of the DCO 114 depends on the matching between the weighting factor W and the gain of the DCO 114. When the other components of the PLL are well gain controlled, this relationship can also be said to depend on the matching between the nominal / target loop bandwidth and the actual loop bandwidth of the PLL 100. In general, the loop bandwidth (LBW) of the PLL 100 is given by:

[0018]

[0025] LBW=K DD ×K DLF ×K DCO ×1 / 2πN, in the formula,

[0019]

[0026] K DD = the gain of the delta detector 102,

[0020]

[0027] K DLF = proportional component of the gain of DLF 112,

[0021]

[0028] K DCO = the frequency gain of the DCO 114,

[0022]

[0029] N=clock divisor, and the output clock CLK_OUT is divided by this divisor in divider circuit 106 to generate feedback signal FB. There are also variables not shown in FIG.

[0023]

[0030] 1B shows an example of an injection signal 120 (N(z)) being summed in the second summer 118, and in the first summer 116, this injection signal 120 is applied with a weight W as 120'. FIG. 1C shows an example of three different gains (K DCO ) that may be generated at the output clock CLK_OUT in response to the injection signal 120 (N(z)) under three different loop bandwidth conditions of the PLL 100. OUT The solid line 124 in FIG. 1C shows an example of the intended output signal N(z) that best corresponds to the injected signal 120 (N(z)) in FIG. 1B. OUT The short dashed line 126 indicates the gain K of the DCO 114.DCO In an example where the loop bandwidth is not the desired loop bandwidth because OUT Here, the DCO 114 responds poorly to changes in the injection signal 120, rising and falling more slowly than expected. In contrast, the long dashed line 128 indicates the gain K DCO is higher than desired, so the output signal N(z) OUT , where the DCO 114 produces a stronger response than desired (i.e., a larger rise and fall than desired). However, the gain K DCO may vary from DCO 114 to DCO 114 based on factors such as manufacturing process variations (process, voltage, temperature (PVT)) and the circuit conditions in which the DCO is implemented. Thus, the gain of DCO 114 of PLL 100 may differ for different clock domains within an IC in response to such factors, causing differences in loop bandwidth and PLLs in different clock domains to respond differently to noise or jitter on the reference clock or other points within PLL 100.

[0024]

[0031] FIG. 2 is a block diagram of an example of an exemplary PLL 200 in an IC 201, showing the nominal gain K of the output clock generator 204 relative to the desired loop bandwidth of the PLL 200. NOM (not shown) to achieve the gain correction factor K CF The IC 201 may include multiple PLLs, each of which may be the exemplary PLL 200, that provide an output clock to a clock domain of a digital logic circuit. The calibration circuit 202 first calculates a gain correction factor K CF Determine the gain correction factor K CF is employed in the calibration method to store the gain correction factor K from the gain control circuit 206 of the calibration circuit 202. After calibration, the output clock generator 204 receives the gain correction factor K from the gain control circuit 206. CF and adjust the gain of output clock generator 204 to a nominal gain K to achieve the desired loop bandwidth. NOMAdjust to.

[0025]

[0032] Before describing the calibration circuit 202 and the calibration method, details of the PLL 200 will first be presented. The PLL 200 corresponds to the PLL 100 of FIG. 1 configured for two-point injection. The PLL 200 includes a delta detector 208 that receives a reference clock CLK_REF and a feedback signal FB. The delta detector 208 generates a delta value DV that indicates the time difference between the reference clock CLK_REF and the feedback signal FB. The delta detector 208 includes a phase-frequency detector 207 and a time-to-digital converter 209. The PLL 200 also includes a divider circuit 210 that receives the output clock CLK_OUT generated by the output clock generator 204 and divides the output clock CLK_OUT to generate the feedback signal FB. The frequency F of the output clock CLK_OUT is OUT is the frequency of the reference clock CLK_REF, F REF The divider circuit 210 divides the output clock CLK_OUT by a clock divisor DVSR (e.g., N), resulting in a frequency F of the feedback signal. FB is the frequency of the reference clock CLK_REF, F REF will be the same as or very close to it.

[0026]

[0033] The output clock generator 204 receives the delta value DV from the delta detector 208 and generates a control signal DCO_CTL. The DCO 214 of the output clock generator 204 generates the output clock CLK_OUT based on the control signal DCO_CTL. The PLL 200 includes a calibration circuit 202, which includes a gain control circuit 206, which controls a gain correction factor K CF The output clock generator 204 further includes a gain correction accumulation circuit 220 ("accumulator 220") that generates and stores the gain K 204 is the gain correction factor K CF In particular, the gain K of the DCO 214 DCO is the nominal gain K that provides the desired loop bandwidth of the PLL 200.DCO_NOM If not, the gain correction factor K CF to determine and apply the (total) gain K of the output clock generator 204 204 can be adjusted.

[0027]

[0034] 2, the output clock generator 204 includes a digital multiplier circuit 216 coupled to the gain control circuit 206 and the delta detector 208. The digital multiplier circuit 216 generates a gain correction factor K CF and the delta value DV as a multi-bit digital value, and multiplying them to obtain an adjusted delta value DV ADJ The delta value DV is multiplied by the gain correction coefficient K CF , the total gain K of the output clock generator 204 is 204 is adjusted to the desired nominal gain value so that the PLL 200 has the desired loop bandwidth for all-pass transfer capability. CF can be applied to each PLL in an IC to provide a similar, if not identical, response to jitter in the reference clock CLK_REF. A consistent jitter response minimizes clock synchronization issues between different clock domains, thereby maintaining optimized interface conditions between the clock domains. Within the output clock generator 204, the adjusted delta value DV ADJ is provided to a digital low pass filter (DLF) 218, which filters the adjusted delta value DV ADJ As discussed further below, summer 234 does not modify the control signal DCO_CTL during normal operation.

[0028]

[0035] 2, output clock generator 204 does not include digital multiplication circuit 216. Instead, DLF 218 can receive delta value DV directly from delta detector 208 and generate a filtered delta value FDV (not shown) that is provided to a multiplier located in place of summer 234 in FIG. 2. This multiplier combines filtered delta value FDV and gain correction factor K CF and multiplies them to generate the control signal DCO_CTL that is provided to the DCO 214. Essentially, the digital multiplier circuit 216 is simply moved from the input side to the output side of the DLF 218. The gain correction factor K CF This alternative is possible because ∇ ...

[0029]

[0036] Returning to PLL 200 of Figure 2, the features of calibration circuit 202 will be described in the context of a method for calibrating PLL 200. This method involves calibrating PLL 200 to a nominal gain K NOM The gain correction factor K required to have CF This includes determining the gain correction factor K CF is stored in accumulator 220. Calibration relies on aspects of a two-point injection method. As described with reference to FIGS. 1A-1C, if a first corner frequency of the high-pass transfer function of DCO 214 corresponds to a second corner frequency of the low-pass transfer function of PLL 200, the loop bandwidth of PLL 200 provides an all-pass transfer function from N(z) to the output clock CLK_OUT. The alignment of the first and second corner frequencies determines the gain K of DCO 214. DCO is the nominal gain value K DCO_NOM The gain K DCO may vary due to various manufacturing and environmental factors. DCO is the nominal gain value K DCO_NOMDetermining whether FB_CALSIG is greater than FB_CALSIG may include monitoring the response of PLL 200 to two-point injection of signals. In this regard, corresponding calibration signals FB_CALSIG and DCO_CALSIG are injected into the feedback signal FB and the control signal DCO_CTL, respectively. DCO_CALSIG is a weighted version of FB_CALSIG, with a weighting factor W=F. REF / K DCO_NOM (i.e., DCO_CALSIG=F REF / K DCO_NOM FB_CALSIG is added to the divisor DVSR of the frequency divider circuit 210, REF ×FB_CALSIG allows OUT At the same time, the gain calibration adjustment GCA(K CF = 1, i.e., if the gain control circuit 206 has not yet been activated, a signal equal to DCO_CALSIG is injected into DCO_CTL, and F REF / K DCO_NOM ×FB_CALSIG×K DCO By F OUT changes instantly. K DCO_NOM =K DCO If , the two-point injection contributes exactly the same amount of frequency change in the all-pass transfer. Otherwise, the access gain of the low-pass or high-pass path will cause distortion in the output, as shown in FIG. 1C. Such distortion will generate a time error (denoted as delta value DV), which is then collected by the gain control circuit 206 to generate an error gradient for the least mean square (LMS) gain correction calculation. After several iterations, the final gain correction value K CF is K DCO_NOM / K DCO The calibration resolution is determined by the bit length used in accumulator 220.

[0030]

[0037] In this example, the calibration input FB_CALSIG is a series of pulses (only two levels: "0" and "1"). Each such pulse has a duration of multiple cycles (e.g., M cycles) of the reference clock CLK_REF. As explained in more detail below, the pulses of the calibration signal FB_CALSIG cause the divider circuit 210 to increment the clock divisor DVSR (e.g., from N to N+1). The delta value DV is monitored / collected during positive pulses of the calibration signal FB_CALSIG (implemented by AND logic circuit ("gate") 228). The accumulator 220 stores the gain correction factor K CF At each cycle of FB_CALSIG, accumulator 220 initializes K CF is the target K with a preset resolution. DCO_NOM / K DCO Based on the error gradient (i.e., the output of gate 228), the gain correction factor K CF is increased or decreased in stages.

[0031]

[0038] Also, during each pulse of the calibration signal FB_CALSIG, the gain correction factor K CF is multiplied by a nominal calibration value DCO_CALSIG to produce a gain calibration adjustment GCA that is the product of the multiplication. The gain calibration adjustment GCA is injected (i.e., added) to the control signal DCO_CTL. The nominal calibration value DCO_CALSIG corresponds to a weighted version of the injection signal 120 of FIG. 1, as discussed above, with the weighting coefficients being a function of the frequency F of the reference clock CLK_REF. REF and the nominal gain K of the DCO 214 DCO_NOM Based on the nominal gain K DCO_NOM is the nominal gain K of the output clock generator 204 for the desired loop bandwidth of the PLL 200 NOM The gain correction factor K CF gives the output clock generator 204 a nominal gain K NOM When this is achieved, the gain correction factor K CF stabilizes (i.e., stops or nearly stops incrementing).

[0032]

[0039] The control signal DCO_CTL is a gain correction factor K CF Depending on the sign of , it can be increased or decreased by the gain calibration adjustment GCA. In this way, the gain correction factor K CF A change in τ causes an adjustment in the control signal DCO_CTL, which in turn changes the output clock CLK_OUT, and the delta value DV reflects that adjustment in the next cycle. After a number of reference clock CLK_REF cycles (between pulses of the calibration signal FB_CALSIG), the gain correction factor K CF The delta value DV decreases due to the change in CF Stop adjusting.

[0033]

[0040] The calibration signal FB_CALSIG is pulsed by a constant period of increasing voltage (for example, from 0 volts to the supply voltage V DD Between pulses of the calibration signal FB_CALSIG (e.g., at 0 volts), the clock divisor DVSR returns from N+1 to N, and the accumulator 220 resets the gain correction factor K CF The gain calibration adjustment GCA does not modify the control signal DCO_CTL. After repeating the above-described operation for the number of pulses of the calibration signal FB_CALSIG, the gain correction coefficient K CF Upon completion of the calibration method, the gain correction factor K is adjusted during normal operation (e.g., thereafter) as described above to operate PLL 200 at the desired loop bandwidth. CF is provided to the output clock generator 204.

[0034]

[0041] As mentioned above, storage circuit 220 is included in gain control circuit 206 of calibration circuit 202. Additional features of calibration circuit 202 shown in FIG. 2 include the following: calibration signal FB_CALSIG is generated by signal divider 224, which receives feedback signal FB and generates calibration signal FB_CALSIG based on feedback signal FB. During the pulse, calibration signal FB_CALSIG is active and is coupled to power supply voltage V DD Between pulses, the calibration signal FB_CALSIG can be at a low voltage (e.g., ground V SS and / or 0 volts). A switch 226 couples the signal divider 224 to the divider circuit 210 while calibration is enabled by a calibration enable signal. The feedback signal FB may be divided by an integer value 2M to generate the calibration signal FB_CALSIG, where each pulse has a duration of M cycles of the feedback signal FB. An AND gate 228 passes the delta value DV to the accumulator 220 in response to the calibration signal FB_CALSIG being active (e.g., during a pulse of the calibration signal FB_CALSIG). Another AND gate 230 multiplies the nominal calibration value DCO_CALSIG by a gain correction factor K CF is multiplied, thereby injecting a gain calibration adjustment GCA into the control signal DCO_CTL. The multiplication circuit 232 multiplies the nominal calibration value DCO_CALSIG by the gain correction factor K CF Multiply the nominal calibration value DCO_CALSIG and the gain correction factor K CF The gain calibration adjustment value GCA, which is a product of DCO_CTL and DCO_CTL, is added to the control signal DCO_CTL by adder 234. The specific details of the calibration circuit 202 and calibration methodology described above are non-limiting examples.

[0035]

[0042] 3 is a flowchart illustrating a method 300 for adjusting the gain of PLL 200. The method includes receiving a reference clock CLK_REF and a feedback signal FB at delta detector 208 (block 302) and generating a delta value DV indicative of a time difference between the reference clock CLK_REF and the feedback signal FB (block 304). The method includes receiving an output clock CLK_OUT at divider circuit 210 (block 306) and dividing the output clock CLK_OUT to generate the feedback signal FB (block 308). The method includes receiving the delta value DV at output clock generator 204 (block 310), generating a control signal DCO_CTL based on the delta value DV (block 312), and generating the output clock CLK_OUT based on the control signal DCO_CTL (block 314). The method includes assigning a gain correction factor K to gain control circuit 206 of calibration circuit 202. CF (block 316), and storing the gain correction factor K CF to the output clock generator 204 (block 318), and providing a gain correction factor K CF and adjusting the gain in response to (Block 320).

[0036]

[0043] FIG. 4 is a block diagram of a second example of an exemplary PLL 400, which has a nominal gain K NOM To achieve this, the output clock generator 404 is provided with a gain correction factor K DCF 4 that have similar functions as features of FIG. 2 are similarly named. As a reminder, in the PLL 200 described above, adjusting the gain of the output clock generator 204 involves applying a gain correction factor K to the delta value DV at the output clock generator. CF to obtain the adjusted delta value DV ADJ Note that this involves generating the adjusted delta value DV ADJ and the gain K of the DCO 214 DCOis the nominal (e.g., desired) gain K of the output clock generator 204 NOM In contrast, as will be described below, adjusting the gain of the output clock generator 404 of the PLL 400 provides a nominal gain K NOM The nominal gain K of the DCO 406 corresponds to DCO_NOM To achieve this, the gain correction factor K DCF The method includes adjusting the amount of bias current to the ring oscillator 442 of the DCO 406 based on the

[0037]

[0044] PLL 400 includes a delta detector 408 and a divider circuit 410, which correspond to delta detector 208 and divider circuit 210 of Figure 2 described in detail above. Delta detector 408 includes a phase frequency detector 407 and a TDC circuit 409. Calibration circuit 402 includes the features of calibration circuit 202 of Figure 2, but does not include the gain correction factor K of Figure 4. DCF is the gain correction coefficient K CF 2 adjusts the gain of output clock generator 404 in a manner different from the way that output clock generator 412 adjusts the gain of output clock generator 204. Additionally, output clock generator 404 does not include a digital multiplier corresponding to digital multiplier circuit 216 of FIG. 2. Instead, gain control circuit 412 controls bias current slices 414(1) through 414(X) of DCO 406 to directly adjust the frequency response of DCO 406 to the control signal DCO_CTL. Bias current slices 414(1) through 414(X) each adjust the frequency response of DCO 406 relative to the power supply voltage V DD The gain of the output clock generator 404 is adjusted using a gain correction factor K DCF Based on this, the gain K of the output clock generator 404 NOM This includes determining the number of bias current slices 414(1) through 414(X) that are activated to provide power to the DCO 406 to achieve this.

[0038]

[0045] In structural details, calibration circuit 402 includes a signal divider 416 that generates calibration signal FB_CALSIG based on feedback signal FB in the manner described with reference to Figure 2. Calibration circuit 402 also includes a switch 418 that couples signal divider 416 to divider circuit 410 in response to a calibration enable signal CALIB_EN. During a pulse of calibration signal FB_CALSIG, divider circuit 410 increments clock divisor DVSR (e.g., from N to N+1) and branches feedback signal FB from reference clock CLK_REF, providing the first injection point in the two-point injection method.

[0039]

[0046] An AND gate 422 provides the delta value DV to an accumulation circuit ("accumulator") 420 within the gain control circuit 412. The accumulator 420 may implement an LMS algorithm to determine the stable gain index STBL over multiple cycles of the reference clock CLK_REF that occur between pulses of the calibration signal FB_CALSIG, as described above. The gain control circuit 412 includes a multiplication circuit 426 and another AND logic circuit 428. In response to the calibration signal FB_CALSIG (active), the AND gate 428 applies a weighting factor F to DCO_CALSIG. REF / K DCO_NOM and sends it to multiplier circuit 426. Multiplier circuit 426 multiplies the nominal calibration value DCO_CALSIG by the stable gain index STBL to generate the gain calibration adjustment GCA. A summing circuit 430 coupled between DLF 432 and DCO 406 provides a second injection point into PLL 400, as described above, where the gain calibration adjustment GCA is added to the control signal DCO_CTL. The calibration signal DCO_CALSIG is a function of the frequency F of the reference clock CLK_REF. REF and the nominal gain K of the DCO 406 DCO_NOM (This is the nominal gain K NOM The stable gain index STBL is based on the fact that the output clock generator 404 has a nominal gain K NOM This is achieved by the gain correction factor K DCF In response to the DCO 406, the DCO 406 has a nominal gain K DCO_NOM This is equivalent to achieving

[0040]

[0047] Gain correction factor K DCF is generated based on the stable gain index STBL and stored in a second storage circuit 434 of the gain control circuit 412. Specifically, the gain control circuit 412 includes a clamp circuit 436 that receives the stable gain index STBL and generates a step adjustment INCR that is provided to the second storage circuit 434. The clamp circuit 436 also receives a high value and a low value for a desired range within which the stable gain index STBL should settle. In response to whether the stable gain index STBL rises above the high value or falls below the low value, the clamp circuit 436 causes the step adjustment INCR to indicate whether to increase, decrease, or leave the second storage circuit 434 unchanged (e.g., with values ​​of +1, −1, or 0) to achieve and stay between the high and low values.

[0041]

[0048] As mentioned above, the gain correction factor K DCF controls the number of bias current slices 414(1) through 414(X). The second storage circuit 434 stores the gain correction factor K as a digital signal that determines how many current units are activated. DCF When calibration of the output clock generator 404 begins, the gain correction factor K DCF can be set to activate, for example, half (X / 2) of the bias current slices 414(1) to 414(X). In response to the stepwise adjustment INCR, the second storage circuit 434 calculates the gain correction factor K based on the stable gain index STBL, which is based on the delta value DV. DCF The change in current through the DCO 406 causes the frequency gain of the output clock CLK_OUT to increase or decrease accordingly. After a number of cycles of the reference clock CLK_REF during which the calibration signal FB_CALSIG is active (i.e., between pulses), the gain correction factor K stored in the second storage circuit 434 DCFThis increases or decreases the number of activated bias current slices 414(1)-414(X), adjusting the output clock CLK_OUT and decreasing the delta value DV, so that the stable gain index STBL stabilizes at a value in the desired range between the high and low values ​​provided to the clamp circuit 436.

[0042]

[0049] The gain correction coefficient K is determined according to the number X of the bias current slices 414(1) to 414(X). DCF can be a low-granularity value (e.g., a binary word with many decimal points). DCF is adjusted gradually because each incremental change can significantly change the amount of current going to DCO 406. By adjusting gradually, PLL 400 adjusts the gain correction factor K DCF , sufficient time is allowed to respond to each change in . In this regard, gain control circuit 412 further includes a counter circuit 438 ("counter 438") that is incremented with each pulse of feedback signal FB until the counter value reaches a maximum number (indicating the end of the calibration period). After reaching the maximum number, counter 438 resets and begins counting again. Second storage circuit 434 is clocked during each calibration period on a transition (e.g., from 1 to 0) of the most significant bit (MSB) of the counter value of counter 438. In this manner, second storage circuit 434 increments gain correction factor K once per period between transitions of the MSB of counter 438. DCF and adjust the gain correction factor K DCF Ensure that the adjustment is gradual.

[0043]

[0050] 4 includes a current matching circuit 440 controlled by a control signal DCO_CTL and a ring oscillator 442 tuned by bias current slices 414(1)-414(X). The bias current slices 414(1)-414(X) are coupled in parallel to a power rail (not shown) and are connected to a supply voltage (e.g., V DD) is provided. The number of bias current slices 414(1) through 414(X) that are activated to provide power to the DCO 406 is determined by the gain correction factor K DCF The operation of such features should be understood by those skilled in the art.

[0044]

[0051] 5 and 6 show variations of PLL 200 of FIG. 2 and PLL 400 of FIG. 4, with nominal gain K NOM has been modified to be configurable.

[0045]

[0052] Features of PLL 500 in Figure 5 that correspond to those in Figure 2 are numbered the same and will not be described again here. Calibration circuit 502 includes a gain control circuit 504 that corresponds to gain control circuit 206, including AND gates 228, 230, multiplier circuit 232, and adder 234. Instead of accumulator 220, gain control circuit 504 includes accumulators 506(1) through 506(K), where K is the number of frequencies at which PLL 500 can be calibrated. Multiplexers 508, 510 are controlled by control logic (not shown) internal or external to PLL 500. Each of the multiple output clock frequencies at which PLL 500 is calibrated corresponds to an integer N1 through N-K, which is employed as divisor DVSR. Multiplexer 508 receives a gain correction factor K determined at one of the K different frequencies during calibration. CF (1)~K CF 2. At each of the calibration frequencies corresponding to integers N1 through NK, the operation of calibration circuit 502 corresponds to the operation of calibration circuit 202 of FIG. 2.

[0046]

[0053] PLL 600 of FIG. 6 essentially corresponds to PLL 400 of FIG. 4, so like features are numbered the same and will not be described again here. PLL 600 differs from PLL 400 with respect to calibration circuit 602, which includes gain control circuit 604, because PLL 600 can be calibrated at multiple frequencies corresponding to different integer clock divisors DVSR. Gain control circuit 604 corresponds to gain control circuit 412 at each of the multiple frequencies, but like PLL 500, PLL 600 can be calibrated to multiple (K) frequencies. In this regard, second accumulation circuit 434 of FIG. 4 has been replaced with second accumulation circuit 605 and multiplexers 608, 610, which correspond to accumulators 506(1) through 506(K) and multiplexers 508, 510 of FIG. 5. Multiplexers 608, 610 multiplex the selected output clock frequency F at each integer clock divisor DVSR(N) provided to divider circuit 410. OUT The gain correction factor K DCF 4. At each individual calibration frequency, the operation of calibration circuit 602 corresponds to the operation of calibration circuit 402 of FIG.

[0047]

[0054] 7 is a block diagram of an exemplary processor-based system 700 including a processor 702 (e.g., a microprocessor) that includes instruction processing circuitry 704. The processor-based system 700 may represent one or more circuits included on an electronic board card, such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing pad, a mobile device, or any other device, for example, a server or a user's computer. In this example, the processor-based system 700 includes a processor 702. The processor 702 represents one or more general-purpose processing circuits, such as a microprocessor, a central processing unit, or the like. More specifically, the processor 702 may be an EDGE instruction set microprocessor or other processor that implements an instruction set that supports explicit consumer money for communicating generated values ​​that are the result of execution of producer instructions. The processor 702 is configured to execute the processing logic of instructions to perform the operations and steps discussed herein. In this example, processor 702 includes an instruction cache 706 for temporary, fast-access memory storage of instructions accessible by instruction processing circuits 704. Instructions fetched or prefetched from memory, such as main memory 708, over a system bus 710 are stored in instruction cache 706. Data may be stored in a cache memory 712 coupled to system bus 710 for low-latency access by processor 702. Instruction processing circuits 704 are configured to process instructions fetched into instruction cache 706 and to process the instructions for execution.

[0048]

[0055] The processor 702 and main memory 708 are coupled to a system bus 710, which may interconnect peripheral devices included in the processor-based system 700. As is well known, the processor 702 communicates with these other devices by exchanging address, control, and data information over the system bus 710. For example, the processor 702 may communicate bus transaction requests to a memory controller 714 in the main memory 708, serving as an example of a slave device. Although not shown in FIG. 7, multiple system buses 710 may be provided, with each system bus 710 constituting a different fabric. In this example, the memory controller 714 is configured to provide memory access requests to a memory array 716 in the main memory 708. The memory array 716 is comprised of an array of storage bit cells for storing data. The main memory 708 may be, by way of non-limiting example, a read-only memory (ROM), a flash memory, a dynamic random access memory (DRAM) such as a synchronous DRAM (SDRAM), and / or a static memory (e.g., flash memory, SRAM, etc.).

[0049]

[0056] Other devices may be connected to the system bus 710. As shown in FIG. 7, these devices may include, by way of example, a main memory 708, one or more input devices 718, one or more output devices 720, a modem 722, and one or more display controllers 724. The input devices 718 may include any type of input device, including, but not limited to, input keys, switches, audio processors, etc. The output devices 720 may include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The modem 722 may be any device configured to exchange data with a network 726. The network 726 may be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The modem 722 may be configured to support any type of communication protocol desired. The processor 702 may also be configured to access a display controller 724 over the system bus 710 to control information sent to one or more displays 728. The displays 728 may include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, etc.

[0050]

[0057] 7 may include an instruction set 730 that is executed by the processor 702 for any desired purpose in accordance with the instructions. The instructions 730 may be stored in the main memory 708, the processor 702, and / or the instruction cache 706, as examples of non-transitory computer-readable media 732. The instructions 730 may also reside, completely or at least partially, within the main memory 708 and / or the processor 702 during their execution. Furthermore, the instructions 730 may be transmitted or received over the network 726 via the modem 722, in which case the network 726 includes the computer-readable medium 732.

[0051]

[0058] Any of the circuits within the processor-based system 700 (particularly the modem 722 and the output device 720) may include multiple clock domains, each of which includes a PLL that includes a calibration circuit configured to provide a gain correction factor to adjust the output clock generator to a nominal gain and normalize the jitter response of the entire IC, as shown in Figures 2, 4, 5, and 6.

[0052]

[0059] While in the exemplary embodiment, computer-readable medium 1132 is shown to be a single medium, the term "computer-readable medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable medium" should also be taken to include any medium capable of storing, encoding, or retaining a set of instructions for execution by a processing device, causing the processing device to perform any one or more of the methodologies of the embodiments disclosed herein. Accordingly, the term "computer-readable medium" should be taken to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0053]

[0060] The embodiments disclosed herein include various steps that may be formed by hardware components, embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor programmed with the instructions to perform the steps, or may be performed by a combination of hardware and software.

[0054]

[0061] The embodiments disclosed herein may be provided as a computer program product or software, which may include a machine-readable medium (or computer-readable medium) having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium includes a machine-readable storage medium (e.g., ROM, random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory devices, etc.), and the like.

[0055]

[0062] Unless specifically stated otherwise, and as will be apparent from the preceding discussion, throughout the description, discussions using terms such as "processing," "computing," "determining," "displaying," or the like, should be understood to refer to the operations and processes of a computer system or similar electronic computing device that manipulate and transform data and memory represented as physical (electronic) quantities in the computer system's registers into other data similarly represented as physical quantities in the computer system's memory or registers or other such information storage, transmission, or display devices.

[0056]

[0063] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various systems can be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the required method steps. The required structure for a variety of such systems will appear from the description above. In addition, the embodiments described herein are not described with reference to any particular programming language. It will be understood that a variety of programming languages ​​can be used to implement the teachings of the embodiments described herein.

[0057]

[0064] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein can be implemented as electronic hardware, as instructions stored in a memory or another computer-readable medium and executed by a processor or other processing device, or as a combination of both. The memories disclosed herein may be any type and size of memory and may be configured to store any desired type of information. To clearly illustrate this interchangeability, the above description describes various illustrative components, blocks, modules, circuits, and steps generally in terms of their functionality. How such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments.

[0058]

[0065] The various example logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed by a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Additionally, a controller may be a processor. A processor may be a microprocessor, but alternatively, a processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0059]

[0066] The embodiments disclosed herein may be embodied in hardware and instructions stored in the hardware, such as RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, removable disk, CD-ROM, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a remote station. In the alternative, the processor and the storage medium may reside as discrete components in a remote station, a base station, or a server.

[0060]

[0067] It should also be noted that the operational steps described in any of the exemplary embodiments herein are set forth for purposes of example and discussion. The described operations may be performed in many different sequences other than the sequence shown. Furthermore, an operation described as a single operational step may actually be performed in many different steps. Additionally, one or more operational steps discussed in the exemplary embodiments may be combined. Those skilled in the art will also appreciate that information and signals may be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields, optical fields, particles, or any combination thereof.

[0061]

[0068] Unless otherwise expressly stated, it is in no way intended that the methodologies described herein be construed as requiring that its steps be performed in a particular order. Accordingly, unless a method claim actually specifies the order in which its steps are to be followed, or the claim or description specifically states that the steps are limited to a particular order, no particular order is intended to be inferred.

[0062]

[0069] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the present invention. Since modifications, combinations, subcombinations, and variations of the disclosed embodiments that incorporate the spirit and substance of the present invention will occur to those skilled in the art, the present invention should be construed as including all within the scope of the appended claims and equivalents thereof.

Claims

1. receiving a reference clock (CLK_REF) and a feedback signal (CLK_FB); Generate a delta value (DV) that indicates the time difference between the reference clock (CLK_REF) and the feedback signal (CLK_FB) a delta detector configured as follows: Receives an output clock (CLK_OUT); Generate the feedback signal (CLK_FB) based on the output clock (CLK_OUT) a frequency divider circuit configured as follows: receiving the delta value (DV); generating a control signal (DCO_CTL) based on the delta value (DV); Generate the output clock (CLK_OUT) based on the control signal (DCO_CTL) an output clock generator configured as follows: A gain correction factor (K ＣＦ a calibration circuit configured to provide A phase locked loop comprising: The output clock generator is configured to generate the gain correction factor (K ＣＦ ) the gain (K ２０４ ).

2. the output clock generator: a first multiplication circuit coupled to the calibration circuit and the delta detector and configured to multiply the delta value by the gain correction factor to generate an adjusted delta value; a digital low-pass filter coupled to the first multiplier circuit and configured to generate the control signal based on the adjusted delta value; 2. The phase-locked loop of claim 1, further comprising:

3. the output clock generator: a digital low pass filter configured to generate a filtered delta value based on the delta value; a first multiplier circuit configured to multiply the delta value by the gain correction factor to generate the control signal; 2. The phase-locked loop of claim 1, further comprising:

4. 2. The phase-locked loop of claim 1, wherein the output clock generator includes a digitally controlled oscillator (DCO) including bias current slices coupled in parallel to a power rail, and wherein the number of bias current slices activated to provide power to the DCO is based on the gain correction factor.

5. 5. The phase-locked loop of claim 4, wherein the DCO further comprises a ring oscillator circuit, and wherein the number of bias current slices that are activated provides power to the ring oscillator circuit.

6. the calibration circuit a calibration multiplication circuit; Addition circuit and Further comprising: The frequency divider circuit dividing the output clock by a clock divisor to generate the feedback signal; incrementing the clock divisor in response to a calibration signal; configured to: the calibration circuit responding to the calibration signal: multiplying the gain correction factor by a nominal calibration value in the calibration multiplication circuit to generate an injection calibration adjustment; adding the injection calibration adjustment to the control signal in the adder circuit; at each of a number of cycles of the reference clock, incrementally adjusting the gain correction factor based on the delta value at each of the number of cycles; 10. The phase-locked loop of claim 1, further configured to:

7. the calibration circuit a storage circuit configured to store the gain correction factor; a calibration multiplication circuit; Injection circuit and Further comprising: The frequency divider circuit dividing the output clock by a clock divisor to generate the feedback signal; incrementing the clock divisor in response to a calibration signal; configured to: the calibration circuit responding to the calibration signal: multiplying, by the calibration multiplication circuit, the gain correction factor by a nominal calibration value to generate a gain calibration adjustment; adding, by the injection circuit, the gain calibration adjustment to the control signal; adjusting the gain correction factor stored in the accumulation circuit based on the delta value during each of a number of cycles of the reference clock; 2. The phase-locked loop of claim 1 configured to:

8. the calibration circuit a clamp circuit; Counter circuit and Further comprising: The clamp circuit determining whether the gain correction factor is within a desired range; generating a gain adjustment in response to said determining; configured to: the counter circuit is configured to count the number of cycles of the reference clock; 8. The phase-locked loop of claim 7, wherein the calibration circuit is configured to adjust the gain correction factor based on the gain adjustment in each period.

9. the calibration circuit receiving the feedback signal; generating a calibration signal based on the feedback signal; modifying the clock divisor provided to the divider circuit in response to the calibration signal; a signal divider configured to: a first logic circuit configured to provide the delta value to the storage circuit in response to the calibration signal; a second logic circuit configured to provide the nominal calibration value to the calibration multiplication circuit in response to the calibration signal; 7. The phase locked loop of claim 6, further comprising:

10. the calibration circuit receiving the feedback signal; generating a calibration signal based on the feedback signal; modifying the clock divisor provided to the divider circuit in response to the calibration signal; a signal divider configured to: a first logic circuit configured to provide the delta value to the storage circuit in response to the calibration signal; a second logic circuit configured to provide the nominal calibration value to the calibration multiplication circuit in response to the calibration signal; 8. The phase locked loop of claim 7, further comprising:

11. 2. The phase-locked loop of claim 1, wherein the calibration circuit includes multiple accumulators, each accumulator corresponding to one of multiple output clock frequencies.

12. 1. A method for generating an output signal (CLK_OUT) in a phase locked loop, comprising: receiving a reference clock (CLK_REF) and a feedback signal (CLK_FB) at a delta detector; generating a delta value (DV) indicative of a time difference between the reference clock (CLK_REF) and the feedback signal (CLK_FB) in the delta detector; receiving an output clock (CLK_OUT) at a divider circuit; generating the feedback signal (CLK_FB) based on the output clock (CLK_OUT); receiving the delta value (DV) at an output clock generator; generating a control signal (DCO_CTL) based on the delta value (DV); generating the output clock (CLK_OUT) based on the control signal (DCO_CTL); A calibration circuit applies a gain correction factor (K ＣＦ ) and The gain correction factor (K ＣＦ ) the gain (K ２０４ ) and A method comprising:

13. adjusting the gain of the output clock generator in response to the gain correction factor; multiplying the delta value by the gain correction factor to generate an adjusted delta value; generating the control signal based on the adjusted delta value; The method of claim 12 further comprising:

14. adjusting the gain of the output clock generator in response to the gain correction factor; generating a filtered delta value based on the delta value; multiplying the delta value by the gain correction factor to generate the control signal; The method of claim 12 further comprising:

15. 1. An integrated circuit IC including logic circuitry arranged in multiple clock domains, each clock domain including multiple phase-locked loops (PLLs) configured to generate clocks provided to the logic circuitry in a corresponding clock domain, each PLL comprising: receiving a reference clock (CLK_REF) and a feedback signal (CLK_FB); Generate a delta value (DV) that indicates the time difference between the reference clock (CLK_REF) and the feedback signal (CLK_FB) a delta detector configured as follows: Receives an output clock (CLK_OUT); Generate the feedback signal (CLK_FB) based on the output clock (CLK_OUT) a frequency divider circuit configured as follows: receiving the delta value (DV); generating a control signal (DCO_CTL) based on the delta value (DV); Generate the output clock (CLK_OUT) based on the control signal (DCO_CTL) an output clock generator configured as follows: The output clock generator (K ＣＦ a calibration circuit configured to provide a gain correction factor to the Including, The output clock generator is configured to generate the gain correction factor (K ＣＦ ) in response to the gain (K ２０４ ).

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