AIII-BV compound semiconductor single crystal manufacturing apparatus and manufacturing method, and AIII-BV compound semiconductor single crystal and wafer

Abstract

An apparatus (1) for producing an AIII-BV compound semiconductor single crystal (4) from a melt of raw material (5) comprises: a crucible (6) for receiving the melt, the crucible (6) having a central axis (M) and a crucible wall (7) having a shell-shaped outer surface facing radially outwardly opposite the central axis (M); and a component (10) that substantially surrounds the crucible (6) and faces the crucible wall (7) at a distance by an inner surface facing the outer surface, the crucible wall (7) being disposed in a substantially thermal radiation exchange relationship with the component (10) surrounding the crucible (6). The outer surface of the crucible wall (7) has a first emissivity (ε1) and the inner surface of the opposing component (10) surrounding the crucible (6) has a second emissivity (ε2), the first emissivity (ε1) and the second emissivity (ε2) indicating how much radiation is emitted from the crucible wall (7) and the component surrounding the crucible (10), respectively, compared to an ideal radiant heater. The outer surface of the crucible wall (7) and the inner surface of the component surrounding the crucible (10) are each at least partially provided with coatings (8a, 8b) defining the first emissivity and / or the second emissivity, respectively, such that the first emissivity (ε1) and the second emissivity (ε2), respectively, have values ​​of 0.1 or less. Such a configuration allows for the fabrication of wafers, particularly from GaAs or InP, whose annular edge region, with a distance of 1-3 mm from the wafer edge, is available for post-fabrication epitaxial processes for the purpose of subsequent device fabrication.

Description

[Technical Field]

[0001] The present invention relates to an apparatus and method for producing an AIII-BV compound semiconductor single crystal, and to the corresponding AIII-BV compound semiconductor single crystal or a large-area substrate or wafer obtained by separating it, respectively. The present invention particularly relates to a single crystal or wafer formed of gallium arsenide and / or indium phosphide. [Background technology]

[0002] Such single crystals considered herein are typically produced by solidifying a melt containing a semiconductor material in a crucible using a seed crystal made of the same semiconductor material as the semiconductor single crystal to be produced. The crucible is generally cylindrical with a central axis, and its diameter essentially corresponds to the nominal diameter of the AIII-BV compound semiconductor wafer to be produced, taking into account slight oversize caused by extensive material removal in post-solidification processes. A narrow seed channel, which may be positioned off-center, is located at the vertical lower end of the crucible. During operation, a temperature field generated by a suitably positioned and controlled heating element positioned parallel to the central axis extends from this channel. A crystallization front or phase boundary, approximately perpendicular to the central axis, moves vertically upward from the seed crystal.

[0003] Gallium arsenide or indium phosphide substrate wafers are particularly suitable for the fabrication of light-emitting components, such as, but not limited to, microLEDs or vertical cavity surface-emitting lasers (VCSELs) or high-frequency transistors (pHEMTs, HBTs, DHBTs, BiHEMTs). Their operational characteristics and performance capabilities can be significantly affected or impaired by the physical properties of the substrate and its surface. Therefore, it is important to distribute the properties as uniformly as possible across the surface of the substrate or wafer so that all optical or electronic devices fabricated from the wafer are subject to the same, uniform, and preferably high-quality requirements.

[0004] The physical properties or variables mentioned include, among others, residual mechanical stresses or distortions, flatness, roughness, grain density, electrical resistivity or dislocation density. Some of these variables, especially dislocations, electrical resistivity or residual mechanical stresses, are subject to greater deviations, especially at the edge of the wafer. This is caused, among other things, by thermal stresses that arise during cooling of the crystal after solidification, especially at and near the crucible walls or the surface of the adjacent single crystal.

[0005] As a result, to ensure a high degree of uniformity in properties, an edge exclusion zone is typically defined, which represents a ring-shaped region on the wafer surface (or a portion shaped as a cylindrical shell in a boule or single crystal not yet separated into wafers) that should not be used by device manufacturers for the actual fabrication of devices, while the central region of the wafer, which is used for device fabrication and complements the edge exclusion zone, always exhibits excellent uniformity values.

[0006] Edge exclusion values ​​known in the patent literature can range, for example, from 2.5 mm to 5 mm, depending on the diameter and material (GaAs or InP) (see, e.g., U.S. Patent Application Publication No. 2021 / 310155, EP Patent Application Publication No. 3514266, U.S. Patent Application Publication No. 2019 / 371620, EP Patent Application No. 1634981, EP Patent Application Publication No. 3591102, U.S. Patent No. 10,473,445, EP Patent Application Publication No. 3862134, EP Patent Application No. 2458041). As an example, for a GaAs wafer with a diameter of 150 mm and an edge exclusion zone of 3 mm, the usable area available for device fabrication is approximately 169.7 cm. 2 and the total wafer area is 176.7 cm 2 Therefore, the edge exclusion results in a relative loss of unusable area of ​​about 4%. Even for InP wafers, which currently have diameters up to 100 mm, the typical edge exclusion can be in the range of 3 mm. In this case, the usable area available for device fabrication is 73.9 cm 2 and the total wafer area is 78.5 cm 2In this case, the edge exclusion results in a relative loss of unusable area of ​​about 6%. This means that the relative loss of area decreases as technology improves (i.e., as the diameter increases). Nevertheless, when a constant amount of edge exclusion is applied, the loss of unusable area in absolute terms increases linearly with increasing diameter.

[0007] Therefore, for both economic and sustainability reasons, there is a need to reduce losses in the AIII-BV compound semiconductor material during device fabrication. An important starting point for this is to improve the quality and uniformity of the mentioned physical parameters (residual stress, specific electrical resistivity), especially in the edge region, so that, for example, the respective specific values ​​of the edge exclusion zone can be reduced.

[0008] Thermal stresses in the edge regions of single crystals can be caused, inter alia, by curvature of the temperature field or phase boundary deflection during crystallization. Vertical Bridgman (VB) or vertical gradient freeze (VGF) processes, or thermally similar processes, are regularly chosen as preferred growth methods due to the relatively low curvature of the respective temperature fields involved here (see, for example, M. Jurisch et al., "Handbook of Crystal Growth Bulk Crystal Growth: Basic Techniques," VOLUME II, Part A, Second Edition, Chapter 9 "Vertical Bridgman Growth of Binary Compound Semiconductors," 2015).

[0009] Experimental and theoretical studies have shown that the amount and distribution of dislocation density are primarily determined by lattice relaxation processes during plastic deformation due to thermal stresses induced by large thermal gradients (see, for example, J. Yang, W. Lu, M. Duan, H. Xie, G. Shen, J. Liu, Z. Dong, Y. Zhao, "VGF growth of high-quality InAs single crystals with low dislocation density," Journal of Crystal Growth 531 (2020), 125350; J. Volkl, "Stress in the cooling crystal," D.T. J. Hurle (Ed.), Handbook of Crystal Growth, Elsevier Science B, 1994, 821; P. Rudolph, M. Jurisch, Crystal Growth Technology, John Wiley & Sons, Ltd., 1994, 800). Therefore, dislocations can be generated when thermal stress exceeds the critical value of shear stress for lattice slip. For such critical values, the thermal gradient and the deviation of the isotherms from the linear plane or the degree of phase boundary deflection play an important role (see, for example, NAAnastaskeva, VT Bublik, VV Karatsev et al., Sov. Phys. Crystallogr. 34 (1989), p. 912).

[0010] A necessary prerequisite for crystal growth from the melt is the existence of a temperature gradient within the crystal. This allows the single crystal to function as a heat transport medium, transferring heat—the heat of fusion released in each case and the heat contained in the melt due to the initial heating—to the environment via the crucible walls. In particular, heat enters the crystal at the interface between the single crystal and the melt and leaves the crystal via radiation and convection through the outer surface. As a result, the interior of the single crystal is hotter than its edges, while the edge of the single crystal near the seed channel is cooler than the material near the phase boundary. The resulting temperature gradients therefore induce thermal stresses and strains in various parts of the single crystal, which can ultimately lead to plastic deformation due to the movement of already formed dislocations (see, for example, Vishwanath Prasad and Srinivas Pendurti, "Part F: Modeling in Crystal Growth and Defects. 39 Models for Stress and Dislocation Generation in Melt-Based Compound Crystal Growth," in "Springer Handbook of Crystal Growth," G. Dhanaraj, K. Byrappa, V. Prasad, M. Dudley (Eds.), Springer-Verlag, Berlin-Heidelberg (2010), p. 1349).

[0011] U.S. Patent Application Publication No. 2020 / 066850 provides specific quantities for the residual strain content at least near the edge of conventionally grown InP wafers with diameters between 100 mm and 205 mm. The near-edge region extending from a 2 mm flat or notch to the inside of the wafer surface was investigated. The substrate thickness was between 300 and 800 μm, and impurity atoms were added in the range of 2.0 to 8.0 × 10 18 cm -3 (sulfur), 1.0–4.0 × 10 18 cm -3 (tin) or 5.0 x 10 15 ~1.0×10 17 cm -3The average residual strain in the edge region defined in this way was 5 × 10 -6 ~5×10 -5 It was.

[0012] In EP 3835465, the residual strain content was measured in the near-edge region of a C-doped semi-insulating GaAs wafer, which in the illustrated embodiment had a diameter of 152.4 mm and a thickness of 700 μm. The near-edge region was characterized herein as a ring-shaped area symmetrical about the wafer center, with a width of 5 mm and a distance to the wafer edge also of 5 mm (i.e., a depth of 5 mm to 10 mm from the edge). Residual stress was measured for various wafers as a function of the temperature difference occurring during cooling after the growth process (VB process) between one end of the seed channel and the other end of a 200 mm-long single crystal (not yet separated into wafers), whereby the temperature difference can ultimately be controlled via a heating element. This temperature difference may also represent the radial temperature gradient at the outer edge of the single crystal. The sample with the lowest set temperature difference (i.e., 2 °C) had a mean value of the distribution of residual strain in the defined near-edge region of 3.5 × 10 -6 (separated wafer corresponding to position in the crucible near the seed channel) ~1.2 × 10 -5 (a separated wafer corresponding to a position near the last crystallized edge in the crucible). Glide and therefore relatively high dislocation density values ​​were recorded only for samples with a high temperature difference (i.e., 20 °C).

[0013] It should be noted that in this document a distinction must be made between dislocations that exhibit a more or less free or "cloudy" distribution in the cross section, following the direction of the advancing crystallization front, for example from the seed channel during crystal growth, and dislocations in so-called slip lines that arise from thermal stresses at the edges during cooling of the solidified crystal.

[0014] Therefore, it may be desirable to determine the deflection of the phase boundary by the cooling rate experienced by the crystal. During crystal growth, the cooling rate must be adjusted from the melting point to room temperature so that the resulting thermal stress is below the critical shear stress for dislocation multiplication and glide. The cooling rate also determines the roughly concave shape of the phase boundary, with increasing curvature toward the crucible wall, which determines the shape of the isotherm of the temperature field and therefore the expression of nonlinearity. As mentioned above, nonlinear temperature fields lead to curved phase boundary shapes, thermal stresses within the growing crystal, dislocations arranged at slip lines if the thermal stress is too high, dislocation multiplication at high thermal stresses, and residual stresses within the crystal at room temperature (see Manfred Jurisch, Stefan Eichler, Martin Bruder, "9-Vertical Bridgeman Growth of Binary Compound Semiconductors," Ed. Peter Rudolph, In Handbook of Crystal Growth, Handbook of Crystal Growth (Second Edition), Elsevier, 2015, pp. 331-372, ISBN 9780444633033, https: / / doi.org / 10.1016 / B978-0-444-63303-3.00009-2).

[0015] Slip lines are generated by the intersection of dislocation loops extending within the slip plane, emitted by the Frank-Read source, and collinear with each other on a cross section, which may be the flat surface of a separated wafer. In single crystals, slip planes form planes between atomic layers with close packing and large interlayer spacing. In the case of the AIII-BV compound semiconductors considered here, these may be regular {111} lattice planes, especially at critical crystal edges. Individual dislocation loops connect to intersections within each cut cross section, and due to the collinearity within the slip plane, these intersections lie on lines called slip lines. Depending on mechanical stress and specific thermal loads, dislocation loops may expand or contract toward the Frank-Read source. However, in this case, the intersections either remain on the slip line or move along it.

[0016] Morphologically, slip lines may have little effect on the surface flatness or roughness of the raw wafer. However, during subsequent epitaxy performed for device fabrication, these slip lines can form undesirable macroscopic steps on the surface. (Sawada, S.; Yoshida, H.; Kiyama, M.; Mukai, H.; Nakai, R.; Takebe, T.; Tatsumi, M.; Kaji, M.; Fujita, K., "Slip defect generation on GaAs wafers during high temperature process: a thermoelastic study from a crystallographic viewpoint," GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium, 18th Annual Technical Digest 1996, (1996), pp. 50-53.)

[0017] Therefore, to enable quantification of slip lines in the edge region of the wafer with respect to unwanted step formation, it is desirable to assign dislocations made detectable in known ways by etch pit formation in the cross section (wafer surface) to slip lines or to classify them as free dislocations.

[0018] The standard SEMI M10-Terminology for Identification of Structures and Features Seen on Gallium Arsenide Wafers (available at semi.org: https: / / store-us.semi.org / products / m01000-semi-m10-terminology-for-identification-of-structures-and-features-seen-on-gallium-arsenide-wafers) defines this in detail: "...slip is evidenced by one or more straight patterns of 10 or more dislocations per millimeter, not necessarily touching each other." This means that the average spacing between dislocations within a slip line is approximately 100 μm. Unfortunately, this definition is not useful for the low dislocation density (EPD; etch pit density) substrates discussed in this application, since in practice the average spacing can be up to 500 μm. Furthermore, the actual slip line (or the arrangement of the associated intersections in the cross section) may deviate from a precise straight line due to point defects and interactions with other dislocations.

[0019] Thus, for substrates with low dislocation density, slip lines are identified or detected as such by the measurements herein when: More than 10 etch pits, representing dislocations, extend along one direction in the cross section; These dislocations form chains of up to 500 μm for each adjacent etch pit. The etch pits are located perpendicular to the direction within a 250 μm wide tolerance interval, and The slip lines extend from a point within the annular edge region of the cross section or flat cross section, respectively, the width of the edge region being defined by a distance of 5 mm measured from the outer edge of the single crystal or wafer, with an edge exclusion zone of 2 mm.

[0020] This definition allows for the detection and quantification of slip lines close to edges.

[0021] However, the problem still exists: devices cannot be fabricated on wafers within a region of the wafer edge up to 3 mm into the crystal (or toward its central axis) because residual stresses and dislocation densities in the edge region are too high or unknown. Devices are built in epitaxial layers grown on the wafer. Residual stresses exceeding critical values ​​at the wafer edge can stress the epitaxial layers and thus cause components or devices originating from the wafer edge to have different properties than those originating from the central region of the wafer. In particular, slip under the influence of thermally induced stresses can significantly increase dislocation density locally, potentially several times the average dislocation density across the wafer. The above correlation between phase boundary deflection and crystal quality in the wafer edge region clearly indicates the desirability of improved crystal growth and cooling processes. In particular, embodiments of the present invention aim to reduce thermal stresses, limit associated dislocations, and improve crystal structure. Furthermore, it is an object to provide an AIII-BV compound semiconductor single crystal and wafers produced by separation therefrom, which limit expensive material losses due to areas that cannot be used for the production of subsequent components or devices. [Prior art documents] [Patent documents]

[0022] [Patent Document 1] U.S. Patent Application Publication No. 2021 / 310155 [Patent Document 2] European Patent Application Publication No. 3514266 [Patent Document 3] US Patent Application Publication No. 2019 / 371620 [Patent Document 4] European Patent No. 1634981 [Patent Document 5] European Patent Application Publication No. 3591102 [Patent Document 6] U.S. Patent No. 10,473,445 [Patent Document 7] European Patent Publication No. 3862134 [License 8] European Patent No. 2458041 [License 9] U.S. Patent and Trademark Office Publication No. 2020 / 066850 [License 10] European Patent Publication No. 3835465

[0023] [Non-licensed Document 1] M.Jurisch, "Handbook of Crystal Growth Bulk Crystal Growth: Basic Techniques", VOLUME II, Part A, Second Edition, Chapter 9 "Vertical Bridgman Growth of Binary Compound Semiconductors", 2015 [Non-licensed Document 2] J. Yang, W. Lu, M. Duan, H. Xie, G. Shen, J. Liu, Z. Dong, Y. Zhao, "VGF growth of high quality InAs single crystals with low dislocation density", Journal of Crystal Growth 531 (2020), 125350 [Non-licensed Document 3] J.Volkl, "Stress in the cooling crystal", DTJ Hurle (Ed.), Handbook of Crystal Growth, Elsevier Science B, 1994, page 821 [Non-licensed Document 4] P.Rudolph, M.Jurisch, Crystal Growth Technology, John Wiley & Sons, Ltd, 1994, 800 pages [Non-licensed Document 5] NAAnastaskeva, VTBublik, VVKaratsev et al., Sov.Phys.Crystallogr.34 (1989), p. 912 [Non-patent document 6] Vishwanath Prasad,Srinivas Pendurti "Part F Modeling in Crystal Growth and Defects.39 Models for Stress and Dislocation Generation in Melt Based Compound Crystal Growth" in "Springer Handbook of Crystal Growth" G. Dhanaraj, K. Byrappa, V. Prasad, M. Dudley (Eds.), Springer-Verlag, Berlin-Heidelberg (2010), 1349 pages [Non-Patent Document 7] Manfred Jurisch, Stefan Eichler, Martin Bruder, "9-Vertical Bridgman Growth of Binary Compound Semiconductors", Ed. Peter Rudolph, In Handbook of Crystal Growth, Handbook of Crystal Growth (Second Edition), Elsevier, 2015, pp. 331-372 [Non-patent document 8] Sawada, S.; Yoshida, H; Kiyama, M.; Mukai, H.; Nakai, R.; Takebe, T.; Tatsumi, M.; Kaji, M.; Fujita, K., "Slip defect generation on GaAs wafers during high temperature process: a thermoelastic study from a crystallographic viewpoint", GaAs IC Symposium IEEE Gallium Arsenide Integrated Circuit Symposium, 18th Annual Technical Digest 1996, (1996), pp. 50-53 [Non-Patent Document 9] SEMI M10-Terminology for Identification of Structures and Features Seen on Gallium Arsenide Wafers Standard Summary of the Invention

[0024] The object is to provide an apparatus for producing AIII-BV compound semiconductor single crystals from a melt of raw materials, comprising: a crucible for receiving a melt, the crucible having a central axis and a crucible wall having a shell-shaped outer surface facing radially outwardly opposite the central axis; a component substantially surrounding the crucible and facing the crucible wall at a distance by an inner surface facing the outer surface, the crucible wall being disposed in a relationship of substantial thermal radiation exchange with the component surrounding the crucible; The problem is solved by an apparatus having the following structure.

[0025] The outer surface of the crucible wall has a first emissivity, and the inner surface of the opposing component surrounding the crucible has a second emissivity. The first and second emissivities indicate how much radiation is emitted from the crucible wall and the component surrounding the crucible, respectively, compared to an ideal radiant heater (i.e., the ratio of thermal radiation from a surface to the radiation from an ideal black surface at the same temperature as given by the Stefan-Boltzmann law).

[0026] The exterior surface of the crucible and / or the interior surface of a component surrounding the crucible is at least partially provided with a coating defining a first emissivity and a second emissivity, respectively, such that the first emissivity and / or the second emissivity each have a value of 0.1 or less.

[0027] The present invention recognizes that the uniformity of crystalline properties perpendicular to the wafer cutting direction, or the central axis of the single crystal from which the wafers are separated, is fundamentally affected by the curvature of the phase boundary between the grown crystal and the melt. Here, increased thermal stress (accompanied by the curvature of the temperature field) can occur, potentially resulting in localized increases in dislocation density. Furthermore, dopant incorporation into the crystal lattice generally occurs at a constant concentration along the curved phase boundary, which can result in non-uniform dopant distribution and electrical properties on straight (flat) cut wafers. Due to the relatively large radial component of heat transport resulting from the transport of latent heat generated at the crystallization front (GaAs: 668.5 J / g, InP: 429.5 J / g), the curvature of the phase boundary is particularly pronounced at the edges of the crystal near the crucible wall. Heat transport is determined, on the one hand, by the relatively high thermal conductivity of the crucible or crucible walls (0.8 W / cmK) compared to the solidified crystal (GaAs: 0.0712 W / cmK, InP: 0.0911 W / cmK). On the other hand, heat transport by radiation at the growth temperatures of GaAs and InP is very efficient, and radially directed radiation of latent heat through the crucible can be substantial. At least the latter situation is addressed by the above-described aspects of the present invention.

[0028] In particular, the radially directed thermal radiation is adjusted by at least partially providing a coating with a relatively low emissivity ε on the surfaces limiting the radiation space outside the crucible. This may be applied to only one or both of the limiting surfaces. The radiation space outside the crucible may have a substantially cylindrical shell shape. The inner surfaces limiting the radiation space may generally be provided by the crucible wall or the surface of the crucible wall facing outward, respectively. The crucible itself may have a cylindrical shape, but deviations from a cylindrical shape are also encompassed in accordance with aspects of the present invention. More specifically, the geometric shape of the crucible may be a body shape with a square, pentagonal, hexagonal, or polygonal base region, or a cylinder with transversely flattened segment faces.

[0029] The outer surface limiting the radiation space is the inner surface of the crucible periphery facing the outer surface of the crucible wall. Depending on the structure of the growth or manufacturing apparatus, various components may be embodied herein. Most commonly, the crucible periphery providing the inner surface is represented by a component that surrounds the crucible approximately the entire periphery, including one or more parts that together form a functional component. Only beyond such a component (as viewed from the central axis of the crucible) may one or more heating elements be located, which are used to initially melt the raw material and are then controlled to adjust or set a suitable temperature gradient within the crucible.

[0030] The radiation power P of a gray body at temperature T and the area A of the corresponding surface may be determined according to the Stefan-Boltzmann law:

number

[0031] where σ is the Stefan-Boltzmann coefficient and ε is the emissivity of the surface. Emissivity is material specific and can take on real values ​​between 0 and 1. Similarly for devices according to this embodiment, the net radiation balance M in the space between two nearly parallel surfaces, where the distance is significantly less than the surface extent of the inner or outer surfaces, may be calculated from:

number

[0032] Thus, the radiation exchange rate E in equation (2) may be expressed as follows:

number

[0033] In the formula, ε1 and ε2 represent the emissivity of the outer and inner surfaces, respectively. In a conventional apparatus configured for AlIII-BV compound semiconductor crystals by the VGF or VB method, ε1 (the outer surface of the crucible wall) is approximately 0.5, and ε2 (the inner surface of the component surrounding the crucible, e.g., a tube made of graphite or SiC) is approximately 0.8. For the resulting degree of radiation exchange, a value of E=0.44 can be obtained by way of example only.

[0034] According to an embodiment of the present invention, a coating that significantly increases the emissivity, ie ε1≦0.1 and / or ε2≦0.1, is proposed on one or the other side of the radiation chamber, preferably on both sides.

[0035] Coatings and strategies are known in the art for adjusting emissivity in various situations.

[0036] U.S. Patent Application Publication No. 2020 / 181796 discloses an apparatus for producing SiC crystals by precipitation from the gas phase. A graphite crucible contains the raw material to be vaporized at the bottom and the seeds for crystal precipitation at the top. A low-emissivity (emissivity) material is attached to the outside of the crucible in the upper region of the raw material. This ensures that the upper raw material enters the gas phase before the lower raw material. Low-emissivity materials include carbides, nitrides, Ta, Mo, Nb, Hf, W, and Zr.

[0037] Patent No. 3,564,740 discloses a crystal growth apparatus using the Czochralski method. The emissivity of the inner wall of a steel boiler is higher in the upper region. As a result, heat is intended to be dissipated more quickly from the grown crystal. This inevitably causes the solid-liquid phase boundary to bend more strongly with respect to the grown crystal.

[0038] JP 2014-162668 A discloses a sapphire crystal manufacturing apparatus in which the emissivity of the crucible in the upper crucible region is higher than that in the lower crucible region, thereby increasing heat exchange between the growing crystal and the environment.

[0039] JP 09-315881 A discloses an apparatus for growing GaAs using the vertical Bridgman method. The shaft carrying the crucible is cooled in the lower region by a surrounding cooling coil. In the region above the cooling coil, the shaft is provided with pyrolytic boron nitride to reduce its emissivity and absorb less heat from the environment. Meanwhile, the emissivity of the outside of the crucible is increased by a carbon coating.

[0040] However, in the present invention, rather than locally increasing or decreasing the emissivity(ies) or degree of radiation exchange, the basic idea is to generally reduce the emissivity(ies) or degree of radiation exchange by a substantial amount over the entire crucible, with the goal of reducing phase boundary deflections during and throughout the crystal growth, i.e., over the entire length of the crystal.

[0041] A preferred embodiment finds application in particular to an apparatus for growing or producing AIII-BV compound semiconductor crystals from a melt, operated according to the vertical gradient freeze (VGF) or vertical Bridgman (VB) method. Both processes are well known in the art, and involve heating and melting a raw material, usually still polycrystalline, in a crucible with a seed crystal at the bottom using one or more heating elements, e.g., resistance heaters, whereby the seed crystal is also slightly melted. A directed temperature field is set and / or adjusted so that an essentially vertical gradient runs from the upper region of the crucible toward the seed crystal in the seed channel at the bottom of the crucible. The temperature field is then moved relative to the crucible. This can be done by mechanically moving the crucible or the heating elements (VB method) or by varying the temperature field via targeted control of the heating elements of the corresponding heater (VGF method). The temperature field is moved in the direction opposite to the gradient, so that the melt first solidifies in the lower region of the crucible, starting from the seed crystal, and crystal growth proceeds in a vertical upward direction. By slowly moving the heated zone upward, the crystallization front also moves upward slowly. The crystallization speed can be determined, inter alia, by the speed at which the temperature field is moved. Thus, the apparatus may, for example, include an actual crucible having a cylindrical portion as described above for holding the raw material melt, a seed channel, and a tapered portion between the cylindrical crucible and the narrower seed channel. It may further include a heater having one or more heating elements and a control unit for adjusting the temperature level and the temperature field according to the selected method. According to the present invention, components surrounding the crucible are arranged between the crucible and the heating element of the heater. The entire apparatus may also include an external housing that also houses the heater.

[0042] A reduction in the emissivity of the outer surface of the crucible wall and / or the inner surface of the components surrounding the crucible can significantly reduce thermal radiation. Heat conduction within the crucible wall is less affected by the measures of the present invention, but it still exists. Nevertheless, in conventional cases, thermal radiation can be widespread, such that regions of the solidified crystal located radially outward relative to the central axis cannot easily release their thermal energy. This significantly reduces the radial component of the temperature gradient; in other words, the temperature gradient is oriented more linearly parallel to the central axis of the crucible. As a result, phase boundary deflection is also reduced, and the phase boundary itself becomes flatter all the way to the edge or crucible wall, respectively. It is recognized that heat transport must thus occur much more axially, which extends the cooling time or reduces the overall cooling rate. Nevertheless, such drawbacks are justified by the benefits of improved quality and yield. However, if the cooling rate is not to be reduced, the heating power can be adjusted accordingly in the way that the cooling rate is typically set in conventional devices.

[0043] To this end, according to certain embodiments, the crucible wall close to the seed channel (e.g., in the tapered portion) or (part of) the peripheral components facing such portions may remain uncoated, i.e., may comprise a conventional emissivity significantly greater than 0.1, to allow heat removal from the crucible. Furthermore, according to embodiments, the end face of the crucible opposite the seed channel and the faces of the peripheral components facing that end face, if provided at this point, do not need to have an emissivity-reducing coating.

[0044] The coating here preferably means a thin adhesive layer. It can be applied by any method, depending in particular on the coating material. The coating can also be a film fixed to the corresponding surface. The coating material is preferably temperature-stable and inert in air to avoid contamination of the crystal.

[0045] According to certain embodiments, the coating may be configured to have an emissivity of 0.05 or less. This may be applied to the inner surface of the crucible-enclosing component, or to the outer surface of the crucible wall, or both. Advantageously, a combination of emissivities of the coatings on both sides is also possible, with values ​​of ε1≦0.1 and ε2≦0.05, or vice versa, with values ​​of ε1≦0.05 and ε2≦0.1. However, as mentioned above, there have been simpler cases in the past where only one coating with ε≦0.05 is applied to one side of the radiation space.

[0046] In one embodiment of the present invention, the degree of radiation exchange E calculated according to equation (3) is less than or equal to 0.1, preferably less than or equal to 0.05, for radiation exchange between the crucible wall and the components surrounding the crucible.

[0047] As explained, in certain embodiments of the apparatus according to the invention, the outer surface of the crucible wall and the inner surface of the opposing component together form and limit an intermediate space or radiation space having the shape of a cylindrical shell in which radiation exchange occurs during operation of the apparatus.

[0048] According to a further embodiment, the coating forming at least part of the outer and / or inner surface is designed as a periodic pattern, in particular a mosaic or stripe pattern. More particularly, the emissivity may also be set via the area coverage of the pattern.

[0049] According to a further embodiment, the coating forming at least part of the outer and / or inner surface may be made of a shiny metal. In this way, a very low emissivity can be achieved.

[0050] According to a further embodiment, the components surrounding the crucible are made of hard graphite and have a rough metal layer, which can achieve the desired moderately low emissivity according to the invention. The rough metal layer can be made of, for example, platinum.

[0051] According to a further embodiment, the components surrounding the crucible are made of hard graphite and have a shiny metal layer, which allows achieving a very low emissivity. The shiny metal layer may be made of, for example, platinum. Alternatively, the hard graphite may be coated with boron nitride.

[0052] According to a further embodiment, the component surrounding the crucible is a quartz tube coated with graphite. In such a case, the component may be a so-called liner.

[0053] According to a further embodiment, the crucible may be fabricated from boron nitride or pyrolytic boron nitride (pBN), with the exterior surface of the crucible wall being at least partially formed by a rough platinum or graphite coating, thereby achieving the desired moderately low emissivity according to the present invention.

[0054] According to a further embodiment, the crucible may be manufactured from boron nitride or pyrolytic boron nitride (pBN), with the outer surface of the crucible wall being at least partially formed by a shiny platinum coating, which in turn allows achieving a very low emissivity.

[0055] According to an embodiment, the apparatus may be configured to produce an AIII-BV compound semiconductor single crystal, preferably having a nominal diameter of 100 mm, 150 mm, or 200 mm, including GaAs or InP. The GaAs (gallium arsenide) or InP (indium phosphide) exhibits a predetermined melting temperature, and the control unit and heating element are configured to be coordinated with each other to set the temperature level and adjust the directional temperature field. With respect to the nominal diameter mentioned, the crucible typically has an inner diameter 1 to 10 mm larger than the nominal diameter. Such oversizing may be primarily due to material removal around the cylinder during post-processing, which involves removing particles from the crucible at the outer edge of the crystal, smoothing the surface, and possibly removing material with a higher dislocation density (in the case of a large oversize).

[0056] The crucible wall may be made of a material with an internal structure that allows for isotropic thermal conduction. This is not a limitation, however. In the case of an apparatus for growing GaAs or InP single crystals, the crucible wall is routinely made of pBN stacked in layers. The stacking direction is perpendicular to the wall, i.e., the layers extend parallel to the central axis of the crucible. Heat transfer (thermal conduction) is easier within the individual layers of the stack than through layer-to-layer thermal conduction. This structure is typically used to minimize material loss within the crucible after each use, since the components are tightly bonded to the crystal. The layered structure allows for quantification of material loss in advance and layer-by-layer, thus extending the crucible's lifespan. However, anisotropic thermal conduction relative to the central axis of the crucible means that heat is dissipated very efficiently radially outward from the edge of the growing crystal. The proposed embodiment helps limit heat dissipation by thermal conduction by using a material that is isotropic in this respect.

[0057] In one embodiment, the crucible wall is made of a material having an internal structure such that the thermal conductivity is less than or equal to 3 W / mK. For example, the crucible may be made of glassy carbon.

[0058] Another aspect of the present invention relates to a corresponding method for producing an AIII-BV compound semiconductor single crystal from a melt of raw materials. For this purpose, an apparatus according to one of the above aspects or one of the above embodiments is first provided. The method comprises the steps of: providing a seed crystal in a seed channel of the device; establishing a directed temperature field parallel to the central axis of the crucible with one or more heating elements; setting the growth rate by controlling the heating elements so that the tilt angle between the phase boundary and the horizontal direction perpendicular to the inner surface of the crucible wall is continuously maintained at 40 degrees or less, preferably 30 degrees or less; A single crystal solidification process and further cooling process Further includes:

[0059] In the step of setting the growth rate, the angle between the phase boundary and a horizontal direction perpendicular to the inner surface of the adjacent crucible sidewall is preferably continuously maintained at 37 degrees or less when the AIII-BV compound semiconductor is GaAs, or 34 degrees or less when the AIII-BV compound semiconductor is InP, more preferably 32 degrees or less when the AIII-BV compound semiconductor is GaAs, or 31 degrees or less when the AIII-BV compound semiconductor is InP.

[0060] The same advantages as above can be achieved. While a tilt angle of 0° is the ideal goal, it is rarely achievable in practice. At least for the range of crystal diameters considered herein, tilt angle or phase boundary deflection generally does not depend strongly on diameter. Deflection occurs particularly near the crystal edge or near the crucible wall. A tilt angle of 40° or less corresponds approximately to a phase boundary deflection of 11–12 mm. A tilt angle of 30° or less corresponds approximately to a phase boundary deflection of 4.5–5.0 mm. Because there is little available suitable sensor technology adapted to the respective temperatures, both quantities, tilt angle and phase boundary deflection, can hardly be determined or measured in practice during the growth process. Therefore, such parameters are determined in advance from simulations using heater or heating element control for a specific configuration. For this purpose, highly suitable simulation programs are available, which can indicate the phase boundary deflection or tilt angle depending on the growth progress. The emissivity can be determined and implemented according to the results of the calculations, and during operation, the heating power can be configured and controlled so that the tilt angle can be achieved.

[0061] A further aspect of the invention relates to an AIII-BV compound semiconductor single crystal, or in particular a wafer obtained by separation therefrom, which crystal or wafer has been produced by an apparatus and / or method as described above.

[0062] A still further aspect of the present invention relates to an AIII-BV compound semiconductor single crystal, or in particular a wafer obtained by separation therefrom, wherein within an annular edge region of a cross-sectional area of ​​the single crystal or wafer perpendicular to the central axis (in the case of a wafer, the cross-sectional area is one of the two flat major faces), the percentage of dislocation etch pits associated with slip lines (glide dislocation lines) extending from the edge region of the single crystal or wafer within the cross-sectional area is 30% or less of the total number of dislocation etch pits formed over the entire cross-sectional area excluding a 2 mm edge exclusion zone measured from the outer edge of the single crystal or wafer.

[0063] The width of the edge region is given or measured at a distance of 5 mm from the outer edge of the single crystal or wafer. However, a 2 mm edge exclusion zone is also defined or subtracted, resulting in a radial annular edge region width of 3 mm. The annular zone is symmetrical about the central axis of the single crystal or wafer. The edge exclusion zone extends directly from the outer edge and takes into account the area that is no longer metrologically accessible for reliably detecting physical quantities due to the normal edge rounding of the target wafer and the area adjacent to it.

[0064] As mentioned above, a problem that arises at the edge of a produced single crystal or wafer is the generation of thermal stresses during the cooling process, which can have the effect of generating slip lines, e.g., originating from Frank-Lead sources, especially in the edge region. The absolute number of dislocation etch pits associated with these slip lines, particularly with regard to the cooling process, is relevant to the quality of the single crystal or wafer production process. Such dislocation etch pits must be distinguished from those associated with dislocations, e.g., those that proceed from seed channels during the growth process and may be more or less freely distributed.

[0065] Therefore, as explained in the previous aspect, certain parameters explain the quality of the approach, especially in the peripheral region. In particular, for single crystals or wafers containing a relatively low proportion of dislocation etch pits arranged on slip lines (glide dislocation lines) geometrically originating from the edge region as described above, the quality of the edge region (EPD) is closer to the corresponding quality of the inner region of the cross-sectional area (i.e., the area within the circle defined by the inner boundary of the edge region facing the central axis). In other words, if the inner region of such a wafer (after separation) meets the requirements for subsequent device fabrication, this situation also extends to the surface area of ​​the etched region, and if the value of certain parameters is sufficiently low, the proportion of the area available for device fabrication can be increased.

[0066] In particular, however, the proportion of dislocation etch pits achieved here belongs to slip lines (herein referred to as slip dislocation lines) extending in a cross-sectional area originating from or coming from the edge region of the single crystal or wafer, and advantageously, the formation of morphological macroscopic steps in the wafer surface in post-production epitaxy steps can be avoided or at least significantly reduced. It is noted that the low parameter values ​​of the present invention can be achieved in particular by the above-mentioned apparatus.

[0067] According to a preferred embodiment, the percentage of dislocation etch pits belonging to slip lines extending from the edge region of the single crystal or wafer in a cross-sectional area relative to the total number of dislocation etch pits may be less than 10%, more preferably less than 5%. The percentage so determined may be referred to herein as the "slip degree."

[0068] To determine the percentage, etch pits are first generated on the surface (cross-sectional area) of the separated wafer at the locations where the dislocations intersect the surface. This can be done in a conventional manner, for example, by immersing the surface in molten KOH. The resulting etch pits allow the dislocations to be detected. All etch pits on the surface can then be recorded, for example, with a lateral resolution of 3.7 μm, using a scanning optical microscope equipped with a camera and image processing, and stored together with their location information (e.g., XY coordinates) in a table.

[0069] There may be tens of thousands of etch pits on an 8 inch wafer. Every etch pit on this database is then examined for assignment to a slip line, where the following requirements must be met for the presence and assignment of a slip line, as described above: Etch pits representing more than 10 dislocations extend along one direction in the cross section; These dislocations form chains of up to 500 μm for each adjacent etch pit. The etch pits are located perpendicular to the direction within a 250 μm wide tolerance interval, and The slip lines each extend from a point within an annular edge region of the cross section, the edge region being defined near the outer edge of the surface, the boundary of which is defined by a distance of 5 mm measured from the outer edge of the single crystal or wafer towards the center of the surface, with an edge exclusion zone of 2 mm.

[0070] A corresponding algorithm may search for the nearest neighbors to the considered location of the etch pit, successively checking the above conditions. Finally, the dislocation etch pits assigned to the slip line are divided by the total number of all dislocation etch pits.

[0071] According to a further embodiment of the above proposed AIII-BV compound semiconductor single crystal or wafer produced by separation therefrom, the relative frequency of slip lines extending within a cross-sectional area originating from or originating from an edge region of the single crystal or wafer relative to the circumferential length of the cross-sectional area of ​​the single crystal or wafer is 0.25 cm -1Below, especially 0.20cm -1 The following is the result.

[0072] In this embodiment, the number of slip lines relative to the circumference of the single crystal or wafer (determined above) is considered. This parameter also relates the quality of the edge region to the amount of etch pit density reduced by improved cooling. This quantity is sometimes referred to as the "glide dislocation line density." A preferred embodiment is one in which such relative frequency is less than 0.1 cm -1 Less than 0.05cm, preferably -1 It provides that it may even be:

[0073] In a further embodiment, the sum of the lengths of the slip lines (determined above) is calculated and related to the diameter of the single crystal or wafer (i.e., the sum of the lengths is divided by the diameter). To avoid macroscopic step formation in post-fabrication epitaxy processes as described above, it has been found that values ​​of this parameter of 6 or less, preferably 1.5 or less, and more preferably 0.8 or less are particularly suitable. This parameter is sometimes referred to as the "slip density" and is a dimensionless parameter.

[0074] A further alternative aspect of the present invention relates to a wafer obtained from an AIII-BV compound semiconductor single crystal, or in particular a wafer obtained by separation from an AIII-BV compound semiconductor single crystal, the wafer having a distribution of specific electrical resistivity within a cross-sectional area perpendicular to its central axis, the global standard deviation (σ global ) of the distribution being less than or equal to 16.0% of the average value of the specific electrical resistivity within the cross-sectional area of ​​the wafer, the global standard deviation being based on a characteristic length of 10 mm and taking into account an edge exclusion zone of 1 mm.

[0075] According to a particular embodiment, the AIII-BV compound semiconductor is GaAs, the wafer has a diameter of 150 mm, or 6 inches, or less, and the global standard deviation of the distribution (σ global ) is 4.0% or less of the average value of the specific electrical resistivity within the cross-sectional area of ​​the wafer.

[0076] According to another particular embodiment, the AIII-BV compound semiconductor is GaAs, the wafer has a diameter of 200 mm or 8 inches or greater, and the global standard deviation of the distribution (σ global ) is 16.0% or less of the average value of the specific electrical resistivity within the cross-sectional area of ​​the wafer.

[0077] According to yet another particular embodiment, the AIII-BV compound semiconductor is InP, the wafer has a diameter preferably of 100 mm or 4 inches, and the global standard deviation of the distribution (σ global ) is 17.0% or less of the average value of the specific electrical resistivity within the cross-sectional area of ​​the wafer.

[0078] Such parameters describing the electrical properties of single crystals and / or wafers include, in particular, the electrical resistivity ρ. Well-known spatially resolved measurements of the electrical resistivity ρ can be performed using the so-called COREMA (Contactless REsistivity Mapping) method (Jantz, W. and Stibal, R., "Contactless resistivity mapping of semi-insulating substrates", III-Vs Review 6[4], pp. 38-39, 1993; and Stibal, R., Wickert, M., Hiesinger, P., and Jantz, W. "Contactless mapping of mesoscopic resistivity variations in semi-insulating substrates", Materials Science and Engineering B 66[1-3], pp. 21-25, 1999). A typical spatial resolution of this method is 1 mm. 2 , and the mapping may be performed over the entire surface, excluding edge exclusions, as reflected in the term cross-sectional area used herein.

[0079] The determination of the overall, local and "total" standard deviations from the corresponding measurement data is described in German Patent Application Publication No. DE 102007026298 and International Publication No. WO 2008 / 148542 (or U.S. Pat. No. 8,652,253). The contents of pages 20 to 23 of International Publication No. WO 2008 / 148542 are incorporated herein by reference and are summarized again below.

[0080] Thus, the COREMA measurement data of a point is divided and for each point (x,y) in the cross section or wafer plane perpendicular to the central axis, a regression plane is calculated from the measurement data of its neighboring points inside a circumscribing circle with radius ζ, i.e. the characteristic length mentioned above.

number

[0081] Measured resistance ρ measured is expressed as the sum of two numbers, where ρ regression plane is the value of the regression plane at the point (x,y), and ρ variation is the distance between the function value on the regression plane and the measurement value.

[0082] The least-squares approximation of the plane ρ(x,y)=a+bx+cy to N data points may be uniquely computed by solving a system of linear equations.

number

[0083] Here, the degree of uniformity of electrical resistance at different length scales across the wafer surface may be expressed as: 1. Total standard deviation:

number

number

number

number

[0084] The measured variables (parameters) are examined at different length scales for more precise analysis. A range of approximately a few dislocation cells or particles (radius ζ 5-10 mm) is designated as local. Variations across the entire wafer with a minimum resolution of radius ζ are referred to as global. Variations at different length scales can be attributed to different physical causes.

[0085] In order to separately consider the local and global variations of the measured electrical resistivity, mapping measurements with high lateral resolution are required: measurement fields that are closer to the edge of the wafer than the edge exclusion zone are not taken into account in the evaluation.

[0086] Therefore, two variables, the boundary exclusion zone and the characteristic length ζ, can be defined, and the numerical calculation of the variables is then clearly defined and can be reproduced by anyone.

[0087] In the COREMA mapping of the electrical resistivity ρ, the global variation is determined by the gradual variation of the defect budget. The global variation is larger than the local variation, and therefore the standard deviation of all measurements of the electrical resistivity is a measure of the more global variation.

[0088] For example, considering a wafer with a diameter of 150 mm, all measurements can be performed with a scan width of 160 × 160 mm in the x and y directions and 320 × 320 data points, averaged over ζ = 10 mm, with an edge exclusion of 1 mm.

[0089] Against this background, certain embodiments of wafers according to this aspect have a corresponding value of the relative global standard deviation (σ global divided by the average value across the wafer) of the electrical resistance measured in the edge region only, taking into account an edge exclusion of 1 mm, of 35.0% or less, and the width of the edge region is defined by a distance of 3 mm or less measured from the outer edge of the wafer, and has an edge exclusion of 1 mm.

[0090] Such values ​​may already create acceptable conditions in terms of uniformity with respect to electrical parameters within the edge region, so that this edge region, i.e., even the portion of the wafer surface at a distance of less than 3 mm from the wafer edge, may be considered for subsequent device fabrication.

[0091] In a further embodiment of the proposed wafer, the mean or median of the distribution of the residual strain content within the annular edge region of the cross-sectional area of ​​the single crystal or wafer perpendicular to its central axis (M) is 2.5×10 -6 Less than or equal to 1.6 x 10 -6 The residual strain in a cross-sectional area within the edge region of a single crystal or wafer is derived in a spatially resolved manner from measurements made by the SIRIS method, the lateral resolution of the spatially resolved measurements being 100 μm, and the width of the edge region being defined by a distance of 3 mm or less measured from the outer edge of the single crystal or wafer, with an edge exclusion zone of 1 mm.

[0092] In this further embodiment, electrical parameters (uniformity of specific electrical resistivity) and mechanical parameters (such as residual strain or residual stress) of the edge region are simultaneously specified. Mechanical parameters are closely related to structural perfection (e.g., as expressed by EPD). Structural perfection and electrical uniformity can be contradictory characteristics regarding their quality in a particular crystal. When one parameter has an excellent value, the other still leaves many potential unresolved issues, and vice versa. This may be due to the commonly known interaction between extrinsic and intrinsic point defects, which are responsible for the electrical material properties, and structural defects such as dislocations or grain boundaries. Microsegregation can be observed here. When the structural defects are very dense, the concentration inhomogeneity is small, resulting in sufficient uniformity of the electrical properties. Conversely, because the average distance between structural defects is large, relatively large concentration differences for point defects can occur as a result of microsegregation.

[0093] Residual strains may be calculated directly from the residual shear stresses determined by measurements according to Kelly, P.A., "Mechanics Lecture Note: An introduction to Solid Mechanics," available from http: / / homepages.engineering.auckland.ac.nz / ~pkel015 / SolidMechanicsBooks / index.html, http: / / homepages.engineering.auckland.ac.nz / ~pkel015 / SolidMechanicsBooks / Part_II / 04_ElasticityPolar / ElasticityPolars_Complete.pdf, as follows: The relationship between two-dimensional stress and strain is:

number

[0094] The following applies to plane stress and strain states, respectively.

number

[0095] As a result, the residual strain can be calculated from:

number

[0096] The material constants, expressed as the elastic constant E and the lateral constriction number v (or Poisson's ratio), are v=0.31 for GaAs E=85.9 GPa and v=0.36 for InP E=61.1 GPa.

[0097] The transverse residual shear stress distribution may be measured by determining the photoelastic infrared depolarization using dark-field polarized light in transmission (see, for example, "Vertical integrating photoelasticity measurement in transmission with lateral resolution, Scanning Infrared Stress Inspection System (SIRIS)": Herms, M., Irmer, G., Kupka, G. et al., "Comparative Study of the Photoelastic Anisotropy of Si and GaAs", J. Electron. Mater. 49, pp. 5205-5212, (2020), https: / / doi.org / 10.1007 / s11664-020-08141-7; Geiler, Hans D. et al., "Photoelastic characterization of residual stress in GaAs wafers." Materials Science in Semiconductor Processing 9 (2006), pp. 345-350). Multipolarized analysis using multiple measurements of wafers with different rotation axes can be used to quantitatively determine residual stress across the entire wafer surface, independent of crystallographic orientation, as is the case with the SIRD method. However, the values ​​given here can also be applied objectively, independent of the measurement method.Further information on the methods and evaluations can be found in the publications Higginbotham, CW, Cardona, M. and Pollak, FH, "Intrinsic Piezobirefringence of Ge, Si and GaAs", Phys. Rev. 184, 821 (1969); Timoshenko, S. and Goodier, JN, Theory of Elasticity, McGraw-Hill Book Company, Inc. 1951; Suzuki, T., Yasutomi, T., Tokuoka, T., Yonenaga, I., "Plastic deformation of GaAs at low temperatures,” Phil. Mag. A, 1999, Vol. 79, No. 11, pp. 2637-2654; Herms, M., Wagner, M., Kayser, S., Kiessling, F. M., Poklad, A., Zhao, M., Kretzer, U., “Defect-induced Stress Imaging in Single and Multi-crystalline Semiconductor Materials,” Materials Today: Proceedings, Volume 5, Issue 6, Part 3, 2018, pp. 14748-14756.

[0098] The measurand in each case is the phase shift between the different polarization directions of the light beam, which depends on the voltage-induced birefringence (photoelastic effect). The phase shift Δ is correlated by Wertheim's law from stress optics to the difference in the principal stress values ​​Δσ and thus to the maximum shear stress via the stress-optic material constants. The stress-induced change in the inverse dielectric tensor ΔB is linearly related to the stress or strain for small changes. In particular, there is a high degree of linearity in the range of stresses considered here up to 1 MPa, since these stresses are orders of magnitude lower than the critical shear stress at room temperature (over 600 MPa). The minimum resolvable shear stress using the SIRIS method is approximately 0.1 kPa, which represents a lower limit for the specific residual stress.

[0099] Thus, according to this embodiment, the wafer is provided such that the edge area is at least partially available for subsequent device fabrication (ie still excluding the edge exclusion zone).

[0100] In an embodiment of a wafer according to the present aspect, the mean or median of the distribution of residual stress content in the edge region is 1.1×10 -6 The following is the result.

[0101] A further aspect of the present invention relates to a wafer produced by separating from an AIII-BV compound semiconductor single crystal, wherein the average value of the distribution of residual stress content within an annular edge region of a cross-sectional area of ​​the wafer perpendicular to its central axis (M) is 60 kPa or less, and the residual stress within the cross-sectional area within the edge region of the crystal or wafer is measured in a spatially resolved manner according to the SIRIS method, the lateral resolution of the spatially resolved measurement being 100 μm, and the width of the edge region is defined by a distance of 3 mm measured from the outer edge of the single crystal or wafer, with an edge exclusion zone of 1 mm.

[0102] Also according to this aspect, the wafer is provided such that its edge region is at least partially available (ie, except for the edge exclusion zone) for subsequent device fabrication.

[0103] In an embodiment of the wafer according to this aspect, the average value of the residual stress distribution in the edge region is 30 kPa or less, preferably 25 kPa or less.

[0104] According to a specific embodiment, the average value of the distribution of residual stress content within the annular edge region of the cross-sectional area of ​​the single crystal or wafer perpendicular to its central axis (M) is 60 kPa or less, the AIII-BV compound semiconductor is GaAs, and the diameter of the wafer is 200 mm or more or 8 inches or more, respectively.

[0105] According to another specific embodiment, the average value of the distribution of residual stress content within the annular edge region of the cross-sectional area of ​​the single crystal or wafer perpendicular to its central axis (M) is 30 kPa or less, the AIII-BV compound semiconductor is GaAs, and the diameter of the wafer is 150 mm or 6 inches, respectively.

[0106] According to another embodiment, the AIII-BV compound semiconductor is InP, the diameter of the wafer is 100 mm or 4 inches or more, respectively, and the average value of the distribution of the residual stress content within the annular edge region of the cross-sectional area perpendicular to the central axis (M) of the single crystal or wafer is 60 Kpa, preferably 30 kPa or less.

[0107] It is noted that the present invention also provides single crystals or wafers that combine the properties according to the independent aspects described above, e.g., wafers that have specific parameter values ​​for slip lines (proportion of dislocation etch pits to be assigned to slip lines, total length of slip lines relative to wafer diameter, number / frequency of slip lines relative to wafer circumference) arising from the edge region, that fit within the range of values ​​of electrical resistance in the edge region as determined, e.g., by COREMA measurements, as described above, and that have residual mechanical shear stresses and / or distortions in the edge region.

[0108] These and all wafers or single crystals listed separately above may have a diameter perpendicular to the central axis of 100 mm to 220 mm, inclusive, in the intervals indicated. In particular, the nominal diameter may be 100 mm (corresponding to 4 inches), 150 mm (corresponding to 6 inches), or 200 mm (corresponding to 8 inches).

[0109] Furthermore, the above-mentioned AIII-BV compound semiconductor single crystals or wafers produced by separation therefrom may in particular comprise gallium arsenide (GaAs) or indium phosphide (InP).

[0110] It is noted that the arrangement proposed here may be configured to carry out crystallization in particular according to the VGF process, or also according to the VB process, or a combination of the VGF and VB processes, i.e., varying the temperature field and moving the crucible relative to the heater or heating element.

[0111] Further advantageous embodiments of the invention can be found in the dependent claims. [Brief explanation of the drawings]

[0112] The present invention will now be described in more detail with reference to the drawings. [Figure 1] 1 is a schematic cross-sectional view of an apparatus for producing an AIII-BV compound semiconductor single crystal from a melt of raw material according to one embodiment. [Figure 2] 2 is a close-up view of the formation of a phase boundary between the raw material melt and the growing single crystal in the region of the crucible wall when using the apparatus of FIG. 1 compared to the conventional case. [Figure 3] FIG. 1 shows, purely schematically, the edge area of ​​the wafer edge that is only reasonably accessible for measuring various parameters such as etch pit density (EPD), specific electrical resistivity, residual mechanical shear stress or strain. [Figure 4] FIG. 1 is a cross-sectional view of a wafer surface with dislocation etch pits formed to capture slip lines. [Figure 5] FIG. 1 is a cross-sectional view of a wafer surface with dislocation etch pits for detecting slip lines. [Figure 6] FIG. 7 is the same as FIG. 6, but in a corresponding top view of the flat wafer surface. [Figure 7] FIG. 10 illustrates the distribution of etch pits across the surface of an 8-inch GaAs wafer (200 mm diameter) according to one embodiment. [Figure 8]8 shows the determined distribution of dislocation etch pits according to FIG. 7 that can be assigned to slip lines originating from an edge region defined at a distance of 2-5 mm from the outer wafer edge (or contacting this edge region with dislocation etch pits). [Figure 9] FIG. 10 shows the distribution of residual stress measured with SIRIS on six 6-inch GaAs wafers made from two different single crystals at a distance of ≦3 mm from the wafer edge (1 mm edge exclusion) according to an embodiment. [Figure 10] FIG. 10 shows the distribution of residual strain calculated from the residual stress according to the embodiment of FIG. 9 measured with SIRIS at a distance of ≦3 mm from the wafer edge on six 6-inch wafers made from two single crystals, where the plane stress state was transformed to a plane strain state with material constants E=85.9 GPa and ν=0.31 (for GaAs). [Figure 11] FIG. 10 shows a profile of values ​​determined by COREMA measurements for specific electrical resistivity across the surface of a wafer, where a wafer with 1 mm oversize and no edge rounding (solid line) and a wafer with edge rounding and no oversize (dashed line) are measured for comparison, according to one embodiment. [Figure 12] FIG. 1 shows the distribution of etch pits across the entire surface (cross-sectional area) of a 4-inch InP wafer (100 mm diameter) according to one embodiment. [Figure 13] FIG. 10 shows the distribution of etch pits across the entire surface (cross-sectional area) of a further 4 inch InP wafer (100 mm diameter) according to one embodiment. [Figure 14] FIG. 1 shows the distribution of etch pits across the entire surface (cross-sectional area) of a 6-inch GaAs wafer (150 mm diameter) according to one embodiment. [Figure 15] FIG. 10 shows the distribution of etch pits across the entire surface (cross-sectional area) of a further 6-inch GaAs wafer (150 mm diameter) according to one embodiment. [Figure 16]FIG. 1 shows the distribution of specific electrical resistivity across the entire surface (cross-sectional area) of a 4-inch InP wafer (100 mm diameter) according to one embodiment. [Figure 17] FIG. 10 shows the distribution of specific electrical resistivity across the entire surface (cross-sectional area) of a further 4 inch InP wafer (100 mm diameter) according to one embodiment. [Figure 18] FIG. 1 shows the distribution of resistivity across the surface (cross-sectional area) of an 8-inch GaAs wafer (200 mm diameter) according to one embodiment. [Figure 19] FIG. 10 shows the distribution of resistivity across the surface (cross-sectional area) of a further 8-inch GaAs wafer (200 mm diameter) according to one embodiment. [Figure 20] FIG. 10 illustrates the distribution of resistivity across the surface (cross-sectional area) of yet another 8-inch GaAs wafer (200 mm diameter) according to one embodiment. [Figure 21] FIG. 10 illustrates the distribution of resistivity across the surface (cross-sectional area) of yet another 8-inch GaAs wafer (200 mm diameter) according to one embodiment. Detailed Description of the Invention

[0113] In the following description of preferred embodiments, it should be considered that the present disclosure in its various aspects is not limited to the details of the structure and arrangement of components as shown in the following description and drawings. The embodiments can be implemented or embodied in various ways. It should also be noted that the expressions and terms used herein are used for specific descriptive purposes only and should not be interpreted in a limiting manner by those skilled in the art. Furthermore, in the following description, the same reference numerals in various embodiments or figures indicate the same or similar features or objects, and therefore, in some cases, repeated detailed descriptions thereof will be omitted to maintain conciseness and clarity of the description.

[0114] FIG. 1 shows a schematic cross-sectional view of an apparatus 1 for producing an AIII-BV compound semiconductor single crystal from a melt of raw material according to one embodiment. The apparatus 1 includes a crucible 6 for holding the raw material melt or for holding the raw material before melting, and components 10 surrounding the crucible 6. The apparatus also includes a heater including one or more heating elements and a controller for controlling the heater to melt the raw material and to generate and maintain a directional temperature field during controlled cooling. In FIG. 1, the heater is not shown separately from the surrounding components 10, but is still present. The crucible has a central axis M, and the heater is located behind / beyond the components 10 surrounding the crucible, as viewed from the central axis M of the crucible 6.

[0115] The crucible 6 has a seed channel 3 into which a seed crystal is inserted. Starting from the seed channel 3, which may have a diameter of, for example, 5-100 mm, a tapered (conical) crucible section extends with increasing diameter, and from this section a cylindrical crucible section extends with a diameter d of, for example, 100-120 mm, 150-170 mm, or 200-220 mm. The specified interval for the diameter corresponds to the nominal diameter of the wafer obtained from the single crystal by separation (cutting) plus an oversize of, for example, 0-20 mm to allow for the removal of inhomogeneous or uneven surface material from the side surfaces. AIII-BV compound semiconductor single crystals can be made from GaAs or InP. Without limiting generality, the nominal diameter of an InP single crystal may be 100 mm (4 inches) or 150 mm (6 inches), and the nominal diameter of a GaAs single crystal may be 150 mm (6 inches) or 200 mm (8 inches). Other diameters (eg 200 mm or 8 inches for InP, 12 inches or 300 mm for GaAs) and other materials (eg GaP) are in principle possible.

[0116] The lower part of the crucible 6 shown in FIG. 1 shows a single crystal 4 growing upward from a seed crystal. A crystal growth or phase boundary 2, 2* represents the transition to the raw material melt 5 located above. The raw material melt 5 is covered by a protective layer (not shown) of boron oxide (BO), which may extend between the melt or single crystal and the crucible wall 7. A heater (not shown in FIG. 1) generates a temperature field in the crucible 6 that is essentially parallel to the central axis M. The gradient points vertically downward. As can be seen in FIG. 1, but especially in the enlarged view in FIG. 2, the phase boundary 2 or 2* does not form a straight, flat surface, but curves in a direction parallel to the central axis M toward the edge of the crucible 6, i.e., toward the outer crucible wall 7. This is because, as mentioned above, on the one hand, heat can be transported along the outer crucible wall 7 more efficiently than through the melt and / or crystal material itself, and, on the other hand, heat losses due to thermal radiation are clearly relevant here. As a result, the edge regions of the single crystal and the overlying melt are subjected to a thermal gradient component, again in the radial direction, which can result in thermal stresses in the edge regions of the single crystal during cooling immediately after crystallization, potentially increasing the formation of dislocations compared to the crystal interior (near the central axis M).

[0117] However, Figure 1 also illustrates a measure according to the present invention intended to offset this deviation from a linear phase boundary. In particular, in this embodiment, the outer crucible wall 7, itself made of pyrolytic boron nitride (pBN), has an outer surface 11a formed by a shiny metal coating 8a made of platinum. Platinum has a melting point of 2041.4 K, which is significantly higher than the melting points of GaAs (1511 K), InP (1343 K), or GaP (1621 K), and can be technically deposited without further effort in a suitable manner on a crucible made of pBN (melting point BN: 3240 K). Without limiting generality, for example, sputtering (which involves bombarding platinum with an electron beam to vaporize it and deposit it on or against the crucible wall) may be considered. A thickness of 1 μm to 10 μm may be sufficient for the platinum layer, although thicker or thinner layers are also possible. In the example embodiment, the outer surface 11a of the crucible wall is essentially formed over its entire surface by the coating 8a, at least in the region of the cylindrical crucible portion.

[0118] Furthermore, the crucible-enclosing element 10 may be, for example, a hard graphite shell or a graphite-coated quartz tube (a so-called liner), and has an inner surface 11b arranged opposite (sandwiched between) the outer surface 11a of the crucible wall 7 formed by the platinum coating 8a, with an intermediate space 8 therebetween, spaced a distance e from the outer surface 11a. Here, the inner surface 11b is also formed by a shiny metal (or optionally a roughened metal) coating 8b, which is formed from a metal in this specification. The intermediate space 8 is limited by the inner surface 11b of the crucible-enclosing element 10 and the outer surface 11a of the crucible wall 6 (however, it may be open at the front or top, as shown in FIG. 1). The distance e may be, for example, 1 mm to 15 mm (including the boundary value of the interval), preferably 1 mm to 3 mm.

[0119] Throughout the intermediate space 8, an exchange of thermal radiation occurs between the crucible 6 and the surroundings (e.g., component 10). Due to the shiny metal coating 8a made of platinum, the emissivity ε1 of the outer surface of the crucible wall 7 has a value of 0.01 in a particular embodiment, where the emissivity describes the radiation emitted by the crucible wall compared to an ideal radiant heater. Furthermore, the shiny metal coating 8b on the inner surface of the component surrounding the crucible has an emissivity ε2, which is, for example, 0.01. Therefore, in equation (3), the value of the degree of radiation exchange E in this design example is about 0.005. Therefore, the exchange of thermal radiation is significantly reduced.

[0120] In FIG. 1, coatings 8a and 8b are shown only on the left side for simple illustration and comparison with the prior art. Nevertheless, in this embodiment, actual coatings 8a and 8b extend around inner surface 11a and outer surface 11b, respectively. The corresponding phase boundary is shown as a dotted line and is labeled 2*. On the right side of FIG. 1, the coatings are omitted for comparison, which corresponds to a conventional structure. Here, the emissivity ε1 of the outer surface side of crucible wall 6 and the emissivity ε2 of the inner surface side of component 10 (conventional example) are, for example, 0.5 and 0.8, respectively, thus resulting in a value of the radiation exchange degree E of 0.44. The corresponding phase boundary is labeled 2 in FIG. 1 and, as can be seen particularly in FIG. 2, has a significantly larger phase boundary deflection compared to phase boundary 2*.

[0121] For both phase boundaries 2 and 2*, the inclination angles of the phase boundaries at the crucible wall 7 are also indicated by arrows in Figure 2. As mentioned above, the shape of the phase boundaries cannot, unfortunately, be directly observed. However, thermal modeling (latent heat, heat conduction, thermal radiation, and laminar convection) using the CGSIM software package (https: / / www.str-soft.com / ) confirmed the effect of measures taken at the crucible edge to reduce the degree of radiation exchange (values ​​calculated for 6-inch GaAs single crystal growth, growth rate 2 mm / h) on reducing the phase boundary deflection.

[0122] [Table 1]

[0123] Unlike Figure 2, which shows the crucible contact angle, Table 1 shows the tilt angle between the horizontal and the phase boundary at or near the crucible wall 7. The tilt angle is calculated as 90° minus the crucible contact angle. A tilt angle of 0° corresponds to a flat phase boundary at the crucible wall 7.

[0124] When the emissivity is 0.5 and 0.8 and the growth rate is 0.4 mm / h, a phase boundary deflection of 11.0 mm and a crucible contact angle of 38° are obtained.

[0125] Table 2 shows the values ​​obtained from the corresponding thermal modeling for indium phosphide (6-inch InP single crystal). The growth rate used here is also 2 mm / h.

[0126] [Table 2]

[0127] Furthermore, the effect of growth rate on the phase boundary deflection was also investigated in the thermal modeling. The results are summarized in Table 3, where we use the example of a 6-inch GaAs single crystal.

[0128] [Table 3]

[0129] Table 4 shows the corresponding results of thermal modeling for a 6-inch InP single crystal.

[0130] [Table 4]

[0131] The effect of the thermal conductivity of the crucible wall material (or its composition) on the resulting phase boundary deflection for different emissivities can also be determined from thermal modeling. Results for a 6-inch GaAs single crystal are shown in Table 5.

[0132] [Table 5]

[0133] Table 6 shows the corresponding results of thermal modeling for a 6-inch InP single crystal.

[0134] [Table 6]

[0135] To achieve the desired emissivity for a given device, the values ​​listed in Table 7 below may be considered.

[0136] [Table 7]

[0137] To obtain a degree of radiation exchange of 0.1 or less, it is sufficient according to the invention to implement an emissivity of 0.1 on only one side, while realizing any kind of surface on the other side, taking into account equation (3) and using, for example, data from Table 2. The suitability of materials for implementing temperature-dependent emissivity is known, for example, from https: / / www.sciencedirect.com / science / article / abs / pii / S0017931019321623.

[0138] Furthermore, simulations have shown that implementing the inventive strategy (emissivity-reducing coating) may correspond to a reduction in growth rate, but may no longer be economical in production due to increased production costs. For example, as shown in Table 1 for the inventive device 1, when ε1 = 0.01 and ε2 = 0.01, the crystal growth rate can be reduced from 2.0 mm / h to 0.4 mm / h (5 times the cooling time) by appropriately controlling the heater or heating element in a conventional setting to obtain a similar phase boundary deflection and similar tilt angle near the crucible edge. Unfortunately, emissivity values ​​below 0.04 are currently technically nearly impossible to achieve, at least from an economic point of view.

[0139] An embodiment of the method according to the present invention also describes the provision of an apparatus 1 shown in Figures 1 and 2, which includes the steps of inserting a seed crystal into a seed channel, filling a crucible with raw material (e.g., containing Ga and As or In and P), melting the raw material until the seed crystal is slightly melted to obtain a raw material melt, implementing a directed temperature field, lowering the temperature level of the temperature field for vertical long-term crystal growth, and controlled cooling of the grown single crystal. This can improve the reduction of phase boundary deviation by further slowing the growth rate, for example, to 1 mm / h or less, 0.5 mm / h or less, or even 0.4 mm / h or less. Here, an economic trade-off can be made between the resulting higher yield (a larger percentage of usable area at each wafer edge) and extended production time.

[0140] The present apparatus and process allow the production of AIII-BV compound semiconductor single crystals and the wafers obtained by separation thereof, which have particularly good characteristics with respect to the wafer edge. Wafers with the corresponding characteristics described below can be produced by the apparatus with reduced growth rate or by the equivalents described above.

[0141] Figure 3 first shows, purely schematically, the edge region at the wafer edge that is only reasonably accessible for measuring various parameters such as etch pit density (EPD). For example, to record slip lines (glide dislocation lines) according to the definition above, an edge exclusion zone of 2 mm (measured from the wafer edge) is required for etch pit density. The width is 3 mm, so the edge region is spaced 2 mm to 5 mm from the wafer edge.

[0142] In measurements to determine the specific electrical resistivity by the COREMA method, the edge exclusion zone is 1 mm and the width of the edge region is 2 mm (spacing 1 mm to 3 mm from the wafer edge). However, this measurement is performed before the usual edge rounding (KV) of the wafer with an additional 1 mm oversize (radius, and therefore diameter, of 2 mm), because otherwise the measurement would be prone to errors. The oversize is later removed from the wafer without edge rounding.

[0143] Figure 4 shows an example of a cross section of a wafer surface with dislocation etch pits. It is immediately apparent from this figure that a slight adaptation of the definition of slip lines was necessary compared to the SEMI M10 standard. The existing definition fails here because the mutual distance between etch pits is so large at low EPDs. Furthermore, for the slip lines involved, a slight lateral shift of the etch pit can be recognized, which may result from interactions with other dislocations. Therefore, the above definition, logically derived from SEMI M10, was used to determine slip lines (and also referred to herein as slip dislocation lines).

[0144] Figure 5 shows a schematic diagram of slip line formation. A slip plane 111 refers to a densely packed plane in a lattice with a relatively large lattice spacing relative to the next plane. It is oriented at an angle relative to the wafer surface 100 or cross-sectional area of ​​the single crystal before separation. In the slip plane, dislocation loops 120 are emitted from Frank-Read sources (visible on the left). These align with slip lines 130 in the wafer surface 100 as dislocation etch pits 140 (when the surface is treated with KOH solution). Figure 6 shows the corresponding top view of the wafer surface 100.

[0145] FIG. 7 shows the distribution of etch pits across the surface of an 8-inch GaAs wafer (200 mm diameter) similarly fabricated in accordance with one embodiment of the present invention described above. FIG. 8 shows the distribution of dislocation etch pits determined from the embodiment, which may be associated with slip lines originating and extending from the edge region as defined above. Measurements to determine slip lines were performed on semiconductor silicon-doped materials (where the corresponding specific electrical resistivity is between 0.05 and 10×10). 18 cm -3 , especially 0.3 to 3 × 10 18 cm -3 The average density of etch pits across the entire wafer (i.e., cross section, but excluding the 2 mm edge exclusion) was 112 cm -2 In the embodiment shown in Figures 7 and 8, the relative frequency of the slip lines extending from the edge region of the single crystal or wafer within the flat wafer surface or cross-sectional area, respectively, is 0.27 cm relative to the circumference of the wafer or single crystal cross-sectional area. -1 This becomes:

[0146] Table 8 below shows the following measured or determined values ​​from measurements of three 8-inch GaAs wafers (200 mm diameter) produced by separation from a single crystal according to an embodiment of the present invention: Etch pit density ((a) average, (b) EPD = 0 cm -2 (c) EPD<500cm -2 (d) EPD<1000cm -2 (percentage of measurement sites), the proportion of dislocation etch pits that can be associated with slip lines extending from the edge region of the wafer (referred to simply as the parameter "slipperiness"); the total length of these slip lines relative to the wafer diameter (divided by the wafer diameter) (simply represented as the parameter "slip density"); and The frequency of such slip lines (simply expressed as the parameter "glide dislocation line density") is related to the wafer circumference (divided by the wafer circumference).

[0147] [Table 8A]

[0148] Wafers with these low values ​​of slip, slip density and slip dislocation line density as defined above are particularly suitable for subsequent use of previously unused edge regions of the wafer edge in epitaxy processes for the manufacture of electronic or optical components without the formation of unacceptable morphological macroscopic steps that exceed certain tolerances regarding the number and / or length of the steps.

[0149] Small diameter (6 inch or 150 mm) GaAs and InP wafers are also being investigated.

[0150] The corresponding measurement results for three 6-inch GaAs wafers (150 mm diameter) are shown in Table 8B below.

[0151] [Table 8B]

[0152] The corresponding measurement results for three 4-inch InP wafers (100 mm diameter) are shown in Table 8C below.

[0153] [Table 8C]

[0154] The same conclusions as for the 8-inch GaAs wafers fabricated in accordance with embodiments of the present invention may be drawn for the 6-inch GaAs and 4-inch InP wafer embodiments. Figures 12 through 15 show the distribution of etch pits across the surface for a 6-inch GaAs wafer (wafer sample #9 in Figure 14 and wafer sample #10 in Figure 15) and a 4-inch InP wafer (wafer sample #7 in Figure 12 and wafer sample #7 in Figure 13) in the same manner as Figure 7 for wafer sample #4 of the 8-inch GaAs wafer.

[0155] Figures 9 and 10 reveal the cumulative distribution of residual mechanical shear stress or residual strain measured using the SIRIS method (described above) within the edge region defined by a distance of 1 to 3 mm from the wafer edge for six 6-inch GaAs wafers (150 mm diameter) according to an embodiment of the present invention.

[0156] Here too, for example, particularly low values ​​were found for the median values: 100% of all residual stress measurements (for each edge region of each wafer) were less than 80 kPa, 80% of all residual stress measurements (for each edge region of each wafer) were less than 50 kPa, and 50% of all residual stress measurements (for each edge region of each wafer) were significantly below 30 kPa, more precisely below 25 kPa. In three out of six samples, the median value (50% of measurement fields) was even less than 15 kPa.

[0157] The same applies to the residual strain calculated directly from the residual shear stress determined for the material, where 100% of all measured residual strains (for each edge region of each wafer) is 2.50 × 10 -6 and 80% of all measured residual strains (for each edge region of each wafer) were less than 1.53 × 10 -6 and 50% (median) of all measured residual strains (for each edge region of each wafer) were less than 0.92 × 10 -6 Less than, or more precisely, 0.75 × 10 -6 It was less than.

[0158] Table 9A below shows the average values ​​of the mechanical parameters of residual stress and residual strain determined for samples according to embodiments.

[0159] [Table 9A]

[0160] In particular, the average value of the residual strain is 2.5×10 -6These values ​​also highlight that wafers according to embodiments are suitable for enabling a step-free post-epitaxial surface on the wafer even within the edge region up to a 1 mm edge exclusion zone.

[0161] Residual stress measurements were also performed on 8-inch GaAs wafers (200 mm diameter, formed from semiconductor material) according to embodiments. Table 9B below shows the average values ​​of mechanical residual stress and strain determined for samples according to embodiments.

[0162] [Table 9B]

[0163] The results can still be considered favorable and reasonable.

[0164] FIG. 11 illustrates a semi-insulating material (having a specific electrical resistivity of, for example, 10 7 ~10 9 Ωcm, especially 1×10 8 Ωcm~8×10 8 Figure 1 shows the profile of the resistivity values ​​over the surface of a wafer, determined by COREMA measurements, for a wafer sample (6-inch GaAs wafer, 150 mm diameter) made with a resistivity in the range of Ωcm. As mentioned above, a wafer with 1 mm oversize and no edge rounding was measured. The dashed line shows the corresponding measurement with edge rounding and no oversize for comparison. The measurements at the extreme edge show very strong and atypical deviations that do not allow any statement about the real conditions regarding the resistivity in the edge region of the sample, which is why measurements were made with wafer oversize, as such measurements are more typical.

[0165] Evaluation of the profiles to determine the uniformity of the resistance distribution showed that the overall standard deviation for the sample in Figure 11, for example, was less than 4% over the entire wafer surface with an edge exclusion of only 1 mm (see equations (4)-(8) above). σ ρ total=5.23% σ ρ global=3.51% σ ρ local=3.61%

[0166] The values ​​for the same wafer sample or embodiment with a 3 mm edge exclusion are as follows: σ ρ total=5.07% σ ρ global=3.39% σ ρ local=3.55%, On the other hand, the annular edge region, defined by a distance of 1-3 mm from the wafer edge itself (i.e., 1 mm edge exclusion), measured alone, had an overall standard deviation of 31.65%.

[0167] Corresponding values ​​for conventionally produced 6-inch GaAs VGF wafers are given in the aforementioned DE 102007026298 A1 or WO 2008 / 148542 A1 (or U.S. Pat. No. 8,652,253), where only the 3 mm edge exclusion zone considered at the time was taken into account. Example 1 σ ρ total=6.5% σ ρ global=5.3% σ ρ local=2.5% Example 2 σ ρ total=4.5% σ ρ global=2.8% σ ρ local=1.25%

[0168] Since the overall standard deviation of the specific electrical resistivity for the edge region encompassing a distance range of 1 to 3 mm towards the wafer edge can be expected to be even higher as in the above embodiment, the values ​​of 5.3% and 4.5% for the comparative examples would increase significantly if an edge exclusion zone of only 1 mm is taken into account.

[0169] Therefore, the values ​​obtained for this embodiment are very low, especially when taking into account the current narrow edge exclusion zone compared to the prior art.

[0170] In view of the positive results for the 6-inch GaAs wafers, an 8-inch GaAs wafer (200 mm diameter, made of semi-insulating material, with a range of specific electrical resistivity values, e.g., 10 7 ~10 9 Ωcm, especially 1×10 8 Ωcm~8×10 8 COREMA measurements were also carried out for the resistivity (Ωcm). As the wafer diameter was too large to fit into the measuring device before edge rounding, the wafer was divided into four exact quadrants and measured separately. Evaluation of the measurement data on the complete (whole) wafer surface with an edge exclusion of only 1 mm gave the following values:

[0171] [Table 10]

[0172] Evaluation of the measurement data of the same embodiment, looking only at the edge region with a distance range of 1-3 mm to the wafer edge (ie, 1 mm edge exclusion), gave the following values:

[0173] [Table 11]

[0174] FIG. 18 shows a topogram of wafer P0790_24, FIG. 19 shows a topogram of wafer Q2250_02, FIG. 20 shows a topogram of wafer Q2250_46, and FIG. 21 shows a topogram of wafer Q2250_93.

[0175] COREMA measurements also show that four 4-inch InP wafers (100 mm diameter, made of semi-insulating material, resistivity 0.8×10) according to the embodiment were measured before edge rounding. 8 Ωcm~4×10 8 Evaluation of the measurement data on the complete (whole) wafer surface with an edge exclusion of only 1 mm gave the following values:

[0176] [Table 12]

[0177] Evaluation of the measurement data of the same embodiment, looking only at the edge region with a distance range of 1-3 mm to the wafer edge (ie, 1 mm edge exclusion), gave the following values:

[0178] [Table 13]

[0179] FIG. 16 shows a topogram of wafer P7763_33, and FIG. 17 shows a topogram of wafer 7763_67.

Claims

1. An apparatus (1) for producing an AIII-BV compound semiconductor single crystal (4) from a melt (5) of raw material, comprising: a crucible (6) for receiving a melt, the crucible (6) having a central axis (M) and a crucible wall (7) having a shell-shaped outer surface facing radially outwardly opposite the central axis (M); a component (10) that substantially surrounds the crucible (6) and faces the crucible wall (7) at a distance by an inner surface facing the outer surface, the crucible wall (7) being disposed in a substantially heat radiation exchange relationship with the component (10) surrounding the crucible (6); Equipped with The outer surface of the crucible wall (7) has a first emissivity (ε １ ), and the inner surface of the opposing component (10) surrounding the crucible (6) has a second emissivity (ε ２ ), and the first emissivity (ε １ ) and the second emissivity (ε ２ ) indicates how much radiation is emitted by the crucible wall (7) and the components surrounding the crucible (10), respectively, compared to an ideal radiant heater; The outer surface of the crucible wall (7) and the inner surface of the component (10) surrounding the crucible have the first emissivity (ε １ ) and the second emissivity (ε ２ ) each having a value of 0.1 or less.

2. The first emissivity (ε １ ) and the second emissivity (ε ２ 2. The device (1) according to claim 1, wherein ≡(f) ... has a value of 0.1 or less.

3. The first emissivity (ε １ ) and the second emissivity (ε ２ 3. The device (1) according to claim 1 or 2, wherein the value of .gtoreq.0.

05.

4. 4. The device (1) according to any one of claims 1 to 3, wherein the degree of radiation exchange between the crucible wall (7) and the component (10) surrounding the crucible is less than or equal to 0.

1.

5. 5. The apparatus (1) according to any one of claims 1 to 4, wherein the outer surface of the crucible wall (7) and the inner surface of the opposing component (10) together form and limit an intermediate space (8) shaped as a cylindrical shell in which radiation exchange occurs during operation of the apparatus.

6. 6. The device (1) according to any one of claims 1 to 5, wherein the coating (8a, 8b) at least partly forming the outer surface and / or the inner surface is provided in a periodic pattern, in particular in a mosaic or stripe pattern.

7. 7. The device (1) according to any one of claims 1 to 6, wherein the coating (8a, 8b) at least partially forming the outer surface and / or the inner surface is prepared as a shiny metal.

8. 7. The device (1) according to any one of claims 1 to 6, wherein the component (10) surrounding the crucible is made from hard graphite and includes a rough metal layer.

9. 7. The device (1) according to any one of claims 1 to 6, wherein the component (10) surrounding the crucible is made from hard graphite and includes a shiny metal layer.

10. 7. Apparatus (1) according to any one of claims 1 to 6, wherein the component (10) surrounding the crucible is a quartz tube coated with graphite.

11. 12. The apparatus (1) according to claim 11, wherein the component (10) surrounding the crucible is a liner.

12. 12. The apparatus (1) according to any one of claims 1 to 11, wherein the crucible (6) is made of boron nitride or pyrolytic boron nitride and the outer surface of the crucible wall (7) is at least partially formed by a crude platinum or graphite coating.

13. 12. Apparatus according to any one of claims 1 to 11, wherein the crucible (6) is made of boron nitride or pyrolytic boron nitride and the outer surface of the crucible wall (7) is at least partly formed by a shiny platinum or graphite coating.

14. 14. The apparatus (1) according to any one of claims 1 to 13, further comprising one or more heating elements arranged outside the component (10) facing the crucible (6) as viewed from the central axis (M) of the crucible (6).

15. 15. The apparatus (1) according to any one of claims 1 to 14, wherein the apparatus (1) is configured to produce AIII-BV compound semiconductor single crystals comprising GaAs or InP for separation into wafers, preferably having a nominal diameter of 100 mm, 150 mm or 200 mm.

16. 16. Apparatus (1) according to any one of the preceding claims, wherein the crucible wall (7) is made of a material having an internal structure such that the heat conduction is isotropic.

17. 17. Apparatus (1) according to any one of the preceding claims, wherein the crucible wall (7) is made from a material having an internal structure such that the thermal conductivity is less than or equal to 3 W / mK.

18. 18. Apparatus according to any one of the preceding claims, wherein the crucible (6) is made from glassy carbon.

19. A method for producing an AIII-BV compound semiconductor single crystal from a melt of a raw material, comprising: Providing an apparatus according to any one of claims 1 to 18; Inserting a seed crystal into a seed channel; establishing a directed temperature field parallel to the central axis of the crucible with one or more heating elements; adjusting the crystal growth rate by controlling the one or more heating elements so that a tilt angle between the phase boundary and a horizontal direction perpendicular to the inner surface of the adjacent crucible side wall is continuously maintained to be 40 degrees or less when the AIII-BV compound semiconductor is GaAs, preferably 37 degrees or less when the AIII-BV compound semiconductor is InP, more preferably 34 degrees or less when the AIII-BV compound semiconductor is GaAs, and more preferably 32 degrees or less when the AIII-BV compound semiconductor is GaAs, and 31 degrees or less when the AIII-BV compound semiconductor is InP; crystallizing the AIII-BV compound semiconductor single crystal and then cooling it; A method comprising:

20. 20. The method of claim 19, wherein the crystal growth rate is 2 mm / h or less.

21. An AIII-BV compound semiconductor single crystal or a wafer obtained by separation therefrom, produced by the method of any one of claims 19 or 20 using the apparatus of any one of claims 1 to 18.

22. 1. An AIII-BV compound semiconductor single crystal or a wafer obtained by separation therefrom, wherein, within an annular edge region of a cross-sectional area perpendicular to a central axis of the AIII-BV compound semiconductor single crystal or the wafer, the percentage of dislocation etch pits associated with slip lines extending from the annular edge region of the AIII-BV compound semiconductor single crystal or the wafer within the cross-sectional area is 30% or less, preferably 10% or less, and more preferably 5% or less of the total number of dislocation etch pits, the width of the annular edge region measured from the outer edge of the AIII-BV compound semiconductor single crystal or the wafer is 5 mm or less, and the AIII-BV compound semiconductor single crystal or wafer has an edge exclusion zone of 2 mm measured from the outer edge of the AIII-BV compound semiconductor single crystal or the wafer.

23. the relative frequency of slip lines extending within the cross-sectional area originating from the annular edge region of the AIII-BV compound semiconductor single crystal or the wafer to the circumferential length of the cross-sectional area of ​​the AIII-BV compound semiconductor single crystal or the wafer is 0.25 cm －１ Less than 0.1 cm, preferably －１ Less than 0.05 cm, more preferably －１ 23. The AIII-BV compound semiconductor single crystal according to claim 22, or a wafer obtained by separation therefrom, wherein:

24. 1. A wafer obtained by separation from an AIII-BV compound semiconductor single crystal, the wafer having a distribution of specific electrical resistivity within a cross-sectional area perpendicular to its central axis, the global standard deviation (σglobal) of the distribution being 17.0% or less, preferably 16.0% or less, of the average value of the specific electrical resistivity within the cross-sectional area of ​​the wafer, the determination of the global standard deviation being based on a characteristic length of 10 mm and an edge exclusion zone of 1 mm measured from the outer edge of the wafer.

25. 25. The wafer of claim 24, wherein the AIII-BV compound semiconductor is GaAs, the global standard deviation (σ global ) is 4.0% or less of the average value of the specific electrical resistivity within the cross-sectional area of ​​the wafer, and / or the wafer has a diameter of 150 mm or 6 inches or less.

26. 25. The wafer of claim 24, wherein the AIII-BV compound semiconductor is GaAs, the global standard deviation (σ global ) is 16.0% or less of the average value of the specific electrical resistivity within the cross-sectional area of ​​the wafer, and / or the wafer has a diameter of 200 mm or 8 inches or greater.

27. 25. The wafer of claim 24, wherein the AIII-BV compound semiconductor is InP, the global standard deviation (σ global ) is 17.0% or less of the average value of the specific electrical resistivity within the cross-sectional area of ​​the wafer, and / or the wafer has a diameter of 100 mm or 4 inches or greater.

28. 28. A wafer according to any one of claims 24 to 27, wherein the value of the global standard deviation (σglobal) measured only in the edge region taking into account an edge exclusion of 1 mm is 35.0% or less, preferably 30.0% or less, of the average value of the specific electrical resistivity, and the width of the edge region is defined by a distance of 3 mm or less measured from the outer edge of the wafer, and has an edge exclusion of 1 mm measured from the outer edge of the wafer.

29. The mean or median of the distribution of residual strain content within the annular edge region of the cross-sectional region perpendicular to the central axis (M) of the AIII-BV compound semiconductor single crystal or the wafer is 2.5×10 －６ or less, preferably 1.6 × 10 －６ 29. The wafer of claim 22, wherein the residual strain in the cross-sectional area within the annular edge region of the AIII-BV compound semiconductor single crystal or the wafer is derived in a spatially resolved manner from measurements made by a SIRIS method, the lateral resolution of the spatially resolved measurements being 100 μm, and the width of the annular edge region is defined by a distance of 3 mm or less measured from the outer edge of the AIII-BV compound semiconductor single crystal or the wafer, with an edge exclusion zone of 1 mm measured from the outer edge.

30. The mean value or the median value of the distribution of the residual strain content within the annular edge region is 1.1×10 －６ 30. The wafer of claim 29, wherein:

31. A wafer obtained by separation from an AIII-BV compound semiconductor single crystal, wherein an average value of a residual stress content distribution in an annular edge region of a cross-sectional area perpendicular to a central axis (M) of the AIII-BV compound semiconductor single crystal or the wafer is 60 kPa or less, the residual stress in the annular edge region of the cross-sectional area of ​​the AIII-BV compound semiconductor single crystal or the wafer is measured in a spatially resolved manner according to the SIRIS method, the lateral resolution of the spatially resolved measurement is 100 μm, and the width of the annular edge region is defined by a distance of 3 mm measured from an outer edge of the AIII-BV compound semiconductor single crystal or the wafer, and has an edge exclusion zone of 1 mm measured from the outer edge.

32. 32. The wafer of claim 31, wherein the average value of the distribution of residual stress content within an annular edge region of a cross-sectional area perpendicular to the central axis (M) of the AIII-BV compound semiconductor single crystal or the wafer is 60 kPa or less, the AIII-BV compound semiconductor is GaAs, and the diameter of the wafer is 200 mm or more or 8 inches or more, respectively.

33. 32. The wafer of claim 31, wherein the average value of the distribution of residual stress content within the annular edge region of the cross-sectional area perpendicular to the central axis (M) of the AIII-BV compound semiconductor single crystal or the wafer is 30 kPa or less, the AIII-BV compound semiconductor is GaAs, and the diameter of the wafer is 150 mm or 6 inches, respectively.

34. 34. The wafer of claim 31, wherein the average value of the distribution of the residual stress content in the edge region is 25 kPa or less.

35. 35. The AIII-BV compound semiconductor single crystal or wafer obtained by separation therefrom according to any one of claims 22 to 34, wherein the diameter perpendicular to the central axis of the AIII-BV compound semiconductor single crystal or the wafer is 100 mm to 220 mm, including the boundary values ​​of the specified interval.

36. 36. The AIII-BV compound semiconductor single crystal or wafer obtained by separation therefrom according to any one of claims 22 to 35, wherein the AIII-BV compound semiconductor comprises gallium arsenide (GaAs) or indium phosphide (InP).

Images