Ferroelectric III-nitride layer thickness scaling, heterostructures and methods for their formation

Abstract

Heterostructures and methods for forming same are provided. The heterostructure includes a template layer and a ferroelectric semiconductor layer supported by the template layer, the ferroelectric semiconductor layer being single crystalline. The ferroelectric semiconductor layer includes an alloy of III-nitride materials. The alloy includes a Group IIIB element. The ferroelectric semiconductor layer is in contact with the template layer. The ferroelectric semiconductor layer has a thickness of less than 100 nm.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 440,900, filed January 24, 2023, entitled "Ferroelectric III-Nitride Layer Thickness Scaling," the disclosure of which is incorporated herein by reference in its entirety. STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] This invention was made with government support under Contract Nos. HR0011-22-2-0024 and HR0011-22-C-0087 awarded by the Defense Advanced Research Projects Agency of the United States Department of Defense. The government has certain rights in this invention. [Technical Field]

[0003] The present invention relates generally to III-nitride heterostructures. [Background technology]

[0004] III-nitride (III-N) semiconductors exhibit a wide, tunable direct bandgap, large breakdown strength, high electron mobility, high electron saturation drift velocity, high thermal and chemical stability, and high radiation hardness, and have emerged as an enabling technology for a wide range of applications, from solid-state lighting, radio frequency (RF), and power electronics to quantum information, renewable energy, and even emerging edge computing and artificial neural networks. Because the wurtzite (wz) crystal structure of III-N semiconductors lacks spatial inversion symmetry, they exhibit large spontaneous polarization properties, which play a useful role in reorganizing interfacial mobile charges to form a two-dimensional electron / hole gas (2DEG / 2DHG) and improve the quantum efficiency of light-emitting diodes (LEDs).

[0005] Recently, ferroelectricity has been demonstrated in both sputter-deposited and epitaxially grown Sc-III-N using molecular beam epitaxy (MBE). In such cases, the intrinsic spontaneous polarization of the nitride semiconductor can be reconfigured by an external electric field, thereby supporting applications in memories, transistors, resonators, filters, and other devices. Summary of the Invention

[0006] According to one aspect of the disclosure, a heterostructure includes a template layer and a ferroelectric semiconductor layer supported by the template layer, the ferroelectric semiconductor layer being single crystalline. The ferroelectric semiconductor layer includes an alloy of a III-nitride material. The alloy includes a IIIB element. The ferroelectric semiconductor layer is in contact with the template layer. The ferroelectric semiconductor layer has a thickness of less than 100 nm.

[0007] According to another aspect of the present disclosure, a heterostructure includes a template layer, a ferroelectric semiconductor layer supported by the template layer, and a conductive layer adjacent to a side of the ferroelectric layer opposite the template layer. The ferroelectric semiconductor layer includes an alloy of Group III nitride materials. The alloy includes a Group IIIB element. The ferroelectric semiconductor layer is in contact with the template layer. The side of the ferroelectric semiconductor layer has a native oxide layer having a thickness of about 1 nm or less.

[0008] According to yet another aspect of the present disclosure, a method for forming a heterostructure includes providing a template layer for the heterostructure. The template layer is supported by a substrate. The method further includes a surface treatment step for removing oxide from a surface of the template layer, and a non-sputter epitaxial growth step after the surface treatment step to form a ferroelectric semiconductor layer of the heterostructure. The ferroelectric semiconductor layer is supported by and in contact with the template layer. The method further includes depositing a conductive layer adjacent to a side of the ferroelectric layer opposite the template layer. The ferroelectric semiconductor layer includes an alloy of a Group III-nitride material. The non-sputter epitaxial growth step is configured to incorporate a Group IIIB element into the alloy of the Group III-nitride material. The deposition of the conductive layer is performed such that exposure of the ferroelectric semiconductor layer to the environment between the non-sputter epitaxial growth step and the deposition of the conductive layer is limited to a time such that a native oxide layer deposited between the conductive layer and the ferroelectric semiconductor layer has a thickness of about 1 nm or less.

[0009] According to yet another aspect of the present disclosure, a heterostructure includes a template layer and a ferroelectric semiconductor layer supported by the template layer, the ferroelectric semiconductor layer being single crystalline. The ferroelectric semiconductor layer includes an alloy of a III-nitride material. The alloy includes a IIIB element. The ferroelectric semiconductor layer is in contact with the template layer. The ferroelectric semiconductor layer has a thickness of less than 10 nm.

[0010] According to yet another aspect of the disclosure, a heterostructure includes a template layer and a ferroelectric semiconductor layer supported by the template layer, the ferroelectric semiconductor layer being single crystalline. The ferroelectric semiconductor layer includes an alloy of III-nitride materials. The alloy includes a Group IIIB element. The ferroelectric semiconductor layer has a thickness of less than 100 nm. The ferroelectric semiconductor layer is in contact with the template layer such that the coercive field of the ferroelectric semiconductor layer is a function of the lattice mismatch between the template layer and the ferroelectric semiconductor layer.

[0011] According to yet another aspect of the present disclosure, a method for forming a heterostructure includes providing a template layer for the heterostructure. The template layer is supported by a substrate. The method further includes performing a surface treatment procedure to remove oxide from a surface of the template layer, and performing a non-sputter epitaxial growth procedure after performing the surface treatment procedure to form a ferroelectric semiconductor layer of the heterostructure. The ferroelectric semiconductor layer is supported by and in contact with the template layer. The method further includes depositing a conductive layer adjacent to a side of the ferroelectric layer opposite the template layer. The ferroelectric semiconductor layer includes an alloy of a Group III-nitride material. The non-sputter epitaxial growth procedure is configured to incorporate a Group IIIB element into the alloy of the Group III-nitride material. The conductive layer is deposited in situ such that the ferroelectric semiconductor layer is not exposed to the environment between the non-sputter epitaxial growth procedure and the deposition of the conductive layer.

[0012] In relation to any one of the preceding aspects, the devices and / or methods described herein may alternatively or additionally include any combination of one or more of the following aspects or features: The heterostructure further includes a conductive non-native passivation layer adjacent to a side of the ferroelectric layer opposite the template layer. An oxide layer is deposited between the conductive non-native passivation layer and the ferroelectric semiconductor layer. The oxide layer has a thickness of about 1 nm or less. The conductive non-native passivation layer includes a metallic material. The metallic material includes Al. The metallic material includes Ti. The heterostructure further includes a non-native oxide layer adjacent to the ferroelectric layer opposite the template layer. The non-native oxide layer includes indium tin oxide (ITO). The ferroelectric semiconductor layer has a thickness of about 30 nm or less. The ferroelectric semiconductor layer has a thickness of about 18 nm or less. The ferroelectric semiconductor layer has a thickness of about 10 nm or less. The ferroelectric semiconductor layer has a thickness of about 5 nm or less. The ferroelectric semiconductor layer has a wurtzite structure. The (0001) plane of the wurtzite structure contacts the template layer. The surface of the template layer contacting the single-crystal semiconductor layer matches the atomic arrangement of the (0001) plane of the wurtzite structure. The surface of the template layer is oriented in the (011) plane. The template layer includes a metal. The surface of the template layer is oriented in the (111) plane. The Group IIIB element is scandium. The alloy of the Group III nitride material includes AlN. The conductive layer includes a metal material. The conductive layer includes a non-native oxide layer. The ferroelectric semiconductor layer has a thickness of about 10 nm or less. The ambient includes a nitrogen-purged vessel. Depositing the conductive layer includes limiting exposure to the ambient to less than about 24 hours. Depositing the conductive layer includes limiting exposure to the ambient to less than about 1 hour. Depositing the conductive layer includes depositing a non-native oxide layer. Depositing the conductive layer includes depositing a metal layer. The non-sputter epitaxial growth procedure is configured such that the ferroelectric semiconductor layer has a thickness of about 10 nm or less. The surface treatment procedure involves annealing the template layer in a vacuum, and the non-sputter epitaxial growth procedure is performed under nitrogen-rich conditions.

[0013] For a more complete understanding of this disclosure, reference should be made to the following detailed description and the accompanying drawings, in which like reference numerals identify like elements throughout the drawings. [Brief explanation of the drawings]

[0014] [Figure 1] (a) Schematic of an example ITO / ScAlN / Mo capacitor, (b) RHEED patterns along the <112*0> and <101*0> directions of a 5-nm-thick ScAlN layer, and (c) XRD 2θ / ω scans of ScAlN films grown on Mo templates of various thicknesses (5-100 nm). The substrate is shown for comparison; the peak at approximately 31.7° is from the Sc2O3 layer in the substrate. Note that the (2*) in the orientation refers to a 2 with a bar over it, and the (1*) also refers to a 1 with a bar over it. [Figure 2] (a) Cross-sectional HAADF-STEM image of an example 5 nm thick ScAlN layer grown on a Mo template; (b, c) Nanobeam electron diffraction patterns captured from the Mo (b) and ScAlN (c) regions labeled in (a); (d) Magnified HAADF-STEM image showing the thickness of the ScAlN layer; (e) Illustrative diagram of the epitaxial relationship between wz-ScAlN and bcc-Mo; (f) EDS element map of an example ITO / ScAlN / Mo capacitor. [Figure 3] This figure shows graphical illustrations of the ferroelectric properties of example ScAlN films grown by MBE. The figure includes (a) CV loops measured at an AC voltage of 200 mV, a frequency of 2 MHz, and a voltage step of 50 mV; (b) PE loops measured using a triangular waveform PUND measurement at 20 kHz at room temperature; and (c) voltage-dependent PUND measurements using a triangular pulse with a pulse width of 25 μs. Here, butterfly-shaped CV loops are demonstrated for a 5 nm thick ScAlN film, and saturated polarization is observed in both bias directions for 100 nm to 18 nm thick ScAlN. For the 12 nm and 5 nm thick examples, only one bias direction is observed. The curves have been scaled to better illustrate the trend. The electrodes used had a nominal diameter of approximately 20 μm and were calibrated by SEM. [Figure 4]Graphical plots comparing (a) the switchable polarization and (b) the coercive field as a function of thickness for a number of exemplary ScAlN thin films are shown, as well as data previously reported using sputter deposition by Fichtner and Schonweger et al. (cyan squares), Wang et al. (black squares), Shinnosuke et al. (purple squares), Sushant et al. (green squares), Mizutani et al. (blue squares), and Ryoo et al. (magenta squares). Error bars represent the standard deviation based on measurements from different exemplary devices. [Figure 5] 1 shows a cross-sectional schematic diagram of a device having a heterostructure with an epitaxially grown monocrystalline III-nitride alloy layer, according to an example. [Figure 6] 1 is a flow diagram of a method for fabricating a heterostructure having an epitaxially grown single crystalline III-nitride alloy layer, according to an example. [Figure 7] 1 illustrates a cross-sectional schematic diagram of a memory cell having a heterostructure with an epitaxially grown monocrystalline III-nitride alloy layer, according to an example. [Figure 8] 1 illustrates a cross-sectional schematic diagram of another transistor device having a heterostructure with an epitaxially grown monocrystalline III-nitride alloy layer, according to an example. [Figure 9] 1 illustrates a cross-sectional schematic diagram of a memory device having a heterostructure with an epitaxially grown monocrystalline III-nitride alloy layer, according to an example. [Figure 10] 1 shows a cross-sectional schematic diagram of a device having a free-standing heterostructure with epitaxially grown monocrystalline III-nitride alloy layers, according to an example. [Figure 11] 1 shows a cross-sectional schematic diagram of an exemplary heterostructure having an epitaxially grown monocrystalline III-nitride alloy layer and a graphical plot comparing the electrical properties of the exemplary heterostructure with and without a seed layer. DETAILED DESCRIPTION OF THE INVENTION

[0015] Embodiments of the disclosed devices and methods may take a variety of forms. Specific embodiments are shown in the drawings and will be described below with the understanding that the disclosure is intended to be illustrative. The present disclosure is not intended to limit the invention to the specific embodiments described and illustrated herein.

[0016] Heterostructures having thin ferroelectric semiconductor layers are described. The thickness of the ferroelectric semiconductor layers can be reduced to less than 100 nm, such as about 5 nm. The ferroelectric semiconductor layers can be composed of or otherwise include III-nitride alloys, such as ScAlN. Methods for fabricating such heterostructures and devices are also described.

[0017] Ferroelectrics that function at reduced dimensions are useful for building highly scaled, energy-efficient electronics and other devices. For example, functioning at reduced dimensions can lead to lower switching voltages and smaller domain sizes, both of which are useful for next-generation low-power, high-density, and multifunction devices and architectures such as memory / sensing / computing devices. The existence of ferroelectric properties at reduced dimensions involves many processes, including domain wall motion and energy transfer, phase stability, strain, stoichiometry, and interfacial bonding, all of which are useful for understanding the fundamental and intrinsic properties of materials.

[0018] Sc-alloy III-nitride semiconductors have emerged as promising ferroelectrics with widely tunable bandgaps, large switchable polarizations, and high coercive fields. The large switchable polarization provides more design freedom for field-charge coupling, and the high coercive fields offer large memory windows when integrated with field-effect transistors. Advances in deposition methods have paved the way for integrating Sc-III-N nitride ferroelectrics with mainstream semiconductors such as silicon and GaN. However, the large switching voltages due to limited thickness scaling pose challenges to the practical application of nitride ferroelectrics. On the other hand, unlike hafnia-based ferroelectrics, which tend to have competing phases, the ferroelectric wurtzite phase is an energetically stable crystalline phase of low-Sc-III-N at room temperature, allowing ferroelectric order to be maintained even in extremely low-dimensional nitride ferroelectrics. Therefore, the examples described here are useful for exploring thickness scaling of nitride ferroelectrics.

[0019] The thickness scaling behavior of sputtered ScAlN has been investigated. The results have been characterized by an increase in leakage current. Furthermore, the polarization switching behavior has been characterized by a non-saturating polarization with the thinnest layer limited to around 10 nm. However, for most conventional ferroelectrics, investigating significant scaling behavior requires reducing the film thickness to the sub-10 nm regime, which has remained difficult and elusive for nitride ferroelectrics.

[0020] Compared to sputter deposition, molecular beam epitaxy (MBE) and other non-sputter epitaxial growth methods offer better film thickness and quality control, making them useful for further expanding the study of thickness scaling and behavior of nitride ferroelectrics.

[0021] Below we present examples of heterostructures to investigate the ferroelectric switching behavior of ScAlN thin films grown by MBE in the thickness range of 100 nm to 5 nm. The wurtzite structure of the as-grown films was characterized using reflection high-energy electron diffraction (RHEED), X-ray diffraction (XRD), and scanning transmission electron microscopy (STEM). The ferroelectric properties of the as-grown films were confirmed and studied by capacitance-voltage (CV) loops and positive-up-negative-down (PUND) measurements. In the example with a 5 nm thick ScAlN layer, a switching voltage close to 2 V and a ferroelectric constant of about 23 μC / cm were observed. 2 A saturated remanent polarization of 1000 Å is demonstrated. The disclosed devices and methods therefore provide fundamental thickness-scaling properties of epitaxial ferroelectric ScAlN thin films and examples of compact, power-efficient devices and applications based on nitride ferroelectrics.

[0022] The Sc content, thickness, and other properties of the wurtzite phase ScAlN layers of the disclosed devices and methods can be derived from the examples described herein. For example, the Sc content, x, can vary from about 0.05 to about 0.5 in some cases. In other cases, the Sc content can be outside this range.

[0023] The disclosed devices and methods may include one or more elements, aspects, or other features described in International Application No. PCT / US2022 / 028365 (filed May 9, 2022, and entitled "Epitaxial Nitride Ferroelectrics"), the disclosure of which is incorporated herein by reference in its entirety.

[0024] The ferroelectric semiconductor layer can be supported and contacted by a metal template layer. For example, the template layer can be composed of or otherwise include a CMOS-compatible metal such as molybdenum. The ferroelectric semiconductor layer can be monocrystalline or single crystalline, despite the polycrystalline nature of the metal layer. The surface of the metal layer can be oriented in a plane that matches the atomic arrangement of the wurtzite (0001) plane of the monocrystalline III-nitride alloy layer. The template layer can be composed of or otherwise include alternative or additional materials, including, for example, GaN, silicon, and other semiconductor materials. Ferroelectric semiconductor layers supported by template layers can be used in a variety of heterostructure arrays and corresponding devices, including, for example, capacitors and memristors (e.g., synaptic memory devices) described below.

[0025] The disclosed heterostructures, devices, and methods enable the integration of ferroelectric ScAlN and other III-nitride alloys with various metallic materials. For example, the metallic materials can include metals compatible with complementary metal-oxide-semiconductor (CMOS) circuits and fabrication processes. Such integration applies the advantages of ferroelectric III-nitride materials (e.g., ScAlN) to enable applications ranging from single devices to systems and even hybrid integrated circuits. For example, creating ferroelectric III-nitride materials compatible with CMOS and other technologies involves achieving single-crystal ferroelectric ScAlN heterostructures on metal electrodes. However, sputter-deposited films are generally polycrystalline, and material quality is very limited.

[0026] The realization of fully epitaxial single-crystalline ferroelectric III-N, such as ScAlN, on metal electrodes offers unique opportunities in bandgap / polarization engineering, interface / defect / doping control, thermal management, and high-yield mass production. However, to date, achieving single-crystalline III-N semiconductors on metals remains challenging due to severe lattice mismatch, highly reactive metal surfaces, and the lack of highly oriented metal substrates / templates.

[0027] Among the commonly used CMOS compatible metals, molybdenum (Mo) has a high melting point (approximately 2160°C) and a low thermal expansion coefficient (5×10 at 20°C). -6 °C -1 ), and low electrical resistivity (5×10 -8 Mo's low electrical resistance (Ω·m) makes it a useful metal that can withstand the thermal budgets encountered in CMOS fabrication processes. Furthermore, Mo has low acoustic attenuation due to its high acoustic velocity and can be easily wet-etched. Therefore, Mo can be used as the bottom electrode for high-frequency acoustic filters and resonators. Therefore, III-N heterostructures epitaxially grown on Mo can be used to realize CMOS-compatible ferroelectric nitride and fully nitride-based complementary circuits, as well as a new class of integrable ultralow-loss and ultrahigh-frequency acoustoelectronic devices. This combination of III-N heterostructures on Mo also supports the integration of nonvolatile ferroelectric memristors (e.g., ScAlN memristors) with processors, which can be used, for example, as building blocks for high-speed data transmission and analysis in artificial neural networks.

[0028] Although described in connection with the example of an epitaxially grown ScAlN layer, the disclosed heterostructures, devices, and methods can be applied to a wide variety of III-nitride alloys. Accordingly, the disclosed heterostructures, devices, and methods can include or incorporate scandium into other III-nitride wurtzite structures. For example, the disclosed heterostructures, devices, and methods can include or incorporate one or more epitaxially grown ScAlGaN, ScAlInN, ScGaN, or ScInN layers. The composition, structure, fabrication, and other characteristics of the heterostructure can also vary from the described example. For example, the heterostructure can include any number of epitaxially grown layers, both ferroelectric and non-ferroelectric.

[0029] The disclosed heterostructures, devices, and methods are not limited to Group III-nitride alloys containing scandium. For example, the Group III-nitride alloys can include additional or alternative Group IIIB elements such as yttrium (Y) and lanthanum (La).

[0030] Although some aspects of the disclosed methods are described in connection with MBE growth procedures, additional or alternative non-sputter epitaxial growth procedures can be used. For example, metalorganic chemical vapor deposition (MOCVD) and hydride vapor phase epitaxy (HVPE) procedures can be used. Still other procedures can be used, including, for example, pulsed laser deposition (PLD) and atomic layer deposition (ALD) procedures.

[0031] Although described in connection with the example of growing III-nitride alloys on Mo layers, the disclosed heterostructures, devices, and methods are not limited to growth on Mo layers. A variety of metals can be used, including, for example, Al, Pt, Ti, Fe, Cu, and Ni. While described in connection with polycrystalline metal layers, the disclosed heterostructures, devices, and methods can alternatively or additionally include or use single-crystal or monocrystalline metal layers.

[0032] III-N semiconductors with a wz phase (space group P63mc) lattice have the strongest polarization along the c-axis. <0001> Growth along a direction maximizes the remanent polarization of the ferroelectric nitride, but in other cases growth along alternative or additional directions may be performed.

[0033] Below, we describe a number of examples grown on Mo(011) / Sc2O3(111) / Si(111) templates using a Veeco GENxplor MBE system. The MBE system is equipped with a Veeco Unibulb radio frequency (RF) N plasma source. The Sc source (99.999% purity) and Al source (99.99995% purity) were provided by a high-temperature Knudsen cell and a dual-filament SUMO Knudsen cell, respectively. All ScAlN layers in the examples were grown under the same conditions except for the growth time. Details regarding the growth conditions are described in the above-mentioned patent documents.

[0034] The thickness of the ScAlN films was varied from 100 nm to 5 nm by varying the growth time. However, the nominal Sc content was maintained at 0.3 to avoid the occurrence of secondary phases (other content levels may be used in other cases). To eliminate the possibility of coupling between the depletion region and substrate polarity pinning, ScAlN films were grown directly on metal substrates without a GaN or AlN buffer. To obtain an oxide-free Mo surface, a high-temperature anneal was performed before ScAlN growth. The Sc content was calibrated by energy-dispersive X-ray (EDX) spectroscopy embedded in a scanning electron microscope (SEM) system. The growth process was monitored in situ using a RHEED system. The crystal structure and film thickness were characterized by X-ray diffraction (XRD). To minimize the formation of an oxide layer after exposure to air, all ScAlN samples were quickly or immediately loaded into a sputtering system (Lab 18) for 10 nm-ITO layer deposition after removal from the MBE load-lock chamber. To fabricate metal-ferroelectric-metal (MFM) capacitors, circular 100-nm Au / 50-nm ITO pads with diameters of 10–50 μm were deposited on the ScAlN surface via a lithography process as the top electrode, while a Mo template was used as the bottom electrode, as shown in Figure 1(a). To separate the capacitors, the residual ITO was etched away using HCl solution.

[0035] FIG. 1(a) shows a schematic diagram of a device 100 according to an example. In some cases, the device 100 may be a (0001) ScAlN ||(011) Mo and [112*0] ScAlN ||"100" Mo The ScAlN layer 102 may be formed of a high-quality wurtzite phase ferroelectric ScAlN layer 102 (e.g., a 100 nm thick layer) on a Mo(011) layer 104 having an epitaxial relationship of . The thickness of the ScAlN layer 102 may be varied as described herein.

[0036] Figure 1(b) shows the RHEED pattern of an example with ultrathin ScAlN nominally 5 nm thick. Only one set of wurtzite phase RHEED patterns was observed, indicating the absence of other phases or in-plane rotation. XRD 2θ / ω scans of all ScAlN films are shown in Figure 1(c). For ScAlN films 18 nm and thicker, a clear characteristic diffraction peak for the (0002) plane of wurtzite ScAlN was observed at approximately 36°. For 12 nm thick ScAlN, only a small shoulder at 36° was observed. Currently, the ScAlN signal is not detectable for 5 nm thick ScAlN due to limitations in the measurement setup. The peak position here is slightly lower than that previously reported for GaN substrates, indicating that the ScAlN layer is under compressive stress. The peak at approximately 31.7° is from the Sc2O3 layer included in the substrate to confirm the epitaxial relationship between the Si substrate and the Mo metal layer and may therefore not be present in the disclosed heterostructure and device examples.

[0037] The crystal structure and thickness of the ultrathin (5 nm) ScAlN layer were characterized using STEM measurements. Figure 2(a) shows a cross-sectional high-angle annular dark-field (HAADF-STEM) image of ScAlN grown on Mo(011), revealing an atomically sharp and clean ScAlN / Mo interface. Figures 2(b) and (c) show nanobeam electron diffraction (NBED) patterns recorded from the Mo and ScAlN layers, respectively, using the same electron beam orientation. The electron diffraction pattern indicates that the ultrathin ScAlN grown on Mo has a single-phase wurtzite structure. This is because the reciprocal lattice spacing ratio between the (0002) and (11-20) plane reflections is consistent with that of a wurtzite crystal structure. The alignment pattern of the electron diffraction pattern, as sketched in Figure 2(e), confirms the aforementioned epitaxial relationship between ScAlN and Mo. The thickness of the 5 nm ScAlN layer was determined from the contrast variation (Figure 2(d)). These results establish that a uniform c-axis oriented wurtzite phase with the strongest polarization can be achieved in ultrathin ScAlN and are useful for investigating thickness scaling effects in ferroelectric ScAlN layers and devices.

[0038] A native oxide layer a few nanometers (5-10 nm) thick can easily form on the ScAlN surface after exposure to air. With thickness scaling (e.g., to thicknesses below 10 nm), the effect of the native oxide on ferroelectricity becomes more pronounced, making ferroelectricity difficult to achieve.

[0039] To eliminate or reduce the effects of native oxide, a 10 nm thick ITO layer is immediately or quickly deposited as a top electrode or other conductive layer after removal from the MBE chamber. The composition, thickness, and other aspects of the deposited layer may vary in other cases. For example, alternative or additional conductive layers (e.g., non-native passivation layers) may be used, including other non-native oxides and metals such as Al and Ti. The characteristics of the deposition procedure may also vary. For example, the conductive non-native passivation layer (or other conductive layer) may be deposited by any method such that the exposure of the ScAlN or other ferroelectric semiconductor layer to the environment between the non-sputter epitaxial growth procedure and the deposition of the conductive layer is limited to a time such that the native oxide layer disposed between the conductive layer and the ferroelectric semiconductor layer has a thickness of about 1 nm or less. In some cases, the exposure to the environment is limited to a period of less than 24 hours or less than 1 hour. The environment may or may not be air. For example, the environment may be established by or otherwise include a nitrogen-purged vessel.

[0040] In still other cases, deposition of a conductive non-native passivation layer or other conductive layer is performed in situ so that the ferroelectric semiconductor layer is not exposed to the ambient between the growth and deposition procedures. For example, the heterostructure may remain in the MBE growth chamber for deposition of the conductive layer. Thus, the formation of a native oxide on the ferroelectric semiconductor layer can be prevented.

[0041] Figure 2(f) shows an EDS element map of an example ITO / ScAlN / Mo capacitor. The map indicates that Sc and Al are uniformly incorporated along the growth direction, with the measured Sc content being approximately 0.3. Oxygen signals are observed on both the top surface of the ScAlN and the ITO region. By comparing the indium signal in the ITO region, the oxide layer on the top surface of the ScAlN is determined to be approximately 1 nm. This indicates that by shortening the exposure time in air, the native oxide layer that typically forms on the ScAlN surface is dramatically reduced to approximately 1 nm (previous reports have reported thicknesses of 5–10 nm). The formation of the ultrathin native oxide layer is consistent with the observation of lattice degradation in Figure 2(a). Except for the 1 nm native oxide layer, the underlying 5 nm thick ScAlN layer remains unoxidized and possesses a well-layered wurtzite lattice, enabling the investigation of ferroelectricity in such thin ScAlN. In other cases, the ITO layer can be replaced by in situ or ex situ deposition of other metal layers, such as Al or Ti, which can further minimize or reduce oxidation.

[0042] To investigate the ferroelectric properties of ScAlN thin films, we performed CV and PE loops and PUND measurements. Figure 3(a) shows the CV loops measured for the exemplary devices. Typical butterfly-shaped CV loops can be observed for each exemplary device, indicating that the films are ferroelectric. In all measurements, the loss tangent, tanδ, was less than 0.1 at zero bias but increased to less than 0.5 near the switching voltage due to increased leakage at high bias voltages. For leakage current compensation, a sequence of unipolar triangular voltage pulses was applied to examine and subtract the contribution of non-switching currents. For ScAlN films with thicknesses from 100 nm to 18 nm, saturated polarization was observed in both bias directions. For ScAlN films with thicknesses of 12 nm and 5 nm, saturated polarization was observed in the bias direction, likely due to increased leakage current associated with the asymmetric electrode configuration. To more precisely quantize the remnant polarization, voltage-dependent PUND measurements using triangular pulses were performed, and the results are shown in Figure 3(c). 100 μC / cm for ScAlN films of 12 nm or more 2A remanent polarization of more than 100 μC / cm was detected. In the 18 nm thick sample, there is an acceleration of the polarization value due to variations in growth or processing conditions. In contrast to the non-saturated partial polarization switching reported in approximately 10 nm ScAlN films deposited by sputtering, saturated polarization was also observed in 12 nm and 5 nm thick ScAlN films at room temperature. This strongly suggests an improvement in film quality achieved by MBE. The switchable polarization was 100 μC / cm for thick films. 2 From the above, in the case of 12 nm thick ScAlN, the 2 , and approximately 23 μC / cm for the 5 nm thick ScAlN example. 2 On the other hand, the coercive field increases monotonically with decreasing film thickness, as can be seen in the CV loops, especially for the 5 nm thick example. By measuring multiple instances of the device for each example, the ratio of the breakdown field to the coercive field, E BD / E C was found to decrease slightly with the scaling down of the film thickness, from about 1.35 to about 1.22 when scaling down from 100 nm to about 5 nm.

[0043] The switchable polarization and switching field are more clearly shown in Figures 4(a) and (b). For comparison, results from previous studies are plotted alongside. Overall, the coercive field increases monotonically with decreasing film thickness, while the remanent polarization decreases significantly when scaling down to below 20 nm. The evolution of the ferroelectric properties is elucidated in the context of changes in surface oxide and strain, as discussed below.

[0044] The driving force for the increase in the coercive field with thickness scaling down is described by the classical Janovec-Kay-Dunn (JKD) model, in which the coercive field of a ferroelectric is expressed as d, where d is the thickness of the ferroelectric film, as shown by the dotted line in Figure 4(b). 2 / 3It scales linearly with . This deviation suggests that the scaling behavior cannot be simply described by this domain nucleation-based model. To explain the sub-JKD scaling, depolarization field corrections based on the assumption of either a non-switching dead layer or a dielectric interfacial layer, or a finite shielding length of the electrodes, have been proposed. In the above example, a thin oxide layer of approximately 1 nm exists on top of the ScAlN thin film. The sub-JKD scaling behavior of the coercive field measured here is likely closely related to the surface oxide layer. However, it cannot explain the dramatic increase in the coercive field in the example with a 5 nm thick layer.

[0045] On the other hand, ScAlN thin films are deposited on Pt(111) or Mo(011) substrates, both of which have smaller in-plane lattice constants than ScAlN. Therefore, compressive stress is expected to accumulate in the ScAlN layer, especially in ultrathin epitaxially grown films. The compressive stress, associated with the JKD scaling behavior, can cause a significant increase in the coercive field. Using NEBD patterns, the in-plane and out-of-plane lattice constants of 5-nm-thick ScAlN with a 0.3 Sc content were measured to be 3.198 Å and 5.068 Å, respectively. This in-plane lattice constant is even smaller than that of thicker ScAlN films grown on Mo substrates with a 0.2 Sc content, indicating the presence of significant compressive stress. Furthermore, spontaneous polarization tends to decrease with compressive stress in ScAlN alloys. Therefore, reducing the thickness may result in a slight decrease in the switchable polarization in wurtzite ScAlN, considering the increased compressive stress in thinner ScAlN films grown on Mo. Therefore, it is concluded that the generation of the coercive field and remnant polarization is a combined effect of the surface oxide and compressive stress in the epilayer. Nevertheless, the above examples establish the feasibility of achieving ferroelectric switching in nitride ferroelectrics as thin as about 5 nm. The switching voltage approaches 2 V according to CV measurements, which is close to silicon CMOS logic circuit standards (e.g., about 1.5 V) and is useful for power-efficient applications. The switchable polarization is about 23 μC / cm. 2Although scaled down to 1000 sq. m, it is comparable to most conventional ferroelectrics of similar thickness, making it suitable for a variety of device applications.

[0046] The above shows a ferroelectric Sc ​​grown on a Mo substrate by molecular beam epitaxy. 0.3 Al 0.7 This example demonstrates the thickness scaling behavior of ScAlN films. Switchable ferroelectricity was confirmed in ScAlN films with thicknesses ranging from 100 nm to 5 nm using CV, PE, and PUND measurements. Scaling the ferroelectric layer down to 20 nm or less resulted in an increase in the coercive field and a significant decrease in the remanent polarization. Furthermore, in an example with a 5 nm thick ScAlN layer, the switching voltage was 2-3.8 V and the saturated remanent polarization was approximately 23 μC / cm. 2 The thickness scaling of MBE-grown ScAlN thin films is thus useful for compact, power-efficient devices and applications based on nitride ferroelectrics.

[0047] The disclosed heterostructures can be used in a variety of applications, including heterogeneous integration with III-N architectures and CMOS technologies. For example, the nitride-based ferroelectrics of the disclosed heterostructures can be integrated with a variety of other devices, systems, or applications, including various advanced computing applications.

[0048] FIG. 5 illustrates a device 500 having a heterostructure 502 with a ferroelectric semiconductor layer 504, according to one example. The ferroelectric semiconductor layer 504 can have a thickness as described herein. In this example, the device 500 is a two-terminal device. In some cases, the device 500 is configured or operated as a capacitor. The device 500 can include any number of alternative or additional layers or structures. For example, the device 500 can be integrated with any number of other devices.

[0049] Device 500 includes a substrate 506 and a heterostructure 502 supported by substrate 506. Substrate 506 may be composed of or include silicon. Additional or alternative substrate materials may be used, including, for example, sapphire, silicon carbide, bulk GaN, bulk AlN, GaN templates, and AlN templates. Substrate 506 may be a homogeneous or composite material.

[0050] The heterostructure 502 includes a template layer 508 and a ferroelectric semiconductor layer 504 supported by the template layer 508. The template layer 508 may be composed of a metal such as molybdenum, or a semiconductor such as GaN or silicon. As described herein, the ferroelectric semiconductor layer 504 is composed of or otherwise includes an alloy of a III-nitride material such as ScAlN. In some cases, the ferroelectric semiconductor layer 504 may have a (0001) orientation. The orientation may vary according to the epitaxial relationship between the template (e.g., metal) layer 508 and the ferroelectric semiconductor layer 504. The template (e.g., metal) layer 508 may be single crystalline or polycrystalline.

[0051] The alloy includes a group IIIB element, such as Sc. The alloy can include one or more alternative or additional group IIIB elements. In some cases, the group III nitride alloy is ScAlN. Alternative or additional group III nitride materials can be used, including alloys of group III nitrides with another group III element, such as Ga or In. Alternative or additional group IIIB elements can be used, including, for example, yttrium (Y) and lanthanum (La).

[0052] As shown in FIG. 5, the ferroelectric semiconductor layer 504 is in contact with a template layer 508 (e.g., a metal layer). In this example, the surface of the metal layer 508 in contact with the ferroelectric semiconductor layer 504 is oxide-free. In some cases, the surface of the metal layer 508 in contact with the ferroelectric semiconductor layer 504 is oriented in the (011) plane. The plane in contact with the semiconductor layer 504 may vary in other cases, for example, depending on the composition of the metal layer 508. For example, for each metal material, a plane that matches (e.g., best matches) the atomic arrangement of the (0001) plane of the wurtzite structure may be used. In the example of FIG. 1, the Mo(011) plane has a rectangular atomic arrangement, but rectangular atomic arrangements match well with the hexagonal lattice of the III-N(0001) plane. Therefore, the way the planes match may vary with other atomic arrangements. For example, the (111) plane may be in contact with the ferroelectric semiconductor layer 504 in a heterostructure having an Al, Ni, or Cu layer in contact with the semiconductor layer. Other metallic materials with a (011) plane conforming to the wurtzite structure may also be used, such as Fe.

[0053] The template (e.g., metal) layer 508 may be composed of or include Mo. As noted above, additional or alternative metals may be used, including, for example, Al, Ni, Cu, and Fe. In yet other cases, the template layer 508 may be composed of or include a semiconductor material such as GaN or silicon. The material composition of the template layer 508 may establish a lattice mismatch between the template layer and the ferroelectric semiconductor layer. This lattice mismatch may then be used to tailor or establish one or more properties or characteristics of the ferroelectric semiconductor layer 504. For example, the coercive field of the ferroelectric nitride layer is a function of the lattice mismatch between the template layer 508 and the ferroelectric semiconductor layer 504. In this manner, the coercive field may be modified (e.g., decreased or increased) according to the amount or degree of lattice mismatch between the template layer 508 and the grown ferroelectric nitride layer 504.

[0054] The device 500 includes one or more electrodes or contacts 510. In this example, the heterostructure 502 further includes a top or bottom contact 510 or other electrode in contact with the ferroelectric semiconductor layer 504. The contact 510 may be comprised of or otherwise include a conductive non-native passivation layer or other conductive layer, as described herein. For example, the contact 510 may be comprised of or otherwise include an ITO layer. The contact 510 may additionally or alternatively be comprised of or otherwise include one or more metal layers, such as Ti and Al.

[0055] In the example of Figure 5, the underlying metal layer 508 functions as the bottom or lower electrode. Additional or alternative contacts, electrodes, or other structures may be included. In one example of a capacitor, a 50 nm Ti / 100 nm Au / 50 nm Ti circular pad with a diameter of 50 μm was lithographically patterned on top of the ScAlN as the top electrode, while the underlying Mo layer was used as the bottom electrode. In other cases, any uncovered portions of the semiconductor layer can be etched away after deposition of the top electrode, for example, using a reactive ion etching (RIE) process, to separate each device.

[0056] 5, heterostructure 502 lacks a buffer layer between ferroelectric semiconductor layer 504 and metal layer 508. Device 500 therefore provides an example of buffer-free direct epitaxial hetero-integration between single-crystalline wurtzite phase ScAlN and a metal layer.

[0057] In this case, the metal layer 508 is in contact with the substrate 506. Alternatively, one or more layers or structures are disposed between the metal layer 508 and the substrate 506.

[0058] In some cases, the ferroelectric semiconductor layer 504 has an atomically smooth surface. The term "atomically smooth" may be used herein in connection with layers of a heterostructure to denote a layer having a surface roughness (e.g., root mean square, or RMS, roughness) of less than or on the order of 1 nm. In some cases, the RMS roughness of such an atomically smooth layer is less than 1% of the layer thickness. Surface roughness may vary according to growth conditions, parameters, and other aspects of the fabrication processes and / or other processes described and / or referenced herein.

[0059] FIG. 6 illustrates a method 600 for fabricating a heterostructure having a ferroelectric semiconductor layer (e.g., a single-crystalline wurtzite structure) of an alloy of III-nitride materials incorporating scandium and / or other IIIB elements, according to one example. As described herein, method 600 is configured so that the ferroelectric semiconductor layer can be grown on a metal template, substrate, or other underlayer. The heterostructure can form a device or part of a wide variety of devices that utilize ferroelectric behavior. Method 600 can be used to fabricate the example ScAlN films and layers described herein, or other ferroelectric semiconductor layers.

[0060] Method 600 may begin at act 602, in which a substrate is prepared and / or otherwise provided. In some cases, act 602 includes providing a silicon substrate in act 604. The silicon substrate may have a (111) orientation. The substrate may be patterned or otherwise treated to configure the substrate to reduce defect formation in subsequently grown layers of the heterostructure and / or otherwise improve material quality therein. Such treatment may also facilitate the formation of different regions of the heterostructure.

[0061] Alternative or additional substrate materials may be used, including, for example, sapphire, bulk GaN, bulk AlN, or other semiconductor materials. Still other materials may be used, including, for example, silicon carbide. In still other cases, metal substrates may be used. For example, the metal substrate may be composed of or otherwise include Al, Pt, and / or Mo.

[0062] The substrate may be cleaned in step 606. Optionally, a native or other oxide layer may be removed from the substrate surface in step 608. Oxide removal may include multiple steps including, for example, an etching step and an annealing step.

[0063] In other cases, additional or alternative processing may be performed, including, for example, doping or deposition procedures. Thus, the substrate may or may not have a uniform composition. The substrate may be a uniform or composite structure. Any number of layers or structures may be deposited on the substrate prior to the performance of the acts described below.

[0064] Method 600 may include act 610, in which one or more template or other layers (e.g., seed layers) are formed or provided. The template layer is supported by a substrate. In some cases, the template layer is in contact with the substrate. In other cases, one or more buffers or other layers or structures are disposed between the template layer and the substrate. As described herein, the template layer may be composed of, or in other cases, may include, a metal or semiconductor material.

[0065] 6, operation 610 includes operation 612, in which a template (e.g., metal) layer is deposited. A wide variety of deposition procedures can be used. In some cases, the metal layer is patterned in operation 614. Alternatively or additionally, operation 610 can include forming a seed layer (e.g., by epitaxial growth). As described herein, the seed layer can be composed of or otherwise include a III-nitride semiconductor, such as AlN or GaN.

[0066] Operation 610 may include deposition or other formation of one or more other metal layers or structures. For example, a bottom contact may be formed in operation 616. Operation 616 may be performed in parallel with (e.g., as part of) operation 612. The number and other characteristics of the metal layers or structures may vary depending on the configuration of the device (such as the number of terminals).

[0067] Method 600 includes operation 618, in which a surface treatment procedure is performed to remove oxide from the surface of the metal layer of the template layer. Optionally, operation 618 includes annealing the polycrystalline metal layer in a vacuum in operation 620. The annealing temperature can vary, for example, depending on the composition of the metal layer. For example, MoO3 has a relatively low melting point (795°C), in which case annealing above the melting point, e.g., about 900°C, can be used. Annealing can also improve the surface roughness of the metal layer. In one example involving a 10-minute anneal at 900°C, a smooth surface was observed on each domain, except for the domain boundaries. To achieve the above-described epitaxial relationship, a pre-anneal can be performed in the MBE growth chamber to remove native oxide (e.g., MoO3) and obtain a fresh, clean, atomically smooth Mo(011) surface. Furthermore, after the high-temperature anneal, the domain boundaries became more uniform, and misoriented clusters were significantly reduced. The oxide can be removed by additional or alternative methods to achieve a highly ordered, atomically smooth surface. For example, the oxide can be removed via an etching procedure using an acid solution such as, for example, hydrochloric acid (HCl) or buffered hydrofluoric acid (BHF).

[0068] In one example, a 120 nm thick Mo layer was grown on a Si(111) substrate. The Mo template was cleaned with acetone, methanol, and deionized water before being loaded into the MBE system used to grow the single-crystalline semiconductor layer. The Mo template was then degassed for 2 hours at 200 °C and 600 °C in the MBE load-lock and preparation chambers, respectively. In the growth chamber, the Mo template was annealed at 900 °C for 10 minutes before starting ScAlN growth; however, the temperature and other parameters may vary in other cases (e.g., related to composition).

[0069] After performing the surface treatment procedure, a non-sputter epitaxial growth procedure is performed in step 622 to form a monocrystalline semiconductor layer supported on and in contact with the polycrystalline metal layer. As described above, the monocrystalline semiconductor layer is composed of or otherwise includes an alloy of Group III-nitride materials. The non-sputter epitaxial growth procedure is configured to incorporate a Group IIIB element into the alloy of Group III-nitride materials.

[0070] The III-nitride alloy layer may or may not be ferroelectric. As described herein, the III-nitride alloy layer has a wurtzite structure. For example, the III-nitride material may be AlN. Additional or alternative III-nitride materials may be used, including, for example, gallium nitride (GaN), indium nitride (InN), and alloys thereof. As also described herein, the epitaxial growth procedure is configured to incorporate scandium and / or another group IIIB element into the III-nitride material alloy. Thus, the alloy may be, for example, ScAlN. In some cases, operation 622 includes operation 624, in which an MBE procedure is performed. In other cases, an MOCVD or other non-sputter epitaxial growth procedure is performed in operation 626.

[0071] The surface treatment of operation 618 may be performed prior to (e.g., in preparation for) performing an epitaxial growth procedure in which the wurtzite structure is formed. Thus, the wurtzite structure may be formed on the metal layer. Thus, the metal layer may act as a template for the wurtzite structure and / or other elements of the heterostructure. In some cases, operation 612 may include operation 628, in which the monocrystalline semiconductor layer is grown in the chamber in which the annealing procedure for the surface treatment of operation 618 is performed. As a result, the substrate can remain in the epitaxial growth chamber, e.g., is not removed therefrom, between forming the metal layer and growing the monocrystalline semiconductor layer.

[0072] Single-crystal semiconductor layers can be grown on metal layers using a wide growth window, for example, in some cases the growth window may be similar to that for ScAlN grown on GaN, where the lower end of the growth temperature window is compatible with CMOS fabrication processes.

[0073] The growth temperature may be at a level such that the wurtzite structure exhibits a breakdown field strength greater than the ferroelectric coercive field strength of the wurtzite structure, and in this manner, ferroelectric switching and other ferroelectric behavior may be achieved.

[0074] The growth temperature may be lower than expected for III-nitride materials. In some instances, the growth temperature may be significantly lower than the temperatures at which III-nitride materials are typically grown. For example, the growth temperature may be such that attempts to grow structures made of III-nitride materials (i.e., without scandium) at the growth temperature may be unwarranted. The resulting structures, while useful, are of such low quality (e.g., too many defects). Nevertheless, growth of single-crystalline scandium-containing alloys (e.g., single-crystalline layers of the alloy) may be achieved at the growth temperature. For example, in some cases, ScAlN alloys can be epitaxially grown at a growth temperature of approximately 650°C, even though the corresponding (scandium-free) III-nitride material, AlN, is conventionally grown at much higher temperatures, e.g., approximately 1000°C. Conversely, attempts to grow AlN at temperatures of approximately 650°C or lower result in such low-quality structures. In contrast, epitaxially grown ScAlN layers grown at these low temperatures exhibit unexpectedly high quality and good electrical properties.

[0075] Growth of ScAlN layers at typical AlN growth temperatures (and other temperatures above the upper limit) unexpectedly results in the formation of dislocations and / or other leakage paths in the ScAlN layer, which cause the breakdown field strength level of the ScAlN layer to be too low (e.g., below the ferroelectric coercive field strength level), and therefore the layer does not exhibit ferroelectric behavior.

[0076] In some cases, the growth temperature may be about 650°C or less. The growth temperature may correspond to the temperature measured by a thermocouple in the growth chamber. The growth temperature at the epitaxial surface may be slightly different. Therefore, the growth temperature is approximated by the temperature measurement at the thermocouple.

[0077] The upper limit of the growth temperature range may vary depending on the alloy and / or epitaxial growth technique. For example, in other cases, the upper limit of the growth temperature may be higher, such as about 700°C or about 750°C. In still other cases, the upper limit may be lower, such as about 550°C or about 600°C.

[0078] At each level within the suitable growth temperature range, the resulting wurtzite structure is single crystalline. This level of single crystal is unattainable, for example, by sputtering-based procedures for forming ScAlN layers. Such procedures can only produce structures with X-ray diffraction rocking curve linewidths of a few degrees at best. In contrast, structures grown by the disclosed method exhibit X-ray diffraction rocking curve linewidths on the order of hundreds of arc-seconds or less, far below an order of magnitude. In this way, leakage current paths are minimized or sufficiently reduced so that the resulting wurtzite structure has an appropriately high breakdown electric field strength level, for example, well above the ferroelectric coercive electric field strength.

[0079] Additional or alternative differences in crystalline quality can be used to distinguish between single-crystal and polycrystalline structures. As used herein, the term "polycrystalline" refers to a structure having multiple domains with in-plane rotation. As used herein, the term "single-crystal" refers to a structure having unique domains without in-plane rotation, as shown, for example, by an X-ray φ scan with only one set of diffraction peaks.

[0080] When comparing the wurtzite structure of layers grown by MBE or other non-sputtering techniques (such as MOCVD or HVPE) with that of sputtering deposition, the microstructure of the former technique is more uniform, with a highly ordered stacking sequence of atoms. In sputter-deposited layers, domains with cubic phase or in-plane misorientation are readily observed. The presence of these misaligned domains inhibits complete polarization switching and results in rapid polarization loss during fatigue testing. With regard to phase purity, the high degree of crystalline orientation of layers grown by MBE or other non-sputtering techniques exhibits more repeatable ferroelectric switching, which is useful in many device applications.

[0081] In some cases, the wurtzite structure of the single crystal semiconductor layer is metal-polar. In other cases, the single crystal semiconductor may be nitrogen-polar (N-polar).

[0082] In some cases, the epitaxial growth procedure is performed under nitrogen-rich conditions. For example, a nitrogen-to-metal flux ratio may be set in step 630 where the nitrogen flow is controlled. In some cases, the unbalanced flux ratio may be set to very or extremely nitrogen (N)-rich conditions, such as an N-to-metal flux ratio of 2 to 1 or greater.

[0083] Controlling the flux ratio between the metal source and the nitrogen source can be useful for improving the material quality of ScAlN or other III-nitride alloy layers. As described herein, N-rich growth conditions can be useful for avoiding Sc-Al intermetallic compounds, ScAlN perovskite phase formation, and / or other defects associated with ScAlN growth.

[0084] In one example, ScAlN films and GaN / ScAlN heterostructures were grown using a Veeco GENxpor MBE system equipped with a dual-filament SUMO Knudsen cell for Al (6N5 purity) and Ga sources (7N purity), a high-temperature Knudsen cell for Sc source (5N purity), and a Veeco Unibulb radio frequency (RF) plasma source. The N source was operated with a N gas (6N purity) flow rate of 0.35 sccm, and 350 W of RF power was used for the metal-rich GaN layer, corresponding to a growth rate of 240 nm / h. N-rich conditions were adopted to maintain the single wz-phase crystal structure of ScAlN. Meanwhile, for the GaN / ScAlN heterostructures, GaN was grown under metal-rich conditions, while Si (electron concentration 1×10 18 cm -3 The thicknesses of the ScAlN and GaN were approximately 100 and 20 nm, respectively. The Sc content was approximately 20%.

[0085] Method 600 includes act 632 of depositing a conductive layer (e.g., a conductive non-native passivation layer) adjacent to a side of the ferroelectric layer opposite the metal layer. As described herein, deposition of the conductive layer may be performed such that exposure of the ferroelectric semiconductor layer to the ambient between the non-sputter epitaxial growth procedure and deposition of the conductive layer is limited to a time such that a native oxide layer disposed between the conductive layer and the ferroelectric semiconductor layer has a thickness of about 1 nm or less. Accordingly, act 632 may include act 634 to limit or prevent exposure to the ambient. In some cases, act 634 may be configured to limit the period of time during which the ferroelectric semiconductor layer is exposed to the ambient. For example, the period may be less than 24 hours or less than 1 hour. Other periods may also be used. In other cases, exposure to the ambient may be prevented by depositing a conductive non-native passivation layer (or other conductive layer) before the ferroelectric semiconductor layer is removed from the chamber in which it is grown.

[0086] The atmosphere may be controlled, for example, in some cases the atmosphere is established by or otherwise includes a nitrogen purged vessel.

[0087] Operation 632 may include depositing a non-native oxide layer, such as ITO, in operation 636. Additional or alternative materials may be deposited, including other non-native oxide materials and metals, such as, for example, Al and Ti.

[0088] In some cases, the single-crystalline semiconductor layer may then be annealed in operation 638. The anneal may be performed at a temperature higher than the growth temperature. In some cases, the annealing temperature ranges from about 700°C to about 1500°C. Example films prepared by such annealing exhibited stable polarization switching with further reduced leakage current compared to unannealed films. Film or device uniformity was also improved by annealing, thereby further improving the polarization switching behavior of ferroelectric Sc-III-N alloys. The underlying mechanism for the improved performance and uniformity due to annealing is attributed to a reduction in threading dislocation and defect densities, which typically act as electrical leakage paths. The utility of such post-growth annealing has been realized despite past concerns that high processing temperatures could lead to loss of ferroelectric properties.

[0089] Such post-growth high temperature annealing of ScAlN can be performed in situ in the same growth chamber (e.g., the same MBE chamber) in step 640. In other cases, the annealing is performed in situ in a chamber dedicated to the annealing procedure.

[0090] The annealing process can be performed under high vacuum in step 642 (e.g., in situ in the growth chamber). In other cases, the annealing can be performed under either nitrogen plasma exposure or nitrogen gas flow in step 644.

[0091] The annealing procedure described above can be performed in connection with films grown under any of the growth conditions described above. For example, the annealing procedure can be performed after growth at a growth temperature below about 650°C under slightly or moderately N-rich conditions. The annealing procedure can also be performed after growth under an unbalanced flux ratio (e.g., N-rich or extremely N-rich conditions) at a growth temperature above about 650°C.

[0092] Method 600 may include step 646, in which one or more layers (e.g., semiconductor layers) are formed after growth of the wurtzite structure. For example, one or more III-nitride (e.g., GaN or AlGaN) or other semiconductor layers may be epitaxially grown in step 648. Step 648 may be performed in the same epitaxial growth chamber used to grow the wurtzite structure. As a result, the substrate (and heterostructure) is not removed from the epitaxial growth chamber between performing steps 622 and 648.

[0093] Alternatively or additionally, step 640 includes step 650, in which one or more metal or other conductive layers or structures are formed. For example, a metal layer can be deposited. The layer or structure can be deposited or otherwise formed. In some cases, the conductive structure is configured as a top or top contact (or a component thereof). For example, the conductive structure can be a gate.

[0094] In some cases, method 600 includes an act 652 of removing the substrate. The substrate may be partially or completely removed. Once the substrate is completely removed, the heterostructure is freestanding. In some cases, operation 652 includes performing an etching procedure, such as a wet or dry etching procedure. Alternatively or additionally, the substrate is mechanically removed. Thus, the manner in which the substrate is removed may vary accordingly.

[0095] Method 600 may include fewer, additional, or alternative operations. For example, one or more operations may be directed to forming other structures or regions of a device, including a heterostructure. In the example of a transistor device, the regions may correspond to source and drain regions. The nature of the regions or structures may vary according to the nature of the device. In another example, method 600 does not include operation 610, in which a buffer layer is grown or otherwise formed.

[0096] The order of operations in method 600 may differ from the example shown in Figure 6. For example, the contacts and / or other structures formed in operation 610 may be performed after the growth of the ferroelectric layer.

[0097] Many different types of devices can be fabricated using the method 600 of Figure 6 and / or other methods for fabricating heterostructures with wurtzite structures of alloys of III-nitride materials incorporating scandium. For example, ferroelectric ScAlN or other alloys of III-nitride materials may be useful in various types of nonvolatile memory devices (e.g., FeRAM, FeFET, FTJ, and FeSFET devices), various types of reconfigurable electronic and other devices (e.g., Fe-HEMT, Fe-capacitor, SAW devices), various types of photodetection, photovoltaic, and optoelectronic devices (e.g., self-powered photodetectors and solar cell devices), and various homojunction devices (e.g., devices using laterally distributed charge plates to tune the Fermi levels of adjacent layers). Still other types of devices can be fabricated, including, for example, Fe-based thin film bulk acoustic wave resonator (FBAR) devices.

[0098] The disclosed heterostructures can be incorporated into a wide variety of devices, in which case conductive non-native passivation layers (or other conductive layers) can flank the ferroelectric layer, as described above and shown, for example, in the example of Figure 1. A number of examples are described below.

[0099] FIG. 7 illustrates an example FeFET memory device 700. A ferroelectric ScAlN layer 702 is disposed between a gate electrode 704 and source-drain conduction regions 706. The ferroelectric layer 702 provides a reversible electrical state for the transistor in device 700. A large remanent field polarization in the ferroelectric ScAlN layer 702 retains the transistor state (e.g., on or off) in the absence of electrical bias, forming a single-transistor nonvolatile memory. In one example, the bulk and / or other semiconductor channel layers are composed of or include GaN or silicon, or two-dimensional materials such as MoS2 or graphene. In each case, the FeFET memory device utilizes, for example, ferroelectric ScAlN as the gate dielectric and barrier. 1-x The device may include a heterostructure comprising N or other alloys of III-nitride materials and one or more layers of a III-nitride semiconductor, such as AlN. A substrate 708 supporting these layers and structures of the device may be comprised of or include, for example, GaN or silicon. A control terminal or gate 704 may be disposed below the III-nitride semiconductor layer 702 as shown. As described herein, the gate 704 may be comprised of or include a metal, such as Mo.

[0100] 8 illustrates a combined FET structure 800 configured as a memory cell according to one example. During switching of the remanent polarization state in the ferroelectric (e.g., ScAlN) layer 802, a current pulse is generated, indicating binary information stored within the cell.

[0101] 9 shows an example FTJ memory device 900. In this example, an epitaxially grown ferroelectric layer 902 (e.g., ScAlN layer) is disposed between metal layers 904, 906 (e.g., nickel and aluminum layers). The ScAlN or other alloy layer 902 provides the ferroelectric and adjusts the on / off current / resistance ratio as memorizer readout.

[0102] FIG. 10 illustrates a device 1000 having a heterostructure according to an example. The device 1000 can be configured or used as a filter, a resonator, or other acoustic device. Such devices may be useful in broadband communications (e.g., 5G, 6G) contexts and other applications. In this example, the heterostructure of the device is free-standing. The heterostructure may be free-standing in the sense that a growth or other sacrificial substrate has been removed. The free-standing heterostructure may then be mounted on or supported by another structure, such as a circuit board.

[0103] In the example of FIG. 10 , the heterostructure includes a monocrystalline III-nitride alloy layer 1002 disposed between and in contact with two metal layers 1004 and 1006. The composition, configuration, and other properties of layers 1004 and 1006 may vary as described herein. For example, metal layers 1004 and 1006 may be composed of or include Ni, Al, Mo, or other metals. Metal layers 1004 and 1006 may or may not be composed of the same metal material. In other examples, monocrystalline III-nitride layer 1002 is in contact with only a single metal layer.

[0104] The heterostructures of the above-described devices may include any number of layers, structures, and / or components depending on the functionality of the device. For example, the heterostructure may or may not include a seed layer disposed between the metal layer and the monocrystalline III-nitride alloy layer.

[0105] FIG. 11(A) compares heterostructures 1100 and 1102 with and without a seed layer for two exemplary metal-insulator-metal capacitors. Each heterostructure 1100 and 1102 is supported by a substrate, such as a silicon substrate. Heterostructure 1100 has a single-crystal III-nitride alloy layer 1104 (e.g., an ultrathin ScAlN film as described herein) supported by and in contact with a metal template layer 1106 (e.g., a Mo layer). In contrast, heterostructure 1102 has a seed layer 1108 disposed between single-crystal III-nitride alloy layer 1110 and metal layer 1112. Seed layer 1108 and metal layer 1112 can together establish a template (or template layer) for III-nitride alloy layer 1110. In such cases, the template layer may be or include multiple layers, e.g., a composite layer or structure. Alternatively, the template layer is formed solely by seed layer 1108. In this example, seed layer 1108 is composed of or includes AlN. Additional or alternative materials may be used, including, for example, other III-nitride materials.

[0106] The seed layer 1108 may be configured to reduce the leakage current of the III-nitride alloy layer 1110. The effect of the seed layer 1108 was investigated. In these two exemplary heterostructures 1100 and 1102, the III-nitride alloy layers 1104 and 1110 have thicknesses of approximately 6 nm. In the heterostructure 1110, the AlN seed layer 1108 has a thickness of approximately 4 nm. Using standard photolithography, the two capacitor heterostructures 1100 and 1102 were fabricated and their electrical properties were characterized. As shown in Figure 11(B), the heterostructure 1102 with the seed layer 1108 exhibited a nearly ten-fold reduction in leakage current. Furthermore, as shown in Figure 11(C), the switchable polarization, measured by polarization-electric field loops, was also significantly improved. These results demonstrate a significant reduction in leakage current, which may be useful in connection with various nitride-based ferroelectric devices and device applications.

[0107] In other examples, substrates other than silicon substrates are used, for example, the substrate may be composed of or may include SiC or sapphire.

[0108] As mentioned above, we have developed ferroelectric ScAlN (e.g., Sc 0.3 Al 0.7 The thickness scaling behavior of ScAlN films is described and examples of heterostructures utilizing them are presented. Switchable ferroelectricity was confirmed in ScAlN films with thicknesses ranging from 100 nm to 5 nm. Scaling the ferroelectric layer down to 20 nm or less showed an increase in the coercive field and a significant decrease in the remnant polarization. In particular, examples with 5 nm thick ScAlN layers showed switching voltages of 2-3.8 V and saturated remnant polarizations of approximately 23 μC / cm. 2 X-ray diffraction and transmission electron microscopy showed that the increase in the coercive field and the decrease in the switchable polarization are closely related to the surface oxidation and strain state of the ultrathin ScAlN films. The thickness-scaling properties of ScAlN thin films may be useful in a variety of devices based on nitride ferroelectrics, including compact and power-efficient devices and applications. Furthermore, the disclosed devices and methods may be useful in integrating III-N architectures with various fabrication technologies, including CMOS technology, and in many applications, including ferroelectric nitride memristors in neuromorphic computing.

[0109] The term "about" is used herein to include deviations from a particular value that would be understood by one of ordinary skill in the art to be substantially the same as the particular value, e.g., because there is no appreciable, detectable, or otherwise effective difference in the operation, results, properties, or other aspects of the disclosed methods and devices.

[0110] The present disclosure has been described with reference to specific examples that are intended to be illustrative only and not limiting of the disclosure. Modifications, additions, and / or deletions may be made to the examples without departing from the spirit and scope of the disclosure.

[0111] The above description has been given for clarity of understanding only, and no unnecessary limitations should be understood therefrom.

Claims

1. the template layer; and a ferroelectric semiconductor layer supported by the template layer, the ferroelectric semiconductor layer being single crystal; the ferroelectric semiconductor layer comprises an alloy of Group III nitride materials; the alloy comprises a Group IIIB element; the ferroelectric semiconductor layer is in contact with the template layer; The ferroelectric semiconductor layer has a thickness of less than 100 nm.

2. 10. The heterostructure of claim 1, further comprising a conductive non-native passivation layer adjacent one of two sides of said ferroelectric semiconductor layer opposite said template layer.

3. an oxide layer disposed between the conductive non-native passivation layer and the ferroelectric semiconductor layer; The heterostructure of claim 2 , wherein the oxide layer has a thickness of about 1 nm or less.

4. The heterostructure of claim 2 , wherein said conductive non-native passivation layer comprises a metallic material.

5. The heterostructure of claim 4 , wherein the metallic material comprises Al.

6. The heterostructure of claim 4 , wherein the metallic material comprises Ti.

7. 10. The heterostructure of claim 1, further comprising a non-native oxide layer adjacent one of two sides of said ferroelectric semiconductor layer opposite said template layer.

8. The heterostructure of claim 7 , wherein said non-native oxide layer comprises indium tin oxide (ITO).

9. 10. The heterostructure of claim 1, wherein said ferroelectric semiconductor layer has a thickness of about 30 nm or less.

10. 10. The heterostructure of claim 1, wherein said ferroelectric semiconductor layer has a thickness of about 18 nm or less.

11. 10. The heterostructure of claim 1, wherein said ferroelectric semiconductor layer has a thickness of about 10 nm or less.

12. 10. The heterostructure of claim 1, wherein said ferroelectric semiconductor layer has a thickness of about 5 nm or less.

13. the ferroelectric semiconductor layer has a wurtzite structure; a (0001) plane of the wurtzite structure contacting the template layer; 2. The heterostructure of claim 1, wherein a surface of the template layer in contact with the single-crystal semiconductor layer conforms to the atomic arrangement of the (0001) plane of the wurtzite structure.

14. The heterostructure of claim 1 , wherein the surface of the template layer is oriented in the (011) plane.

15. The heterostructure of claim 1 , wherein the template layer comprises a metal.

16. The heterostructure of claim 1 , wherein the surface of the template layer is oriented in the (111) plane.

17. The heterostructure of claim 1 wherein said Group IIIB element is scandium.

18. The heterostructure of claim 1 , wherein the alloy of III-nitride materials comprises AlN.

19. The heterostructure of claim 1 , wherein the template layer comprises a III-nitride semiconductor layer.

20. A template layer; a ferroelectric semiconductor layer supported by the template layer; a conductive layer adjacent to one of the two side surfaces of the ferroelectric semiconductor layer opposite to the template layer; the ferroelectric semiconductor layer comprises an alloy of Group III nitride materials; the alloy comprises a Group IIIB element; the ferroelectric semiconductor layer is in contact with the template layer; The heterostructure wherein the ferroelectric semiconductor layer has a native oxide layer on the side thereof having a thickness of about 1 nm or less.

21. 21. The heterostructure of claim 20, wherein the conductive layer comprises a metallic material.

22. 21. The heterostructure of claim 20, wherein said conductive layer comprises a non-native oxide layer.

23. 21. The heterostructure of claim 20, wherein said ferroelectric semiconductor layer has a thickness of about 10 nm or less.

24. 1. A method for forming a heterostructure, comprising: providing a heterostructure template layer supported by a substrate; performing a surface treatment procedure to remove oxides from the surface of the template layer; and after performing the surface treatment procedure, performing a non-sputter epitaxial growth procedure to form a ferroelectric semiconductor layer of the heterostructure, the ferroelectric semiconductor layer being supported by and in contact with the template layer; The method further comprises depositing a conductive layer adjacent a side of the ferroelectric semiconductor layer opposite the template layer; the ferroelectric semiconductor layer comprises an alloy of Group III nitride materials; the non-sputtered epitaxial growth procedure is configured to incorporate a Group IIIB element into an alloy of Group III nitride materials; 10. A method for forming a heterostructure, wherein depositing the conductive layer is performed such that exposure of the ferroelectric semiconductor layer to the ambient between the non-sputtered epitaxial growth procedure and the deposition of the conductive layer is limited to a time such that a native oxide layer disposed between the conductive layer and the ferroelectric semiconductor layer has a thickness of about 1 nm or less.

25. 25. The method of claim 24, wherein the environment comprises a nitrogen-purged vessel.

26. 25. The method of claim 24, wherein depositing the conductive layer includes limiting the ambient exposure to less than about 24 hours.

27. 25. The method of claim 24, wherein depositing the conductive layer includes limiting the ambient exposure to less than about 1 hour.

28. 25. The method of claim 24, wherein depositing the conductive layer comprises depositing a non-native oxide layer.

29. 25. The method of claim 24, wherein depositing the conductive layer comprises depositing a metal layer.

30. 25. The method of claim 24, wherein the non-sputter epitaxial growth procedure is configured such that the ferroelectric semiconductor layer has a thickness of about 10 nm or less.

31. 25. The method of claim 24, wherein performing the surface treatment procedure comprises annealing the template layer in a vacuum.

32. 25. The method of claim 24, wherein the non-sputter epitaxial growth procedure is carried out under nitrogen-rich conditions.

33. 25. The method of claim 24, wherein providing the template layer comprises growing a seed layer.

34. A template layer; a ferroelectric semiconductor layer supported by the template layer and being single crystal; the ferroelectric semiconductor layer comprises an alloy of Group III nitride materials; the alloy comprises a Group IIIB element; the ferroelectric semiconductor layer is in contact with the template layer; A heterostructure wherein the ferroelectric semiconductor layer has a thickness of less than 10 nm.

35. A template layer; a ferroelectric semiconductor layer supported by the template layer and being single crystal; the ferroelectric semiconductor layer comprises an alloy of Group III nitride materials; the alloy comprises a Group IIIB element; the ferroelectric semiconductor layer has a thickness of less than 100 nm; A heterostructure wherein the ferroelectric semiconductor layer is in contact with the template layer such that a coercive field of the ferroelectric semiconductor layer is a function of a lattice mismatch between the template layer and the ferroelectric semiconductor layer.

36. 1. A method for forming a heterostructure, comprising: providing a template layer, the heterostructure supported by a substrate; performing a surface treatment procedure to remove oxides from the surface of the template layer; and after performing the surface treatment procedure, performing a non-sputter epitaxial growth procedure to form a ferroelectric semiconductor layer of the heterostructure, the ferroelectric semiconductor layer being supported by and in contact with the template layer; The method further comprises depositing a conductive layer adjacent a side of the ferroelectric semiconductor layer opposite the template layer; the ferroelectric semiconductor layer comprises an alloy of Group III nitride materials; the non-sputtered epitaxial growth procedure is configured to incorporate a Group IIIB element into an alloy of Group III nitride materials; A method for forming a heterostructure, wherein the conductive layer is deposited in situ such that the ferroelectric semiconductor layer is not exposed to the atmosphere between the non-sputter epitaxial growth procedure and the deposition of the conductive layer.

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