Reactive Matched and Distributed Power Amplifier Topologies

Abstract

The power amplifier has multiple stages, with one stage including a non-uniform distributed power amplifier circuit and the electrically subsequent stage including a reactive matching power amplifier circuit. There is an intermediate impedance between the distributed stage and the reactive matching stage that is not 50 ohms. The ratio of the perimeter between the subsequent reactive matching stage and the previous distributed stage is 2:1 or less.

Description

[Technical Field]

[0001]

[0001] The present disclosure relates generally to power amplifiers, and more particularly to power amplifier topologies. [Background technology]

[0002]

[0002] Power amplifier monolithic microwave integrated circuits (MMICs) are important components in many electronic systems, such as synthetic aperture radar (SAR), electronic warfare, and security communications, among other electronic systems. In power amplifiers, the trade-off between output power, efficiency, and bandwidth is a challenge in achieving the best possible performance. Today, there are at least two types of power amplifier topologies: reactively matched power amplifiers (RMPAs) and nonuniform distributed power amplifiers (NDPAs).

[0003]

[0003] Reactive matched power amplifiers have good output power and efficiency but suffer from the drawback of limited bandwidth, whereas distributed power amplifiers have good output power and bandwidth but suffer from low efficiency.

[0004] One conventional power amplifier is a semi-reactive matched amplifier (SRMA) with an NDPA driver stage with a center input and two outputs on the drain line driving a reactive matched output stage. This power amplifier has a mid-impedance of 30 ohms, a stage ratio of 1.44:1, and is biased at 30 V, 100 mA / mm.

[0005] Another previous power amplifier was similar to this one, but increased all FET sizes (same stage ratio) and added a third stage due to the low gain from increasing finger length for higher output power. This amplifier was biased at 30 V, 150 mA / mm.

[0006] Another prior art power amplifier provides the use of one distributed power amplifier stage to drive two reactively matched power amplifier stages, all of which have stage ratios of 2:1 or greater. This utilizes a 50 ohm intermediate impedance, but does not teach the use of an intermediate impedance other than 50 ohms. Summary of the Invention

[0007]

[0007] In many cases, the desired bandwidth for a power amplifier lies between these two power amplifier topologies (i.e., between the bandwidth provided by a reactive-matched power amplifier and the bandwidth provided by a non-uniform distributed power amplifier). Therefore, the present disclosure provides a solution for using a combination of two power amplifier topologies (i.e., a combined reactive-matched power amplifier and a non-uniform distributed power amplifier) ​​that allows the power amplifier of the present disclosure to achieve optimal or sufficient output power with a bandwidth and efficiency that is intermediate between the extremes of the two topologies used individually (without mixing). For example, while neither the non-uniform distributed power amplifier nor the reactive-matched power amplifier is optimal for the 30-40 GHz bandwidth, a combination of the two power amplifier topologies (i.e., a combined reactive-matched power amplifier and a non-uniform distributed power amplifier) ​​is advantageous.

[0008] In one exemplary embodiment, there are two aspects of the power amplifier topology of the present disclosure that provide improved performance: (i) using a non-50 ohm intermediate impedance between a non-uniform distributed amplifier stage and a reactive matched amplifier stage; and (ii) maintaining a periphery ratio between an adjacent non-uniform distributed amplifier stage and a subsequent reactive matching stage, where the periphery ratio of the subsequent reactive matching stage to the adjacent non-uniform distributed amplifier stage is 2:1 or less. The non-50 ohm intermediate impedance can be in the range of 1 ohm to 40 ohms, such as 28 ohms or 30 ohms. Additionally, the non-50 ohm intermediate impedance can be in the range of 60 ohms to 100 ohms, such as 75 ohms.

[0009] Another exemplary embodiment of the present disclosure provides a three-stage balanced reactively matched power amplifier (RMPA) / non-uniformly distributed power amplifier (NDPA) in a 28-40 GHz bandwidth with 20 dB small signal gain and 80 W DC power consumption. This or other exemplary embodiments utilize or include, among other features, a GaN 0.18 um NFP 2 mil on-axis N+ process, a three-stage design with a first stage including a four-cell 4×75 um NDPA, a second stage reactive match, and a third stage reactive match, and a drive ratio of 1.5:2:4, with each stage having half the PA perimeter, resulting in four 16×50 um unit cells used in the output stage, two 16×50 um unit cells used in the second stage, and a 4×4×75 um NDPA used in the first stage.

[0010] In another aspect, exemplary embodiments of the present disclosure may provide a reactive-matched distributed amplifier circuit topology that combines both reactive-matched and distributed amplifier stages to achieve efficiency and bandwidth intermediate between those achieved by the two topologies themselves. The first amplifier stage should be distributed, and the subsequent or final amplifier stage should be reactive-matched. Any number of stages of each topology may be used. At the interface between the final distributed stage and the first reactive matching stage, a real impedance other than 50 ohms may be selected for matching. Also, at this interface, the perimeter ratio between the reactive matching stage and the distributed stage should be less than 2:1 for optimal performance and to avoid premature compression issues at high temperatures. This topology may also be balanced by using Lange couplers or any other 90-degree hybrid couplers at the input and output. Because the previous distributed stage has good input return loss, a hybrid coupler may be inserted at the interface between the final distributed stage and the first reactive matching stage.

[0011] In one aspect, an exemplary embodiment of the present disclosure may provide a power amplifier, the power amplifier including a first stage comprising a distributed power amplifier circuit, a second stage electrically operating after the first stage, the second stage comprising a reactive matched power amplifier circuit, an intermediate impedance interface between the first stage and the second stage, wherein the intermediate impedance interface has an intermediate impedance other than 50 ohms, and a perimeter ratio between the second stage and the first stage of 2:1 or less. This exemplary embodiment or another exemplary embodiment may further provide that the first stage comprises at least four unit cells in the distributed power amplifier circuit. This exemplary embodiment or another exemplary embodiment may further provide that the second stage comprises at least two unit cells in the reactive matched power amplifier circuit. This exemplary embodiment or another exemplary embodiment may further provide that a third stage electrically operating after the second stage, the third stage comprising a reactive matched power amplifier circuit. This exemplary embodiment or another exemplary embodiment may further provide that the perimeter ratio of the first stage to the second stage to the third stage increases in the order of the first stage, the second stage, and the third stage. This exemplary embodiment or another exemplary embodiment may further provide that the perimeter ratio of the first stage to the second stage to the third stage is 1.5:2:4. This exemplary embodiment or another exemplary embodiment may further provide that the third stage comprises at least four unit cells within the third-stage reactive matched power amplifier circuit. This exemplary embodiment or another exemplary embodiment may further provide an operating bandwidth in the range of 28 to 40 GHz. This exemplary embodiment or another exemplary embodiment may further provide that the input comprises a first hybrid coupler, wherein the input operates electrically before the first stage, and the output comprises a second hybrid coupler, wherein the output operates electrically after the second stage.

[0012] In yet another aspect, another exemplary embodiment of the present disclosure may provide a method for a power amplifier, the method comprising: transmitting a signal to be amplified to a first stage of the power amplifier, wherein the first stage includes a distributed power amplifier circuit, and amplifying the signal in the first stage; transmitting the signal to a second stage via an intermediate impedance interface between the first stage and a second stage, wherein the second stage includes a reactive matched power amplifier circuit, and amplifying the signal in the second stage; and maintaining a perimeter ratio of the second stage to the first stage of 2:1 or less. This exemplary embodiment or another exemplary embodiment may further include transmitting the signal to a third stage electrically operating after the second stage, wherein the third stage includes a reactive matched power amplifier circuit, and amplifying the signal in the third stage. This or another exemplary embodiment may further provide that a circumference ratio between the first stage, the second stage, and the third stage increases in the order of the first stage, the second stage, and the third stage. The circumference ratio between the first stage, the second stage, and the third stage is 1.5:2:4. This or another exemplary embodiment may further include maintaining the intermediate impedance interface at an intermediate impedance other than 50 ohms.

[0013]

[0013] Exemplary embodiments of the present disclosure are set forth in the following description, shown in the drawings, and particularly and distinctly pointed out and described in the appended claims. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a schematic block diagram of a power amplifier according to a first embodiment of the present disclosure. [Figure 2]

[0015] FIG. 2 is a diagram illustrating the topology of the power amplifier of the first embodiment. [Figure 3A-3C]

[0016] FIG. 3A is a diagram illustrating the topology of a hybrid coupler in a power amplifier according to a first embodiment.

[0017] FIG. 3B is a diagram illustrating the topology of the first and second stages comprising a distributed power amplifier circuit in the power amplifier of the first embodiment.

[0018] FIG. 3C is a diagram illustrating a third stage topology including a reactive matched power amplifier circuit in the power amplifier of the first embodiment. [Figure 4]

[0019] FIG. 4 is a table showing effective thermal resistances for an exemplary power amplifier of the present disclosure. [Figure 5]

[0020] FIG. 5 is a schematic block diagram of a power amplifier according to a second embodiment of the present disclosure. [Figure 6]

[0021] FIG. 6 is a diagram illustrating the topology of the power amplifier of the second embodiment. [Figure 7A-7C]

[0022] FIG. 7A is a diagram of a first stage topology including a distributed power amplifier circuit in a second embodiment of the power amplifier.

[0023] FIG. 7B is a diagram illustrating the topology of a second stage including a reactive matched power amplifier circuit in a power amplifier according to a second embodiment.

[0024] FIG. 7C is a diagram illustrating a third stage topology including a reactive matched power amplifier circuit in the power amplifier of the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015]

[0025] Like numbers refer to like parts throughout the drawings.

[0016]

[0026] 1 shows a schematic diagram of a power amplifier configuration according to a first embodiment of the present disclosure, generally designated 10. FIG. 2 shows an exemplary topology or configuration of power amplifier 10.

[0017]

[0027] Power amplifier 10 combines a non-uniform distributed power amplifier topology and a reactive-matched power amplifier topology into a single power amplifier 10. Power amplifier 10 includes at least two stages, at least one of which is a non-uniform distributed power amplifier stage and at least one of which is a reactive-matched power amplifier stage. In one example, the non-uniform distributed power amplifier stage is electrically “upstream” from the reactive-matched power amplifier stage. In one particular embodiment, power amplifier 10 includes a first stage 12, a second stage 14, and a third stage 16. The term “upstream” electrically refers to the placement of one component relative to another component within power amplifier 10, and being “upstream” electrically refers to the first component being located or processed before the second component. Similarly, when a component is referred to as being electrically “downstream” from another component, the second component is located or processed after the first component.

[0018]

[0028] As shown in FIGS. 1, 2, and 3B, the first stage 12 includes a non-uniform distributed power amplifier circuit 20. More specifically, a first non-uniform distributed power amplifier circuit 20A is electrically parallel with a second non-uniform distributed power amplifier circuit 20B. The first NDPA circuit 20A is coupled to a drain voltage (Vd1) and a gate voltage (Vg1). The second NDPA circuit 20B is coupled to a drain voltage (Vd1) and a gate voltage (Vg1). In one exemplary embodiment, the power amplifier 10 is symmetrical about two halves within which signal processing is performed in parallel. Thus, there may be a drain voltage (Vd1) and a gate voltage (Vg1) for the first half or upper half circuit 20A, and a second drain voltage (Vd1) and a second gate voltage (Vg1) for the second half or lower half circuit 20B.

[0019]

[0029] The second stage 14 includes a distributed power amplifier circuit 20. More specifically, the second stage 14 includes a third NDPA circuit 20C electrically parallel with a fourth NDPA circuit 20D. The third NDPA circuit 20C is coupled to a drain voltage (Vd2) and a gate voltage (Vg2). The fourth NDPA circuit 20D is coupled to the drain voltage (Vd2) and a gate voltage (Vg2).

[0020]

[0030] The first NDPA circuit 20A is electrically in series with the third NDPA circuit 20C. The second NDPA circuit 20B is electrically in series with the fourth NDPA circuit 20D.

[0021]

[0031] As shown in Figures 1, 2, and 3C, the third stage 16 includes a reactive matched power amplifier circuit. More specifically, the third stage 16 includes a first reactive matched power amplifier circuit 22A electrically in parallel with a second reactive matched power amplifier circuit 22B. The first RMPA circuit 22A is coupled to a drain voltage (Vd3) and a gate voltage (Vg3). The second RMPA circuit 22B is coupled to a drain voltage (Vd3) and a gate voltage (Vg3). The first reactive matched power amplifier circuit 22A is electrically in series with a third distributed power amplifier circuit 20C, and the second reactive matched power amplifier circuit 22B is electrically in series with a fourth distributed power amplifier circuit 20D.

[0022]

[0032] As shown in Figures 1, 2, and 3A, power amplifier 10 includes a radio frequency (RF) input 24 to feed three stages 12, 14, and 16. Input 24 is in electrical communication with hybrid coupler 26A. In one embodiment, hybrid coupler 26A is a Lange coupler, although other types of hybrid couplers may be utilized. From hybrid coupler 26A, the RF signal is split into two parallel streams, indicated by lines 28A and 28B. First line 28A, carrying the signal from hybrid coupler 26A, feeds first distributed power amplifier 20A, third distributed power amplifier 20C, and first reactive matched power amplifier circuit 22A, all in series with each other. Second line 28B feeds second distributed power amplifier circuit 20B, fourth distributed power amplifier circuit 20D, and second reactive matched power amplifier circuit 22B, all in electrical series with each other. The outputs of the reactive matched power amplifier circuits 22 in the third stage 16 are combined in a second hybrid coupler 26B, which may be a Lange coupler or other type of hybrid coupler. The output of the second hybrid coupler 26B is sent to an RF output 30.

[0023]

[0033] In this exemplary embodiment of power amplifier 10, first distributed power amplifier circuit 20A includes at least four unit cells, which may be four 2×75 micron field effect transistors (FETs). In FIG. 2, these four FET transistors are labeled Q1, Q2, Q3, and Q4. Second distributed power amplifier circuit 20B includes at least four unit cells, which may be four 2×75 micron FET transistors. In FIG. 2, these four FET transistors are labeled Q5, Q6, Q7, and Q8. Thus, first stage 12 has at least a total of eight unit cells, i.e., eight 2×75 micron FET transistors (Q1-Q8). However, it should be noted that other exemplary embodiments may have a different number of transistors in the first stage. Furthermore, while FET transistors are preferred given the current state of transistor technology, the use of FET transistors is not required, as other transistors may be utilized. Note that a “unit cell” is the basic unit in the layout of a semiconductor integrated circuit device.

[0024]

[0034] The second stage 14 includes at least ten total FET transistors. There are at least five unit cells within the second stage 14, which may be five 2×75 micron FET transistors in the third distributed power amplifier circuit 20C. In FIG. 2, these five FET transistors are labeled Q9, Q10, Q11, Q12, and Q13. The fourth distributed power amplifier circuit 20D includes at least five unit cells, which may be five 2×75 micron FET transistors. In FIG. 2, these five unit cells or five FET transistors are labeled Q14, Q15, Q16, Q17, and Q18. Thus, there are at least ten total unit cells or FET transistors (Q9-Q18) in the second stage 14.

[0025]

[0035] The third stage 16 has at least eight FET transistors in total, and the first reactive matched power amplifier circuit 22A includes at least four unit cells, which may be four 4×75 micron FET transistors. In FIG. 2, these four FET transistors are labeled Q19, Q20, Q21, and Q22. The second reactive matched power amplifier includes at least four unit cells, which may be four 4×75 micron FET transistors. In FIG. 2, these five FET transistors are labeled Q23, Q24, Q25, and Q26. In this particular embodiment, all 26 FET transistors (Q1-Q26) are approximately 0.18 microns in length and 75 microns in width. The base layer forming the power amplifier 10 may have air-cut vias through all of the substrate from which the topside gold and silicon nitride have been removed. The backside gold may be 2 microns thick.

[0026]

[0036] In this exemplary embodiment of power amplifier 10, two distributed power amplifier stages 12, 14 precede a reactive-matched power amplifier stage 16. The first stage 12 has a perimeter value of 600 microns. The second stage 14 has a perimeter value of 750 microns. The third stage 16 has a perimeter value of 1200 microns. The ratio between each successive stage is less than 2:1; for example, the ratio between the second stage 14 and the first stage is less than 2:1 (750 microns to 600 microns is a ratio less than 2:1). Similarly, the ratio between the third stage 16 and the second stage 14 is less than 2:1. In other words, the ratio between 1200 microns and 750 microns is less than 2:1. Other embodiments may have a different number of distributed power amplifier stages and reactive-matched power amplifier stages. Perimeter is a parameter or method for numerically describing the amount of transistors in a stage. The ratio defining the perimeter is obtained for each stage. This ratio increases with each stage. Typically, the most conservative ratio is 2:1, meaning that subsequent stages are twice the circumference of the current stage. However, because distributed topologies generate less power, ratios less than 2:1 should be utilized in some of the embodiments detailed herein. However, it is entirely possible for this ratio to be greater than 2:1 if desired for application-specific needs.

[0027]

[0037] The power amplifier 10 includes two stages that are distributed power amplifier circuits and a subsequent stage that is reactively matched. There is at least one stage preceding the subsequent reactively matched power amplifier circuit 22 that is either a distributed power amplifier stage 20 or has a distributed power amplifier circuit in electrical operative communication with it. There is an interface between the final distributed power amplifier circuit 20 and the previous reactively matched power amplifier circuit 22. At this interface, impedance is matched between the final distributed power amplifier stage and the first reactively matched power amplifier stage, resulting in efficient power flow between the two. Matching impedances ensures that power flows efficiently through the circuit, thereby ensuring that bandwidth is not limited. In other words, impedance is matched between the object or circuit between the final distributed power amplifier circuit and the previous first reactively matched power amplifier circuit to assist in power flow management.

[0028]

[0038] "Perimeter" is a measure of transistor size. The perimeter of a FET is measured in the linear dimension of the gate width, such as microns or millimeters. "Perimeter ratio" is the ratio of transistor sizes from stage to stage.

[0029]

[0039] In operation, the power amplifier 10 provides a matched amplifier architecture that eliminates inter-stage complex impedances by maintaining a perimeter ratio between each successive stage of less than 2:1. The NDPA stages have nearly pure real input / output impedances, resulting in an inter-stage match between one real impedance (the output impedance of the NDPA stage) and one complex impedance (the input impedance of the RMPA stage), improving bandwidth over the match between two complex impedances that occurs between pure RMPA stages. The distributed power amplifier circuit 20 is designed using a non-uniform distributed power amplifier topology that increases maximum output power by providing each transistor section with an optimized output power load conductance. The FET output capacitance of the distributed power amplifier circuit 20 can be absorbed in an artificial transmission line. Gradually decreasing the drain line characteristics can better maintain an optimal load for all FET cells. A capacitor in the distributed power amplifier circuit 20 can be placed in series with the gate of each FET to increase the cutoff frequency of the gate transmission line. These series capacitors are also gradually reduced to ensure equal drive levels on the transistor gates. A mesa or TaN resistor can be placed in parallel with each gate capacitor to provide a DC path for gate bias. Alternatively, NiCr resistors or other types of resistors can be utilized. The reactive matched power amplifier circuit 22 can achieve high output power by connecting multiple active cells in parallel. This increases the total gate width of the power amplifier, and therefore allows for higher currents. The reactive matched power amplifier circuit 22 should be configured to achieve wideband behavior of the matching network.

[0030]

[0040] In the power amplifier 10, a signal, such as an RF signal, to be amplified is connected to the input 24. The signal is transmitted to a first hybrid coupler 26A. The first hybrid coupler 26A splits the signal and transmits it along parallel transmission lines 28A and 28B. The first hybrid coupler 26A applies a 90-degree phase shift to the signal between branches or between transmission lines 28A and 28B. Thus, the signal traveling along transmission line 28A has a 90-degree phase shift relative to the signal traveling along transmission line 28B. In one embodiment, the coupler 26A splits the signal equally along lines 28A and 28B. The first transmission line 28A transmits a portion of the signal to be amplified to a first distributed power amplifier circuit 20A of the first stage 12. The second transmission line 28B transmits a portion of the signal to be amplified to a second distributed power amplifier circuit 20B of the first stage 12. The signal is amplified by distributed power amplifier circuits 20 in the first stage 12. That is, a first portion of the signal is amplified by four 2×75 micron FET transistors (Q1-Q4) in a first distributed power amplifier circuit 20A. A second portion of the signal is amplified by four 2×75 micron FET transistors (Q5-Q8) in a second distributed power amplifier circuit 20B.

[0031]

[0041] A first portion of the amplified signal exits the first distributed power amplifier circuit 20A of the first stage 12 and is transmitted to a third distributed power amplifier circuit 20C of the second stage 14. This signal is amplified by at least five 2×75 micron FET transistors (Q9-Q13) in the third distributed power amplifier circuit 20C. A second portion of the amplified signal exits the second distributed power amplifier circuit 20B of the first stage 12 and is transmitted to a fourth distributed power amplifier circuit 20D of the second stage 14. This signal is amplified by at least five 2×75 micron FET transistors (Q14-Q18) in the fourth distributed power amplifier circuit 20D.

[0032]

[0042] The portion of the signal exiting the third distributed power amplifier circuit 20C transitions through an interface 32 between the second stage 14 and the third stage 16. The impedance of the signal exiting the third distributed power amplifier circuit 20C is matched to the reactive matched power amplifier circuit 22A of the third stage 16, resulting in efficient power flow therebetween. The portion of the signal exiting the fourth distributed power amplifier circuit 20D transitions through an interface 32 between the second stage 14 and the third stage 16. The impedance of the signal exiting the fourth distributed power amplifier circuit 20D is matched to the reactive matched power amplifier circuit 22B, resulting in efficient power flow therebetween. The interface 32 may be an intermediate impedance interface.

[0033]

[0043] In one exemplary embodiment, matching the impedance of the signal at the interface between the final distributed power amplifier circuit 20 and before the reactive matched power amplifier circuit 22 is achieved through a wideband impedance matching technique, which in this exemplary embodiment comprises a series of transmission lines, shunt transmission line stubs, shunt shorted MIM capacitors, and series MIM capacitors.

[0034]

[0044] The portion of the signal exiting the third distributed power amplifier circuit 20C transitions through an interface 32 between the second stage 14 and the third stage 16 and is then amplified by the first reactive matched power amplifier circuit 22A via at least four 4×75 micron FET transistors (Q19-Q22). The portion of the signal exiting the fourth distributed power amplifier circuit 20D transitions through an interface between the second stage 14 and the third stage 16 and is then amplified by the second reactive matched power amplifier circuit 22B via at least four 4×75 micron FET transistors (Q23-Q26). A second hybrid coupler then receives the amplified signals from the first reactive matched power amplifier circuit 22A and the second reactive matched power amplifier circuit 22B. A second hybrid coupler 26B combines the two signals and transmits the amplified signal to an output 30.

[0035]

[0045] Because the efficiency of the power amplifier of the present disclosure is improved, thermal performance is also improved. Figure 4 is a table showing stackup temperature rise and effective thermal resistance. The values ​​in the table shown in Figure 4 are explicitly based on 36.5 GHz operation of the power amplifier, which results in the maximum peak channel temperature according to this embodiment. Specifically, the total die heat dissipation is 30.49 W (Q die (W)=30.49). Even with identical stackups and similar die characteristics, effective thermal resistance values ​​can vary significantly. This is largely due to the choice of total die heat dissipation for calculating effective thermal resistance. Layer temperature rise is primarily due to FET transistor heat dissipation in the channel at the top of the die; as heat flows downward through the stackup, local effects become smaller, until the layer temperature is more strongly attributed to total die heat dissipation. The remaining variation is primarily due to differences in die layout and heat distribution, with temperature-dependent effects being secondary. The layer temperature rise and effective thermal resistance shown in the table in Figure 4 are limited not only to the range of housing peak temperatures, but also to the total die heat dissipation and heat distribution implied by the referenced operating frequency.

[0036]

[0046] 5 shows a schematic diagram of a power amplifier configuration according to a second embodiment of the present disclosure, generally designated 110. FIG. 6 shows an exemplary topology or configuration of the power amplifier 110.

[0037]

[0047] The power amplifier 110 combines a non-uniform distributed power amplifier topology and a reactively matched power amplifier topology into a single power amplifier 110. The power amplifier 110 includes at least two stages, at least one of which is a non-uniform distributed power amplifier stage and at least one of which is a reactively matched power amplifier stage. More specifically, the power amplifier 110 includes a first stage 112, a second stage 114, and a third stage 116.

[0038]

[0048] 5, 6, and 7A, the first stage 112 comprises a non-uniform distributed power amplifier circuit 120. More specifically, a first distributed power amplifier circuit 120A is electrically in parallel with a second distributed power amplifier circuit 120B.

[0039]

[0049] 5, 6, and 7B, the second stage 114 includes a reactive matched power amplifier circuit 122. More specifically, the second stage 114 includes a first reactive matched power amplifier circuit 122A electrically in parallel with a second reactive matched power amplifier circuit 122B. The first reactive matched power amplifier circuit 122A is in series with the first non-uniform distributed power amplifier circuit 120A. The second reactive matched power amplifier circuit 122B is electrically in series with the second non-uniform distributed power amplifier circuit 120B.

[0040]

[0050] 5, 6, and 7C, the third stage 116 includes a reactive matched power amplifier circuit 122. More specifically, the third stage 116 includes a third reactive matched power amplifier circuit 122C that is electrically parallel to a fourth reactive matched power amplifier circuit 122D. The third reactive matched power amplifier circuit 122C is electrically in series with the first reactive matched power amplifier circuit 122A. The fourth reactive matched power amplifier circuit 122D is electrically in series with the second reactive matched power amplifier circuit 122B.

[0041]

[0051] 5 and 6, to feed the three stages 112, 114, and 116, the power amplifier 110 includes a radio frequency (RF) input 124. The input 124 is in electrical communication with a hybrid coupler 126. In one embodiment, the hybrid coupler 126A is a Lange coupler, although other types of hybrid couplers may be utilized. From the hybrid coupler 126A, the RF signal is split into two parallel streams, represented by lines 128A and 128B. The first line 128A, carrying the signal from the hybrid coupler 126A, feeds a first non-uniform distributed power amplifier 120A, a first reactive matched power amplifier circuit 122A, and a third reactive matched power amplifier circuit 122C, all in series with each other. The second line 128B feeds a second non-uniform distributed power amplifier circuit 120B, a second reactive matched power amplifier circuit 122B, and a fourth reactive matched power amplifier circuit 122D, which are electrically in series with one another. The outputs of the reactive matched power amplifier circuits 122 in the third stage 116 are combined in a second hybrid coupler 126B, which may be a Lange coupler or other type of hybrid coupler. The output of the second hybrid coupler 126B is sent to an RF output 130.

[0042]

[0052] In this exemplary embodiment of power amplifier 110, first non-uniform distributed power amplifier circuit 120A includes at least four unit cells, which may be four 4×75 micron (FET) transistors, represented by transistors Q101, Q102, Q103, and Q104. Second distributed power amplifier circuit 120B includes at least four unit cells, which may be four 4×75 micron FET transistors, represented by transistors Q105, Q106, Q107, and Q108. Thus, there are at least eight total FET transistors (4×75 microns) in first stage 112 (represented by Q101 through Q108). Second stage 114 includes at least four unit cells, which may be four total FET transistors. Within the second stage 114, there are at least two 16×50 micron FET transistors in a first reactive matched power amplifier circuit 122A, designated Q109 and Q110. There are at least two 16×50 micron FET transistors in a second reactive matched power amplifier circuit 122B, designated Q111 and Q112. There are at least eight total unit cells, which may be eight FET transistors, in the third stage 116. The third reactive matched power amplifier circuit 122C includes at least four unit cells, which may be four 16×50 micron FET transistors, designated Q113, Q114, Q115, and Q116. The fourth reactive matched power amplifier circuit 122D includes at least four unit cells, which may be four 16×50 micron FET transistors, designated Q117, Q118, Q119, and Q120. In this particular embodiment, there will be at least 20 total FET transistors (i.e., transistors Q101-Q120). The base layer forming power amplifier 110 may have air-cut vias through all of the substrate where the topside gold and silicon nitride have been removed. The backside gold may be 2 microns thick.

[0043]

[0053] In this exemplary embodiment of the power amplifier 110, two reactively matched power amplifier stages 114, 116 are preceded by one non-uniform distributed power amplifier stage 112. This embodiment has a 1.5:2:4 perimeter drive ratio for the first stage 112:the second stage 114:the third stage 116. Thus, if the first stage 112 has a perimeter value of 450 microns, the second stage 114 has a perimeter value of 600 microns, and the third stage 116 has a perimeter value of 1200 microns. The ratio between each respective successive stage is 2:1 or less; for example, the ratio between the second stage 114 and the first stage 112 is less than 2:1 (in this case, 600 microns to 450 microns is a ratio less than 2:1). Similarly, the ratio between the third stage 116 and the second stage 114 is 2:1 or less. In other words, the ratio between 1200 microns and 600 microns is less than or equal to 2:1. Other embodiments may have different numbers of distributed power amplifier stages and reactively matched power amplifier stages.

[0044]

[0054] Power amplifier 110 includes one stage that is a non-uniform distributed power amplifier and two subsequent stages that are reactive matching stages. This design approach differs from the previous embodiment (i.e., power amplifier 10), which utilized two distributed stages and a single subsequent reactive matching stage. However, in both embodiments (i.e., power amplifier 10 or power amplifier 110), there is at least one stage prior to the subsequent reactive matched power amplifier circuit that is either a non-uniform distributed power amplifier stage or has a non-uniform distributed power amplifier circuit in electrical operative communication (i.e., the non-uniform distributed power amplifier circuit is electrically "upstream" from the reactive matched power amplifier circuit). In each embodiment, there is an interface 32 or 132 between the last distributed power amplifier circuit 20 or 120 and prior to the first reactive matched power amplifier circuit 22 or 122. This interface 32 or 132 provides impedance matching between the last distributed power amplifier stage and the first reactive matched power amplifier stage, allowing power to flow efficiently between the two. Matching impedances ensures that power flows efficiently through the circuit, ensuring that bandwidth is not limited. In other words, impedances are matched between the objects or circuits between the last distributed power amplifier circuit and the circuit before the first reactive matched power amplifier circuit to aid in power flow management.

[0045]

[0055] In operation, the power amplifier 110 provides a matched amplifier architecture that eliminates complex impedance between stages by maintaining a perimeter ratio of 2:1 or less between each successive stage. The distributed power amplifier circuit 120 is designed using a non-uniform distributed power amplifier topology that increases maximum output power by providing each transistor section with an optimized output power load conductance. The FET output capacitance of the distributed power amplifier circuit 120 can be absorbed in an artificial transmission line. Gradually decreasing the drain line characteristics can better maintain optimal loads for all FET cells. Capacitors in the distributed power amplifier circuit 120 can be placed in series with the gate of each FET to increase the cutoff frequency of the gate transmission line. These series capacitors are also gradually decreased to ensure equal drive levels on the transistor gates. NiCr resistors can be placed in parallel with each gate capacitor to provide a DC path for gate bias. The reactive matched power amplifier circuit 122 can achieve high output power by connecting multiple active cells in parallel. This increases the total gate width of the power amplifier, thereby enabling higher currents. The reactive matched power amplifier circuit 122 should be configured to achieve wideband behavior of the matching network.

[0046]

[0056] In the power amplifier 110, a signal, such as an RF signal, to be amplified is connected to the input 124. The signal is transmitted to a first hybrid coupler 126A. The first hybrid coupler 126A splits the signal and transmits the signal equally along parallel transmission lines 128A and 128B. The first transmission line 128A transmits a portion of the signal to be amplified to a first distributed power amplifier circuit 120A in the first stage 112. The second transmission line 128B transmits a portion of the signal to a second distributed power amplifier circuit 20B in the first stage 112. The signal is amplified by the distributed power amplifier circuit 120 in the first stage 112. That is, a first portion of the signal is amplified by four 4×75 micron FET transistors Q101-Q104 within the first distributed power amplifier circuit 120A. A second portion of the signal is amplified by four 4×75 micron FET transistors Q105-Q108 in a second distributed power amplifier circuit 120B.

[0047]

[0057] The portion of the signal exiting the first distributed power amplifier circuit 120A transitions through an interface 132 between the first stage 112 and the second stage 114. The impedance of the signal exiting the first distributed power amplifier circuit 120A is matched to the reactive matched power amplifier circuit 122A stage, so that power flows efficiently therebetween. The portion of the signal exiting the second distributed power amplifier circuit 120B transitions through an interface 132 between the first stage 112 and the second stage 114. The impedance of the signal exiting the second distributed power amplifier circuit 120B is matched to the reactive matched power amplifier circuit 122B stage, so that power flows efficiently therebetween. The interface 132 may be an intermediate impedance interface.

[0048]

[0058] In one exemplary embodiment, matching the impedance of the signal at the interface 132 between the final distributed power amplifier circuit 120 (i.e., the first stage 112) and before the reactive matched power amplifier circuit 122 (i.e., the second stage 114) is achieved through a wideband impedance matching technique, which in this exemplary embodiment comprises a series of transmission lines, shunt short-circuit MIM capacitors, and series MIM capacitors.

[0049]

[0059] A first portion of the amplified signal exits the first distributed power amplifier circuit 120A of the first stage 112 and is transmitted to the first reactive matched power amplifier circuit 122A of the second stage 114. This signal is amplified by at least two 16×50 micron FET transistors Q109 and Q110 in the first reactive matched power amplifier circuit 122A. A second portion of the amplified signal exits the second distributed power amplifier circuit 120B of the first stage 112 and is transmitted to the second reactive matched power amplifier circuit 122B of the second stage 114. This signal is amplified by at least two 16×50 micron FET transistors Q111 and Q112 in the second reactive matched power amplifier circuit 122B.

[0050]

[0060] The portion of the signal exiting the first reactive matched power amplifier circuit 122A is then amplified by a third reactive matched power amplifier circuit 122C via at least four 16×50 micron FET transistors Q113-Q116. The portion of the signal exiting the second reactive matched power amplifier circuit 122B is then amplified by a fourth reactive matched power amplifier circuit 122D via at least four 16×50 micron FET transistors Q117-Q120. A second hybrid coupler then receives the amplified signals from the third reactive matched power amplifier circuit 122C and the fourth reactive matched power amplifier circuit 122D. A second hybrid coupler 126B combines the two signals and transmits the amplified signal to an output 130.

[0051]

[0061] Table 1 (below) shows the parameters of the topology of the power amplifier 10 or 110 of the present disclosure and the specifications achieved for each respective parameter.

[0052] [Table 1]

[0053]

[0062] With respect to power amplifier circuits or circuits, there is a trade-off between bandwidth and DC (direct current) power. DC power is the input to the power amplifier circuit to obtain output power. What governs the relationship between input power and output power is the efficiency of the power amplifier. Typically, circuit designers are limited by input power and want the maximum possible output power. Therefore, they want the highest possible efficiency. The bandwidth governs how much output power can be obtained per efficiency. Typically, reactive-matched power amplifiers can be performed with a bandwidth up to about 20%. Beyond that 20% bandwidth, distributed power amplifiers can obtain higher bandwidths or higher bandwidth percentages, typically well above 100%, but bandwidth-limited reactive-matched power amplifiers have higher efficiency compared to architectures such as distributed power amplifiers that have wide bandwidths but low or limited efficiency. Recall that efficiency governs the amount of output power for a given amount of DC input power. Different embodiments of the combined power amplifier 10 or 110 described herein utilize both of these features. Embodiments of the power amplifier(s) 10 or 100 of the present disclosure utilize a combination of two architectures to find a multi-stage "middle ground." The earlier stages are a distributed power amplifier topology. The later stages largely drive power and efficiency performance, and these later stages are reactively matched. This combination allows the power amplifier 10 or 110 of the present disclosure to achieve performance between the other two architectures alone. Thus, the power amplifier 10 or 110 of the present disclosure can achieve a bandwidth wider than a pure or standalone reactively matched power amplifier, but not as wide as a distributed power amplifier, and can also achieve better efficiency than a pure or standalone distributed amplifier, but not as high as a reactively matched power amplifier. This results in a solution that is a hybrid or combination of the two previously available versions. For example, for a 32-38 GHz power amplifier, the power amplifier 10 or 110 of the present disclosure can achieve a higher efficiency ratio than previously available.More specifically, the power amplifier 10 or 110 may have an operating bandwidth in the range of 28 to 40 GHz. Depending on the impedance being matched, there is a criterion called the Bode-Fano criterion that determines how well the match can be achieved and how wide the bandwidth can be. In other words, the Bode-Fano criterion states that for any passive, linear, and time-invariant matching network, there is a severe trade-off between matching bandwidth and efficiency, implying severe constraints for various electromagnetic systems. Therefore, having a single stage that improves bandwidth allows the power amplifier of the present disclosure to remove the bandwidth-limiting factor.

[0054]

[0063] As described herein, aspects of the present disclosure may include one or more electrical or other similar subcomponents and / or systems. Accordingly, it is contemplated and understood that the present disclosure includes any necessary operating components thereof. For example, it will be understood that an electrical component includes any suitable and necessary wiring, fuses, etc. for its normal operation. It will further be understood that any connections between various components not explicitly described herein may be made through any suitable means, including mechanical fasteners or more permanent attachment means such as welding. Alternatively, where feasible and / or desirable, the various components of the present disclosure may be integrally formed as a single unit.

[0055]

[0064] Various inventive concepts may be embodied as one or more methods, examples of which are provided. The actions performed as part of a method may be ordered in any suitable manner. Thus, embodiments may be constructed in which actions are performed in an order different from that illustrated, and may involve performing some actions simultaneously even though they are shown as sequential actions in the illustrative embodiments.

[0056]

[0065] While various embodiments of the present invention have been described and illustrated herein, those skilled in the art will readily envision various other means and / or structures for performing the functions described herein and / or obtaining one or more of the results and / or advantages described herein, and each such variation and / or modification is deemed to be within the scope of the embodiments of the present invention described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary, and that the actual parameters, dimensions, materials, and / or configurations will depend on the particular application or applications for which the teachings of the present invention are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments of the present invention described herein. Accordingly, it should be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and their equivalents, embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and / or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and / or methods is included within the inventive scope of the present disclosure, if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent.

[0057]

[0066] The above-described embodiments can be implemented in any of numerous ways. For example, embodiments of the technology disclosed herein may be implemented using hardware, software, or a combination thereof. When implemented in software, the software code or instructions may be executed on any suitable processor or collection of processors, whether provided on a single computer or distributed among multiple computers. Furthermore, the instructions or software code may be stored on at least one non-transitory computer-readable storage medium.

[0058]

[0067] Additionally, a computer or smartphone that may be used to execute software code or instructions via a processor may have one or more input and output devices. These devices may be used, among other things, to present a user interface. Examples of output devices that may be used to provide a user interface include a printer or display screen for visual presentation of output and a speaker or other sound-generating device for audible presentation of output. Examples of input devices that may be used for a user interface include a keyboard and pointing devices such as a mouse, touchpad, and digitizing tablet. As another example, a computer may receive input information through voice recognition or in other audible formats.

[0059]

[0068] Such computers or smartphones may be interconnected by one or more networks of any suitable form, including enterprise networks, and local or wide area networks such as intelligent networks (INs) or the Internet. Such networks may be based on any suitable technology and may operate according to any suitable protocol, and may include wireless networks, wired networks, or fiber optic networks.

[0060]

[0069] The various methods or processes outlined herein may be coded as software / instructions executable on one or more processors employing any one of a variety of operating systems or platforms. Further, such software may be written using any of a number of suitable programming languages ​​and / or programming or scripting tools, and may be compiled as executable machine code or intermediate code that runs on a framework or virtual machine.

[0061]

[0070] In this regard, various inventive concepts may be embodied as a computer-readable storage medium (or multiple computer-readable storage media) (e.g., computer memory, one or more floppy disks, compact disks, optical disks, magnetic tapes, flash memory, USB flash drives, SD cards, circuitry within a field programmable gate array or other semiconductor device, or other non-transitory or tangible computer storage medium) encoded with one or more programs that, when executed on one or more computers or other processors, perform methods that implement various embodiments of the present disclosure described above. The one or more computer-readable media may be portable, such that the stored program or programs can be loaded onto one or more different computers or other processors to implement various aspects of the present disclosure described above.

[0062]

[0071] The terms "program" or "software" or "instructions" are used herein in a generic sense to refer to any type of computer code or set of computer-executable instructions that may be employed to program a computer or other processor to implement various aspects of the above-described embodiments. Furthermore, it should be recognized that, according to one aspect, one or more computer programs that, when executed, perform the methods of the present disclosure need not reside on a single computer or processor, but may be distributed in a modular manner among several different computers or processors to implement various aspects of the present disclosure.

[0063]

[0072] Computer-executable instructions may be in many forms, such as program modules, executed by one or more computers or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. Typically, the functionality of the program modules may be combined or distributed as desired in various embodiments. Thus, one aspect or embodiment of the present disclosure may be a computer program product that includes at least one non-transitory computer-readable storage medium in operative communication with a processor, the storage medium storing instructions that, when executed by the processor, implement the method or process described herein, the instructions comprising steps for performing the method(s) or process(es) detailed herein.

[0064]

[0073] Additionally, data structures may be stored in computer-readable media in any suitable form. For ease of illustration, data structures may be shown as having fields that are related through their locations within the data structure. Such relationships may in turn be achieved by assigning locations within the computer-readable media that convey the relationship between the fields to the storage for the fields. However, any suitable mechanism may be used to establish relationships between information within fields of a data structure, including the use of pointers, tags, or other mechanisms for establishing relationships between data elements.

[0065]

[0074] All definitions defined and used herein should be understood to govern dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms.

[0066]

[0075] As used herein, "logic" includes, but is not limited to, hardware, firmware, software, and / or combinations of each for performing a function(s) or action(s) and / or causing a function or action from another logic, method, and / or system. For example, based on a desired application or need, logic may include a software-controlled microprocessor, discrete logic such as a processor (e.g., a microprocessor), an application-specific integrated circuit (ASIC), a programmed logic device, a memory device containing instructions, or an electrical device having memory, etc. Logic may include one or more gates, combinations of gates, or other circuit components. Logic may be embodied entirely as software. Where multiple logics are described, it may be possible for the multiple logics to be incorporated into one physical logic. Similarly, where a single logic is described, it may be possible for the single logic to be distributed among multiple physical logics.

[0067]

[0076] Furthermore, the logic(s) presented herein for achieving the various methods of the present system may be directed to improving existing computer- or internet-centric technologies that may not have previous analog versions. The logic(s) may provide specific functionality directly related to structures that address and solve certain problems identified herein. The logic(s) may also provide significantly more advantages for solving these problems by providing exemplary inventive concepts as specific logical structures and coordinated functionality of methods and systems. Furthermore, the logic(s) may also provide specific computer-implemented rules that improve existing technological processes. The logic(s) provided herein extend beyond simply collecting data, analyzing information, and displaying results. Furthermore, some or all of the present disclosure may rely on underlying equations derived from specific arrangements of equipment or components described herein. Thus, portions of the present disclosure are not directed to abstract concepts as they relate to specific arrangements of components. Furthermore, this disclosure and the appended claims present teachings that involve more than the performance of well-understood, routine, and conventional activities previously known in the art. In some of the methods or processes of the present disclosure, which may incorporate some aspect of natural phenomena, the process or method step is a new and useful additional feature.

[0068]

[0077] As used herein and in the claims, the articles "a" and "an" should be understood to mean "at least one" unless expressly indicated otherwise. The phrase "and / or," when used herein and in the claims, should be understood to mean "either or both" of the elements so conjoined, i.e., elements that are present conjunctively in some cases and disjunctively in other cases. Multiple elements listed with "and / or" should be construed in the same manner, i.e., "one or more" of the elements so conjoined. Other elements other than the elements specifically identified by the "and / or" clause may optionally be present, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to "A and / or B," when used in conjunction with open-ended language such as "comprising," may, in one embodiment, refer to A only (optionally including elements other than B); in another embodiment, refer to B only (optionally including elements other than A); in yet another embodiment, refer to both A and B (optionally including other elements), etc. As used in this specification and the claims, "or" should be understood to have the same meaning as "and / or" as defined above. For example, when separating items in a list, "or" or "and / or" shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also two or more, of a number of elements or list of elements, and optionally additional unlisted items. Only terms expressly indicated to the contrary, such as "only one of" or "exactly one of," or, when used in the claims, "consisting of," shall refer to the inclusion of exactly one element of a number of elements or list of elements. In general, the term "or" as used herein shall only be interpreted as indicating exclusive alternatives (i.e., "one or the other, but not both") when preceded by terms of exclusivity, such as "either," "one of," "only one of," or "exactly one of." "Consisting essentially of," when used in the claims, shall have its ordinary meaning as used in the field of patent law.

[0069]

[0078] As used in this specification and claims, the phrase "at least one," in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but does not necessarily include at least one of every element specifically listed within the list of elements, nor does it exclude any combination of elements in the list of elements. This definition also allows for elements to optionally be present other than those specifically identified in the list of elements to which the phrase "at least one" refers, whether related or unrelated to those specifically identified elements. Thus, as a non-limiting example, "at least one of A and B" (or, equivalently, "at least one of A or B," or, equivalently, "at least one of A and / or B") can refer in one embodiment to at least one, optionally more than one, A (and optionally including elements other than B) with no B present; in another embodiment to at least one, optionally more than one, B (and optionally including elements other than A); in yet another embodiment to at least one, optionally more than one, A and at least one, optionally more than one, B (and optionally including other elements); and so forth.

[0070]

[0079] As used herein in the specification and claims, the term "effecting" or a phrase or claim element beginning with the term "causing" should be understood to mean causing something to happen or bringing about something. For example, causing an event to occur can be caused by the actions of a first party, even if the second party actually performs the event or causes the second party to cause the event. In other words, causing refers to one party providing another party with the tools, objects, or resources to cause the event to occur. Thus, in this example, the claim element "causing an event" means that the first party provides the second party with the tools or resources necessary for the second party to perform the event, but the affirmative single action is the first party's responsibility to provide the tools or resources to cause the event to occur.

[0071]

[0080] When a feature or element is referred to herein as being "on" another feature or element, it may be directly on the other feature or element, or there may be intervening features and / or elements present. In contrast, when a feature or element is referred to as being "directly on" another feature or element, there are no intervening features or elements present. When a feature or element is referred to as being "connected," "attached," or "coupled" to another feature or element, it will be understood that it may be directly connected, attached, or coupled to the other feature or element, or there may be intervening features or elements present. In contrast, when a feature or element is referred to as being "directly connected," "directly attached," or "directly coupled" to another feature or element, there are no intervening features or elements present. Although described or illustrated with respect to one embodiment, features and elements so described or illustrated can be applied to other embodiments. It will also be understood by those skilled in the art that a reference to a structure or feature disposed "adjacent" to another feature may have portions that overlap or underlie the adjacent feature.

[0072]

[0081] Spatially relative terms, such as "under," "below," "lower," "over," "upper," "above," "behind," and "in front of," may be used herein for ease of explanation to describe the relationship of an element or feature illustrated in the figures to another element(s) or feature(s). It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures were inverted, elements described as "under" or "beneath" another element or feature would then be oriented "over" that other element or feature. Thus, the exemplary term "under" can encompass both an orientation of over and under. The device may be otherwise oriented (rotated 90 degrees or to another orientation), and the spatially relative descriptions used herein would be interpreted accordingly. Similarly, terms such as "upwardly," "downwardly," "vertical," "horizontal," "lateral," "transverse," and "longitudinal" are used herein for descriptive purposes only, unless otherwise indicated.

[0073]

[0082] The terms "first" and "second" may be used herein to describe various features / elements, but these features / elements should not be limited by these terms unless the context dictates otherwise. These terms may be used to distinguish one feature / element from another. Thus, a first feature / element described herein could be referred to as a second feature / element, and similarly, a second feature / element described herein could be referred to as a first feature / element, without departing from the teachings of the present invention.

[0074]

[0083] An embodiment is an implementation or example of the present disclosure. References herein to "one embodiment," "one embodiment," "some embodiments," "one particular embodiment," "exemplary embodiment," or "other embodiments" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least some embodiments of the invention, but not necessarily in all embodiments. Various appearances of "one embodiment," "one embodiment," "some embodiments," "one particular embodiment," "exemplary embodiment," or "other embodiments" do not necessarily all refer to the same embodiment.

[0075]

[0084] When this specification describes a component, feature, structure, or characteristic as "may," "might," or "could be included," it does not require that particular component, feature, structure, or characteristic be included. When this specification or claims refer to "a" or "an" element, it does not mean that there is only one of that element. When this specification or claims refer to "additional" elements, it does not exclude the presence of more than one of the additional element.

[0076]

[0085] As used in this specification and claims, including when used in the examples, unless otherwise specified, all numbers may be read as if preceded by the word "about" or "approximately," even if these terms do not explicitly appear. The phrase "about" or "approximately," when describing a size and / or location, may be used to indicate that the described value and / or location is within a reasonably expected range of values ​​and / or locations. For example, a numerical value may have a value that is + / - 0.1% of the stated value (or range of values), + / - 1% of the stated value (or range of values), + / - 2% of the stated value (or range of values), + / - 5% of the stated value (or range of values), + / - 10% of the stated value (or range of values), etc. Any numerical ranges set forth herein are intended to include all subranges subsumed therein.

[0077]

[0086] Additionally, methods of carrying out the present disclosure may be performed in an order different from that described herein. Accordingly, the order of the method should not be read as a limitation unless expressly stated. It is recognizable that similar results can be achieved by performing some of the method steps in a different order.

[0078]

[0087] In the claims and in the above specification, all transitional phrases such as "comprising," "including," "carrying," "having," "containing," "involving," "holding," and "consisting of" are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases "consisting of" and "consisting essentially of" shall be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedure.

[0079]

[0088] To the extent this disclosure utilizes the term "invention" in various titles or sections herein, this term is included as required by formatting requirements for word document submissions in accordance with U.S. Patent and Trademark Office guidelines / requirements and should not be construed in any manner as a disclaimer of any subject matter.

[0080]

[0089] In the foregoing description, specific terms have been used for brevity, clarity, and understanding. Such terms are used for purposes of description and are intended to be broadly construed, without unnecessary limitations being implied beyond the requirements of the prior art.

[0081]

[0090] Moreover, the description and illustration of various embodiments of the present disclosure are by way of example, and the present disclosure is not limited to the exact details shown or described.

Claims

1. 1. A power amplifier comprising: a first stage comprising a distributed power amplifier circuit; a second stage electrically operating after the first stage, the second stage comprising a reactive matched power amplifier circuit; an intermediate impedance interface between the first stage and the second stage; a circumference ratio of the second step to the first step that is 2:1 or less; A power amplifier comprising:

2. The power amplifier of claim 1 , wherein the first stage comprises at least two unit cells within the distributed power amplifier circuit.

3. The power amplifier of claim 1 , wherein the second stage comprises at least two unit cells in the reactive matched power amplifier circuit.

4. a third stage electrically operating after the second stage, the third stage comprising another reactive matched power amplifier circuit; 2. The power amplifier of claim 1.

5. 5. The power amplifier of claim 4, wherein the perimeter ratios of the first stage, the second stage, and the third stage increase in the order of the first stage, the second stage, and the third stage.

6. 6. The power amplifier of claim 5, wherein the perimeter ratio of the first stage to the second stage to the third stage is 1.5:2:

4.

7. The power amplifier of claim 4 , wherein the third stage comprises at least two unit cells in the other reactive matched power amplifier circuit.

8. further comprising an operating bandwidth of the power amplifier in the range of 28-40 Ghz.

2. The power amplifier of claim 1.

9. a first hybrid coupler coupled to an input of the power amplifier, wherein the input is electrically operated before the first stage; a second hybrid coupler coupled to the output of the power amplifier, wherein the output is electrically operated after the second stage; The power amplifier of claim 1 further comprising:

10. 2. The power amplifier of claim 1, wherein the intermediate impedance interface is an intermediate impedance other than 50 ohms.

11. 1. A method for a power amplifier, comprising: transmitting the signal to be amplified to a first stage of a power amplifier, wherein the first stage includes a distributed power amplifier circuit; amplifying the signal in the first stage; transmitting the signal to the second stage via an intermediate impedance interface between the first stage and the second stage, the second stage including a reactive matched power amplifier circuit; amplifying the signal in the second stage; maintaining a circumference ratio of the second step to the first step of 2:1 or less; A method comprising:

12. transmitting the signal to a third stage electrically operating after the second stage, wherein the third stage includes a reactive matched power amplifier circuit; amplifying the signal in the third stage; The method of claim 11 further comprising:

13. The method of claim 12 , wherein the perimeter ratios of the first stage to the second stage to the third stage increase in the order of the first stage, the second stage, and the third stage.

14. 14. The method of claim 13, wherein the perimeter ratio of the first step to the second step to the third step is 1.5:2:

4.

15. further comprising maintaining the intermediate impedance interface at an intermediate impedance other than 50 ohms. The method of claim 11.

16. and matching at least one real impedance from the output impedance of the first stage with at least one complex impedance from the input impedance of the second stage adapted to improve bandwidth compared to matching two complex impedances. The method of claim 11.

17. 1. A power amplifier comprising: a distributed power amplifier stage; a reactive matched power amplifier stage electrically coupled to the distributed power amplifier stage; an intermediate impedance interface between the distributed power amplifier stage and the reactive matched power amplifier stage; Equipped with A power amplifier having a perimeter ratio of 2:1 or less between the distributed power amplifier stage and the reactive matched power amplifier stage.

18. 18. The power amplifier of claim 17, wherein the intermediate impedance interface is an intermediate impedance other than 50 ohms.

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