Impedance conversion circuit and amplification module

Abstract

Provided are an impedance conversion circuit and an amplification module, which can easily ensure the isolation between the node on the input side and the node on the output side. The two ends of the first main line are the first node and the third node, and high-frequency signals are transmitted between the first node and the third node. The two ends of the second main line are the second node and the fourth node, and high-frequency signals are transmitted between the second node and the fourth node. One end of the first auxiliary line is connected to the second node. The first auxiliary line is electromagnetically coupled to the first main line. One end of the second auxiliary line is connected to the first node, and the other end is connected to the end of the first auxiliary line that is not connected to the second node. The second auxiliary line is electromagnetically coupled to the second main line. A first capacitor is connected in parallel to at least one of the at least one part of the second main line and the at least one part of the second auxiliary line.

Description

Technical Field

[0001] This invention relates to impedance conversion circuits and amplification modules. Background Technology

[0002] In high-frequency power amplifiers using differential amplifier circuits, baluns are connected to both the input and output sides of the differential amplifier circuit. Furthermore, in the case of a high-frequency power amplifier composed of multi-stage differential amplifier circuits, impedance conversion circuits for differential signals are inserted between stages. A Guanella-type balun is disclosed in Non-Patent Document 1 below. Figure 39 The equivalent circuit diagram of the Guanella-type balanced-unbalanced switching circuit disclosed in Non-Patent Document 1 is shown.

[0003] The Guanella-type balun circuit includes a first node P1, a second node P2, a third node P3, and a fourth node P4. The first node P1 and the third node P3 are connected via a first main line 101, and the second node P2 and the fourth node P4 are connected via a second main line 102. A first auxiliary line 103 and a second auxiliary line 104 are coupled to the first main line 101 and the second main line 102, respectively. For example, the turns ratio (line length ratio) of the first main line 101 to the first auxiliary line 103 and the turns ratio (line length ratio) of the second main line 102 to the second auxiliary line 104 are both 1:1.

[0004] The first node P1 and the second node P2 are respectively connected to one end of the second sub-line 104 and the first sub-line 103, and the other ends of the second sub-line 104 and the first sub-line 103 are connected to each other.

[0005] The second node P2 is connected to ground. The first node P1 is used as a node for single-ended signals, and the third node P3 and the fourth node P4 are used as nodes for differential signals.

[0006] When a load is connected between the third node P3 and the fourth node P4, the impedance observed from the first node P1 on the load side becomes 1 / 4 of the load impedance. Conversely, when a load is connected to the first node P1, the impedance observed from both the third node P3 and the fourth node P4 on the load side becomes 4 times the load impedance. Thus, the Guanella-type balancing / unbalancing converter circuit has impedance conversion functionality.

[0007] Prior art literature

[0008] Non-patent literature

[0009] Non-patent document 1: Hua-Yen et.al., "Design of Step-Down Broadband and Low-Loss Ruthroff-Type Baluns Using IPD Technology", IEEE TRANSACTIONS ONCOMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL.4, NO.6, JUNE 2014 Summary of the Invention

[0010] The problem the invention aims to solve

[0011] In the Guanella-type balun circuit, the fourth node P4 is connected to ground via the second main line 102. It utilizes integrated passive components (IPDs) constructed from resin substrates, low-temperature co-fired ceramic (LTCC) substrates, semiconductor substrates, etc. Figure 39 In the case of the balun circuit shown, since the substrate is not made of magnetic material, it is difficult to sufficiently increase the inductance of transmission lines such as the second main line 102. Therefore, the isolation between the fourth node P4 and ground becomes insufficient, resulting in phase imbalance in the differential signal. Furthermore, insertion loss increases, especially at low frequencies.

[0012] Do not Figure 39 The transmission line transformer connected to ground in the second node P2 of the balancing-unbalancing conversion circuit shown can be used as an impedance conversion circuit for differential signals. In this case, it is possible that sufficient isolation cannot be ensured between the first node P1 and the third node P3, and between the second node P2 and the fourth node P4.

[0013] The purpose of this invention is to provide an impedance conversion circuit that easily ensures the isolation between nodes on the input side and nodes on the output side, and an amplification module equipped with the impedance conversion circuit.

[0014] Solution for solving the problem

[0015] According to one aspect of the present invention, an impedance conversion circuit is provided, wherein,

[0016] The impedance conversion circuit includes:

[0017] The first main line has a first node and a third node at its two ends, and high-frequency signals are transmitted between the first node and the third node.

[0018] The second main line has a second node and a fourth node at its two ends, and high-frequency signals are transmitted between the second node and the fourth node.

[0019] The first secondary line is connected to the second node and is electromagnetically coupled to the first main line;

[0020] The second auxiliary line has one end connected to the first node, and the other end connected to the end of the first auxiliary line that is not connected to the second node, and is electromagnetically coupled to the second main line; and

[0021] A first capacitor is connected in parallel with at least one of at least a portion of the second main line and at least a portion of the second secondary line.

[0022] According to another aspect of the present invention, an amplification module is provided, wherein,

[0023] The amplification module has the following features:

[0024] The impedance conversion circuit described above; and

[0025] A differential amplifier, wherein one of a pair of differential output nodes and a pair of differential input nodes is connected to the first node and the second node, respectively.

[0026] Invention Effects

[0027] The inductive component of at least one of at least a portion of the second main circuit and at least a portion of the second auxiliary circuit resonates in parallel with the first capacitor at a certain frequency. When parallel resonance occurs, the impedance of the parallel circuit becomes high impedance. Therefore, sufficient isolation can be ensured between the second node and the fourth node. Attached Figure Description

[0028] Figure 1A This is the equivalent circuit diagram of the impedance conversion circuit in the first embodiment. Figure 1B This is a schematic cross-sectional view illustrating the impedance conversion circuit of the first embodiment. Figure 1C This is a coordinate graph showing the pass coefficient S24 from the fourth node P4 to the second node P2.

[0029] Figure 2A Figure 2B is an equivalent circuit diagram of the impedance conversion circuit of the first variation of the first embodiment. Figure 2B is a coordinate graph showing the pass coefficient S24 from the fourth node P4 to the second node P2.

[0030] Figure 3A This is an equivalent circuit diagram of the impedance conversion circuit in the second variation of the first embodiment. Figure 3B This is a coordinate graph showing the pass coefficient S24 from the fourth node P4 to the second node P2.

[0031] Figure 4AThis is the equivalent circuit diagram of the impedance conversion circuit in the second embodiment. Figure 4B This is a schematic diagram showing the cross-sectional structure of the impedance conversion circuit of the second embodiment.

[0032] Figure 5A This is a coordinate graph showing the insertion loss of the impedance conversion circuits in the second embodiment and the comparative example. Figure 5B This is a graph showing the in-phase signal removal ratio of the impedance conversion circuit.

[0033] Figure 6A This is a coordinate graph showing the amplitude imbalance of the impedance conversion circuits in the second embodiment and the comparative example. Figure 6B This is a coordinate graph showing the phase imbalance of the impedance conversion circuit.

[0034] Figure 7 This is a coordinate graph showing the pass coefficient S24 from the fourth node P4 to the second node P2 of the impedance conversion circuit of the second embodiment and the comparative example.

[0035] Figure 8 This is the equivalent circuit diagram of the impedance conversion circuit in the third embodiment.

[0036] Figure 9A This is a coordinate graph showing the insertion loss of the impedance conversion circuits in the third embodiment and the comparative example. Figure 9B This is a graph showing the in-phase signal removal ratio of the impedance conversion circuit.

[0037] Figure 10A This is a coordinate graph showing the amplitude imbalance of the impedance conversion circuits in the third embodiment and the comparative example. Figure 10B This is a coordinate graph showing the phase imbalance of the impedance conversion circuit.

[0038] Figure 11 This is the equivalent circuit diagram of the impedance conversion circuit in the fourth embodiment.

[0039] Figure 12A This is a coordinate graph showing the insertion loss of the impedance conversion circuit of the fourth embodiment and the comparative example. Figure 12B This is a graph showing the in-phase signal removal ratio of the impedance conversion circuit.

[0040] Figure 13A This is a coordinate graph showing the amplitude imbalance of the impedance conversion circuits in the fourth embodiment and the comparative example. Figure 13B This is a coordinate graph showing the phase imbalance of the impedance conversion circuit.

[0041] Figure 14 This is a schematic equivalent circuit diagram of the impedance conversion circuit in the fifth embodiment.

[0042] Figure 15This is a schematic equivalent circuit diagram of the impedance conversion circuit of a variant of the fifth embodiment.

[0043] Figure 16 This is a schematic equivalent circuit diagram of an impedance conversion circuit of another variation of the fifth embodiment.

[0044] Figure 17 This is a schematic equivalent circuit diagram of an impedance conversion circuit, which is another variation of the fifth embodiment.

[0045] Figure 18 This is a schematic equivalent circuit diagram of an impedance conversion circuit, which is another variation of the fifth embodiment.

[0046] Figure 19 This is a schematic equivalent circuit diagram of an impedance conversion circuit, which is another variation of the fifth embodiment.

[0047] Figure 20 This is the equivalent circuit diagram of the impedance conversion circuit in the sixth embodiment.

[0048] Figure 21 This is an equivalent circuit diagram of the impedance conversion circuit of a variant of the sixth embodiment.

[0049] Figure 22 This is a schematic equivalent circuit diagram of the impedance conversion circuit in the seventh embodiment.

[0050] Figure 23 This is the equivalent circuit diagram of the impedance conversion circuit in the eighth embodiment.

[0051] Figure 24A This is a coordinate graph showing the insertion loss of the impedance conversion circuit of the eighth embodiment and the comparative example. Figure 24B This is a graph showing the in-phase signal removal ratio of the impedance conversion circuit.

[0052] Figure 25A This is a coordinate graph showing the amplitude imbalance of the impedance conversion circuits in the eighth embodiment and the comparative example. Figure 25B This is a coordinate graph showing the phase imbalance of the impedance conversion circuit.

[0053] Figure 26 This is the equivalent circuit diagram of the impedance conversion circuit in the ninth embodiment.

[0054] Figure 27A This is the equivalent circuit diagram of the impedance conversion circuit in the tenth embodiment. Figure 27B This is a coordinate graph showing the pass coefficient S24 from the fourth node P4 to the second node P2.

[0055] Figure 28A This is an equivalent circuit diagram of the impedance conversion circuit of the first variation of the tenth embodiment. Figure 28BThis is a coordinate graph showing the simulation results of the pass coefficient S24 from the fourth node P4 to the second node P2.

[0056] Figure 29 This is an equivalent circuit diagram of the impedance conversion circuit of the second variation of the tenth embodiment.

[0057] Figure 30A This is a coordinate graph showing the insertion loss of the impedance conversion circuit of the second modified example and comparative example of the tenth embodiment. Figure 30B This is a graph showing the in-phase signal removal ratio of the impedance conversion circuit.

[0058] Figure 31A This is a coordinate graph showing the amplitude imbalance of the impedance conversion circuit in the second modified example and comparative example of the tenth embodiment. Figure 31B This is a coordinate graph showing the phase imbalance of the impedance conversion circuit.

[0059] Figure 32 This is the equivalent circuit diagram of the impedance conversion circuit in the eleventh embodiment.

[0060] Figure 33A This is a coordinate graph showing the insertion loss of the impedance conversion circuit of the eleventh embodiment and the comparative example. Figure 33B This is a graph showing the in-phase signal removal ratio of the impedance conversion circuit.

[0061] Figure 34A This is a coordinate graph showing the amplitude imbalance of the impedance conversion circuit in the eleventh embodiment and the comparative example. Figure 34B This is a coordinate graph showing the phase imbalance of the impedance conversion circuit.

[0062] Figure 35 This is the equivalent circuit diagram of the impedance conversion circuit in the twelfth embodiment.

[0063] Figure 36 This is an exploded perspective view showing the conductor pattern of the impedance conversion circuit of the twelfth embodiment.

[0064] Figure 37 This is a block diagram of the high-frequency power amplifier in the thirteenth embodiment.

[0065] Figure 38 This is a block diagram of a high-frequency power amplifier according to a modified embodiment of the thirteenth example.

[0066] Figure 39 This is the equivalent circuit diagram of the Guanella-type balanced-unbalanced switching circuit disclosed in Non-Patent Document 1.

[0067] Explanation of reference numerals in the attached figures

[0068] 11. First main line;

[0069] 12. Second main line;

[0070] 21. First Sub-line;

[0071] 22 Second Sub-line;

[0072] 30-layer stacked substrate;

[0073] 40 Transmission line transformer;

[0074] 41 Power supply circuit;

[0075] 42 Differential Amplifier;

[0076] Impedance conversion circuit for 50BB differential signals;

[0077] 50BI balun / unbalanced converter circuit;

[0078] 50IB unbalanced to balanced converter circuit;

[0079] 50II Impedance conversion circuit for single-ended signals;

[0080] 51D differential amplifier;

[0081] 51S single-ended signal amplifier;

[0082] 101 First Main Line;

[0083] 102 Second Main Line;

[0084] 103 First Sub-line;

[0085] 104 Second Sub-line. Detailed Implementation

[0086] [First Embodiment]

[0087] Reference Figure 1A , Figure 1B and Figure 1C The impedance conversion circuit of the first embodiment will be described.

[0088] Figure 1A This is an equivalent circuit diagram of the impedance conversion circuit of the first embodiment. The impedance conversion circuit of the first embodiment includes a first main line 11, a second main line 12, a first auxiliary line 21, and a second auxiliary line 22 for transmitting high-frequency signals, and includes a capacitor Cp2. Figure 1AIn the diagram, the first secondary line 21 and the second secondary line 22 are marked with shaded lines. The first main line 11 and the second main line 12, which transmit high-frequency signals, are electromagnetically coupled to the first secondary line 21 and the second secondary line 22, respectively. The two ends of the first main line 11 are referred to as the first node P1 and the third node P3, respectively, and the two ends of the second main line 12 are referred to as the second node P2 and the fourth node P4, respectively.

[0089] The end of the first secondary line 21, corresponding to the end of the first main line 11 at the first node P1, is connected to the second node P2. The end of the second secondary line 22, corresponding to the end of the second main line 12 at the second node P2, is connected to the first node P1. The ends of the first secondary line 21, corresponding to the end of the first main line 11 at the third node P3, and the ends of the second secondary line 22, corresponding to the end of the second main line 12 at the fourth node P4, are interconnected.

[0090] Capacitor Cp2 is connected in parallel with the second main line 12.

[0091] When a high-frequency current flows in the first main line 11, a non-normal current flows in the first auxiliary line 21. Similarly, when a high-frequency current flows in the second main line 12, a non-normal current flows in the second auxiliary line 22. Figure 1A In the diagram, the reverse parallel arrows marking two coupled transmission lines indicate the flow of odd-mode currents in the two coupled transmission lines.

[0092] As an example, the turns ratio (ratio of line lengths) of the first main line 11 to the first secondary line 21, and the turns ratio (ratio of line lengths) of the second main line 12 to the second secondary line 22, are both 1:1. The impedance transformation ratio of the first main line 11 and the first secondary line 21 is equal to the impedance transformation ratio of the second main line 12 and the second secondary line 22. Therefore, the voltage between the two ends of the first secondary line 21 is equal to the voltage between the two ends of the first main line 11. Similarly, the voltage between the two ends of the second secondary line 22 is equal to the voltage between the two ends of the second main line 12. In other words, the voltage V1 between the end of the first main line 11 at the first node P1 and the corresponding end of the first secondary line 21 is equal to the voltage V3 between the end of the first main line 11 at the third node P3 and the corresponding end of the first secondary line 21. Similarly, the voltage V2 between the end of the second main line 12 at the second node P2 side and the corresponding end of the second sub-line 22 is equal to the voltage V4 between the end of the second main line 12 at the fourth node P4 side and the corresponding end of the second sub-line 22.

[0093] The first node P1, the second node P2, the third node P3, and the fourth node P4 are directly connected to the first connection terminal T1, the second connection terminal T2, the third connection terminal T3, and the fourth connection terminal T4 for external connection, respectively. The fourth connection terminal T4 is used as a grounding terminal. The grounding terminal is connected to the grounding potential of the mounting substrate, etc.

[0094] Figure 1B Figure 1B is a schematic cross-sectional view illustrating the impedance conversion circuit of the first embodiment. It does not show a specific cross-section of the impedance conversion circuit, but rather is a schematic diagram focusing on the electrical connections and electromagnetic coupling of the transmission lines. The first main line 11, the second main line 12, the first secondary line 21, and the second secondary line 22 can also be transmission lines such as microstrip lines. Figure 1B The description of the microstrip line's ground plane is omitted.

[0095] The impedance conversion circuit of the first embodiment includes a multilayer substrate 30, which includes a plurality of dielectric layers and a plurality of conductor layers stacked alternately. For the multilayer substrate 30, a multilayer resin substrate with stacked resin layers can be used, for example. As an example of a multilayer resin substrate, a printed wiring substrate is provided. Alternatively, a multilayer resin substrate using a liquid crystal polymer with a lower dielectric constant or a multilayer resin substrate using a fluorine-based resin can also be used. Furthermore, as the multilayer substrate 30, a ceramic multilayer substrate with stacked ceramic layers can also be used, for example. As examples of ceramic multilayer substrates, low-temperature co-fired ceramic (LTCC) substrates and substrates using ceramics fired at high temperatures are provided. Furthermore, as the multilayer substrate 30, a semiconductor substrate with multiple wiring layers can also be used. The first main line 11 and the second main line 12 are disposed on the same conductor layer, and the first sub-line 21 and the second sub-line 22 are disposed on the same conductor layer adjacent to the conductor layer where the first main line 11 and the second main line 12 are disposed in the thickness direction.

[0096] A pair of pads for mounting a capacitor Cp2 are provided on the upper surface of the laminated substrate 30, and the capacitor Cp2 is mounted on the surface of the pair of pads. A first connection terminal T1, a second connection terminal T2, a third connection terminal T3, and a fourth connection terminal T4 are provided on the lower surface of the laminated substrate 30 on the side opposite to the upper surface. The first main circuit 11, the second main circuit 12, the first sub-circuit 21, the second sub-circuit 22, the first connection terminal T1, the second connection terminal T2, the third connection terminal T3, and the fourth connection terminal T4 disposed on the laminated substrate 30, and the pads on the upper surface, are connected via vias and conductor patterns within the laminated substrate 30, thereby constituting... Figure 1A The impedance conversion circuit shown is used in this example. Figure 1B In the diagram, solid lines marked with black circles at both ends represent these vias and conductor patterns.

[0097] Next, the operation of the impedance conversion circuit in the first embodiment will be explained.

[0098] When differential signals RF+ and RF- are input to the terminal pairs including the first connection terminal T1 and the second connection terminal T2, a single-ended signal RF is output from the third connection terminal T3. The magnitude (RMS value) of the voltage between the first connection terminal T1 and the second connection terminal T2 is denoted as V0. At this time, voltages V1 and V2 are equal to voltage V0 (i.e., V1 = V2 = V0). In the first embodiment, V1 = V3 and V2 = V4 are true; therefore, voltages V3 and V4 are also equal to voltage V0 (i.e., V3 = V4 = V0). At this time, the voltage at the third connection terminal T3 becomes twice V0.

[0099] The magnitude (RMS value) of the current flowing in the first main line 11 and the second main line 12 is denoted as I0. The magnitude of the odd-mode current flowing in the first auxiliary line 21 and the second auxiliary line 22 is also equal to I0. Therefore, the magnitude of the current flowing in and out of the first connection terminal T1 and the second connection terminal T2 is equal to twice I0. In addition, the magnitude of the current flowing in and out of the third connection terminal T3 is equal to I0.

[0100] Thus, the voltage of the single-ended signal RF becomes twice the voltage of the differential signals RF+ and RF-, and the current of the single-ended signal RF becomes half the current of the differential signals RF+ and RF-. Therefore, when a load impedance is connected between the third connection terminal T3 and the fourth connection terminal T4, the impedance observed from the first connection terminal T1 and the second connection terminal T2 on the load side becomes one-quarter of the load impedance. Conversely, when a load impedance is connected between the first connection terminal T1 and the second connection terminal T2, the impedance observed from the third connection terminal T3 on the load side becomes four times the load impedance.

[0101] The impedance conversion circuit of the first embodiment has the function of performing balanced-unbalanced conversion and impedance conversion.

[0102] Furthermore, since capacitor Cp2 is connected in parallel with the second main circuit 12, the second main circuit 12 and capacitor Cp2 resonate in parallel at a certain frequency. At this resonant frequency, the second node P2 and the fourth node P4 are in a high-impedance state.

[0103] Next, the superior effects of the first embodiment will be described in comparison with the impedance conversion circuit of the comparative example. In the impedance conversion circuit of the comparative example, the capacitor Cp2 of the impedance conversion circuit of the first embodiment is not connected.

[0104] In the impedance conversion circuit of the comparative example, the second node P2 is connected to ground via the second main line 12. When the laminated substrate 30 uses a resin substrate, a low-temperature co-fired ceramic (LTCC) substrate, or a semiconductor substrate with multiple wiring layers, it is difficult to sufficiently increase the self-inductance of the second main line 12 compared to the case where a substrate made of magnetic material is used. Therefore, the isolation between the second node P2 and ground becomes insufficient. The decrease in isolation leads to an increase in insertion loss, a decrease in the in-phase signal rejection ratio, and an increase in amplitude imbalance and phase imbalance.

[0105] In the impedance conversion circuit of the first embodiment, capacitor Cp2 is connected in parallel with the second main line 12. Therefore, a parallel resonance occurs between the inductive component of the second main line 12 at a certain frequency and capacitor Cp2. When parallel resonance occurs, the second node P2 and the fourth node P4 (ground) become a high-impedance state. Therefore, sufficient isolation between the second node P2 and ground can be ensured.

[0106] In a structure where the first node P1 and the second node P2 are respectively connected to a pair of differential output nodes or differential input nodes of a differential amplifier, the characteristics of the impedance conversion circuit in the operating frequency band can be improved by setting the capacitance of capacitor Cp2 to generate parallel resonance in the operating frequency band of the differential amplifier. The impedance conversion circuit of the first embodiment is, for example, mounted on an RF front-end module.

[0107] Figure 1C This is a coordinate graph showing the simulation results of the pass factor S24 from the fourth node P4 to the second node P2. The horizontal axis represents frequency in "GHz", and the vertical axis represents the pass factor S24 in "dB". The solid line in the coordinate graph represents the simulation results of the impedance conversion circuit of the first embodiment with capacitor Cp2 connected, and the dashed line represents the simulation results of the impedance conversion circuit of the comparative example without capacitor Cp2 connected.

[0108] The simulation conditions are as follows.

[0109] The length, width, and thickness of the first main line 11, the second main line 12, the first auxiliary line 21, and the second auxiliary line 22 are set to 2000 μm, 25 μm, and 3 μm, respectively. The line spacing between the first main line 11 and the first auxiliary line 21, and between the second main line 12 and the second auxiliary line 22, are both set to 3 μm. The capacitance of capacitor Cp2 is set to 0.7 pF. The relative permittivity of the laminated substrate 30 is set to 4.

[0110] In the comparative example, isolation between the second node P2 and the fourth node P4 was ensured only around a frequency of 2.5 GHz. In contrast, when capacitor Cp2 was connected, isolation was also ensured around a frequency of 7 GHz. Therefore, even when operating around a frequency of 7 GHz, sufficient isolation between the second node P2 and the fourth node P4 can be ensured.

[0111] Next, refer to Figure 2A and Figure 2B The impedance conversion circuit of the first variation of the first embodiment will be described.

[0112] Figure 2A This is an equivalent circuit diagram of the impedance conversion circuit of the first variation of the first embodiment. In the first embodiment ( Figure 1A In the first embodiment, capacitor Cp2 is connected in parallel with the second main line 12. However, in the first variation of the first embodiment, capacitor Cp2 is not connected to the second main line 12. Instead, capacitor Cp1 is connected in parallel with the first main line 11.

[0113] Figure 2B This is a coordinate graph showing the simulation results of the pass factor S24 from the fourth node P4 to the second node P2. The horizontal axis represents frequency in "GHz", and the vertical axis represents the pass factor S24 in "dB". The solid line in the coordinate graph represents the impedance transformation circuit of the first variation of the first embodiment ( Figure 2A The simulation results are shown in the figure. The dashed line represents the simulation results of the impedance conversion circuit of the comparative example without capacitor Cp1 connected.

[0114] Simulation conditions other than the capacitance of capacitor Cp1 Figure 1C The simulation conditions shown are the same. The capacitance of capacitor Cp1 is set to 0.7pF. In this modified example, the conditions are the same as in the first embodiment ( Figure 1C Similarly, sufficient isolation is ensured near the 7GHz frequency.

[0115] Next, refer to Figure 3A and Figure 3B The impedance conversion circuit of the second variation of the first embodiment will be described.

[0116] Figure 3A This is an equivalent circuit diagram of the impedance conversion circuit in the second variation of the first embodiment. In the first embodiment ( Figure 1A In the first embodiment, capacitor Cp2 is connected to both ends of the second main line 12. However, in the second variation of the first embodiment, capacitor Cp2 is connected between the end of the second node P2 side of the second main line 12 and the midpoint of the second main line 12.

[0117] Figure 3BThis is a coordinate graph showing the simulation results of the pass factor S24 from the fourth node P4 to the second node P2. The horizontal axis represents frequency in "GHz", and the vertical axis represents the pass factor S24 in "dB". The solid line in the coordinate graph represents the impedance transformation circuit of the second variation of the first embodiment. Figure 3A The simulation results are shown in the figure. The dashed line represents the simulation results of the impedance conversion circuit of the comparative example without capacitor Cp2 connected.

[0118] Simulation conditions and Figure 1C The simulation conditions shown are the same. The length of the portion of the second main circuit 12 connected in parallel with capacitor Cp2 is 1000 μm. In the second variation of the first embodiment, the same as the first embodiment ( Figure 1A In contrast, the parallel resonant frequency of the second main line 12 and capacitor Cp2 changes, thereby ensuring sufficient isolation around 8 GHz. By changing the length of the portion of the second main line 12 connected in parallel with capacitor Cp2, the frequency range in which sufficient isolation is ensured can be varied.

[0119] [Second Embodiment]

[0120] Next, refer to Figures 4A to 7 The impedance conversion circuit of the second embodiment will be described with reference to the accompanying drawings. Hereinafter, the impedance conversion circuit of the second embodiment (…) will be discussed in relation to the first embodiment. Figure 1A , Figure 1B The common structure of impedance conversion circuits is omitted from the description.

[0121] Figure 4A This is the equivalent circuit diagram of the impedance conversion circuit in the second embodiment. Figure 4B This is a schematic cross-sectional view illustrating the impedance conversion circuit of the second embodiment. In the second embodiment, in addition to a capacitor Cp2 connected in parallel with the second main line 12, a capacitor Cp1 connected in parallel with the first main line 11 is also included. Capacitor Cp1 ( Figure 4B It is mounted on the upper surface of the laminated substrate 30 in the same manner as capacitor Cp2.

[0122] A simulation was performed to confirm the superior performance of the second embodiment. The simulation will be described below.

[0123] The insertion loss, in-phase rejection ratio (CMRR), amplitude imbalance, and phase imbalance of the impedance conversion circuit in the second embodiment and the comparative example were determined through simulation. The impedance conversion circuit of the comparative example is the same as the impedance conversion circuit of the second embodiment except that capacitors Cp1 and Cp2 have been removed. Simulation conditions and reference... Figure 1C The simulation conditions are the same as in the first embodiment described. It should be noted that the capacitance of capacitors Cp1 and Cp2 is 0.7pF.

[0124] Figure 5A This is a graph showing the insertion loss of an impedance conversion circuit. The horizontal axis represents frequency in "GHz", and the vertical axis represents insertion loss in "dB". It should be noted that the insertion loss increases towards the bottom of the vertical axis. Here, insertion loss refers to the insertion loss when the first connection terminal T1 and the second connection terminal T2 are driven by a differential signal and a single-ended signal is output from the third connection terminal T3. Figure 5A The solid and dashed lines in the coordinate graph represent the insertion loss of the impedance conversion circuits of the second embodiment and the comparative example, respectively. It can be seen that the insertion loss of the impedance conversion circuit of the second embodiment is improved in the frequency range below approximately 5.3 GHz.

[0125] Figure 5B This is a graph showing the non-inverting signal rejection ratio (CMRR) of the impedance switching circuit. The horizontal axis represents frequency in "GHz", and the vertical axis represents the non-inverting signal rejection ratio in "dB". Figure 5B The solid and dashed lines in the coordinate graph represent the in-phase signal removal ratios of the second embodiment and the comparative example, respectively. The definition of the in-phase signal removal ratio is explained below.

[0126] When the responses of the single-ended signal output from the third connection terminal T3 when the first connection terminal T1 and the second connection terminal T2 are driven by differential and in-phase signals, respectively, are labeled SSD12 and SSC12, the in-phase signal rejection ratio (CMRR) is defined as CMRR = SSD12 / SSC12. In the case of an ideal balanced-to-unbalanced impedance conversion circuit, the response SSC12 of the single-ended signal output from the third connection terminal T3 when the first connection terminal T1 and the second connection terminal T2 are driven by an in-phase signal is approximately zero. Therefore, it can be said that the larger the value of the in-phase signal rejection ratio (CMRR), the better the characteristics of the balanced-to-unbalanced impedance conversion circuit.

[0127] like Figure 5B As shown, in a frequency range of approximately 2 GHz and above to 6.5 GHz, the in-phase signal removal ratio of the impedance conversion circuit in the second embodiment is greater than that of the impedance conversion circuit in the comparative example. That is, the characteristics as a balanced-to-unbalanced conversion circuit are improved.

[0128] Figure 6A and Figure 6B These are coordinate graphs showing the amplitude imbalance and phase imbalance of the impedance conversion circuit, respectively. Figure 6A and Figure 6B The horizontal axis represents frequency in units of "GHz". Figure 6A The vertical axis represents the amplitude imbalance in dB. Figure 6B The vertical axis represents the phase imbalance in degrees. Figure 6A and Figure 6B The solid and dashed lines in the coordinate graph represent the simulation results of the impedance conversion circuits in the second embodiment and the comparative example, respectively. The definitions of amplitude imbalance and phase imbalance are explained below.

[0129] The response of the single-ended signal output from the third connection terminal T3 when the first connection terminal T1 is driven by a single-ended signal is denoted as S13, and the response of the single-ended signal output from the third connection terminal T3 when the second connection terminal T2 is driven by a single-ended signal is denoted as S23. The imbalance degree IMB is defined as IMB = -S13 / S23. Amplitude imbalance and phase imbalance are the amplitude and phase components of the imbalance degree IMB, respectively. It can be said that the closer the amplitude imbalance is to 0dB and the closer the phase imbalance is to 0 degrees, the better the characteristics of the balanced-to-unbalanced conversion circuit.

[0130] like Figure 6A and Figure 6B As shown, by adopting the impedance conversion circuit structure of the second embodiment, the amplitude imbalance and phase imbalance are improved in the frequency range of approximately 6 GHz and below.

[0131] Figure 7 This is a coordinate graph showing the simulation results of the pass factor S24 from the fourth node P4 to the second node P2. The horizontal axis represents frequency in "GHz", and the vertical axis represents the pass factor S24 in "dB". The solid line in the coordinate graph represents the simulation results of the impedance conversion circuit of the second embodiment, and the dashed line represents the simulation results of the impedance conversion circuit of the comparative example.

[0132] In the first embodiment ( Figure 1C In the first embodiment, sufficient isolation is ensured around 7 GHz, but in the second embodiment, sufficient isolation is ensured around 5 GHz. By adjusting the capacitances of capacitors Cp1 and Cp2, the frequency range in which sufficient isolation is ensured can be varied. In the second embodiment, sufficient isolation between the second node P2 and the fourth node P4 can also be ensured within a specific frequency range.

[0133] according to Figures 5A to 7 The simulation results shown in the attached figure confirm that the characteristics of the impedance conversion circuit are improved by connecting capacitors Cp1 and Cp2 in parallel with the first main line 11 and the second main line 12, respectively.

[0134] Furthermore, by connecting capacitor Cp2 in parallel with the second main line 12 and capacitor Cp1 in parallel with the first main line 11, the symmetry between the first main line 11 and the second main line 12 can be maintained. To maintain symmetry, it is preferable to make the inductances of the first main line 11 and the second main line 12 equal, and to make the capacitances of capacitors Cp1 and Cp2 equal.

[0135] [Third Embodiment]

[0136] Next, refer to Figures 8 to 10B The impedance conversion circuit of the third embodiment is described in the accompanying drawings. The following description refers to the circuit with reference to... Figures 4A to 7 The common structure of the impedance conversion circuit of the second embodiment illustrated in the accompanying drawings is omitted from the description.

[0137] Figure 8 This is the equivalent circuit diagram of the impedance conversion circuit in the third embodiment. In the second embodiment (Figure 4A), the turns ratio (line length ratio) of the first main line 11 to the first auxiliary line 21 and the turns ratio (line length ratio) of the second main line 12 to the second auxiliary line 22 are both 1:1. In contrast, in the third embodiment, the turns ratio (line length ratio) of the first main line 11 to the first auxiliary line 21 and the turns ratio (line length ratio) of the second main line 12 to the second auxiliary line 22 are both 2:1.

[0138] In addition, in the second embodiment ( Figure 4A In the first main line 11, capacitors Cp1 and Cp2 are connected to the two ends of the second main line 12, respectively. In contrast, in the third embodiment, capacitor Cp1 is connected in parallel with a portion of the first main line 11, and capacitor Cp2 is connected in parallel with a portion of the second main line 12. For example, capacitor Cp2 is connected between the second node P2 and the midpoint of the second main line 12. That is, capacitor Cp2 is connected in parallel with the inductive component of a portion of the second main line 12. Similarly, capacitor Cp1 is connected between the first node P1 and the midpoint of the first main line 11.

[0139] Next, the operation of the impedance conversion circuit in the third embodiment will be explained.

[0140] In the impedance conversion circuit of the third embodiment, the voltage between the third connection terminal T3 and the fourth connection terminal T4 is three times the voltage between the first connection terminal T1 and the second connection terminal T2. Furthermore, the current flowing in and out of the third connection terminal T3 is one-third the current flowing in and out of the first connection terminal T1 and the second connection terminal T2.

[0141] Thus, the voltage of the single-ended signal RF appearing in the third connection terminal T3 is three times the voltage of the differential signals RF+ and RF- appearing in the first connection terminal T1 and the second connection terminal T2, and the current of the single-ended signal RF is one-third the current of the differential signals RF+ and RF-. Therefore, when a load impedance is connected between the third connection terminal T3 and the fourth connection terminal T4, the impedance observed from the first connection terminal T1 and the second connection terminal T2 is one-ninth of the load impedance. Conversely, when a load impedance is connected between the first connection terminal T1 and the second connection terminal T2, the impedance observed from the third connection terminal T3 is nine times the load impedance. Thus, the impedance conversion ratio of the impedance conversion circuit in the third embodiment is 9.

[0142] Furthermore, in the third embodiment, a portion of the second main line 12 resonates in parallel with capacitor Cp2. When this portion of the second main line 12 resonates in parallel with capacitor Cp2, a high impedance state is achieved between the second node P2 and the fourth node P4 (ground). Therefore, as in the second embodiment, sufficient isolation between the second node P2 and ground can be ensured. Additionally, by connecting capacitor Cp1 in parallel with a portion of the first main line 11, the symmetry between the first main line 11 and the second main line 12 can be maintained.

[0143] Next, refer to Figures 9A to 10B The accompanying drawings illustrate the simulation results performed to confirm the superior performance of the third embodiment. The lengths of the first main line 11 and the second main line 12 of the impedance conversion circuit in the simulation are set to 3200 μm, and the width is set to 30 μm. The lengths of the first auxiliary line 21 and the second auxiliary line 22 are set to 1600 μm, and the width is set to 34 μm. The capacitances of capacitors Cp1 and Cp2 are set to 0.3 pF. Other simulation conditions are the same as in the first embodiment. Figure 1C The simulation conditions shown are the same.

[0144] Figure 9A , Figure 9B , Figure 10A and Figure 10B Compared with the second embodiment Figure 5A , Figure 5B , Figure 6A and Figure 6B Similarly, graphs are shown illustrating the insertion loss, in-phase signal removal ratio, amplitude imbalance, and phase imbalance of the impedance conversion circuit. The solid and dashed lines in these graphs represent the simulation results of the impedance conversion circuits in the third embodiment and the comparative example without capacitors Cp1 and Cp2, respectively.

[0145] like Figure 9AAs shown, the impedance transformation circuit of the third embodiment does not show any improvement in insertion loss compared to the impedance transformation circuit of the comparative example. Figure 9B As shown, in the impedance conversion circuit of the third embodiment, the in-phase signal removal ratio is improved in a frequency range of approximately 3 GHz and above to 5.3 GHz. Figure 10A As shown, in the impedance transformation circuit of the third embodiment, the amplitude imbalance is improved in a frequency range of approximately 2 GHz to 5 GHz. Figure 10B As shown, in the impedance conversion circuit of the third embodiment, the phase imbalance is improved in a frequency range of approximately 3 GHz and above to 5 GHz.

[0146] according to Figures 9A to 10B The simulation results shown in the attached figure confirm that the characteristics of the impedance conversion circuit are improved by connecting capacitors Cp1 and Cp2 in parallel with a portion of the first main line 11 and a portion of the second main line 12, respectively.

[0147] Next, a variation of the third embodiment will be described.

[0148] In the third embodiment, the turns ratio (line length ratio) of the first main line 11 to the first auxiliary line 21 and the turns ratio (line length ratio) of the second main line 12 to the second auxiliary line 22 are both 2:1. This turns ratio can also be set to something other than 2:1. Therefore, the impedance transformation ratio can be adjusted.

[0149] [Fourth Embodiment]

[0150] Next, refer to Figures 11 to 13B The impedance conversion circuit of the fourth embodiment will be described in the accompanying drawings. Hereinafter, with reference to the drawings... Figures 8 to 10B The common structure of the impedance conversion circuit of the third embodiment, illustrated in the accompanying drawings, is omitted from the description.

[0151] Figure 11 This is the equivalent circuit diagram of the impedance conversion circuit in the fourth embodiment. In the impedance conversion circuit of the third embodiment ( Figure 8 In the first main line 11, capacitor Cp2 is connected in parallel with a portion of the second main line 12, and capacitor Cp1 is connected in parallel with a portion of the first main line 11. In contrast, in the fourth embodiment, capacitor Cp2 is connected to both ends of the second main line 12, and capacitor Cp1 is connected to both ends of the first main line 11.

[0152] The impedance conversion ratio of the impedance conversion circuit in the fourth embodiment is the same as that of the impedance conversion circuit in the third embodiment.

[0153] Next, the superior effects of the fourth embodiment will be explained.

[0154] In the fourth embodiment, the second main line 12 is connected in parallel with capacitor Cp2 for resonance, thereby ensuring sufficient isolation between the second node P2 and the fourth node P4 (grounded). Furthermore, since capacitor Cp1 is connected in parallel with the first main line 11, the symmetry between the first main line 11 and the second main line 12 is ensured.

[0155] Next, refer to Figures 12A to 13B The accompanying drawings illustrate the simulation results performed to confirm the superior performance of the fourth embodiment. The lengths of the first main line 11 and the second main line 12 of the impedance conversion circuit in the simulation are set to 3200 μm, and the width is set to 30 μm. The lengths of the first auxiliary line 21 and the second auxiliary line 22 are set to 1600 μm, and the width is set to 34 μm. The capacitances of capacitors Cp1 and Cp2 are set to 0.3 pF. Other simulation conditions are the same as in the first embodiment. Figure 1C The simulation conditions shown are the same.

[0156] Figure 12A , Figure 12B , Figure 13A and Figure 13B Compared with the third embodiment Figure 9A , Figure 9B , Figure 10A and Figure 10B Similarly, graphs are shown illustrating the insertion loss, in-phase signal removal ratio, amplitude imbalance, and phase imbalance of the impedance conversion circuit. The solid and dashed lines in these graphs represent simulation results of the impedance conversion circuits in the fourth embodiment and the comparative example without capacitors Cp1 and Cp2, respectively.

[0157] like Figure 12A As shown, the impedance transformation circuit of the fourth embodiment shows an improvement in insertion loss in a frequency range of approximately 1.5 GHz and above to 3 GHz compared to the impedance transformation circuit of the comparative example. Figure 12B As shown, in the impedance transformation circuit of the fourth embodiment, the in-phase signal removal ratio is improved in a frequency range of approximately 2 GHz and above to 4.2 GHz. Figure 13A As shown, in the impedance transformation circuit of the fourth embodiment, the amplitude imbalance is improved in a frequency range of approximately 2 GHz to 4 GHz. Figure 13B As shown, in the impedance conversion circuit of the fourth embodiment, the phase imbalance is improved in a frequency range of approximately 3 GHz and above to 4 GHz.

[0158] according to Figures 12A to 13B The simulation results shown in the attached figure confirm that the characteristics of the impedance conversion circuit are improved by connecting capacitors Cp1 and Cp2 in parallel with the first main line 11 and the second main line 12, respectively.

[0159] [Fifth Embodiment]

[0160] Next, refer to Figure 14 The impedance conversion circuit of the fifth embodiment will be described below. Hereinafter, it will be discussed in relation to the reference circuit. Figures 4A to 7 The common structure of the impedance conversion circuit of the second embodiment illustrated in the accompanying drawings is omitted from the description.

[0161] Figure 14 This is a schematic equivalent circuit diagram of the impedance conversion circuit in the fifth embodiment. Figure 14 In the middle, the dashed lines indicate the inclusion of the second embodiment ( Figure 4A The impedance conversion circuit comprises a first main line 11, a second main line 12, a first auxiliary line 21, and a second auxiliary line 22, and a transmission line transformer 40. The transmission line transformer 40 has a first node P1, a second node P2, a third node P3, and a fourth node P4 as input and output nodes for high-frequency signals.

[0162] Second embodiment ( Figure 4A In the first embodiment, the first node P1 and the third node P3 are directly connected to the first connecting terminal T1 and the third connecting terminal T3, respectively, and the second node P2 and the fourth node P4 are directly connected to the second connecting terminal T2 and the fourth connecting terminal T4, respectively. In contrast, in the fifth embodiment, capacitors Cdc1, Cdc2, Cdc3, and Cdc4 are connected in series between the first node P1 and the first connecting terminal T1, between the second node P2 and the second connecting terminal T2, between the third node P3 and the third connecting terminal T3, and between the fourth node P4 and the fourth connecting terminal T4.

[0163] The first connection terminal T1 and the second connection terminal T2 are used as input / output terminals for differential signals RF+ and RF-, respectively. The third connection terminal T3 is used as an input / output terminal for a single-ended signal RF. The fourth connection terminal T4 is connected to ground.

[0164] Capacitors Cdc1, Cdc2, Cdc3, and Cdc4 function as impedance matching capacitors and DC cutoff capacitors.

[0165] Next, the superior effects of the fifth embodiment will be explained.

[0166] In the fifth embodiment, by connecting capacitors Cdc1, Cdc2, Cdc3, and Cdc4, the DC component of the signal input to and output from the transmission line transformer 40 can be removed. Furthermore, by appropriately setting the capacitance of capacitors Cdc1, Cdc2, Cdc3, and Cdc4, the input impedance of the impedance conversion circuit can be adjusted to the target value.

[0167] Next, the impedance conversion circuit of the modified example of the fifth embodiment will be described. In the fifth embodiment, capacitors Cdc1, Cdc2, Cdc3, and Cdc4 are connected to the first node P1, the second node P2, the third node P3, and the fourth node P4. However, it is also possible to connect capacitors only on the input side and the output side of the signal. In addition, as the transmission line transformer 40, in addition to the structure of the second embodiment, the first embodiment can also be used (…). Figure 1A ), Third embodiment ( Figure 8 ), Fourth embodiment ( Figure 11 The structure of the impedance conversion circuit.

[0168] Next, refer to Figures 15 to 19 The accompanying drawings illustrate impedance conversion circuits for various other modifications of the fifth embodiment. Figure 15 , Figure 16 , Figure 17 , Figure 18 and Figure 19 This is a schematic equivalent circuit diagram of the impedance conversion circuit of a variant of the fifth embodiment.

[0169] exist Figure 15 In the modified example shown, inductors Lz1, Lz2, Lz3, and Lz4 are used instead of capacitors Cdc1, Cdc2, Cdc3, and Cdc4 in the impedance matching circuit of the fifth embodiment. Based on the inductance of inductor Lz4 and the design frequency of the impedance matching circuit, the impedance of inductor Lz4 is sufficiently low, thus allowing the fourth node P4 to be grounded at a high frequency. In this case, inductor Lz4 achieves impedance matching.

[0170] exist Figure 16 In the variant shown, instead of the fifth embodiment ( Figure 14 The impedance conversion circuit has capacitors Cdc1, Cdc2, Cdc3, and Cdc4. A capacitor Cmn1 is connected between the first node P1 and the second node P2, and a capacitor Cmn2 is connected between the third node P3 and the fourth node P4.

[0171] exist Figure 17 In the variant shown, instead of Figure 16 The capacitors Cmn1 and Cmn2 in the modified example shown use inductors Lmn1 and Lmn2, respectively. Figure 18 In the variations shown, except for the fifth embodiment ( Figure 14 In addition to capacitors Cdc1, Cdc2, Cdc3, and Cdc4 in the impedance conversion circuit, capacitor Cmn1 is connected between the first node P1 and the second node P2, and capacitor Cmn2 is connected between the third node P3 and the fourth node P4. Figure 19In the variant shown, instead of Figure 18 The capacitors Cmn1 and Cmn2 in the modified example shown use inductors Lmn1 and Lmn2 respectively.

[0172] As in the aforementioned variation, reactive elements can also be inserted in series between at least one of the following: between the first node P1 and the first connection terminal T1; between the second node P2 and the second connection terminal T2; between the third node P3 and the third connection terminal T3; and between the fourth node P4 and the fourth connection terminal T4. Alternatively, reactive elements can be inserted in parallel with the transmission line transformer 40 between at least one of the following: between the first node P1 and the second node P2; and between the third node P3 and the fourth node P4. By adjusting the capacitance or inductance of these reactive elements, the input impedance of the impedance conversion circuit can be adjusted to the target value.

[0173] [Sixth Embodiment]

[0174] Next, refer to Figure 20 The amplification module of the sixth embodiment will be described. The amplification module of the sixth embodiment is equipped with the impedance conversion circuit of the second embodiment. Figure 4A The following is for reference only. Figures 4A to 6B The common structure of the impedance conversion circuit of the second embodiment illustrated in the accompanying drawings is omitted from the description.

[0175] Figure 20 This is an equivalent circuit diagram of the impedance conversion circuit of the sixth embodiment. In the impedance conversion circuit of the sixth embodiment, a power supply circuit 41 is connected at the point where the first secondary line 21 and the second secondary line 22 are interconnected. The power supply circuit 41 includes a choke coil Lch, a bypass capacitor Cbp, and a power supply terminal Vcc.

[0176] The connection point between the first auxiliary circuit 21 and the second auxiliary circuit 22 is connected to the power supply terminal Vcc via a choke Lch. A power supply voltage is applied to the power supply terminal Vcc from an external power supply circuit. A bypass capacitor Cbp is connected between the power supply terminal Vcc and ground.

[0177] A pair of output terminals of the differential amplifier 42 are connected to the first connection terminal T1 and the second connection terminal T2, respectively. For example, the differential amplifier 42 includes bipolar transistors Q1 and Q2 with their emitters grounded, and the collectors of bipolar transistors Q1 and Q2 are connected to the first connection terminal T1 and the second connection terminal T2, respectively.

[0178] A power supply voltage is applied to the collector of bipolar transistor Q1 via the power supply terminal Vcc, choke Lch, and second auxiliary line 22. Additionally, a power supply voltage is applied to the collector of bipolar transistor Q2 via the power supply terminal Vcc, choke Lch, and first auxiliary line 21.

[0179] Next, the superior effects of the sixth embodiment will be explained.

[0180] In the sixth embodiment, power can be supplied to the differential amplifier 42, which is connected to the first connection terminal T1 and the second connection terminal T2, via an impedance conversion circuit. Additionally, power can be supplied to the two bipolar transistors Q1 and Q2 via a choke coil Lch.

[0181] Next, refer to Figure 21 The impedance conversion circuit of the modified example of the sixth embodiment will be described.

[0182] Figure 21 This is an equivalent circuit diagram of the impedance conversion circuit in a modified embodiment of the sixth embodiment. In this modified embodiment, a capacitor Cdc3 is inserted in series between the third node P3 and the third connection terminal T3, and a capacitor Cdc4 is inserted in series between the fourth node P4 and the fourth connection terminal T4 (ground). By inserting capacitors Cdc3 and Cdc4, the impedance observed from the differential amplifier 42 on the load side can be adjusted.

[0183] [Seventh Embodiment]

[0184] Next, refer to Figure 22 The impedance conversion circuit of the seventh embodiment will be described below. Hereinafter, it will be described in relation to the reference circuit. Figure 20 The common structure of the impedance conversion circuit in the sixth embodiment described herein is omitted from the description.

[0185] Figure 22 This is a schematic equivalent circuit diagram of the impedance conversion circuit in the seventh embodiment. In the sixth embodiment ( Figure 20 In the first embodiment, a power supply circuit 41 is connected at the point where the first auxiliary line 21 and the second auxiliary line 22 are interconnected. In contrast, in the seventh embodiment, the power supply circuit 41 is connected to the first connection terminal T1 and the second connection terminal T2 on the differential signal input side.

[0186] For example, the power supply terminal Vcc is connected to the first connection terminal T1 and the second connection terminal T2 via choke coils Lch1 and Lch2, respectively. The power supply terminal Vcc is also connected to ground via a bypass capacitor Cbp. In the sixth embodiment ( Figure 20 In the first embodiment, the first connecting terminal T1 is directly connected to the first node P1, and the second connecting terminal T2 is directly connected to the second node P2. In contrast, in the seventh embodiment, a capacitor Cdc1 is connected in series between the first connecting terminal T1 and the first node P1, and a capacitor Cdc2 is connected in series between the second connecting terminal T2 and the second node P2. Furthermore, compared to a variation of the sixth embodiment (…),… Figure 21Similarly, capacitors Cdc3 and Cdc4 are connected between the third node P3 and the third connection terminal T3, and between the fourth node P4 and the fourth connection terminal T4, respectively.

[0187] Next, the superior effects of the seventh embodiment will be explained.

[0188] In the seventh embodiment, power can be supplied to the differential amplifier 42 from the power supply circuit 41 connected to the first connection terminal T1 and the second connection terminal T2 of the impedance conversion circuit. In the sixth embodiment, in order to supply power to the differential amplifier 42 via the first auxiliary line 21 and the second auxiliary line 22, it is not possible to insert capacitors in series between the differential amplifier 42 and the first node P1 and between the differential amplifier 42 and the second node P2. In contrast, in the seventh embodiment, capacitors Cdc1 and Cdc2 can be inserted in series between the differential amplifier 42 and the first node P1 and between the differential amplifier 42 and the second node P2, respectively. Therefore, the excellent effect of increased freedom in impedance adjustment can be obtained.

[0189] [Eighth Embodiment]

[0190] Next, refer to Figures 23 to 25B The impedance conversion circuit of the eighth embodiment will be described with reference to the accompanying drawings. Hereinafter, the impedance conversion circuit will be described with reference to the accompanying drawings. Figures 4A to 6B The common structure of the impedance conversion circuit of the second embodiment illustrated in the accompanying drawings is omitted from the description.

[0191] Figure 23 This is an equivalent circuit diagram of the impedance conversion circuit in the eighth embodiment. In the second embodiment (Fig. 4A), the fourth connection terminal T4 connected to the fourth node P4 is a grounding terminal, and the fourth node P4 is connected to ground. In contrast, in the eighth embodiment, the second connection terminal T2 connected to the second node P2 is a grounding terminal, and the second node P2 is connected to ground.

[0192] In the eighth embodiment, the first connection terminal T1 is used as an input / output terminal for a single-ended signal RF, and the third connection terminal T3 and the fourth connection terminal T4 are used as input / output terminals for differential signals RF+ and RF-. In the second embodiment ( Figure 4A In the first embodiment, when converting the differential signals RF+ and RF- into single-ended signals RF, the impedance observed on the load side is multiplied by 1 / 4, and when converting the single-ended signal RF into differential signals RF+ and RF-, the impedance observed on the load side is multiplied by 4. Conversely, in the eighth embodiment, the impedance observed on the load side is multiplied by 4 when converting the differential signals RF+ and RF- into single-ended signals RF, and the impedance observed on the load side is multiplied by 1 / 4 when converting the single-ended signal RF into differential signals RF+ and RF-.

[0193] Next, the superior effects of the eighth embodiment will be explained. In the eighth embodiment, similarly to the second embodiment, capacitor Cp2 is connected in parallel with the second main line 12, thus ensuring sufficient isolation between the fourth node P4 and the second node P2 (grounded). Furthermore, capacitor Cp1 is also connected in parallel with the first main line 11, thus maintaining the symmetry between the first main line 11 and the second main line 12.

[0194] Next, refer to Figures 24A to 25B The accompanying drawings illustrate the simulation results performed to confirm the superior performance of the eighth embodiment. The lengths of the first main line 11, the second main line 12, the first auxiliary line 21, and the second auxiliary line 22 of the impedance conversion circuit in the simulation object are each set to 2000 μm, and the widths are set to 25 μm. The capacitances of capacitors Cp1 and Cp2 are set to 0.7 pF. Other simulation conditions are the same as... Figure 1C The simulation conditions in the first embodiment shown are the same.

[0195] Figure 24A , Figure 24B , Figure 25A and Figure 25B Compared with the second embodiment Figure 5A , Figure 5B , Figure 6A and Figure 6B Similarly, a coordinate graph showing the insertion loss, in-phase signal removal ratio, amplitude imbalance, and phase imbalance of the impedance conversion circuit is also provided. Figure 24A , Figure 24B , Figure 25A The solid and dashed lines in the coordinate graph of Figure 25B represent the simulation results of the impedance conversion circuits of the eighth embodiment and the comparative example without capacitors Cp1 and Cp2, respectively. Figure 24A The insertion loss shown refers to the insertion loss when the third connection terminal T3 and the fourth connection terminal T4 are driven by differential signals RF+ and RF- and a single-ended signal is output from the first connection terminal T1.

[0196] like Figure 24A As shown, the impedance transformation circuit of the eighth embodiment shows an improvement in insertion loss in a frequency range of approximately 1.5 GHz and above to 6 GHz compared to the impedance transformation circuit of the comparative example. Figure 24B As shown, in the impedance conversion circuit of the eighth embodiment, the in-phase signal removal ratio is improved in a frequency range of approximately 2 GHz and above to 7 GHz. Figure 25A As shown, in the impedance transformation circuit of the eighth embodiment, amplitude imbalance is improved in a frequency range of approximately 3 GHz to 8 GHz. Figure 25BAs shown, in the impedance conversion circuit of the eighth embodiment, the phase imbalance is improved in a frequency range of approximately 3 GHz and above to 6 GHz.

[0197] according to Figures 24A to 25B The simulation results shown in the attached figure confirm that the characteristics of the impedance conversion circuit are also improved in the structure that connects the second node P2 to ground.

[0198] [Ninth Embodiment]

[0199] Next, refer to Figure 26 The impedance conversion circuit of the ninth embodiment will be described below. Hereinafter, it will be described in relation to the reference circuit. Figures 4A to 6B The common structure of the impedance conversion circuit of the second embodiment illustrated in the accompanying drawings is omitted from the description.

[0200] Figure 26 This is an equivalent circuit diagram of the impedance conversion circuit of the ninth embodiment. In the second embodiment (Fig. 4A), the impedance conversion circuit is connected to ground via the fourth node P4 and functions as a balanced-to-unbalanced conversion circuit. In contrast, in the ninth embodiment, no node of the impedance conversion circuit is connected to ground. The terminal pairs including the first connection terminal T1 and the second connection terminal T2, and the terminal pairs including the third connection terminal T3 and the fourth connection terminal T4, are used as input / output terminals for differential signals RF+ and RF-. That is, the impedance conversion circuit of the ninth embodiment operates as a differential signal impedance conversion circuit on both the input and output sides.

[0201] Next, the superior effects of the ninth embodiment will be explained.

[0202] In the ninth embodiment, by connecting capacitor Cp1 in parallel with the first main line 11, the isolation between the first node P1 and the third node P3 can be improved within a frequency range including the parallel resonant frequency. By connecting capacitor Cp2 in parallel with the second main line 12, the isolation between the second node P2 and the fourth node P4 can be improved within a frequency range including the parallel resonant frequency.

[0203] [Tenth Embodiment]

[0204] Next, refer to Figure 27A and Figure 27B The tenth embodiment will be described below. Hereinafter, the description will focus on the embodiment with reference to... Figures 1A to 1C The common structure of the impedance conversion circuit of the first embodiment illustrated in the accompanying drawings is omitted from the description.

[0205] Figure 27AThis is an equivalent circuit diagram of the impedance conversion circuit of the tenth embodiment. In the first embodiment (Fig. 1A), capacitor Cp2 is connected in parallel with the second main line 12. In contrast, in the tenth embodiment, capacitor Cp4 is connected in parallel with the second auxiliary line 22.

[0206] Next, the superior effects of the tenth embodiment will be explained.

[0207] Since capacitor Cp4 is connected in parallel with the second auxiliary line 22, the inductive component of the second auxiliary line 22 resonates in parallel with capacitor Cp4 at a certain frequency. Within the frequency range encompassing this resonant frequency, the two ends of the second auxiliary line 22 become a high-impedance state. Therefore, the second node P2 and the fourth node P4 (ground) at the two ends of the second main line 12, which is electromagnetically coupled to the second auxiliary line 22, become a high-impedance state. As a result, sufficient isolation can be ensured between the second node P2 and ground.

[0208] Figure 27B This is a coordinate graph showing the simulation results of the pass factor S24 from the fourth node P4 to the second node P2. The horizontal axis represents frequency in "GHz", and the vertical axis represents the pass factor S24 in "dB". The solid line in the coordinate graph represents the simulation results of the impedance conversion circuit of the tenth embodiment, and the dashed line represents the simulation results of the impedance conversion circuit of the comparative example without capacitor Cp4 connected.

[0209] Simulation conditions and references other than those related to capacitors Figure 1C The simulation conditions in the first embodiment described are the same. It should be noted that the capacitance of capacitor Cp4 is set to 0.7pF.

[0210] In the comparative example, isolation between the second node P2 and the fourth node P4 was ensured only around a frequency of 2.5 GHz. In contrast, when capacitor Cp4 was connected, isolation was also ensured around a frequency of 7.3 GHz. Therefore, even when operating around a frequency of 7.3 GHz, sufficient isolation between the second node P2 and the fourth node P4 can be ensured.

[0211] Next, refer to Figure 28A and Figure 28B The first variation of the tenth embodiment will be described.

[0212] Figure 28A This is an equivalent circuit diagram of the impedance conversion circuit in the first variation of the tenth embodiment. In this variation, capacitor Cp4 is not connected. Figure 27A The capacitor Cp3 is connected in parallel with the first auxiliary line 21.

[0213] Figure 28BThis is a coordinate graph showing the simulation results of the pass coefficient S24 from the fourth node P4 to the second node P2. The horizontal axis represents frequency in "GHz", and the vertical axis represents the pass coefficient S24 in "dB". The solid line in the coordinate graph represents the simulation results of the impedance conversion circuit of the first variant of the tenth embodiment, and the dashed line represents the simulation results of the impedance conversion circuit of the comparative example without capacitor Cp3 connected.

[0214] Simulation conditions and references other than those related to capacitors Figure 1C The simulation conditions in the first embodiment described are the same. It should be noted that the capacitance of capacitor Cp3 is set to 0.7pF.

[0215] In the first variation of the tenth embodiment, it can be seen that isolation is also ensured near the frequency of 7.5 GHz.

[0216] Next, refer to Figures 29 to 31B The accompanying drawings illustrate the impedance conversion circuit of the second variation of the tenth embodiment.

[0217] Figure 29 This is an equivalent circuit diagram of the impedance conversion circuit in the second variation of the tenth embodiment. In the tenth embodiment ( Figure 27A In this embodiment, capacitor Cp4 is connected in parallel with the second auxiliary line 22. In this modified example, capacitor Cp3 is also connected in parallel with the first auxiliary line 21.

[0218] Next, the superior effects of the second variation of the tenth embodiment will be explained. In the second variation of the tenth embodiment, similar to the tenth embodiment, the isolation between the second node P2 and ground can be ensured. Furthermore, since capacitors Cp3 and Cp4 are connected in parallel with the first sub-line 21 and the second sub-line 22, respectively, the symmetry of the coupled transmission line including the first main line 11 and the first sub-line 21 and the coupled transmission line including the second main line 12 and the second sub-line 22 can be maintained.

[0219] Next, refer to Figures 30A to 31B The accompanying drawings illustrate the simulation results performed to confirm the superior performance of the second variation of the tenth embodiment. The lengths of the first main line 11, the second main line 12, the first auxiliary line 21, and the second auxiliary line 22 of the impedance conversion circuit in the simulation object are set to 2000 μm, and the widths are set to 25 μm. The capacitances of capacitors Cp3 and Cp4 are set to 0.7 pF.

[0220] Figure 30A , Figure 30B , Figure 31A and Figure 31B Compared with the second embodiment Figure 5A , Figure 5B , Figure 6Aand Figure 6B Similarly, graphs are shown illustrating the insertion loss, in-phase signal removal ratio, amplitude imbalance, and phase imbalance of the impedance conversion circuit. The solid and dashed lines in these graphs represent simulation results of the impedance conversion circuits in the second variation of the tenth embodiment and the comparative example excluding capacitors Cp3 and Cp4, respectively.

[0221] like Figure 30A As shown, the impedance transformation circuit of the second modification of the tenth embodiment shows an improvement in insertion loss in a frequency range of approximately 2 GHz and above to 5.5 GHz, compared to the impedance transformation circuit of the comparative example. Figure 30B As shown, in the impedance conversion circuit of the second variation of the tenth embodiment, the in-phase signal removal ratio is improved in a frequency range of approximately 2 GHz and above to 5.5 GHz. Figure 31A As shown, in the impedance conversion circuit of the second variation of the tenth embodiment, the amplitude imbalance is improved in a frequency range of approximately 1.5 GHz and above to 6 GHz. Figure 31B As shown, in the impedance conversion circuit of the second variation of the tenth embodiment, the phase imbalance is improved in a frequency range of about 3 GHz and below 6 GHz.

[0222] according to Figures 30A to 31B The simulation results shown in the attached figure confirm that the characteristics of the impedance conversion circuit are improved by connecting capacitors Cp3 and Cp4 in parallel with the first sub-line 21 and the second sub-line 22, respectively.

[0223] [Eleventh Embodiment]

[0224] Next, refer to Figures 32 to 34B The impedance conversion circuit of the eleventh embodiment will be described in the accompanying drawings. Hereinafter, with reference to the drawings... Figures 4A to 7 The common structure of the impedance conversion circuit of the second embodiment illustrated in the accompanying drawings is omitted from the description.

[0225] Figure 32 This is the equivalent circuit diagram of the impedance conversion circuit in the eleventh embodiment. In the second embodiment ( Figure 4A In the first main line 11 and the second main line 12, capacitors Cp1 and Cp2 are connected in parallel. In contrast, in the eleventh embodiment, capacitors Cp3 and Cp4 are connected in parallel to the first auxiliary line 21 and the second auxiliary line 22, respectively.

[0226] Next, the superior effects of the eleventh embodiment will be explained.

[0227] In the eleventh embodiment, the second main line 12 resonates in parallel with capacitor Cp2, and the second auxiliary line 22 resonates in parallel with capacitor Cp4. Within the frequency range encompassing this resonant frequency, a high impedance state exists between the second node P2 and the fourth node P4 (ground). Therefore, sufficient isolation can be ensured between the second node P2 and ground. Furthermore, capacitor Cp1 is connected in parallel with the first main line 11, capacitor Cp3 is connected in parallel with the first auxiliary line 21, capacitor Cp2 is connected in parallel with the second main line 12, and capacitor Cp4 is connected in parallel with the second auxiliary line 22. Therefore, the symmetry between the coupled transmission line including the first main line 11 and the first auxiliary line 21 and the coupled transmission line including the second main line 12 and the second auxiliary line 22 can be maintained.

[0228] Next, refer to Figures 33A to 34B The accompanying drawings illustrate the simulation results performed to confirm the superior performance of the eleventh embodiment. The lengths of the first main line 11, second main line 12, first auxiliary line 21, and second auxiliary line 22 of the impedance conversion circuit in the simulation object are set to 2000 μm, and the widths are set to 25 μm. The capacitances of capacitors Cp1, Cp2, Cp3, and Cp4 are set to 0.7 pF. Other simulation conditions are the same as... Figure 1C The simulation conditions in the first embodiment shown are the same.

[0229] Figure 33A , Figure 33B , Figure 34A and Figure 34B Compared with the second embodiment Figure 5A , Figure 5B , Figure 6A and Figure 6B Similarly, graphs are shown illustrating the insertion loss, in-phase signal removal ratio, amplitude imbalance, and phase imbalance of the impedance conversion circuit. The solid and dashed lines in these graphs represent simulation results of the impedance conversion circuits in the eleventh embodiment and a comparative example excluding capacitors Cp1, Cp2, Cp3, and Cp4, respectively.

[0230] like Figure 33A As shown, the impedance transformation circuit of the eleventh embodiment shows an improvement in insertion loss in a frequency range of approximately 2 GHz and above to 4.5 GHz, compared to the impedance transformation circuit of the comparative example. Figure 33B As shown, in the impedance conversion circuit of the eleventh embodiment, the in-phase signal removal ratio is improved in a frequency range of approximately 1 GHz to 5 GHz. Figure 34A As shown, in the impedance transformation circuit of the eleventh embodiment, amplitude imbalance is improved in a frequency range of approximately 1.5 GHz to 6 GHz. Figure 34BAs shown, in the impedance conversion circuit of the eleventh embodiment, the phase imbalance is improved in a frequency range of approximately 3 GHz and above to 4.5 GHz.

[0231] according to Figures 33A to 34B The simulation results shown in the attached figure confirm that by connecting capacitors Cp1 and Cp2 in parallel with the first main line 11 and the second main line 12 respectively, and by connecting capacitors Cp3 and Cp4 in parallel with the first auxiliary line 21 and the second auxiliary line 22 respectively, the characteristics of the impedance conversion circuit are improved.

[0232] [Twelfth Embodiment]

[0233] Next, refer to Figure 35 and Figure 36 The impedance conversion circuit of the twelfth embodiment will be described.

[0234] Figure 35 This is an equivalent circuit diagram of the impedance conversion circuit of the twelfth embodiment. The impedance conversion circuit of the seventh embodiment is omitted in the twelfth embodiment. Figure 22 Instead of capacitors Cdc1 and Cdc2, capacitor Cmn1 is connected between the first node P1 and the second node P2.

[0235] Figure 36 This is an exploded perspective view showing the conductor pattern of the impedance conversion circuit of the twelfth embodiment. The impedance conversion circuit of the twelfth embodiment includes a laminated substrate on which dielectric layers and conductor layers are alternately stacked. A surface conductor layer L0 is disposed on the upper surface of the laminated substrate. Within the laminated substrate, counting from the upper surface, a first conductor layer L1, a second conductor layer L2, a third conductor layer L3, and a fourth conductor layer L4 are disposed. A fifth conductor layer, functioning as a ground plane, is disposed below the fourth conductor layer L4. Figure 36 Not shown in the diagram. This ground plane can also function as a ground plane for microstrip lines relative to the first main line 11, the second main line 12, the first sub-line 21, and the second sub-line 22. Furthermore, on the lower surface of the laminated substrate, conductor patterns are arranged for use as the first connection terminal T1, the second connection terminal T2, the third connection terminal T3, the fourth connection terminal T4 (grounding terminal), and the power supply terminal Vcc.

[0236] The surface conductor layer L0 is provided with conductor patterns that function as first node P1, second node P2, third node P3, and fourth node P4. In addition, there are conductor patterns that are connected to the third connection terminal T3, the fourth connection terminal T4, and the power supply terminal Vcc, respectively, conductor pattern L0A that is connected to ground, and conductor pattern L0B for relaying.

[0237] The first conductor layer L1 is provided with conductor patterns that constitute the first main circuit 11 and the second main circuit 12, respectively. The first main circuit 11 and the second main circuit 12 have a spiral shape with approximately 5 / 4 turns. When viewed from the top surface, the first main circuit 11 rotates clockwise from the inner circumference to the outer circumference, and the second main circuit 12 rotates counterclockwise from the inner circumference to the outer circumference.

[0238] The conductor layer L2 of the second layer is provided with conductor patterns that constitute the first sub-circuit 21 and the second sub-circuit 22, respectively. The first sub-circuit 21 has a shape that substantially overlaps with the first main circuit 11 when viewed from above, and the second sub-circuit 22 has a shape that substantially overlaps with the second main circuit 12 when viewed from above.

[0239] Conductor patterns L3A and L4A are respectively configured on the third conductor layer L3 and the fourth conductor layer L4. It should be noted that, in addition to these conductor patterns, inner layer pads for relaying vias are also configured on conductor layers L1, L2, L3, and L4. Figure 36 The inner layer pads are omitted from the display.

[0240] The outer periphery of the first main line 11 is connected to the conductor pattern of the first node P1 via a via, and the inner periphery is connected to the conductor pattern of the third node P3 via a via. The outer periphery of the second main line 12 is connected to the conductor pattern of the second node P2 via a via, and the inner periphery is connected to the conductor pattern of the fourth node P4 via a via.

[0241] The outer periphery of the first main line 11 is connected to the outer periphery of the second secondary line 22 via a via. The outer periphery of the second main line 12 is connected to the outer periphery of the first secondary line 21 via a via. The inner periphery of the first secondary line 21 is connected to the inner periphery of the second secondary line 22 via a via, conductor pattern L3A, and a via. The conductor pattern connected to the power supply terminal Vcc is connected to the relay conductor pattern L0B via a via, conductor pattern L4A, and a via.

[0242] The conductor pattern of the surface conductor layer L0 is used as a terminal for mounting surface mount components. Capacitor Cp1 is mounted on the conductor pattern of the first node P1 and the conductor pattern of the third node P3. Capacitor Cp2 is mounted on the conductor pattern of the second node P2 and the conductor pattern of the fourth node P4. Capacitor Cmn1 is mounted on the conductor pattern of the first node P1 and the conductor pattern of the second node P2.

[0243] A choke Lch1 is installed on the conductor pattern of the first node P1 and the conductor pattern connected to the power supply terminal Vcc. A choke Lch2 is installed on the conductor pattern of the second node P2 and the relay conductor pattern L0B.

[0244] Install a bypass capacitor Cbp on the conductor pattern and conductor pattern L0A connected to the power supply terminal Vcc. Conductor pattern L0A is connected to ground. Install capacitor Cdc3 on the conductor pattern and conductor pattern of the third node P3 connected to the third connection terminal T3. Install capacitor Cdc4 on the conductor pattern and conductor pattern of the fourth node P4 connected to the fourth connection terminal T4.

[0245] Next, the superior effects of the twelfth embodiment will be explained.

[0246] By arranging the first main line 11, the second main line 12, the first auxiliary line 21, and the second auxiliary line 22 on a common laminated substrate, miniaturization of the impedance conversion circuit can be achieved. By forming the first main line 11, the second main line 12, the first auxiliary line 21, and the second auxiliary line 22 with a spiral-shaped conductor pattern, the self-inductance of these transmission lines can be increased. By arranging the first main line 11 and the first auxiliary line 21 in an overlapping manner in top view, their electromagnetic coupling can be enhanced. The same applies to the second main line 12 and the second auxiliary line 22.

[0247] Next, the impedance conversion circuit of the modified example of the twelfth embodiment will be described.

[0248] In the twelfth embodiment, surface mount components are used as capacitors Cp1, Cp2, Cdc3, Cdc4, bypass capacitors Cbp, and chokes Lch1 and Lch2, but some passive components may also be formed by conductor patterns within the laminated substrate.

[0249] In the twelfth embodiment, the first main line 11, the second main line 12, the first auxiliary line 21, and the second auxiliary line 22 are arranged in a spiral shape, but these transmission lines can also form a distributed constant circuit and adopt other shapes. For example, these transmission lines can also be arranged in a straight line.

[0250] [Thirteenth Embodiment]

[0251] Next, refer to Figure 37 The high-frequency power amplifier of the thirteenth embodiment will be described.

[0252] Figure 37This is a block diagram of the high-frequency power amplifier according to the thirteenth embodiment. The high-frequency power amplifier of the thirteenth embodiment includes multiple differential amplifiers 51D connected in multiple stages. An unbalanced-to-balance converter circuit 50IB is connected to the input side of the primary differential amplifier 51D to convert a single-ended signal into a differential signal. The unbalanced-to-balance converter circuit 50IB has the function of converting the single-ended signal RFin into differential signals RF+ and RF- and performing impedance matching.

[0253] As an unbalanced-to-balance conversion circuit 50IB, for example, the impedance conversion circuit of the second embodiment is used ( Figure 4A A single-ended signal RFin is input to the third connection terminal T3, and differential signals RF+ and RF- are output from the first connection terminal T1 and the second connection terminal T2. The fourth connection terminal T4 is connected to ground. It should be noted that, as an unbalanced-to-balance conversion circuit 50IB, impedance conversion circuits with unbalanced-to-balance conversion functions in other embodiments can also be used.

[0254] Impedance conversion circuits 50BB are connected between the stages of the multi-stage differential amplifier 51D as inter-stage impedance matching circuits. For example, the impedance conversion circuit 50BB of the differential signal can be used (see the ninth embodiment). Figure 26 A differential signal is input from one of the terminal pairs including the first connection terminal T1 and the second connection terminal T2, and the terminal pair including the third connection terminal T3 and the fourth connection terminal T4, and a differential signal is output from the other terminal pair.

[0255] On the output side of the final stage differential amplifier 51D, a balun circuit 50BI is connected to convert the differential signal into a single-ended signal. The balun circuit 50BI has the function of converting the differential signals RF+ and RF- into a single-ended signal RFout and performing impedance matching.

[0256] For the balanced-to-unbalanced conversion circuit 50BI, for example, the impedance conversion circuit of the second embodiment is used ( Figure 4A Differential signals RF+ and RF- are input to the first connection terminal T1 and the second connection terminal T2, and a single-ended signal RFout is output from the third connection terminal T3. The fourth connection terminal T4 is connected to ground. It should be noted that, as the balun circuit 50BI, impedance conversion circuits with balun functions in other embodiments can also be used.

[0257] Next, the superior effects of the thirteenth embodiment will be explained.

[0258] In the thirteenth embodiment, the impedance switching circuit of the second embodiment, etc., is used for the primary unbalanced-to-balance switching circuit 50IB and the final-stage balanced-to-unbalanced switching circuit 50BI. Figure 4A For the interstage impedance transformation circuit 50BB, the impedance transformation circuit of the ninth embodiment is used. Figure 26 Therefore, sufficient isolation can be ensured between the input-side connection terminals and the output-side connection terminals.

[0259] Next, a variation of the thirteenth embodiment will be described.

[0260] In the thirteenth embodiment, the impedance conversion circuit of the above embodiment is used as the primary unbalanced-to-balance conversion circuit 50IB, the interstage impedance conversion circuit 50BB, and the final stage balanced-to-unbalance conversion circuit 50BI. However, the impedance conversion circuit of the above embodiment may also be used only for a portion of the primary unbalanced-to-balance conversion circuit 50IB, a portion of the interstage impedance conversion circuit 50BB, and a portion of the final stage balanced-to-unbalance conversion circuit 50BI.

[0261] Next, refer to Figure 38 A high-frequency power amplifier of another variation of the thirteenth embodiment will be described. Figure 38 This is a block diagram of a high-frequency power amplifier according to another variation of the thirteenth embodiment. In this variation, a single-ended signal amplifier 51S is used for the input side of the multi-stage amplifier, and a differential amplifier 51D is used for the remaining multi-stage amplifier. An impedance matching circuit 50II is connected between the input side of the primary amplifier 51S and the stage of the single-ended signal amplifier 51S.

[0262] An unbalanced-to-balanced converter circuit 50IB is connected between the final stage single-ended signal amplifier 51S and the first stage differential amplifier 51D. The structure of the stage following the unbalanced-to-balanced converter circuit 50IB is similar to that of the high-frequency power amplifier in the thirteenth embodiment. Figure 37 The structures are the same.

[0263] Alternatively, as in this variant, the single-ended signal amplifier 51S can be combined with the differential amplifier 51D to form a multi-stage high-frequency power amplifier.

[0264] The above embodiments are illustrative, and of course, partial substitutions or combinations of the structures shown in different embodiments are possible. The same effects resulting from the same structures in multiple embodiments are not mentioned sequentially in each embodiment. Furthermore, the present invention is not limited to the above embodiments. For example, it will be clear to those skilled in the art that various changes, modifications, combinations, etc., can be made.

Claims

1. An impedance conversion circuit, wherein, The impedance conversion circuit includes: The first main line has a first node and a third node at its two ends, and high-frequency signals are transmitted between the first node and the third node. The second main line has a second node and a fourth node at its two ends, and high-frequency signals are transmitted between the second node and the fourth node. The first secondary line is connected to the second node and is electromagnetically coupled to the first main line; The second auxiliary line has one end connected to the first node, and the other end connected to the end of the first auxiliary line that is not connected to the second node, and is electromagnetically coupled to the second main line; as well as A first capacitor is connected in parallel with at least one of at least a portion of the second main line and at least a portion of the second secondary line.

2. The impedance conversion circuit according to claim 1, wherein, The first capacitor is connected to both ends of the second main circuit.

3. The impedance conversion circuit according to claim 2, wherein, The first capacitor is connected in parallel with the second main line.

4. The impedance conversion circuit according to any one of claims 1 to 3, wherein, The impedance conversion circuit further includes a second capacitor connected in parallel with at least one of at least a portion of the first main line and at least a portion of the first secondary line.

5. The impedance conversion circuit according to any one of claims 1 to 4, wherein, The impedance conversion circuit further comprises: a parallel reactance element with one terminal connected to the first node and another terminal connected to the second node; or a parallel reactance element with one terminal connected to the third node and another terminal connected to the fourth node.

6. The impedance conversion circuit according to any one of claims 1 to 5, wherein, The impedance conversion circuit further includes a first connection terminal, a second connection terminal, a third connection terminal, and a fourth connection terminal that are respectively connected to the first node, the second node, the third node, and the fourth node.

7. The impedance conversion circuit according to claim 6, wherein, One of the second and fourth connection terminals is a grounding terminal connected to the ground potential.

8. The impedance conversion circuit according to claim 7, wherein, The impedance conversion circuit constitutes a balanced-unbalanced conversion circuit, which outputs a signal input from one of the node pairs of the first node and the second node and the third node and the fourth node from the other node pair.

9. The impedance conversion circuit according to any one of claims 6 to 8, wherein, The impedance conversion circuit further includes a series reactance element that is connected in series between the first node and the first connection terminal, between the second node and the second connection terminal, between the third node and the third connection terminal, and between the fourth node and the fourth connection terminal.

10. The impedance conversion circuit according to any one of claims 1 to 9, wherein, The impedance conversion circuit also includes: Power supply terminals; and A choke coil is connected between the junction of the first and second auxiliary lines and the power supply terminal.

11. The impedance conversion circuit according to any one of claims 6 to 9, wherein, The impedance conversion circuit also includes: Power supply terminals; A first choke coil is connected between the power supply terminal and the first connection terminal; and The second choke is connected between the power supply terminal and the second connection terminal.

12. The impedance conversion circuit according to any one of claims 1 to 11, wherein, The impedance conversion circuit further comprises a laminated substrate, wherein dielectric layers and conductor layers are alternately stacked on the laminated substrate. The first main circuit and the second main circuit are disposed on the conductor layer of the laminated substrate.

13. The impedance conversion circuit according to claim 12, wherein, The multilayer substrate includes a ceramic multilayer substrate, a multilayer resin substrate, or a semiconductor substrate with multiple wiring layers.

14. An amplification module, wherein, The amplification module has the following features: The impedance conversion circuit as described in claim 9 or 10; and A differential amplifier, wherein one of a pair of differential output nodes and a pair of differential input nodes is connected to the first node and the second node, respectively.

15. An amplification module, wherein, The amplification module has the following features: The impedance conversion circuit according to any one of claims 1 to 13; and A differential amplifier, wherein one of its pair of differential output nodes and pair of differential input nodes is connected to the first node and the second node, respectively. The first capacitor resonates in parallel with at least a portion of the second main circuit or at least a portion of the second secondary circuit connected in parallel to the first capacitor at a certain frequency in the operating frequency band of the differential amplifier.

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