Integrated cavity for conductor formation in memory die

Abstract

Methods, systems, and devices are described for integrated cavities for forming conductors within a memory die. An array of cavities may be formed through a stack of material layers of a memory die, and conductors may be formed at least in part by integrating some of the cavities of the array. Such cavities may be sized according to the relatively smallest feature implementing a subset of such cavities, and the smallest relevant feature may be formed using a first subset of the array of cavities. The conductors may be formed at least in part by integrating two or more cavities of a second subset of the array of cavities using a material removal operation that removes a portion of the stack of material layers. Such integration may support conductors formed with cross-sections larger than the cross-sections of other features formed using such cavities that are not integrated.

Description

[Technical Field]

[0001] cross reference This patent application claims priority to U.S. patent application Ser. No. 18 / 443,013, filed February 15, 2023, by Wells et al., entitled "MERGED CAVITIES FOR CONDUCTOR FORMATION IN A MEMORY DIE," and U.S. provisional patent application Ser. No. 63 / 486,175, filed February 21, 2023, by Wells et al., entitled "MERGED CAVITIES FOR CONDUCTOR FORMATION IN A MEMORY DIE," each of which is assigned to the assignee herein and is expressly incorporated by reference in its entirety.

[0002] The following relates to one or more systems for memory that include integrated cavities for conductor formation in a memory die. [Background technology]

[0003] Memory devices are widely used to store information in various electronic devices, such as computers, user devices, wireless communication devices, cameras, digital displays, etc. Information is stored by programming memory cells within a memory device to various states. For example, a binary memory cell may be programmed to one of two supported states, which often correspond to a logic 1 or a logic 0. In some examples, a single memory cell may support three or more possible states, any one of which may be stored by the memory cell. To access information stored by a memory device, a component can read (e.g., sense, detect, obtain, identify, determine, evaluate) the state of one or more memory cells within the memory device. To store information, a component can write (e.g., program, set, assign) one or more memory cells within the memory device to a corresponding state.

[0004] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), three-dimensional cross-point memory (3D cross-point), not-or (NOR) memory devices, and not-and (NAND) memory devices. Memory devices can be described in terms of volatile or non-volatile configurations. Volatile memory cells (e.g., DRAM) may lose their programmed state over time unless periodically refreshed by an external power source. Non-volatile memory (e.g., NAND) can maintain their programmed state for long periods of time, even in the absence of an external power source. [Brief explanation of the drawings]

[0005] [Figure 1] 1 illustrates an example system supporting an integrated cavity for forming conductors in a memory die, according to embodiments disclosed herein. [Figure 2] 1 illustrates an example memory architecture that supports integrated cavities for conductor formation in a memory die, according to embodiments disclosed herein. [Figure 3] 1 illustrates an example of a manufacturing operation that can support integrated cavities for conductor formation in a memory die according to embodiments disclosed herein. [Figure 4] 1 illustrates an example of a manufacturing operation that can support integrated cavities for conductor formation in a memory die according to embodiments disclosed herein. [Figure 5] 1 illustrates an example of a manufacturing operation that can support integrated cavities for conductor formation in a memory die according to embodiments disclosed herein. [Figure 6]1 illustrates an example of a manufacturing operation that can support integrated cavities for conductor formation in a memory die according to embodiments disclosed herein. [Figure 7] 1 illustrates an example of a manufacturing operation that can support integrated cavities for conductor formation in a memory die according to embodiments disclosed herein. [Figure 8] 1 illustrates an example of a manufacturing operation that can support integrated cavities for conductor formation in a memory die according to embodiments disclosed herein. [Figure 9] 1 illustrates an example of a manufacturing operation that can support integrated cavities for conductor formation in a memory die according to embodiments disclosed herein. [Figure 10] 1 illustrates an example of a manufacturing operation that can support integrated cavities for conductor formation in a memory die according to embodiments disclosed herein. [Figure 11] 1 illustrates an example of a manufacturing operation that can support integrated cavities for conductor formation in a memory die according to embodiments disclosed herein. [Figure 12] 1 illustrates an example of a manufacturing operation that can support integrated cavities for conductor formation in a memory die according to embodiments disclosed herein. [Figure 13] 1 illustrates an example of a manufacturing operation that can support integrated cavities for conductor formation in a memory die according to embodiments disclosed herein. [Figure 14] 1 illustrates a flowchart of method(s) for supporting integrated cavities for conductor formation in a memory die according to embodiments disclosed herein. DETAILED DESCRIPTION OF THE INVENTION

[0006] In some memory manufacturing operations, one or more materials may be deposited on a substrate, such as a semiconductor substrate, and portions of the one or more materials may be removed according to various patterning operations. For example, a pattern of cavities may be formed by removing one or more materials along a thickness direction according to a pattern of openings having one or more various cross-sectional shapes. In some examples, memory cells may be formed at least in part by depositing one or more storage materials in some cavities, and conductors (e.g., to support access of the memory cells or for other operations or signaling) may be formed at least in part by depositing one or more conductive materials in some other cavities.

[0007] In some implementations, conductors may be associated with a set conductivity or resistance, and cavities for forming the conductors may have different sizes or patterns to support the conductivity or resistance. However, forming cavities with different sizes or patterns may involve non-uniformities (e.g., structural non-uniformities, processing non-uniformities) within a memory array region or at transitions between regions of a memory array that use cavities of different sizes. Additionally or alternatively, forming patterns of cavities of different sizes (e.g., high aspect ratio cavities) may involve relatively complex or expensive processing. Thus, in some examples, it may be desirable to form an array of uniformly sized cavities and form memory cells and conductors from each subset of the cavities in the same array. However, cavities may be formed according to a relatively small cross-section (e.g., in connection with forming minimum features such as memory pillar formation), and the desired conductivity or resistance may not be supported by conductors formed in cavities with a relatively small cross-section.

[0008] According to embodiments disclosed herein, an array of cavities may be formed through a stack of material layers of a memory die, and conductors (e.g., conductive pillars) may be formed at least in part by integrating some of the cavities of the array. For example, such cavities may be sized according to the relatively smallest feature (e.g., memory pillar formation) that implements a subset of such cavities, and the smallest associated feature (e.g., memory pillar) may be formed using a first subset of the array of cavities. A conductor may be formed at least in part by integrating two or more cavities of a second subset of the array of cavities. For example, a pattern of cavities may be integrated using selective material removal (e.g., forming a void extending between two or more adjacent cavities, such as one or more nearest adjacent cavities, or removing all material between adjacent cavities), and conductive material may be formed within the integrated cavities to form a conductive pillar. Such integration may support conductors formed with a cross-section larger than a single cavity. Thus, a uniform pattern of cavities can be formed to maintain processing and structural consistency across the memory die, and several cavities can be merged to provide larger openings for conductors to achieve desired conductivity or resistance values. Additionally, forming memory pillars and conductive pillars from the same array of cavities can improve processing efficiency and reduce manufacturing costs.

[0009] Features of the present disclosure will be described and illustrated in the context of systems, devices, and circuits with reference to Figures 1 and 2. Features of the present disclosure will be described and illustrated in the context of material arrangements and methods with reference to Figures 3-14.

[0010] FIG. 1 illustrates an example of a memory device 100 that supports integrated cavities for conductor formation in a memory die, according to embodiments disclosed herein. FIG. 1 is an exemplary representation of various components and features of memory device 100. As such, the components and features of memory device 100 are illustrated to represent their functional interrelationships, not necessarily their physical locations within memory device 100. Additionally, some elements included in FIG. 1 are labeled with numerical designations, while other corresponding elements are not labeled to enhance visibility and clarity of the illustrated features, even if they may be understood to be identical or similar.

[0011] The memory device 100 may include one or more memory cells 105, such as memory cell 105-a and memory cell 105-b. In some examples, the memory cells 105 may be NAND memory cells, as shown in the close-up of memory cell 105-a. Each memory cell 105 may be programmed to store a logical value representing one or more bits of information. In some examples, a single memory cell 105, such as a memory cell 105 configured as a single-level cell (SLC), may be programmed to one of two supported states and thus can store one bit of information at a time (e.g., a logic 0 or a logic 1). In some other examples, a single memory cell 105 (such as a memory cell 105 configured as a multi-level cell (MLC), tri-level cell (TLC), quad-level cell (QLC), or other type of multi-level memory cell 105) may be programmed to one of three or more supported states and thus can store more than one bit of information at a time.

[0012] In some NAND memory arrays, each memory cell 105 may be represented as a transistor including a charge trapping structure (e.g., a floating gate, a replacement gate, a dielectric material) for storing an amount of charge that represents a logical value. For example, the expanded view of FIG. 1 shows a NAND memory cell 105-a including a transistor 110 (e.g., a metal-oxide semiconductor (MOS) transistor) that may be used to store logical values. The transistor 110 may include a control gate 115 and a charge trapping structure 120 (e.g., a floating gate, a replacement gate), which, in some examples, may be between two portions of a dielectric material 125. The transistor 110 may also include a first node 130 (e.g., a source or drain) and a second node 135 (e.g., a drain or source). A logical value may be stored in the transistor 110 by storing (e.g., writing) a number of electrons (e.g., an amount of charge) on the charge trapping structure 120. The amount of charge stored in the charge trapping structure 120 may depend on the logical value being stored. Charge stored in charge trapping structure 120 can affect the threshold voltage of transistor 110, thereby affecting the amount of current that flows through transistor 110 when transistor 110 is activated (e.g., when a voltage is applied to control gate 115, when memory cell 105-a is read). In some examples, charge trapping structure 120 can be an example of a floating gate or replacement gate structure. For example, a NAND array can include multiple control gates 115 and charge trapping structures 120 arranged around a single channel (e.g., a horizontal channel, a vertical channel, a columnar channel, a pillar channel).

[0013] The logical value stored in transistor 110 can be sensed (e.g., as part of a read operation) by applying a voltage to control gate 115 (e.g., via word line 165, to control node 140) to activate transistor 110 and measuring (e.g., detecting, sensing) the amount of current flowing through first node 130 or second node 135 (e.g., via bit line 155). For example, sensing component 170 can determine whether SLC memory cell 105 stores a logical 0 or a logical 1 in a binary manner (e.g., based on the presence or absence of current through memory cell 105 when a read voltage is applied to control gate 115, whether the current is above or below a threshold current). In the case of a multilevel memory cell 105, the sensing component 170 may determine the logical value stored in the memory cell 105 based on various intermediate threshold levels of current when a read voltage is applied to the control gate 115, or by applying different read voltages to the control gate and evaluating the resulting different levels of current through the transistor 110, or various combinations thereof.

[0014] The SLC memory cell 105 may be written by applying one of two voltages (e.g., a voltage above a threshold or a voltage below a threshold) to the memory cell 105 to either store or not store charge on the charge trapping structure 120, causing the memory cell 105 to store one of two possible logical values. For example, when a first voltage is applied to the control node 140 (e.g., via word line 165) relative to the bulk node 145 (e.g., body node) of the transistor 110 (e.g., when the control node 140 is at a voltage higher than the bulk), electrons may tunnel into the charge trapping structure 120. The injection of electrons into the charge trapping structure 120 may be referred to as programming the memory cell 105 and may occur as part of a write operation. In some cases, a programmed memory cell may be considered to store a logical 0. When a second voltage is applied to the control node 140 (e.g., via the word line 165) relative to the bulk node 145 of the transistor 110 (e.g., when the control node 140 is at a lower voltage than the bulk node 145), electrons may leave the charge trapping structure 120. The removal of electrons from within the charge trapping structure 120 may be referred to as erasing the memory cell 105 and may occur as part of an erase operation. In some cases, an erased memory cell may be considered to store a logic one. In some cases, the memory cells 105 may be programmed with page-level granularity due to a page of memory cells 105 sharing a common word line 165, and the memory cells 105 may be erased with block-level granularity due to a block of memory cells 105 sharing a commonly biased bulk node 145.

[0015] In some examples, programming a multi-level (e.g., MLC, TLC, or QLC) memory cell 105 may involve applying different voltages to the memory cell 105 (e.g., to its control node 140 or bulk node 145) at a finer level of granularity, allowing it to represent a larger set of logical values ​​by more precisely controlling the amount of charge stored in the charge trapping structure 120. Thus, a multi-level memory cell 105 may offer higher density storage compared to an SLC memory cell 105, but in some cases may involve narrower read or write margins or more complex supporting circuitry.

[0016] Charge trapping NAND memory cells 105 may operate similarly to floating gate NAND memory cells 105, except that instead of or in addition to storing charge on charge trapping structures 120, charge trapping NAND memory cells 105 may store charge representing a logic state in the dielectric material between control gate 115 and the channel (e.g., the channel between first node 130 and second node 135). Thus, charge trapping NAND memory cells 105 may include charge trapping structures 120 or may implement charge trapping functionality in one or more portions of dielectric material 125, among other configurations.

[0017] In some examples, each page of memory cells 105 may be connected to a corresponding word line 165, and each column of memory cells 105 may be connected to a corresponding bit line 155 (e.g., digit line). Generally, one memory cell 105 may be located at the intersection of a word line 165 and a bit line 155. This intersection may be referred to as the address of the memory cell 105. In some cases, the word lines 165 and bit lines 155 may be substantially perpendicular to one another and may generally be referred to as access lines or select lines. In some examples, the access lines (e.g., word lines 165 and bit lines 155) may be formed in a direction away from the substrate of the memory device 100 and may each be located between layers of dielectric material in the array region of the memory device 100. The direction away from the substrate may refer to the thickness (e.g., height) direction and may be subject to some degree of skew associated with the manufacturing process.

[0018] Access to the memory cells 105 may be controlled via row decoder 160 and column decoder 150. For example, row decoder 160 may receive a row address from memory controller 180 and activate an appropriate word line 165 based on the received row address. Similarly, column decoder 150 may receive a column address from memory controller 180 and activate an appropriate bit line 155. Thus, one memory cell 105 may be accessed by activating one word line 165 and one bit line 155. As part of such an access, memory cell 105 may be read (e.g., sensed) by sensing component 170. For example, sensing component 170 may be configured to determine the stored logical value of memory cell 105 based on a signal generated by accessing memory cell 105. The signal may include a current, a voltage, or both a current and a voltage on the bit line 155 of memory cell 105 and may depend on the logical value stored by memory cell 105. Sensing component 170 may include various circuits (e.g., transistors, amplifiers) configured to detect and amplify signals (e.g., current or voltage) on bit lines 155. The logic value of memory cell 105 detected by sensing component 170 may be output via input / output component 190. In some cases, sensing component 170 may be part of column decoder 150 or row decoder 160 or may otherwise be connected to or in electronic communication with column decoder 150 or row decoder 160.

[0019] A memory cell 105 may be programmed or written by activating associated word lines 165 and bit lines 155, allowing a logical value (e.g., representing one or more bits of information) to be stored in the memory cell 105. A column decoder 150 or a row decoder 160 may receive data to be written to the memory cell 105 (e.g., from input / output components 190). In the case of NAND memory, the memory cell 105 may be written by storing electrons in charge trapping structures or insulating layers.

[0020] The memory controller 180 can control the operation (e.g., read, write, rewrite, refresh) of the memory cells 105 through various components (e.g., row decoder 160, column decoder 150, and sensing components 170). In some cases, one or more of the row decoder 160, column decoder 150, and sensing components 170 may be co-located with the memory controller 180. The memory controller 180 can generate row and column address signals to activate desired word lines 165 and bit lines 155. In some examples, the memory controller 180 can generate and control various voltages or currents used during operation of the memory device 100.

[0021] In some techniques for fabricating memory device 100 (e.g., for fabricating a memory die including one or more aspects of memory device 100), one or more materials may be deposited on a substrate, such as a semiconductor substrate, and portions of the one or more materials may be removed following various patterning operations. According to embodiments disclosed herein, an array of cavities may be formed through a stack of material layers of a memory die to support aspects of memory device 100, and conductors (e.g., conductive pillars, conductors associated with word lines 165 or bit lines 155) may be formed at least in part by integrating some of the cavities of the array. For example, such cavities may be sized according to the relatively smallest features implementing a subset of such cavities (e.g., for forming pillars of memory cells 105), and the smallest associated features may be formed using a first subset of the array of cavities. The conductors may be formed at least in part by integrating two or more cavities of a second subset of the array of cavities. For example, a pattern of cavities may be consolidated using selective material removal (e.g., to form voids extending between two or more adjacent cavities or to remove all material between the cavities), and conductive material may be formed in the consolidated cavities to form conductive pillars. Such consolidation can support conductors formed with a cross-section larger than that of a single cavity. Thus, a uniform pattern of cavities can be formed to maintain processing and structural consistency across the memory die, and several cavities can be consolidated to provide larger openings for conductors to achieve a set conductivity or resistance value. Furthermore, forming memory pillars and conductive pillars from the same array of cavities can improve processing efficiency and reduce manufacturing costs.

[0022] FIG. 2 illustrates an example memory architecture 200 supporting integrated cavities for conductor formation in a memory die, according to embodiments disclosed herein. Memory architecture 200 may be an example of a portion of a memory device, such as memory device 100. While some elements of a set of elements (e.g., an array of elements) are included in FIG. 2 , some elements may be omitted for visibility and clarity of the illustrated elements. Additionally, some elements included in FIG. 2 are labeled with reference numerals, while some other corresponding elements are not labeled, but would be understood by one skilled in the art to be identical or similar. Aspects of memory architecture 200 may be described with reference to the x-, y-, and z-directions of the illustrated coordinate system.

[0023] The memory architecture 200 includes a three-dimensional array of memory cells 205, which may be the example memory cells 105 (e.g., transistors 110, NAND memory cells) described with reference to FIG. 1 . For example, the memory cells 205 may be included in blocks 210, which may be arranged as a 3D array of m memory cells along the x direction, n memory cells along the y direction, and o memory cells along the z direction. Each memory cell 205 may be positioned (e.g., addressed) according to an index i along the x direction, an index j along the y direction, and an index k along the z direction (e.g., to identify memory cell 205-a-ijk). The memory device 100 may include any number of one or more blocks 210, and different blocks 210 may be adjacent along the x direction, along the y direction, or along the z direction, or any combination thereof, according to embodiments disclosed herein.

[0024] In the example memory architecture 200, the block 210 may be divided into a set of pages 215 (e.g., o pages 215) along the z-direction, including page 215-a-1 associated with memory cells 205-a-111 through 205-a-mn1. In some examples, each page 215 may be associated with the same word line 265 (e.g., word line 165 described with reference to FIG. 1), and the same word line 265 may be coupled to each control gate 115 of the memory cells 205 of the page 215. For example, page 215-a-1 may be associated with word line 265-a-1, and other pages 215-ai may be associated with different word lines 265-ai (not shown). In some examples, the word lines 265 according to the memory architecture 200 may be implemented as planar conductors (e.g., in the xy plane) coupled to each of the memory cells 205 of the page 215.

[0025] In the example memory architecture 200, the block 210 may be divided into sets of strings 220 in the xy plane (e.g., (m x n) number of strings 220), each including a string 220-a-mn associated with a memory cell 205-a-mn1 through 205-a-mn0. In some examples, each string 220 may include a set of memory cells 205 connected in series (e.g., along the z direction, where the drain of one memory cell 205 in the string 220 may be coupled to the source of another memory cell 205 in the string 220). In some examples, the memory cells 205 in a string 220 may be implemented along a common channel, such as a pillar channel (e.g., a cylindrical channel, a pillar of doped semiconductor) along the z direction. Each memory cell 205 in a string 220 may be associated with a different word line 265, such that the number of word lines 265 in the memory architecture 200 may be equal to the number of memory cells 205 in the string 220. Thus, a string 220 may include memory cells 205 from multiple pages 215 , and a page 215 may include memory cells 205 from multiple strings 220 .

[0026] In some examples, memory cells 205 may be programmed (e.g., set to a logic 0 value) and read according to a granularity, such as the granularity of page 215, but may not be erasable (e.g., not reset to a logic 1 value) according to a granularity, such as the granularity of page 215. For example, NAND memory may instead be erasable according to a different (e.g., higher) level of granularity, such as the level of granularity of block 210. In some cases, memory cells 205 may be erased before they can be reprogrammed. Different memory devices may have different read, write, or erase characteristics.

[0027] In some examples, each string 220 in the block 210 may be coupled to a respective transistor 230 (e.g., a string select transistor, a drain select transistor) at one end of the string 220 (e.g., along the z-direction) and to a respective transistor 240 (e.g., a source select transistor, a ground select transistor) at the other end of the string 220. In some examples, the drain of each transistor 230 may be coupled to a bit line 250 of a set of bit lines 250 associated with the block 210, which may be an example of the bit line 155 described with reference to FIG. 1 . The gate of each transistor 230 may be coupled to a select line 235 (e.g., a string select line, a drain select line). Thus, the transistor 230 may be used to couple the string 220 to the bit line 250 based on applying a voltage to the select line 235 and, therefore, to the gate of the transistor 230. Although shown as separate lines along the x-direction, in some examples, the select lines 235 may be common to all of the transistors 230 associated with the block 210 (e.g., commonly biased string select nodes). For example, the select lines 235 associated with the block 210, like the word lines 265 of the block 210, may in some examples be implemented as planar conductors (e.g., in the x-y plane) coupled to each of the transistors 230 associated with the block 210. In some examples, the access lines (e.g., the bit lines 250 and the word lines 265) may be formed in a direction away from the substrate of the memory device 100 and each may be disposed between layers of dielectric material in the array region of the memory device 100. The direction away from the substrate may point in the z-direction (e.g., thickness or height) and may be subject to some degree of skew related to the manufacturing process.

[0028] In some examples, the source of each transistor 240 associated with the block 210 may be coupled to a source line 260 of the set of source lines 260 associated with the block 210. In some examples, the set of source lines 260 may be associated with a common source node (e.g., a ground node) corresponding to the block 210. The gate of each transistor 240 may be coupled to a select line 245 (e.g., a source select line, a ground select line). Thus, the transistors 240 may be used to couple the string 220 to the source lines 260 based on applying a voltage to the select line 245 and, therefore, to the gates of the transistors 240. Although shown as separate lines along the x-direction, in some examples, the select line 245 may be common to all of the transistors 240 associated with the block 210 (e.g., a commonly biased ground select node). For example, like the word lines 265 of the block 210, the select lines 245 associated with the block 210 may, in some examples, be implemented as planar conductors (e.g., in the xy plane) coupled to each of the transistors 240 associated with the block 210.

[0029] To operate the memory architecture 200 (e.g., to perform a program, read, or erase operation on one or more memory cells 205 of a block 210), various voltages may be applied to one or more select lines 235 (e.g., to the gates of transistors 230), one or more bit lines 250 (e.g., to the drains of one or more transistors 230), one or more word lines 265, one or more select lines 245 (e.g., to the gates of transistors 240), one or more source lines 260 (e.g., to the sources of transistors 240), or to the bulks of the memory cells 205 (not shown) of the block 210. In some cases, each memory cell 205 of a block 210 may have a common bulk, the voltage of which may be controlled independently of the bulks of the other blocks 210.

[0030] In some cases, as part of a read operation for a memory cell 205, a positive voltage may be applied to the corresponding bit line 250, while the corresponding source line 260 may be grounded or otherwise biased at a voltage lower than the voltage applied to the bit line 250. In some examples, for a memory cell 205, voltages that exceed the threshold voltages of transistors 230 and 240, respectively, may be simultaneously applied to select line 235 and select line 245, thereby activating transistors 230 and 240, such that a channel (e.g., a pillar channel) associated with the string 220 that includes the memory cell 205 may be electrically connected to (e.g., electrically connected between) the corresponding bit line 250 and source line 260. The channel may be an electrical path through the memory cells 205 in the string 220 (e.g., through the source and drain of a transistor in the memory cells 205 of the string 220) and may conduct current under some operating conditions.

[0031] In some examples, multiple word lines 265 (e.g., possibly all word lines 265) of a block 210 (except for the word lines 265 associated with the page 215 of memory cells 205 to be read) may be simultaneously set to a voltage (e.g., VREAD) higher than the threshold voltage (VT) of the memory cells 205. VREAD may activate all memory cells 205 in unselected pages 215, such that each unselected memory cell 205 in a string 220 may maintain high conductivity in its channel. In some examples, the word line 265 associated with a memory cell 205 to be read may be set to a voltage, VTarget. When the memory cells 205 are operated as SLC memory cells, VTarget may be a voltage between (i) the VT of the erased memory cells 205 and (ii) the VT of the programmed memory cells 205.

[0032] When the memory cell 205 to be read exhibits an erased VT (e.g., VTarget>VT of memory cell 205), the memory cell 205 may be turned “on” in response to application of VTarget to the word line 265 of the selected page 215, thereby allowing current to flow in the channel of the string 220 and thus from the bit line 250 to the source line 260. When the memory cell 205 to be read exhibits a programmed VT (e.g., VTarget<VT of the selected memory cell), the memory cell 205 may remain “off” regardless of application of VTarget to the word line 265 of the selected page 215, thereby preventing current from flowing in the channel of the string 220 and thus from the bit line 250 to the source line 260.

[0033] A signal on the bit line 250 for the memory cell 205 (e.g., an amount of current below or above a threshold) may be sensed (e.g., by a sensing component 170 as described with reference to FIG. 1 ) and may indicate whether the memory cell 205 becomes conductive or remains non-conductive in response to application of VTarget to the word line 265 of the selected page 215. Thus, the sensed signal may indicate whether the memory cell 205 was in an erased state (e.g., storing a logic 1) or a programmed state (e.g., storing a logic 0). While aspects of the above example read operation were described in the context of an SLC memory cell 205 for clarity, such techniques may be extended or modified and applied in the context of a multilevel memory cell 205 (e.g., using multiple values ​​of VTarget corresponding to different amounts of charge that may be stored in a single multilevel memory cell 205).

[0034] In some cases, as part of a program operation for memory cell 205, charge may be added to a portion of memory cell 205, thereby suppressing current flow through memory cell 205 and, therefore, corresponding string 220, when memory cell 205 is later read. For example, charge may be injected into charge trapping structure 120 shown in memory cell 105-a of FIG. 1 . In some cases, voltages may be applied to word line 265 of page 215 and the bulk of memory cell 205 to be programmed (e.g., a positive voltage may be applied to the word line) so that control gate 115 of memory cell 205 is at a higher voltage than the bulk of memory cell 205. At the same time, voltages above the threshold voltages of transistors 230 and 240 may be applied to select line 235 and select line 245, respectively, thereby activating transistors 230 and 240 and setting bit line 250 of memory cell 205 to be programmed at a relatively high voltage. This may create an electric field that attracts electrons from the source toward the drain of memory cell 205. The electric field may also pull some of these electrons through the dielectric material 125, thereby injecting them into the charge trapping structure 120 of the memory cell 205 via a process that may sometimes be referred to as tunnel injection.

[0035] In some cases, the memory cells 205 of a page 215 may all share a common word line 265 and a common bulk, so that a single program operation can program some or all of the memory cells 205 in the page 215. For memory cells 205 of a page 215 for which it is not desirable to write a logic 0 (e.g., it is not desirable to program the memory cell 205), the corresponding bit line 250 may be set to a relatively low voltage (e.g., ground), which may inhibit the injection of electrons into the charge trapping structure 120. While aspects of the exemplary program operation above are described in the context of SLC memory cells 205 for clarity, such techniques may be extended and applied in the context of multilevel memory cells 205 (e.g., through the use of multiple program voltages applied to word lines 265, multiple passes or pulses of program voltages applied to word lines 265, corresponding to different amounts of charge that may be stored in a single multilevel memory cell 205).

[0036] In some cases, as part of an erase operation on a memory cell 205, charge may be removed from a portion of the memory cell 205, so that when the memory cell 205 is later read, current flow through the memory cell 205 and thus the corresponding string 220 may be unimpeded (e.g., may be allowed, at least to a greater extent). For example, charge may be removed from the charge trapping structure 120 shown in memory cell 105-a of FIG. 1. In some cases, voltages may be applied to the word line 265 of the page 215 and to the bulk of the memory cell 205 to be erased (e.g., a positive voltage may be applied to the bulk) so that the control gate 115 of the memory cell 205 is at a lower voltage than the bulk of the memory cell 205, which may create an electric field that draws electrons from the charge trapping structure 120 to the bulk of the memory cell 205. In some cases, the memory cells 205 of a block 210 may all share a common bulk, so that a single program operation may erase all of the memory cells 205 of the block 210.

[0037] In some techniques for fabricating memory architecture 200 (e.g., for fabricating a memory die including one or more aspects of memory architecture 200), one or more materials may be deposited on a substrate, such as a semiconductor substrate, and portions of the one or more materials may be removed according to various patterning operations. According to embodiments disclosed herein, an array of cavities may be formed through a stack of material layers of a memory die to support aspects of memory architecture 200, and conductors (e.g., conductors associated with conductive pillars, word lines 265, bit lines 250, select lines 235, select lines 245, and source lines 260) may be formed at least in part by integrating some of the cavities of the array. For example, such cavities may be sized according to the relatively smallest features implementing a subset of such cavities (e.g., for the formation of strings 220), and the smallest associated features may be formed using a first subset of the array of cavities. A conductor may be formed at least in part by integrating two or more cavities of a second subset of the array of cavities. For example, a pattern of cavities may be integrated using selective material removal, and a conductive material may be formed in the integrated cavities to form conductive pillars. Such integration may allow conductor cavities to be formed with a cross-section larger than that of a single cavity. Thus, a uniform pattern of cavities may be formed to maintain processing and structural consistency across the memory die, and several cavities may be integrated to provide larger openings for the conductors to achieve a set conductivity or resistance value. Furthermore, forming memory pillars and conductive pillars from the same array of cavities may improve processing efficiency and reduce manufacturing costs.

[0038] 3-13 illustrate example manufacturing operations that may support integrated cavities for conductor formation in a memory die, according to embodiments disclosed herein. For example, FIGS. 3-13 may illustrate an embodiment of a sequence of operations for fabricating an embodiment of material arrangement 300. Material arrangement 300 may be an example that implements an embodiment of memory architecture 200 described with reference to FIG. 2, among other types of memory architectures. Each of FIGS. 3-13 may illustrate an embodiment of material arrangement 300 after a different subset or alternative of the manufacturing operations for forming material arrangement 300 (e.g., shown as material arrangement 300-a after a first set of one or more manufacturing operations, material arrangement 300-b after a second set of one or more manufacturing operations, etc.). Each view of the diagram may be described with reference to the illustrated x-, y-, and z-directions, which may correspond to the directions described with reference to memory architecture 200.

[0039] Some of the views provided include cross-sectional views illustrating example cross sections of material arrangement 300. For example, in Figures 3-5, view "section AA" may relate to a cross section in the xz plane (e.g., along cutting plane AA) through a portion of material arrangement 300 associated with a set of cavities (e.g., including a cavity for at least one memory cell 205 along the z-direction, such as string 220). Although material arrangement 300 illustrates some example relative dimensions and numbers of various features, aspects of material arrangement 300 may be implemented with other relative dimensions or numbers of such features according to examples disclosed herein.

[0040] 3-13 may be performed by a manufacturing system, such as a semiconductor manufacturing system configured to perform additive operations (e.g., deposition, epitaxy, bonding), removal operations (e.g., etching, trenching, planarization, polishing), modification operations (e.g., oxidation, doping, reacting, converting), and support operations (e.g., masking, patterning, photolithography, aligning), among other operations in support of the described techniques. In some examples, the operations performed by such a manufacturing system may be supported by a process controller or components thereof, as described herein.

[0041] FIG. 3 illustrates an example of material arrangement 300 (e.g., as material arrangement 300-a) after a first set of one or more fabrication operations. As shown, material arrangement 300-a may be associated with region 301 (e.g., an array region associated with one or more blocks 210) including cavities 305 associated with an array of memory cells 205, as well as region 302 and region 306 (e.g., contact region, word line region) including cavities 310 that may be associated with the formation of conductors for transmitting signals associated with accessing memory cells 205. Each of cavities 305 and 310 may extend through at least a portion of material arrangement 300-a along the z-direction. In material arrangement 300-a, at least some features of regions 301 and 302 may be electrically isolated from one another, which may be supported by insulating region 303 or insulating region 304 (e.g., trench isolation regions), or various combinations thereof. In some examples, features associated with insulating region 304 may be omitted from material arrangement 300-a.

[0042] The first set of operations may include forming a layer of material 325 (e.g., depositing material 325 over substrate 315), where material 325 may include a conductive material (e.g., a metal, a metal alloy, or a conductive ceramic such as tungsten silicide). In some examples, the layer of material 325 may support a ground node of memory architecture 200, such as a source node (e.g., source line 260, common source) of one or more blocks 210. While material 325 is shown in regions 302, 303, and 304, in some examples, at least a portion of material 325 may be omitted from one or more of regions 302, 303, or 304. The layer of material 325 may be formed in contact with substrate 315, although in some other examples, material arrangement 300-a may include other materials or components between the layer of material 325 and substrate 315. Substrate 315 may include or otherwise be associated with circuitry 320, which may include, among other circuitry, interconnect or routing circuitry (e.g., access lines, power routing lines), control circuitry (e.g., transistors, logic, decoding circuitry, addressing circuitry, aspects of memory controller 180, column decoder 150, row decoder 160, sensing components 170, input / output components 190), which may include, among other configurations, various conductive, semiconductor, or dielectric materials of substrate 315 between the layer of material 325 and substrate 315. For example, circuitry 320 may include, at least partially, an arrangement of complementary metal-oxide-semiconductor (CMOS) transistors, or thin-film transistors (TFTs), or any combination thereof, between substrate 315 and the layer of material 325, among others.

[0043] The first set of operations may also include forming stack 330 (e.g., forming a stack of material layers, depositing a stack of material layers) on substrate 315 (e.g., on the layer of material 325), which may support the formation of various components that support access of memory cell 205 (e.g., in region 301). In some examples, stack 330 may include a layer of material 331, a layer of material 332, a layer of material 333, and a layer of material 334. In some examples, material 331 may be a semiconductor material (e.g., doped polysilicon, n-doped polysilicon), which may support the formation of a channel portion of transistor 240. In some examples, each of material 332, material 333, and material 334 may be a sacrificial material, at least a portion of which may be patterned and removed in a subsequent processing operation. In some examples, material 332, material 333, and material 334 may be selected to support various techniques for differential processing (e.g., differential etching, high selectivity). For example, material 332 may be a dielectric material (e.g., oxide, oxide of silicon, liner oxide), material 333 may be a semiconductor material (e.g., polysilicon), and material 334 may be a dielectric material (e.g., oxide, oxide of silicon, cap oxide) that may be the same as material 332.

[0044] In some examples, the first set of operations may include operations supporting the formation of an etch stop in stack 330 (e.g., a vertical etch stop to prevent material removal beyond stack 330 in at least some regions of material arrangement 300-a). For example, the first set of operations may include operations for forming a cavity aligned (e.g., in the x-y plane) with the location of cavity 305 and operations for forming a trench aligned with the location of isolation region 303. In some examples, such trenches may connect with other such trenches (e.g., along the x-direction) to provide trench isolation around portions of material arrangement 300-a associated with block 210 (e.g., surrounding areas in the x-y plane associated with block 210, surrounding region 301 or portions thereof). Such cavities and trenches may extend at least partially through the layer of material 321 to support the formation of material 335 (e.g., oxidized doped polysilicon, which may include oxidizing material 331) along bottoms and sidewalls of the cavities and trenches. In some examples, after forming the etch stop feature in stack 330, a first set of operations may include forming (e.g., depositing, oxidizing) a layer of material 336 and a layer of material 337 over stack 330. Material 336 may be an oxide material (e.g., an oxide of silicon), and material 337 may be a semiconductor material (e.g., polysilicon). In some examples, material 336 may be a sacrificial material (e.g., a portion of which is removed in one or more subsequent operations), and material 337 may support the formation of one or more transistor structures (e.g., as part of the channel of transistor 240 in memory architecture 200).

[0045] The first set of operations may also include forming stack 340 (e.g., forming a stack of material layers, depositing a stack of material layers), which may include various formation operations. For example, forming stack 340 may include forming alternating layers of material 341 and material 342 (e.g., following an alternating material deposition operation or other formation operation). In some examples, material 341 may include a dielectric material (e.g., oxide, layered oxide, oxide of silicon) that may provide electrical insulation between features of material arrangement 300-a (e.g., along the z-direction, between pages 215, between wordlines 265). Material 342 may include various materials different from material 341 (e.g., nitride material, nitride of silicon) and may be a sacrificial material (e.g., to support a subsequent differential etch procedure). Although stack 340 is shown with 25 layers (e.g., 13 layers of material 341 and 12 layers of material 342), stack 340 according to embodiments disclosed herein may include any number of layers (e.g., tens of layers, hundreds of layers, etc.) of each of two or more materials, including as little as one layer of material 342.

[0046] The first set of operations may also include operations to form cavities 310. For example, the first set of operations may include operations (e.g., dry etching operations, photolithography operations) to form cavities 310 through stacks 340 and 330 in regions 302 and 306 (e.g., to expose electrical contacts, such as conductive material portions, associated with circuitry 320). In some examples, one or more cavities 310 may be aligned with a corresponding set of cavities 305 along the y-direction or other direction (e.g., a row of cavities 305 along the x-direction or other direction). In some examples, cavities 305 and 310 may be formed in a continuous pattern (e.g., without discontinuities along one or more directions in the x-y plane), and may include region 306 directly adjacent to region 301, among other examples.

[0047] Forming cavities 310 and cavities 305 may support forming contacts associated with one or more cavities 310 (e.g., in region 302) that couple with bit lines 250 formed above (e.g., along the z-direction) a corresponding set of cavities 305. However, cavities 310 may be formed in region 302 or region 306 for other purposes and, accordingly, may be arranged in various other configurations. Cavities 310 may be formed by openings (e.g., cross-sectional openings, openings in the xy plane) that do not overlap one another (e.g., in the xy plane). In some examples, the openings for forming cavities 310 may have the same or similar cross-section (e.g., size, shape) as the openings for forming cavities 305. Additionally or alternatively, the openings for forming cavities 310 may be formed in the same or similar pattern (e.g., a honeycomb pattern that may include the same or similar spacing between openings) as the openings for forming cavities 305. Forming cavity 310 may be associated with forming (e.g., exposing) sidewalls of one or more materials of stack 340 and stack 330, and such sidewalls may have a tapered shape along the z-direction.

[0048] In some examples, cavity 310 may be formed through stack 340 and stack 330 in a single material removal operation, while in some other examples, such cavities may be formed using a sequence of material removal operations. For example, for each cavity 310, each first cavity may be formed through at least stack 330, and in some examples, one or both of material 336 or material 337, and each first cavity may be filled with a sacrificial material (e.g., sacrificial carbon, with or without a liner material, or a stack of different materials). In some examples, such operations may be performed prior to forming stack 340. Each second cavity that coincides with (e.g., aligns with) each first cavity (e.g., coaxial along the z direction, subject to alignment tolerances in the xy plane) may be formed through at least a subset of the material layers of stack 340 (e.g., before forming another subset of the material layers of stack 340), and the second cavities may be filled with a sacrificial material (e.g., that coincides with the sacrificial material formed before the other subset of the material layers of stack 340 may be formed on top of it). Such a sequence may be repeated any number of times, and a single collective cavity 310 may be formed by removing sacrificial material from the previous cavity fill operation.

[0049] The first set of operations may also include operations for forming cavities 305. For example, the first set of operations may include operations (e.g., dry etching operations, photolithography operations) for forming cavities 305 through stack 340 of region 301 and through at least a portion of stack 330 (e.g., exposing portions of material 325 using material 325 as a cavity etch stop). The cavities 305 may be formed in a pattern, which may include staggering rows to increase the density of cavities 305 (e.g., in the xy plane). The cavities 305 may be formed through non-overlapping openings, and forming the cavities 305 may be associated with forming sidewalls of one or more materials of stack 340 and stack 330. In some examples, one or more operations associated with forming cavity 305 may be performed simultaneously (e.g., one or more operations may occur during overlapping periods or the same period or process) with a corresponding operation (e.g., an etching operation, a sacrificial material deposition operation) associated with forming cavity 310. For example, cavity 305 and cavity 310 may be formed using similar patterns (e.g., etching patterns) and may have similar dimensions (e.g., opening size, shape, depth).

[0050] In some examples, the cavities 305 may be formed at least through the stack 340 in a single material removal operation, while in some other examples, the cavities 305 may be formed using a sequence of material removal operations. For example, for each cavity 305, each first cavity may be formed through a first subset of the material layers of the stack 340, and the first cavity may be filled with a sacrificial material (e.g., before forming a second subset of the material layers of the stack 340). Each second cavity aligned with each first cavity may be formed through a second subset of the material layers of the stack 340, and the second cavity may be filled with a sacrificial material. Such a sequence may be repeated any number of times, and a single collective cavity 305 may be formed by removing sacrificial material from the previous cavity fill operation.

[0051] In some examples, each of cavities 305 and cavities 310 may be filled with a sacrificial material 351 (e.g., sacrificial carbon, or a different material). In some cases, each cavity 310 may be filled with sacrificial material 351 during one or more filling operations that also include forming a sacrificial material in each cavity 305 (e.g., simultaneously). In some examples, after forming cavities 310, a first set of operations may include forming a layer of material 355 (e.g., a dielectric material, an oxide of silicon) over stack 340, which may provide a barrier to protect cavities 305 or cavities 310 during subsequent operations (e.g., which may include removing sacrificial material 351 from a subset of cavities to perform the subsequent operations).

[0052] Cavity 305 may participate in various operations to support the formation of memory cells associated with cavity 305 (e.g., memory cell 105, memory cell 205, memory cells of string 220). For example, sacrificial material 351 may be removed from each cavity 305, and at least material 361 and material 362, and in some examples, material 363, may be formed (e.g., deposited, oxidized) in the formed cavity associated with cavity 305 to form pillar 307 (e.g., cell pillar, memory pillar corresponding to string 220). Cavity 305 may extend along the z-direction, such that pillar 307 formed within cavity 305 may extend along the z-direction. Material 361 may support charge trapping functionality of memory cell 205 and, in various examples, may include one or more layers of material. In some examples, material 361 may include a first layer (e.g., a dielectric layer, an oxide layer, an oxide of silicon) that contacts the walls of the formed cavity and may support the first dielectric material 125 of the string of memory cells 205, a second layer (e.g., a charge trapping layer, a nitride layer, a nitride of silicon) on the first layer that may support the charge trapping structure 120 of the string of memory cells 205, and a third layer (e.g., a dielectric layer, an oxide layer, an oxide of silicon) on the second layer that may support the second dielectric material 125 of the string of memory cells 205. Material 362 may be a semiconductor material (e.g., polysilicon in contact with material 361 or its third layer) that may support a channel portion of the string of memory cells 205 (e.g., between each first node 130 and each second node 135). Material 363 may be a dielectric material (e.g., silicon oxide in contact with material 362) that, in some examples, may fill the remainder of the cavity. In some examples, at least a portion of material 363 may be removed (e.g., recessed) from the top of cavity 305, and an additional portion of material 362 may be formed (e.g., deposited, oxidized) to fill the top of cavity 305 (e.g., during a plug-forming operation).In some examples, after forming pillars 307, a first set of operations may include forming a layer of material 365 (e.g., a dielectric material, an oxide of silicon) over stack 340, which may provide a barrier to protect pillars 307 during subsequent operations.

[0053] For example, the first set of operations may also include various operations (e.g., dry etching operations, photolithography operations) to form trenches 370 through stack 340 along insulating region 303 and through at least a portion of stack 330 (e.g., exposing a portion of material 325 using material 325 as a trench etch stop). In some examples, one or more operations associated with forming trenches 370 in insulating region 303 may be performed simultaneously with corresponding operations (e.g., etching operations, sacrificial material deposition operations) associated with forming the cavities of pillars 307. In some examples, trenches 370 may be formed at least through stack 340 in a single material removal operation, while in some other examples, trenches 370 may be formed using a sequence of material removal operations. For example, for each insulating region 303, each first trench may be formed through a first subset of material layers of stack 340, and the first trench may be filled with a sacrificial material (e.g., before forming a second subset of material layers of stack 340). Each second trench aligned with each first trench may be formed through a second subset of material layers of stack 340, and the second trenches may be filled with a sacrificial material. This sequence may be repeated any number of times, and trenches 370 may be formed by removing sacrificial material from a previous trench fill operation. In some examples, forming trenches 370 may include removing at least a portion of material 355 or material 365 from insulating region 303.

[0054] Opening trench 370 can support the formation of structures associated with pillar 307. For example, void 371 can be formed through trench 370, which can include removing exposed portions of material 332, material 333, material 334, material 336, and material 361 (e.g., via a wet etching operation). In some examples, such an operation can be preceded by forming a liner material (not shown) on the surface of stack 340 associated with trench 370, which can prevent removal of materials 341 and 342 during such an operation. Material 375 can be formed within void 371, which can further support the formation of aspects of transistor 240. For example, material 375 can include a semiconductor material (e.g., a doped polysilicon material, an n-doped polysilicon material), which can be the same as material 331. In some examples, after forming material 375, the liner along trench 370 may be removed and the exposed surfaces of material 331 and material 375 may be oxidized to form additional portions of material 335.

[0055] In some examples, forming word lines 265 in material arrangement 300-a may include forming voids by removing portions of material 342 from stack 340 in region 301 and forming one or more conductive materials within the formed voids. However, in some techniques for forming such voids, the extent of material 342 removal (e.g., along the x-direction, along the y-direction) may be uncertain or difficult to control due to variations in material removal rates and different material removal dimensions. Thus, in some examples, voids may extend into region 302, among other regions (e.g., between adjacent regions 301 intended to be electrically isolated), which may allow conductive material to be detrimentally formed near cavity 310 or between cavity 310 and cavity 305, among other features of the material arrangement intended to be electrically isolated. In some examples, the cavity 310 may be positioned relatively far from the trench 370 to avoid deleterious bonding with the conductive material, among other techniques to compensate for indefinite or otherwise variable ranges of voids and conductor deposition, but such techniques may be associated with relatively inefficient utilization of the area (e.g., in the xy plane) of the material arrangement 300-a.

[0056] In some examples, to form the features of insulating region 304, a first set of operations may include an operation (e.g., a dry etching operation, a photolithography operation) to form trench 380 at least through stack 340, and in some examples, through stack 330 and layers of material 325 along insulating region 304. In some examples, one or more operations associated with forming trench 380 in insulating region 304 may be performed simultaneously with a corresponding operation (e.g., an etching operation, a sacrificial material deposition operation) associated with forming the cavity of cavity 310. In some examples, trench 380 may be formed in a single material removal operation, while in some other examples, trench 380 may be formed using a sequence of material removal operations according to embodiments disclosed herein (e.g., as described with reference to forming cavity 310). After forming trench 380, material 381, which may include a dielectric material (e.g., oxide, oxide of silicon), may be formed (e.g., deposited, oxidized) in trench 380.

[0057] 4 illustrates material arrangement 300 (e.g., as material arrangement 300-b) in a cross-sectional side view (e.g., along section plane AA) after a second set of one or more fabrication operations. The second set of operations may include operations (e.g., wet etching operations, exhuming operations) that support forming word lines 265 in region 301. For example, the second set of operations may include forming voids 405 between layers of material 341 by removing material 342 from a portion of stack 340 (e.g., in region 301). Forming voids 405 may expose portions of pillars 307 (e.g., exposing sidewalls of material 361 between layers of material 341), which may remain in contact with material 341 and support material 341 across voids 405 (e.g., along the z-direction) for the formation of word lines (e.g., word lines 265), among other structures of memory architecture 200. In some examples, void 405 may extend into insulating region 304, which may include exposing sidewalls of material 381 between layers of material 341. However, by including insulating region 304, void 405 may not extend into region 302 (e.g., such that a layer of material 342 of stack 340 may remain in region 302), which may prevent the formation of conductive material in region 302 during the formation of wordline 265.

[0058] 5 illustrates material arrangement 300 (e.g., as material arrangement 300-c) in a cross-sectional side view (e.g., along section plane AA) after a third set of one or more fabrication operations. The third set of operations may include further operations (e.g., one or more deposition operations, metal fill operations, etching operations) that support forming word lines 265 between layers of material 341 (e.g., within portions of voids 405). For example, the third set of operations may include forming (e.g., depositing) material 505 in voids 405 (e.g., between layers of material 341), which may include forming material 505 in contact with pillars 307 or otherwise electrically coupled to pillars 307 (e.g., in contact with material 361). Material 505 may include one or more conductive materials, such as tungsten, which may be the same as material 325. In some examples, forming material 505 may include forming (e.g., depositing, oxidizing) a dielectric material (e.g., aluminum oxide) in contact with pillars 307 (e.g., prior to depositing one or more conductive materials) in contact with material 361, which may support the dielectric function of memory cells 205 (e.g., dielectric material 125). Portions of material 505 may be removed (e.g., in a recess etch operation) from portions of voids 405 to provide electrical isolation between wordlines 265.

[0059] Additionally, the third set of operations may include operations (e.g., one or more deposition operations, one or more oxidation operations) that support the formation of electrical isolation in insulating region 303 based at least in part on forming (e.g., depositing, oxidizing) material 510 in insulating region 303 (e.g., in at least a portion of trench 370 and void 405). Material 510 may be a dielectric material (e.g., an oxide, an oxide of silicon), which may be the same as material 355 or material 365, among other materials in material arrangement 300.

[0060] The third set of operations may be followed by other operations supporting aspects of memory architecture 200, such as, among other features, forming bit lines 250 (e.g., conductive lines on material arrangement 300-c that may be aligned along the x-direction and operable to couple between material 362 and conductors) coupled to strings 220, and forming vertical contacts (e.g., vertical conductors) coupled to each of word lines 265 (e.g., contacts electrically coupled to each layer of material 505).

[0061] 6-9 illustrate a first alternative for implementing integrated cavities for conductor formation within a memory die (e.g., implementing full integration of cavity 310) according to embodiments disclosed herein. Each of FIGS. 6-9 may illustrate an aspect of material placement 300 after a different subset of fabrication operations (e.g., after a third set of operations) to form material placement 300 according to the first alternative. In FIGS. 6-9, view "cross-section BB" may be associated with a cross-section in the x-z plane (e.g., at cut plane BB) through a portion of material placement 300 associated with a set of cavities 310 (e.g., including multiple cavities 310 for conductor formation and insulation). While an embodiment of the first alternative for implementing integrated cavities for conductor formation is shown in region 306, similar techniques may be implemented using cavities 310 in region 302, among other regions of a memory die, to form conductors using integrated cavities 310.

[0062] 6 illustrates material arrangement 300 (e.g., as material arrangement 300-d) in a cross-sectional side view (e.g., along section plane BB) after a fourth set of one or more fabrication operations. The fourth set of operations may include operations (e.g., etching operations, wet etching operations, recess forming operations) that support the formation of integrated cavity 605, at least in part, by integrating multiple cavities 310 (e.g., integrating completely along the z-direction).

[0063] The fourth set of operations may include operations (e.g., masking operations, photolithography operations, patterning operations) supporting the formation of a mask 610 (e.g., a masking material) over the pillars 307 and at least some of the cavities 310 (e.g., in regions 302 and 306). The mask 610 may prevent the pillars 307 and at least some of the cavities 310, among other intervening features, from being affected (e.g., etched) by subsequent operations (e.g., etching operations, wet etching operations). Forming the mask 610 may include a patterning operation to expose an area (e.g., in the xy plane) corresponding to the set of cavities 310 to be integrated. For example, the mask 610 may include a masking material (e.g., a hard mask) formed in a pattern over the stack 340 such that the masking material does not cover the locations of the cavities 310 to be integrated. In various examples, the boundaries of the mask 610 (e.g., the boundaries of the openings in the xy plane) may coincide with the boundaries of the cavities 310 (e.g., the openings), or the boundaries of the mask 610 may not coincide with the boundaries of the cavities 310. For example, the boundaries of the mask 610 may be wider than the cavities 310 to be integrated (e.g., may surround the cavities 310), which may support a relatively larger integrated cavity.

[0064] In some cases, different patterns for forming the mask 610 may be employed. For example, the number or pattern of cavities 310 exposed (e.g., grouped) to form the integrated cavities 605 may vary between configurations. Additionally or alternatively, the number or pattern of cavities 310 remaining masked between exposed locations of the integrated cavities 605 may vary between configurations. Such techniques may result in different spacing (e.g., different amounts of electrical insulation) between the integrated cavities 605 or different amounts (e.g., cross-sections) of conductive material formed within the integrated cavities 605. Thus, a uniform pattern of cavities 310 can be formed to maintain processing and structural consistency across the memory die, and different sizes of the integrated cavities 605 and different spacing between the cavities 605 can be implemented to achieve desired conductivity or resistance values.

[0065] A fourth set of operations may include integrating (e.g., fully integrating) multiple cavities 310 by removing sacrificial material 351 and at least materials 341 and 342 from a portion of stack 340 (e.g., along the z-direction, between cavities 310), among other materials (e.g., materials 336 and 337, one or more materials of stack 330, or a combination thereof, if applicable). Integrating cavities 310 to form integrated cavity 605 may form a continuous region free of material between at least two cavities 310. In some examples, forming integrated cavity 605 may include removing material to expose circuitry 320 (e.g., conductors of circuitry 320) or portions of material 325 (e.g., at least portions of material 325 in region 306 or other regions are part of a distribution layer or other electrical node without exposing conductors of circuitry 320).

[0066] In some examples, forming the integrated cavities 605 may include operations (e.g., wet etching operations, recess-forming operations) that may recess the material 342 and expose sidewalls 615 of the material 342 between layers of material 341. The fourth set of operations may thus result in forming one or more protrusions 620 of the material 341 toward an axis 625 of each integrated cavity 605 extending along the z-direction (e.g., toward an axis 625 along the x-direction or along another direction in the xy-plane).

[0067] 7 illustrates material arrangement 300 (e.g., as material arrangement 300-e) in a cross-sectional side view (e.g., along section plane BB) after a fifth set of one or more fabrication operations. The fifth set of operations may include operations (e.g., one or more deposition operations, metal fill operations) that support the formation of conductor 705 at least in part by forming material 710 in integrated cavity 605. For example, the third set of operations may include forming (e.g., depositing) material 710 in integrated cavity 605 (e.g., at least through stack 340, and in some examples, through stack 340, if applicable). Material 710 may include one or more conductive materials (e.g., a metal, a metal alloy, a conductive ceramic such as tungsten silicide, deposition of an electrode layer followed by bulk fill deposition of a conductor), which may be the same as material 325, or material 505, or any combination thereof. The cavity 310 and the integrated cavity 605 may extend along the z-direction, and thus the conductor 705 may have an extent along the z-direction that may at least partially overlap with an extent along the z-direction associated with the pillars 307 formed in the cavity 305.

[0068] Forming material 710 may include depositing material 710 in voids formed by recesses in material 342. For example, the voids may be formed by removal of material (e.g., material 342) as a result of a omnidirectional etch (e.g., a wet etch). Thus, conductor 705 may have one or more protrusions (e.g., in contact with sidewall 615) extending away from axis 625 (e.g., along the x-direction or along other directions in the xy plane). In some examples, such techniques may include forming material 710 in contact with or otherwise electrically coupled to material 325 (e.g., a portion of material 325 in region 306 or other regions is part of a distribution layer or other electrical node, which may not include forming material 710 in contact with a conductor of circuit 320). Additionally or alternatively, such techniques may include forming material 710 that is electrically isolated from material 325, or forming material 710 in contact with or otherwise electrically coupled to circuitry 320 (e.g., in areas where material 325 is omitted). By forming conductor 705 in contact with or otherwise electrically coupled to circuitry 320, the conductor may be electrically coupled to one or more transistor structures (e.g., transistors of circuitry 320, transistors formed at least in part by doped portions of substrate 315).

[0069] 8 illustrates a sixth set of material arrangement 300 (e.g., as material arrangement 300-f) in a cross-sectional side view (e.g., along section plane BB) after one or more fabrication operations. The sixth set of operations may include operations (e.g., etching operations, wet etching operations, recess formation operations) that support the formation of electrical isolation between conductors 705. For example, the sixth set of operations may include removing mask 610 and sacrificial material 351 from cavities 310 not associated with conductors 705. The sixth set of operations may also include removing portions of material 342 (e.g., between layers of material 341 through at least a portion of region 306, among other regions) to form voids 805, which may expose portions of conductors 705 (e.g., sidewalls of material 710 between layers of material 341).

[0070] FIG. 9 illustrates material arrangement 300 (e.g., as material arrangement 300-g) in a cross-sectional side view (e.g., along cross section BB) after a seventh set of one or more fabrication operations. The seventh set of operations may include, among other features, operations (e.g., one or more deposition operations, one or more oxidation operations) that support the formation of electrical insulation between conductors 705. For example, the seventh set of operations may include forming material 905 in cavities 310 and voids 805. For example, the seventh set of operations may include forming (e.g., depositing) material 905 in at least some cavities 310 not used to form conductors 705, which may include forming material 905 in contact with exposed portions of material 710. Material 905 may be the same as material 341, material 336, material 355, material 365, material 381, material 510, or any combination thereof, among other materials in material arrangement 300, and may be a dielectric material (e.g., an oxide, an oxide of silicon). Material 905 (eg, including insulating pillars 910 associated with cavities 310 filled with material 905 ) provides electrical insulation between conductors 705 and other features of material arrangement 300 .

[0071] Conductors 705 may support coupling between various features of memory architecture 200. For example, conductors 705 may be implemented as part of an electrical coupling between circuit 320 and any one or more of word line 265 (e.g., part of material 505), source line 260, select line 245, bit line 250, or select line 235, among other nodes of memory architecture 200, and may support implementing circuit 320 for operation of memory architecture 200. Such electrical coupling may include the formation of one or more conductive materials, not shown, between each component (e.g., over or otherwise through region 303 above or below stack 340, among other examples, where applicable). Additionally or alternatively, conductors 705 may be implemented to support electrical coupling of other elements of material arrangement 300.

[0072] 10-13 illustrate a second alternative for implementing integrated cavities for conductor formation within a memory die (e.g., implementing partial integration of cavities 310 to form conductors) according to examples disclosed herein. Each of FIGS. 10-13 may illustrate an aspect of material arrangement 300 after a different subset of fabrication operations (e.g., after a third set of operations) to form material arrangement 300 according to the second alternative. In FIGS. 10-13, view "cross section BB" may be associated with a cross section in the xz plane (e.g., at cut plane BB) through a portion of material arrangement 300 associated with a set of cavities 310 (e.g., including multiple cavities 310 for conductor formation and insulation). Although a second alternative embodiment for implementing an integrated cavity for conductor formation is shown in region 306, similar techniques may be implemented to form conductors using the integrated cavity 310 in region 302, among other regions of the memory die, using the cavity 310 in region 302.

[0073] 10 illustrates material arrangement 300 in a top view (e.g., as material arrangement 300-h) and a cross-sectional side view (e.g., along cross section BB) after an eighth set of one or more fabrication operations. The eighth set of operations may include operations (e.g., etching operations, wet etching operations, recessing operations) that support the formation of insulating regions.

[0074] The eighth set of operations may include operations (e.g., masking operations, photolithography operations, patterning operations) supporting the formation of the mask 1005 (e.g., a masking material). Forming the mask 1005 may include a patterning operation that masks regions corresponding to cavities 310 to be integrated to form conductors and at least some of the cavities 305 and 310 (e.g., in regions 301 and 302), while exposing regions corresponding to cavities 310 to form electrically insulating regions. For example, the mask 1005 may include a masking material (e.g., a hard mask) patterned over the stack 340, whereby the masking material covers the locations of the cavities 310 in the region 306 that will be integrated to form the conductors. In some cases, different patterns for forming the mask 1005 may be employed. For example, the number or pattern of exposed cavities 310 to form insulating regions may vary between configurations. Additionally or alternatively, the number or pattern of cavities 310 that remain masked by mask 1005 may vary between configurations. Such techniques may result in different spacing (e.g., different amounts of electrical insulation) between the masked cavities 310 and different amounts of conductive material formed within the cavities 310 that are later integrated to form conductors. Thus, a uniform pattern of cavities 310 can be formed to maintain processing and structural consistency across the memory die, and different sizes of integrated cavities 310 and different spacing between cavities 310 can be formed to achieve desired conductivity or resistance values.

[0075] The eighth set of operations may include operations (e.g., etching operations, wet etching operations, recess formation operations) that support the formation of insulating regions between integrated cavities 310. For example, the eighth set of operations may include removing sacrificial material 351 from non-integrated cavities 310 to form conductors. The eighth set of operations may also include removing portions of material 342 to form voids 1015 (e.g., between layers of material 341 through at least a portion of region 306, among other regions), which may expose portions of sacrificial material 351 corresponding to cavities 310 masked by mask 1005 (e.g., sidewalls of sacrificial material 351 between layers of material 341).

[0076] 11 illustrates material arrangement 300 (e.g., as material arrangement 300-i) in a cross-sectional side view (e.g., along section plane BB) after a ninth set of one or more fabrication operations. The ninth set of operations may include further operations (e.g., one or more deposition operations, one or more oxidation operations) that support the formation of electrical isolation (e.g., including insulating pillars 1110) between cavities 310 that are integrated for conductor formation. For example, the ninth set of operations may include forming material 1105 in cavities 310 and voids 1015. For example, the ninth set of operations may include forming (e.g., depositing) material 1105 in at least some cavities 310 that are not integrated, which may include forming material 1105 in contact with exposed portions of sacrificial material 351. Material 1105 may be the same as material 341, material 336, material 355, material 365, material 381, material 510, or any combination thereof, among other materials in material arrangement 300, and may be a dielectric material (e.g., oxide, oxide of silicon). Insulating pillars 1110 may provide electrical isolation between conductors formed in integrated cavity 310 and other features of material arrangement 300.

[0077] 12 illustrates material arrangement 300 (e.g., as material arrangement 300-j) in a cross-sectional side view (e.g., along section plane BB) after a tenth set of one or more fabrication operations. The tenth set of operations may include operations (e.g., etching operations, wet etching operations, recess forming operations) that support forming integrated cavity 1210, at least in part, by integrating multiple cavities 310 (e.g., partially integrating cavities along the z-direction).

[0078] The tenth set of operations may include integrating multiple cavities 310 by removing mask 1005 and removing sacrificial material 351 from cavities 310 to be integrated for conductor formation. The tenth set of operations may also include removing at least material 342 from portions of stack 340 (e.g., between layers of material 341 in region 306) to form voids 1215 between layers of material 341 (e.g., forming partial integration between cavities 310). However, in some other examples (not shown), the tenth set of operations may also include removing material 341, among other materials, to form fully integrated cavities (e.g., without intervening portions of material 341 or other materials). Integrating cavities 310 to form integrated cavity 1210 may form a continuous region free of material between at least two cavities 310. In some examples, forming integrated cavity 1210 may include removing material to expose circuitry 320 (e.g., conductors of circuitry 320) or a portion of material 325 (e.g., at least a portion of material 325 in region 306 or other regions is part of a distribution layer or other electrical node without exposing conductors of circuitry 320).

[0079] 13 illustrates material arrangement 300 (e.g., as material arrangement 300-k) in a cross-sectional side view (e.g., along cross section B-B) after an eleventh set of one or more fabrication operations. The eleventh set of operations may include an operation (e.g., one or more deposition operations, metal fill operations) that supports the formation of conductor 1305 at least in part by forming material 1310 in integrated cavity 1210. For example, the third set of operations may include forming (e.g., depositing) material 1310 in integrated cavity 1210 (e.g., at least through stack 340, and in some examples, through stack 330, if applicable) and void 1215. Material 1310 may include one or more conductive materials (e.g., a metal, a metal alloy, a conductive ceramic such as tungsten silicide, deposition of an electrode layer followed by bulk fill deposition of a conductor), which may be the same as material 325, or material 505, or any combination thereof. Cavity 310 and integrated cavity 1210 may extend along the z-direction, such that conductor 1305 may have an extent along the z-direction that may at least partially overlap with an extent in the z-direction associated with pillars 307 formed in cavity 305. Forming material 1310 may include depositing material 1310 within void 1215 (e.g., within partially integrated cavity 1210), if applicable.

[0080] In some examples, such techniques may include forming material 1310 in contact with or otherwise electrically coupled to material 325 (e.g., a portion of material 325 in region 306 or other regions is part of a distribution layer or other electrical node, which may not include forming material 1310 in contact with a conductor of circuitry 320). Additionally or alternatively, such techniques may include forming material 1310 that is electrically insulated from material 325 or forming material 1310 in contact with or otherwise electrically coupled to circuitry 320 (e.g., in regions where material 325 is omitted). By forming conductor 1305 in contact with or otherwise electrically coupled to circuitry 320, the conductor may be electrically coupled to one or more transistor structures (e.g., transistors formed at least in part by doped portions of substrate 315).

[0081] Conductors 1305 may support coupling between various features of memory architecture 200. For example, conductors 1305 may be implemented as part of an electrical coupling between circuit 320 and any one or more of word line 265 (e.g., part of material 505), source line 260, select line 245, bit line 250, or select line 235, among other nodes of memory architecture 200, and may support implementing circuit 320 for operation of memory architecture 200. Such electrical coupling may include the formation of one or more conductive materials, not shown, between each component (e.g., over or otherwise through region 303 above or below stack 340, among other examples, where applicable). Additionally or alternatively, conductors 1305 may be implemented to support electrical coupling of other elements of material arrangement 300.

[0082] 14 illustrates a flowchart of a method 1400 for supporting integrated cavities for conductor formation in a memory die according to embodiments disclosed herein. The operations of method 1400 may be performed by a manufacturing system or one or more controllers associated with the manufacturing system. In some examples, the one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform desired functions. Additionally or alternatively, the manufacturing system may use dedicated hardware to perform aspects of the described functionality.

[0083] At 1405, the method may include forming a stack of material layers over a substrate of the memory die.

[0084] At 1410, the method may include forming a plurality of cavities through the stack of material layers.

[0085] At 1415, the method may include forming an integrated cavity through the stack of material layers at least in part by integrating at least two cavities of the plurality of cavities.

[0086] At 1420, the method may include forming a conductor through the stack of material layers based at least in part on forming one or more conductive materials in the integrated cavity.

[0087] In some examples, an apparatus (e.g., a manufacturing system) described herein may perform a method(s), such as method 1400. The apparatus may include features, circuits, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by one or more controllers to control one or more functional elements of the manufacturing system), or any combination thereof, for performing the following aspects of the present disclosure:

[0088] Aspect 1: A method or apparatus comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for forming a stack of material layers over a substrate of a memory die; forming a plurality of cavities through the stack of material layers; forming an integrated cavity through the stack of material layers at least in part by integrating at least two cavities of the plurality of cavities; and forming a conductor through the stack of material layers based at least in part on forming one or more conductive materials in the integrated cavity.

[0089] Aspect 2: The method or apparatus of aspect 1, further comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for forming a plurality of second cavities through the stack of material layers and forming a plurality of memory cells based at least in part on forming semiconductor material in the plurality of second cavities, wherein the conductor is operable to electrically couple with at least a subset of the plurality of memory cells.

[0090] Aspect 3: The method or apparatus of aspect 2, wherein the plurality of second cavities are formed simultaneously with forming the plurality of cavities.

[0091] Aspect 4: The method or apparatus of any of Aspects 2-3, further including operations, features, circuits, logic, means, or instructions, or any combination thereof, for forming a plurality of voids based at least in part on removing portions of a second material of the stack of material layers from between layers of a first material of the stack of material layers, and forming a plurality of word lines electrically coupled to the plurality of memory cells based at least in part on forming one or more second conductive materials in the plurality of voids, wherein the conductor is electrically coupled to at least one word line of the plurality of word lines.

[0092] Aspect 5: A method or apparatus according to any of Aspects 1 to 4, wherein forming the at least two cavities exposes a third conductive material between the stack of material layers and the substrate, and forming the conductor includes forming a conductive material of the one or more conductive materials that contacts the third conductive material.

[0093] Embodiment 6: The method or apparatus of any of embodiments 1-5, wherein the conductor is electrically coupled to one or more transistors formed at least in part from doped portions of the substrate.

[0094] Aspect 7: A method or apparatus according to any of aspects 1 to 6, wherein integrating the at least two cavities includes operations, features, circuits, logic, means, or instructions, or any combination thereof, for forming a plurality of voids between adjacent ones of the at least two cavities based at least in part on removing portions of a second material of the material layer stack between layers of a first material of the material layer stack.

[0095] Aspect 8: A method or apparatus according to any of aspects 1 to 7, wherein integrating the at least two cavities includes an operation, feature, circuit, logic, means, or instruction, or any combination thereof, for removing portions of a first material of the stack of material layers and a second material of the stack of material layers between adjacent cavities of the at least two cavities.

[0096] Aspect 9: The method or apparatus of any of aspects 1-8, further comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for forming a dielectric material in one or more cavities of the plurality of cavities adjacent to the at least two cavities.

[0097] Aspect 10: The method or apparatus of any of Aspects 1-9, further comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for forming a sacrificial material in the plurality of cavities; removing the sacrificial material from at least two second cavities of the plurality of cavities; recessing a second material of the stack of material layers by the at least two second cavities to expose sidewalls of the second material between layers of a first material of the stack of material layers; forming a portion of the first material on the exposed sidewalls of the second material; removing the sacrificial material from the at least two cavities of the plurality of cavities; removing a portion of the second material by the at least two cavities to expose sidewalls of the portion of the first material; and forming a conductive material in contact with the exposed sidewalls of the portion of the first material of the one or more conductive materials.

[0098] Aspect 11: The method or apparatus of any of Aspects 1-10, further comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for forming a sacrificial material in the plurality of cavities; removing the sacrificial material from at least two of the plurality of cavities; recessing the second material of the stack of materials through the at least two cavities to expose sidewalls of a second material between layers of first material of the stack of material layers; forming a portion of the first material on the exposed sidewalls of the second material; and forming a conductive material of the one or more conductive materials in contact with the portion of the first material.

[0099] Aspect 12: The method or apparatus of aspect 11, further comprising operations, features, circuits, logic, means, or instructions, or any combination thereof, for removing the sacrificial material from one or more cavities of the plurality of cavities that are different from the at least two cavities, and forming a portion of the first material in the one or more cavities.

[0100] Aspect 13: A method or apparatus according to any of aspects 1 to 12, wherein forming the plurality of cavities includes operations, features, circuits, logic, means, or instructions, or any combination thereof, for forming a first plurality of cavities through a first subset of the stack of material layers, and forming a second plurality of cavities through a second subset of the stack of material layers, each of the second plurality of cavities coinciding with a respective cavity of the first plurality of cavities.

[0101] Embodiment 14: The method or apparatus of any one of embodiments 1-13, wherein the stack of material layers comprises alternating layers of oxide and nitride materials.

[0102] It should be noted that the described methods include possible implementations, and that operations and steps may be rearranged or otherwise modified, and that other implementations are possible. Furthermore, portions of two or more of the methods may be combined.

[0103] Apparatus Described Below, a summary of aspects of the apparatus described herein is provided.

[0104] Aspect 15: A device comprising an array region on a substrate including a plurality of memory cells and a plurality of access lines coupled to the plurality of memory cells, the plurality of access lines being arranged along a direction away from the substrate and each including the array region located between a first layer of dielectric material in the array region and a conductor operable to couple to at least one memory cell of the plurality of memory cells, the conductor being located outside the array region, the conductor each including a plurality of first conductor portions aligned along a direction away from the substrate and at least one second conductor portion coupled to adjacent first conductor portions of the plurality of first conductor portions, the second conductor portion being each located between a second layer of dielectric material outside the array region.

[0105] Aspect 16: The device of aspect 15, wherein the conductor is operable to couple the at least one memory cell of the plurality of memory cells to one or more transistors formed at least in part from a doped portion of the substrate.

[0106] Aspect 17: The device of any one of Aspects 15 to 16, wherein the conductor contacts a portion of at least one access line of the plurality of access lines outside the array region.

[0107] Embodiment 18: The device of any of embodiments 15 to 17, wherein the memory cells are associated with a first range along the direction, and the conductors are associated with a second range along the direction that at least partially overlaps with the first range.

[0108] Aspect 19: A device described in any of aspects 15 to 18, wherein a subset of memory cells among the plurality of memory cells are respectively arranged along each cell pillar extending along the direction, and each cell pillar is associated with a cross-sectional area smaller than the cross-sectional area of ​​the conductor.

[0109] Aspect 20: A device described in any of Aspects 15 to 19, wherein the conductor includes a first conductive material in contact with at least a portion of the dielectric material and a second conductive material in contact with the first conductive material.

[0110] Apparatus Described Below, a summary of aspects of the apparatus described herein is provided.

[0111] Aspect 21: A device comprising: an array region on a substrate including a plurality of memory cells and a plurality of access lines coupled to the plurality of memory cells, the plurality of access lines being arranged along a direction away from the substrate and each being located between layers of dielectric material in the array region; a conductor operable to couple to at least one memory cell of the plurality of memory cells, the conductor being located outside the array region and associated with an axis aligned along the direction; and one or more dielectric portions around at least a portion of the conductor, each dielectric portion of the one or more dielectric portions including at least one protrusion of the dielectric material toward the axis.

[0112] Aspect 22: The device of aspect 21, wherein the conductor is operable to couple the at least one memory cell of the plurality of memory cells to one or more transistors formed at least in part from a doped portion of the substrate.

[0113] Aspect 23: The device described in any one of Aspects 21 to 22, wherein the conductor contacts a portion of at least one access line of the plurality of access lines outside the array region.

[0114] Aspect 24: A device described in any of aspects 21 to 23, wherein the memory cells are associated with a first range along the direction, and the conductors are associated with a second range along the direction that at least partially overlaps with the first range.

[0115] Aspect 25: A device described in any of aspects 21 to 24, wherein a subset of memory cells among the plurality of memory cells are respectively arranged along each cell pillar extending along the direction, and each cell pillar is associated with a cross-sectional area smaller than the cross-sectional area of ​​the conductor.

[0116] The terms “electronic communication,” “conductive contact,” “connected,” and “coupled” may refer to a relationship between components that supports the flow of signals between them. Components are considered to be in electronic communication with each other (or in conductive contact, or connected, or coupled) if any conductive path exists between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication with each other (e.g., in conductive contact, or connected, or coupled) can be an open circuit or a closed circuit based on the operation of the device including the connected components. The conductive path between connected components may be a direct conductive path between the components, or the conductive path between connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between connected components may be temporarily interrupted using one or more intermediate components, such as, for example, a switch or transistor.

[0117] The term "coupling" (e.g., "electrically coupling") may refer to a state of transitioning from an open-circuit relationship between components, where signals cannot currently be communicated between the components via a conductive path, to a closed-circuit relationship between the components, where signals can be communicated between the components via a conductive path. When a component, such as a controller, couples other components together, it initiates a change that allows signals to flow between the other components via a conductive path where signals previously could not flow.

[0118] The term "isolated" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from one another if an open circuit exists between them. For example, two components separated by a switch placed between them are isolated from one another if the switch is open. When a controller isolates two components, the controller affects a change that prevents signals from flowing between the components using a conductive path through which signals previously could flow.

[0119] The terms "if," "when," "based on," or "based at least in part on" may be used interchangeably. In some examples, when the terms "if," "when," "based on," or "based at least in part on" are used to describe a conditional action, a conditional process, or a connection between portions of a process, the terms may be interchangeable.

[0120] The devices described herein, including memory arrays, may be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloy, gallium arsenide, or gallium nitride. In some cases, the substrate is a semiconductor wafer. In other examples, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled through doping using various chemical species, including, but not limited to, phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate, or by any other doping means.

[0121] The switching components or transistors described herein may represent field-effect transistors (FETs) and may include three-terminal devices including a source, a drain, and a gate. The terminals may be connected to other electronic elements through conductive materials, such as metals. The source and drain may be conductive and may include heavily doped, e.g., degenerate, semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., when the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., when the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. The conductivity of the channel can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may result in the channel becoming conductive. A transistor may be "turned on" or "activated" when a voltage equal to or greater than the transistor's threshold voltage is applied to the transistor gate. When a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor can be "off" or "deactivated."

[0122] The description set forth herein with reference to the accompanying drawings describes exemplary configurations and does not represent every example that may be implemented or that is within the scope of the claims. As used herein, the term "exemplary" means "serving as an example, instance, or illustration," and does not mean "preferred" or "advantageous over other examples." The detailed description includes specific details to provide an understanding of the described technology. However, these technologies may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0123] In the accompanying figures, similar components or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that distinguishes between the similar components. When only a first reference label is used in the specification, the description can apply to any one of the similar components having the same first reference label, regardless of the second reference label.

[0124] As used herein, including the claims, "or" when used in a list of items (e.g., a list of items ending with a phrase such as "at least one of" or "one or more of") indicates an inclusive list; for example, a list of at least one of A, B, or C means A, or B, or C, or AB, or AC, or BC, or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an example step described as "based on condition A" could be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" is to be construed the same as the phrase "based at least in part on."

[0125] The description herein is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not limited to the embodiments and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. 1. A method comprising: forming a stack of material layers over a substrate of a memory die; forming a plurality of cavities through the stack of material layers; forming an integrated cavity through the stack of material layers at least in part by integrating at least two cavities of the plurality of cavities; forming a conductor through the stack of material layers based at least in part on forming one or more conductive materials within the integrated cavity; and The method comprising:

2. forming a plurality of second cavities through the stack of material layers; forming a plurality of memory cells based at least in part on forming a semiconductor material in the plurality of second cavities; and Including, the conductors are operable to electrically couple to at least a subset of the plurality of memory cells. The method of claim 1.

3. The method of claim 2 , wherein the plurality of second cavities are formed simultaneously with forming the plurality of cavities.

4. forming a plurality of voids based at least in part on removing portions of a second material of the stack of material layers from between layers of a first material of the stack of material layers; forming a plurality of word lines electrically coupled to the plurality of memory cells based at least in part on forming one or more second conductive materials in the plurality of voids; further comprising the conductor is electrically coupled to at least one word line of the plurality of word lines; The method of claim 2.

5. forming the at least two cavities exposes a third conductive material between the stack of material layers and the substrate; forming the conductor includes forming a conductive material of the one or more conductive materials in contact with the third conductive material; The method of claim 1.

6. The method of claim 1 , wherein the conductor is electrically coupled to one or more transistors formed at least in part from doped portions of the substrate.

7. Integrating the at least two cavities includes: forming a plurality of voids between adjacent ones of the at least two cavities based at least in part on removing portions of a second material of the stack of material layers from between layers of a first material of the stack of material layers. The method of claim 1.

8. Integrating the at least two cavities includes: The method of claim 1 , further comprising removing portions of a first material of the stack of material layers and a second material of the stack of material layers between adjacent ones of the at least two cavities.

9. forming a sacrificial material within the plurality of cavities; removing the sacrificial material from at least two second cavities of the plurality of cavities; recessing the second material of the stack of material layers with the at least two second cavities to expose sidewalls of the second material between layers of the first material of the stack of material layers; forming a portion of the first material on the exposed sidewall of the second material; removing the sacrificial material from the at least two cavities of the plurality of cavities; removing a portion of the second material through the at least two cavities to expose a sidewall of the portion of the first material; forming a conductive material in contact with the exposed sidewall of the portion of the first material of the one or more conductive materials; The method of claim 1 further comprising:

10. forming a sacrificial material within the plurality of cavities; removing the sacrificial material from the at least two cavities of the plurality of cavities; recessing a second material of the stack of materials with the at least two cavities to expose sidewalls of a second material between layers of a first material of the stack of material layers; forming a portion of the first material on the exposed sidewall of the second material; forming a conductive material of the one or more conductive materials in contact with the portion of the first material; The method of claim 1 further comprising:

11. The method of claim 1 , wherein the stack of material layers comprises alternating layers of oxide and nitride materials.

12. 1. An apparatus comprising: an array region on a substrate including a plurality of memory cells and a plurality of access lines coupled to the plurality of memory cells, the plurality of access lines being disposed along a direction away from the substrate and each being disposed between a first layer of dielectric material in the array region; a conductor operable to couple to at least one memory cell of the plurality of memory cells, the conductor located outside the array area; a plurality of first conductor portions each aligned along the direction away from the substrate; and at least one second conductor portion coupled to an adjacent first conductor portion of the plurality of first conductor portions, each second conductor portion being located between the second layers of the dielectric material outside the array region. The device comprising:

13. 13. The apparatus of claim 12, wherein the conductor is operable to couple the at least one memory cell of the plurality of memory cells with one or more transistors formed at least in part from doped portions of the substrate.

14. The apparatus of claim 12 , wherein the conductor contacts a portion of at least one access line of the plurality of access lines outside the array area.

15. the plurality of memory cells are associated with a first range along the direction; and The apparatus of claim 12 , wherein the conductor is associated with a second range along the direction that at least partially overlaps the first range.

16. 13. The device of claim 12, wherein a subset of memory cells of the plurality of memory cells are respectively disposed along respective cell pillars extending along the direction, each cell pillar being associated with a cross-sectional area smaller than a cross-sectional area of ​​the conductor.

17. 1. An apparatus comprising: an array region on a substrate including a plurality of memory cells and a plurality of access lines coupled to the plurality of memory cells, the plurality of access lines being disposed along a direction away from the substrate and each being disposed between layers of dielectric material in the array region; a conductor operable to couple to at least one memory cell of the plurality of memory cells, the conductor located outside the array area and associated with an axis aligned along the direction; one or more dielectric portions around at least a portion of the conductor, each dielectric portion of the one or more dielectric portions including at least one protrusion of the dielectric material toward the axis; The device comprising:

18. 20. The apparatus of claim 17, wherein the conductor is operable to couple the at least one memory cell of the plurality of memory cells with one or more transistors formed at least in part from doped portions of the substrate.

19. 20. The apparatus of claim 17, wherein the conductor contacts a portion of at least one access line of the plurality of access lines outside the array area.

20. 20. The device of claim 17, wherein a subset of memory cells of the plurality of memory cells are respectively disposed along respective cell pillars extending along the direction, each cell pillar being associated with a cross-sectional area smaller than a cross-sectional area of ​​the conductor.

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