Die-to-die and chip-to-chip connectivity monitoring

Abstract

An input / output (I / O) sensor for a multi-IC (integrated circuit) module is provided. The I / O sensor includes a signal input configured to receive a data signal from an interconnection portion of an IC of the multi-IC module, and a duration measurement circuit configured to measure the duration between a first time when the data signal is at a first level and a second time when the data signal is at a second level different from the first level. The sensor can be incorporated into an I / O block, an IC, and / or the multi-IC module. An I / O sensor including a controller configured to measure duty cycle distortion of a multi-phase clock is also disclosed.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to U.S. Provisional Patent Application No. 63 / 444,016, filed February 8, 2023, entitled "Die-to-Die and Chip-to-Chip Connectivity Monitoring," and U.S. Patent Application No. 18 / 209,685, filed June 14, 2023, entitled "Die-to-Die and Chip-to-Chip Connectivity Monitoring," the contents of both applications being incorporated herein by reference.

[0002] FIELD OF THE INVENTION The present invention relates to the field of integrated circuits. [Background technology]

[0003] A semiconductor integrated circuit (IC) typically contains analog and digital electronic circuits on a flat semiconductor substrate such as a silicon wafer. Using photolithography techniques, tiny transistors are printed onto the substrate to create complex circuits with billions of transistors in a very small area, making modern electronic circuit designs using ICs low-cost and high-performance. ICs are manufactured on assembly lines in factories called foundries, which have commoditized the production of ICs, such as complementary metal-oxide-semiconductor (CMOS) ICs.

[0004] Typically, ICs are manufactured in large batches on a single wafer of electronic-grade silicon (EGS) or other semiconductor (such as GaAs). The wafer is cut (diced) into many pieces, each containing one copy of the circuit. Each of these pieces is called a "die."

[0005] Digital ICs are typically packaged in a metal, plastic, glass, or ceramic casing. The casing, or "package," is connected to a circuit board, such as by using solder. Package types include lead frames (through-hole, surface mount, chip carriers, etc.), pin grid arrays, chip scale packages, ball grid arrays, etc., for connecting between the IC pads and the circuit board.

[0006] Some modern ICs are actually modules composed of multiple interconnected ICs (sometimes called "chips," "dies," "tiles," or "chiplets") configured to work together. A typical example is a logic IC interconnected with a memory IC, but many other types exist. Many die-to-die (i.e., IC-to-IC) connection technologies also exist. One example is wafer-level integration, featuring high-density connectivity based on redistribution layers (RDLs) and Through Integrated Fan-Out Vias (TIVs), as sold by Taiwan Semiconductor Manufacturing Company (TSMC), Limited. Another example is system-level integration, featuring individual chips bonded via microbumps on a silicon interposer, such as Chip on Wafer on Substrate (CoWoS) technology sold by TSMC Limited and Embedded Interconnect Bridge (EMIB) technology sold by Intel Corporation. Both enable High Bandwidth Memory (HBM) subsystems. A third example is three-dimensional (3D) chip stacking technologies based on Through Silicon Via (TSV), such as the Chip-on-Wafer (CoW) and Wafer-on-Wafer (WoW) technologies sold by TSMC Limited.

[0007] The foregoing examples of the related art and their associated limitations are intended to be illustrative and not exhaustive. Other limitations of the related art will become apparent to those skilled in the art upon reading the specification and studying the drawings. Summary of the Invention

[0008] The following embodiments and aspects thereof are described and illustrated in conjunction with systems, tools, and methods that are meant to be exemplary and illustrative, not limiting in scope.

[0009] In a first aspect, an input / output (I / O) sensor for a multi-IC (integrated circuit) module is provided, the I / O sensor comprising: a signal input configured to receive a data signal from an interconnection portion of an IC of the multi-IC module; and a duration measurement circuit configured to measure the duration between a first time that the data signal is at a first level and a second time that the data signal is at a second level different from the first level.

[0010] In a further aspect, a non-transitory computer-readable medium having stored thereon computer-readable encoding of an I / O sensor is provided, the computer-readable encoding of the I / O sensor comprising: a signal input configured to receive a data signal from an interconnect portion of an IC of a multi-IC module; and a duration measurement circuit configured to measure a duration between a first time that the data signal is at a first level and a second time that the data signal is at a second level different from the first level.

[0011] In some embodiments, the duration measurement circuit comprises a first comparator circuit configured to generate a first timing signal having an edge when the received data signal is at a first given level, a second comparator circuit configured to generate a second timing signal having an edge when the received data signal is at a second given level, and a timing measurement circuit configured to receive the first timing signal and the second timing signal and measure the time between an edge of the first timing signal and an edge of the second timing signal.

[0012] In some embodiments, the timing measurement circuit comprises: a delay circuit configured to receive a first timing signal and generate a delayed data signal, the delay circuit comprising an adjustable delay line configured to delay the input signal by a set time span; a comparison circuit configured to generate a comparison signal by comparing a second timing signal with the delayed data signal; and timing measurement processing logic configured to set the time span of the adjustable delay line and to determine the duration based on the comparison signal.

[0013] In some embodiments, the timing measurement processing logic is configured to, for each of a plurality of time spans, set an adjustable delay line to the respective time span, determine whether the comparison signal for each time span indicates a pass state or a fail state, and identify a minimum time span from the plurality of time spans for which the comparison signal indicates a fail state.

[0014] In some embodiments, the I / O sensor (or computer-readable encoding thereof) further comprises an offset cancellation circuit configured to selectively apply a signal derived from the received data signal to the duration measurement circuit such that, in a first mode, the first given level is the first level and the second given level is the second level, and in a second mode, the first given level is the second level and the second given level is the first level.

[0015] In some embodiments, the offset cancellation circuit comprises a first multiplexing arrangement configured to operate in a first mode in which a first level is provided to a first comparator circuit and a second level is provided to a second comparator circuit, or in a second mode in which the first level is provided to the second comparator circuit and the second level is provided to the first comparator circuit; and a second multiplexing arrangement configured to operate in the first mode in which an output of the first comparator circuit is provided as a first timing signal to the timing measurement circuit and an output of the second comparator circuit is provided as a second timing signal to the timing measurement circuit, or in the second mode in which an output of the second comparator circuit is provided as the first timing signal to the timing measurement circuit and an output of the first comparator circuit is provided as a second timing signal to the timing measurement circuit.

[0016] In some embodiments, each of the first comparator circuit and the second comparator circuit is configured to operate in a first mode in which the respective comparator circuit generates a respective timing signal having a positive edge when the rising edge of the received data signal is at a respective given level, or in a second mode in which the respective comparator circuit generates a respective timing signal having a positive edge when the falling edge of the received data signal is at a respective given level.

[0017] In some embodiments, the timing measurement circuit comprises: a delay circuit configured to receive a first timing signal and generate a delayed data signal, the delay circuit comprising an adjustable delay line configured to delay the input signal by a set time span; a comparison circuit configured to generate a comparison signal by comparing a second timing signal with the delayed data signal; and timing measurement processing logic configured to set the time span of the adjustable delay line and to determine the duration based on the comparison signal.

[0018] In some embodiments, the comparison circuit comprises a first state element configured to receive the delayed data signal and provide a first state element output based on the delayed data signal and a clock input, a logic arrangement comprising a NOT gate and a NOR gate and configured to provide a logic arrangement output based on the first state element output, and a second state element configured to receive the logic arrangement output and provide a second state element output based on the logic arrangement output and the clock input, the clock input is preferably based on the second timing signal, and the local arrangement is configured to receive the first state element output at the NOT gate and provide the output of the NOT gate as a first input to the NOR gate and provide the second state element output at a second input to the NOR, the logic arrangement output being the output of the NOR gate.

[0019] In some embodiments, the clock input is the second timing signal or a delayed version of the second timing signal.

[0020] In some embodiments, the comparison circuit further comprises a third state element configured to receive a low logic level at its third state element data input and to provide a third state element output based on the received low logic level and the clock input, and further configured to receive a reset signal at its third state element set state input, and a fourth state element configured to receive a signal based on the third state element output at its fourth state element data input and to provide a fourth state element output based on the signal received at the fourth state element data input and the clock input, and further configured to receive a reset signal at its fourth state element set state input. The first state element is preferably further configured to receive the reset signal at its first state element set state input, and the second state element is further configured to receive a signal based on the fourth state element output at its second state element state reset input.

[0021] In some embodiments, the I / O sensor (or each of the computer-readable encodings thereof) further comprises sensor processing logic configured to control the offset cancellation circuit and the duration measurement circuit to measure a first duration in a first mode of the offset cancellation circuit and a second duration in a second mode of the offset cancellation circuit, and to determine a signal duration based on the measured first and second durations.

[0022] In some embodiments, the duration measurement circuitry is further configured to measure the duration between a second time when the data signal is at the second level and a third time when the data signal is at a third level.

[0023] In some embodiments, the I / O sensor (or each of its computer-readable encodings) further comprises sensor processing logic configured to determine the slew rate of the data signal from the duration measured by the duration measurement circuitry.

[0024] In one aspect, an input / output (I / O) block for a multi-IC (integrated circuit) module is also provided, and in a related aspect, a computer-readable encoding of the I / O block is provided on a non-transitory computer-readable medium. The I / O block includes a receive buffer configured to receive voltage signals from interconnect portions of ICs of the multi-IC module and provide a receive buffer output, and an I / O sensor provided herein, the receive buffer output being provided as a signal input to the I / O sensor.

[0025] In some embodiments, the receiving buffer is further configured to receive a reference level input, the reference level input being the first level or the second level.

[0026] In some embodiments, the I / O block is located on an IC of the multi-IC module and is configured to interface with an external processor to store the measured duration.

[0027] Also contemplated is an input / output (I / O) monitoring system comprising a plurality of I / O blocks, each I / O block as provided herein, the plurality of I / O blocks being controlled by a common I / O controller. In a related aspect, computer-readable encoding of the I / O monitoring system is provided on a non-transitory computer-readable medium.

[0028] An integrated circuit (IC) that is part of a multi-IC module may also be contemplated, the IC comprising an input / output (I / O) block provided herein or an input / output (I / O) monitoring system provided herein. In a related aspect, computer-readable encoding of the IC is provided on a non-transitory computer-readable medium.

[0029] A multi-IC module may also be provided, comprising: a first IC provided herein; a second IC provided herein; and an interconnection between the first IC and the second IC, the interconnection comprising one or more lanes, each of the one or more lanes providing an interconnection between a transmit buffer of one of the first IC and the second IC and a receive buffer of the other of the first IC and the second IC. In a related aspect, computer-readable encoding of the multi-IC module is provided on a non-transitory computer-readable medium.

[0030] Still further, an input / output (I / O) sensor for a multi-IC (integrated circuit) module may be provided, the I / O sensor comprising: two multiplexers each configured to select a different phase signal from a plurality of phase signals of a multi-phase clock; a duration measurement circuit configured to measure a time difference between an edge of a first one of the selected phase signals and an edge of a second one of the selected phase signals; and a controller configured to measure duty cycle distortion of the multi-phase clock by comparing the measured time difference with known time differences expected from an optimal multi-phase clock.

[0031] Further, a non-transitory computer-readable medium may be provided having stored thereon a computer-readable encoding of an I / O sensor comprising: two multiplexers each configured to select a different phase signal from a plurality of phase signals of a multi-phase clock; a duration measurement circuit configured to measure a time difference between an edge of a first one of the selected phase signals and an edge of a second one of the selected phase signals; and a controller configured to measure duty cycle distortion of the multi-phase clock by comparing the measured time difference to a known time difference expected from an optimal multi-phase clock.

[0032] In addition to the exemplary aspects and embodiments described above, further aspects and embodiments will become apparent by reference to the drawings and by study of the following detailed description. Those skilled in the art will appreciate that combinations and subcombinations of specific features disclosed herein may also be provided even if not explicitly set forth. [Brief explanation of the drawings]

[0033] Exemplary embodiments are illustrated in the referenced figures. Dimensions of components and features shown in the figures have generally been chosen for convenience and clarity of presentation and have not necessarily been drawn to scale. The figures are listed below. [Figure 1] 1 shows a schematic block diagram of a die-to-die connectivity monitoring system according to the present disclosure; [Figure 2] 1 shows a schematic block diagram of an input / output (I / O) block for use in a die-to-die connectivity monitoring system. [Figure 3] 1 shows a schematic circuit diagram of an I / O sensor forming part of an I / O block. [Figure 4] 1 illustrates a waveform timing diagram for monitoring margin parameters with reference to setup time in accordance with the present disclosure. [Figure 5] 1 illustrates a waveform timing diagram for monitoring margin parameters with reference to hold time in accordance with the present disclosure. [Figure 6] 10 illustrates waveform timing diagrams of the operation of the die-to-die connectivity monitoring system throughout a measurement cycle. [Figure 7] 4 shows waveform timing diagrams for activating and resetting the I / O sensor according to FIG. 3. [Figure 8] 1 shows a schematic block diagram of an I / O block controller forming part of an I / O block. [Figure 9] 9 illustrates a schematic circuit diagram of a portion of the I / O block controller of FIG. 8 configured for Automatic Test Pattern Generation (ATPG) mode and sensor reset. [Figure 10] 1 illustrates a schematic circuit diagram of an implementation of an I / O sensor according to the present disclosure for monitoring degradation of a bidirectional or receive-only interconnect signal channel. [Figure 11] 1 illustrates a schematic circuit diagram of one implementation of an I / O sensor for monitoring degradation of a transmit-only signal interconnect channel. [Figure 12A] 1 shows waveform timings for three scenarios in monitoring degradation of transmit-only signal interconnection channels. [Figure 12B] 1 shows waveform timings for three scenarios in monitoring degradation of transmit-only signal interconnection channels. [Figure 12C] 1 shows waveform timings for three scenarios in monitoring degradation of transmit-only signal interconnection channels. [Figure 13] 1 illustrates a schematic circuit diagram of one implementation of an I / O sensor for monitoring degradation of a differential interconnect receive channel. [Figure 14] 1 illustrates a schematic circuit diagram of one implementation of an I / O sensor for monitoring degradation of a differential interconnect transmission channel. [Figure 15] 1 shows a schematic circuit diagram of chip-to-chip interconnects showing I / O sensors for monitoring degradation. [Figure 16A] FIG. 1 shows a first block diagram of an I / O sensor for monitoring degradation of chip-to-chip interconnects, showing inputs and outputs. [Figure 16B]FIG. 1 shows a second block diagram of an I / O sensor for monitoring degradation of chip-to-chip interconnects based on a general-purpose delay time measurement sensor. [Figure 17] FIG. 16 shows a simplified schematic circuit diagram of the inter-chip interconnection according to FIG. 15, illustrating slew rate measurements. [Figure 18] 1 shows an exemplary eye diagram of a received signal illustrating an I / O sensor measurement. [Figure 19] 1 shows a first variation of an I / O sensor structure incorporating offset cancellation. [Figure 20] 10 shows a second variation of the I / O sensor structure incorporating offset cancellation. [Figure 21] 10 shows an exemplary eye diagram of a received signal showing I / O sensor measurements when using offset cancellation. [Figure 22] FIG. 10 shows a timing diagram for measuring rising and falling edge timing when using offset cancellation. [Figure 23] A schematic circuit diagram of an I / O sensor for multiphase clock measurement is shown. [Figure 24] 10 shows a schematic circuit diagram of a further embodiment of an I / O sensor that allows multi-phase clock measurement and measurement of adjustable delays. DETAILED DESCRIPTION OF THE INVENTION

[0034] Disclosed herein are devices, systems, and methods for measuring and / or estimating input / output (I / O) margin and / or eye pattern parameters and / or integrity and / or degradation of a multi-IC module (sometimes referred to as a "multi-chip module") or one or more portions thereof, and / or for optimizing the power and / or performance of such a multi-IC module or one or more portions thereof.

[0035] The term "multi-IC module" as referred to herein may refer to a group of interconnected ICs that are integrated and packaged together and configured to cooperate through this interconnection to achieve a particular integrated function. The ICs within the module may communicate with each other, for example, via an interconnect bus (sometimes simply referred to as an "interconnect," "lane," or "channel"). Their physical integration may be horizontal, vertical, or both.

[0036] Multi-IC modules to which this disclosure pertains can be constructed with any known or later-introduced integration technology that provides either direct connections between ICs or indirect connections via intermediaries such as specific interposers, substrates, or circuit boards. A multi-IC module can also use both direct and indirect connectivity between various pairs of its integrated ICs. Current examples of multi-IC module integration technologies include chip-on-wafer-on-substrate (CoWoS), wafer-on-wafer (WoW), chip-on-wafer (CoW), and 3D (three-dimensional) ICs. However, embodiments of the present invention will certainly benefit any other type of multi-IC module featuring die-to-die (IC-to-IC) or chip-to-chip (C2C) connectivity.

[0037] C2C connectivity may differ from die-to-die connectivity. C2C interconnects may have significantly higher capacitance than other multi-IC module integration technologies due to longer lane lengths. To reduce speed limitations on the interconnect, coding of data transmitted over the interconnect channel may be performed (error control or channel coding). Therefore, specific coding patterns may be used for interconnect calibration. The same or similar patterns may be used for I / O monitoring. I / O monitoring may be enabled during the lane training phase at a predefined data rate.

[0038] Despite the use of the terms D2D and C2C throughout this specification, those skilled in the art will recognize that embodiments described as useful for D2D may also be useful for C2C, and vice versa.

[0039] Disclosed herein are devices, systems, and methods that involve die-to-die connectivity monitoring, particularly determining the quality of connectivity for high-speed die-to-die interconnects. Such interconnects may implement wide buses and / or low power (picojoules / bit). Quality issues can be due to open circuits, short circuits, bridge shorts (between signals), degradation of microbump resistors on the receiver side, and / or degradation of microbump resistors on the transmitter side. In this case, a change in signal timing at the receiver is expected, and the change can be detected by the monitoring system. The timing and power effects of this monitoring are minimal.

[0040] HBM3 (High Bandwidth Memory 3) is a type of inter-die connectivity that implements different types of lanes: bidirectional lanes, receive-only lanes, transmit-only lanes, and differential lanes. Each of these lane types can be monitored in a different manner, as described herein.

[0041] The margin need not be measured by examining the timing difference between signals, but instead by comparing the received data signal with that data signal delayed using an adjustable delay line configured to provide a predetermined time delay. If the comparison results in a pass, the margin is greater than the delay applied to the data signal. The minimum delay applied to the data signal that causes the comparison to fail can be considered the margin. By using an adjustable delay line in this manner, high resolution in margin measurement can be achieved. Existing direct time measurements have relatively poor resolution (e.g., about one buffer delay), which, depending on the technology, can be in the range of 10 picoseconds (ps). In contrast, using techniques according to the present disclosure, a resolution of about 2 ps (a fraction of the buffer delay) can be achieved.

[0042] The primary use is eye measurements for characterization, specifically measuring margin to failure, or performance, per pin or lane. An input / output (I / O) sensor is located at each receiver for each lane. The delay of an adjustable delay line is gradually shifted (adjusted in small increments) until a failure is detected. The I / O sensor can be configured for four modes to fully characterize the eye opening at the receiver. For degradation monitoring, the position of the adjustable delay line can be stored and compared with ongoing lifetime measurements. For eye width characterization, the delay line position can be used to measure the setup time to failure.

[0043] In a general sense according to a first aspect, an I / O sensor for a semiconductor IC may be considered. The I / O sensor comprises a delay circuit configured to receive a data signal from an interconnect portion of the semiconductor IC (e.g., at a pin or lane of one IC in a multi-IC module) and generate a delayed data signal. The delay circuit comprises an adjustable delay line configured to delay the input signal by a set duration (although, as explained below, the delayed data signal need not be the output of the adjustable delay line). The I / O sensor further comprises a comparison circuit configured to generate a comparison signal by comparing the data signal with the delayed data signal. Further, processing logic is provided that is configured to set the duration of the adjustable delay line and, based on the comparison signal, determine a margin measurement of the data signal for determining an interconnect quality parameter. According to this general sense, methods of manufacturing and / or operating an I / O sensor may also be provided, including corresponding steps of providing and / or configuring the I / O sensor accordingly.

[0044] The processing logic may be configured to set the adjustable delay line to each of a plurality of durations and, for each of the set durations, determine whether the comparison signal for the respective duration indicates a pass or fail state. The processing logic may then be configured to identify a minimum of the durations from the plurality of durations for which the comparison signal indicates a fail state. This minimum may correspond to a margin measurement.

[0045] The margin measurement may include one of a data signal setup time to a clock rising edge, a data signal setup time to a clock falling edge, a data signal hold time to a clock rising edge, and a data signal hold time to a clock falling edge. Multiple margin measurements may be determined for the same interconnect (pin or lane), each for a different one of the margins enumerated herein.

[0046] The interconnect quality parameters may include, for example, one or more of an eye pattern parameter, a microbump resistance parameter, a systematic effects parameter, and a parameter indicative of differential signal symmetry, which may be determined from margin measurements, optionally using other factors.

[0047] Other specific features are described below. The generalized meaning is again discussed further below.

[0048] Referring to FIG. 1, FIG. 1 shows a schematic block diagram of a die-to-die connectivity monitoring system, particularly, but not limited to, 3D ICs. The same system can be used to monitor any type of die-to-die connectivity, not just 3D ICs. In 2.5D packaging, interconnects (lanes) connect adjacent chips, e.g., a DRAM controller located in a System on Chip (SoC), to DRAM located in a stacked DRAM (HBM3) chip. In 3D packaging, interconnects (lanes) connect chips stacked on top of each other, e.g., a DRAM controller (first chip) located at the bottom of the stack, to SRAM dies stacked on top of each other. In other packaging types, the connectivity can be described as a transmitter driving a line with a receiver at the end, and the die-to-die connectivity monitoring system can still be used. However, this system is advantageous for 3D ICs in that there are area limitations and the system can service multiple receivers using a single I / O sensor.

[0049] The inter-die connectivity monitoring system detects reliability issues in mission mode per pin and enables margin characterization performance in four measurement modes per pin. Quality monitoring is based on (ongoing) tracking of received signal (Rx signal) timing at the receiver. Monitoring is performed lane-by-lane with minimal timing and power penalty. Possible quality issues can be related to open pins, shorted pins, bridged shorts (between signals), degradation of micro-bump resistors on the receiver side, and / or degradation of micro-bump resistors on the transmitter side.

[0050] The inter-die connectivity monitoring system supports multiple k I / O blocks, and each block supports multiple n I / O lanes. An I / O lane can be a bidirectional lane (providing both transmit and receive), a receive-only lane, a transmit-only lane, and / or a differential lane. The measurement process of each block is managed by a dedicated controller (Prtn_tca_block_controller) located within the block. The block controller controls n I / O sensors (one per lane or pin).

[0051] Configuration data and control signals are passed from the block controller to the I / O sensors, and fail indication data is passed from each I / O sensor to its respective block controller. During a measurement cycle, all n I / O sensors are activated in parallel to measure the margin to failure of each of the n pins. At the end of the measurement cycle, the controller retains the margin to failure of each pin, which in one embodiment is represented by a 6-bit digital display.

[0052] All block controllers are controlled by a central Full-Chip (FC) controller (prtn_tca_top_ctrl). The FC controller generates a low-frequency clock (Prtn_clk) that is used to start the finite state machines (FSMs) within the block controllers. The low-frequency clock (Prtn_clk) signal is generated from the Advanced Peripheral Bus (APB) clock. The frequency division is programmable and is related to the APB clock. The FC controller also generates a central active-low reset signal (prtn_rst_n) for all block controllers. The FC controller collects data from each of the block controllers and transmits it over a serial bus (e.g., APB, JTAG, I / O). 2 C) to send data to an external source.

[0053] In the characterization phase, an offline data analysis system receives margin data via an external source and uses this data to measure or calculate one or more of per-pin eye width, per-pin eye height, effect of clock duty cycle on per-pin eye width, jitter amplitude of per-pin eye width and / or eye height, systematic effect per pin group, and differential signal symmetry.

[0054] In mission mode, the offline data analysis system receives margin data via an external source and uses this data to calculate eye width degradation and / or micro-bump resistance degradation at the receiver side and / or micro-bump resistance degradation and / or differential lane micro-bump degradation at the transmitter side, which may include one or more of outlier detection, systematic shift detection, alerts, and lane repair.

[0055] Data analysis from multiple such inter-die connectivity monitoring systems, each embedded in a different IC, can be advantageously performed in an analysis system. The analysis system can be a computerized system including one or more hardware processors (e.g., CPUs), random-access memory (RAM), one or more non-transitory computer-readable storage devices, and a network interface controller (NIC). The storage devices can store program instructions and / or components configured to operate the hardware processors. The program instructions can include one or more software modules, such as a data analysis module that analyzes margin data received from ICs operating in the field.

[0056] The software components may include an operating system having various software components and / or drivers for controlling and managing general system tasks (e.g., memory management, storage device control, power management, network communications, etc.) and facilitating communication between various hardware and software components.

[0057] The analysis system may operate by loading the data analysis module's instructions into RAM, where the instructions are executed by the processor. The data analysis module's instructions may cause the analysis system to receive margin data collected from multiple ICs, such as via its network interface controller (e.g., via the Internet), process the data, and output a statistical analysis of the data. The statistical analysis may indicate, for example, eye pattern parameters (e.g., eye width), degradation rates, lanes and / or pins that typically weaken or degrade over a shorter period of time, etc. Based on the analysis performed in the system, one or more of the ICs may be reconfigured to adjust one or more of data throughput, clock rate, and processing time. In this regard, the system may send a message to each IC to be reconfigured through the system's NIC, via a communications network (e.g., the Internet), and the ICs' communications interfaces. The message may include instructions on how to set or change internal IC parameters to affect data flow or clock speed. The instructions may be individual for each IC and for each of that IC's specific margin data. Alternatively, the same instructions may be sent to multiple ICs whose statistical analysis has classified them as closely related.

[0058] The analytical systems described herein are merely exemplary embodiments of the invention and may in fact be implemented solely in hardware, solely in software, or a combination of both hardware and software. The analytical system may have more or fewer components and modules than shown, may combine two or more of the components, or may have a different configuration or arrangement of the components. The analytical system may include any additional components that enable it to function as an operational computer system, such as a motherboard, data bus, power supply, display, input devices (e.g., keyboard, pointing device, touch-sensitive display), etc. Furthermore, the components of the analytical system may be co-located or distributed, or the analytical system may operate as one or more cloud computing “instances,” “containers,” and / or “virtual machines,” as known in the art.

[0059] Referring to Figure 2, a schematic block diagram of an I / O block is shown. This diagram depicts the block controller's connectivity to the I / O sensors (the pin names of the I / O sensors are the same as the signal names). The signals are described in more detail below.

[0060] The block controller (Prtn_tca_block_controller) is clocked by a Phase Locked Loop (PLL) divided clock (in one embodiment, a 10 GHz PLL clock and a divide by 10 equals 1 GHz) and by a low frequency clock (Prtn_clk) generated by the FC controller. The PLL clock is provided by the PLL block. The divided clock is therefore a derivative of the main clock used for data transmission. The two clocks are separate.

[0061] A divided PLL clock is used to synchronize the sensor fail indication signal and the internal FSM. A low frequency clock (Prtn_clk) interfaces with the FC controller and is used to acquire commands and read measurements. As described below, each I / O sensor is clocked by a PLL clock (10 GHz as mentioned above). The fail data margin is relative to the rising edge of this clock.

[0062] Referring to FIG. 3, there is shown a schematic circuit diagram of an I / O sensor that forms part of the I / O block. This is sometimes referred to as the Unified Tile Connectivity Agent (UTCA). As mentioned above, the main input to the I / O sensor is a clock signal, which is an undivided clock provided from the PLL block. In practice, the clock signal can be provided in two forms: a positive clock signal (clkp) and a negative clock signal (clkn), which is an inverted version of the positive clock signal. Another input is a data signal (d_in) from the pin or lane being measured. A configuration signal (ptrn_io_sensor_cfg) is also provided as an input to the I / O sensor. The I / O sensor also receives an enable signal (ptrn_io_sensor_en).

[0063] The main components of the I / O sensor are an adjustable delay line 10 and an XOR comparison logic gate that provides an output comparison signal (X0). The adjustable delay line provides an output signal (x_in_d) that is a version of its input delayed by a set, configurable duration. A number of state elements, or sampling elements, or flip-flops (FFs) are also provided, with a first state element (FF1) and a second state element (FF2) being the most relevant since the outputs of these two state elements are the two inputs to the XOR comparison logic gate. The I / O sensor also includes a signal multiplexing arrangement 20 that configures the inputs to the adjustable delay line, the first state element (FF1), and the second state element (FF2). Each of the state elements has two inputs: a respective data signal input 4 and a respective clock signal input. If the output of the first state element and the output of the second state element are the same, the output comparison signal (X0) will be a logic low value, indicating a pass result in which the margin is less than the set delay duration. If the output of the first state element and the output of the second state element differ, the output comparison signal (X0) will be a logic high value, indicating a fail result that the margin is less than or equal to the set delay duration.

[0064] The input signals are processed to define further signals. The data signal (d_in) and the enable signal (ptrn_io_sensor_en) are provided as inputs to a first AND gate to define a processed data signal (d_in_i). The positive clock signal (clkp) and the enable signal (ptrn_io_sensor_en) are provided as inputs to a second AND gate to define a processed positive clock signal (clk_p_i). The negative clock signal (clkn) and the enable signal (ptrn_io_sensor_en) are provided as inputs to a third AND gate to define a processed negative clock signal (clk_n_i).

[0065] The signal multiplexing arrangement 20 comprises a first multiplexer (Mux1), a second multiplexer (Mux2), a third multiplexer (Mux3), a fourth multiplexer (Mux4), a fifth multiplexer (Mux5), a sixth multiplexer (Mux6), and a seventh multiplexer (Mux7). Of course, the use of seven multiplexers is merely an illustrative example, and any number of multiplexers may be used as needed for a particular implementation while still following the principles described herein. The first multiplexer (Mux1) is controlled by a first 3-bit multiplexer control signal (S1) and provides the first multiplexer output by selecting from the inputs, i.e., the processed data signal (d_in_i), the processed positive clock signal (clk_p_i), and the processed negative clock signal (clk_n_i). The first multiplexer output is the input to an adjustable delay line.

[0066] The second multiplexer (Mux2) is controlled by a second 3-bit multiplexer control signal (S2) and provides the second multiplexer output by selecting from the inputs, i.e., the constant logic low signal (1'b0), the processed positive clock signal (clk_p_i), and the processed negative clock signal (clk_n_i). The third multiplexer (Mux3) is controlled by a third 3-bit multiplexer control signal (S3) and provides the third multiplexer output by selecting from the inputs, i.e., the processed data signal (d_in_i), the constant logic low signal (1'b0), and the constant logic low signal (1'b0).

[0067] The fourth multiplexer (Mux4), fifth multiplexer (Mux5), sixth multiplexer (Mux6), and seventh multiplexer (Mux7) are all controlled by a 1-bit common control signal (C0). For each of these multiplexers, when the common control signal is at a high logic level, the enumerated first input is provided as the output, and when the common control signal is at a low logic level, the enumerated second input is provided as the output. The fourth multiplexer (Mux4) provides the fourth multiplexer output by selecting from its input, i.e., the third multiplexer output and the adjustable delay line output signal (x_in_d). The fourth multiplexer output is the data input to the first state element (FF1). The fifth multiplexer (Mux5) provides the fifth multiplexer output by selecting from its input, i.e., the adjustable delay line output signal (x_in_d) and the second multiplexer output. The fifth multiplexer output is the clock input to the first state element (FF1). The sixth multiplexer (Mux6) provides the sixth multiplexer output by selecting from the inputs, i.e., the third multiplexer output and the first multiplexer output. The sixth multiplexer output is the data input to the second state element (FF2). The seventh multiplexer (Mux6) provides the seventh multiplexer output by selecting from the inputs, i.e., the first multiplexer output and the second multiplexer output. The seventh multiplexer output is the clock input to the second state element (FF2).

[0068] The I / O sensors can measure the relative timing characteristics of data and clock signals, and by appropriate configuration of the signal multiplexing arrangement, can measure the data signal setup time to the rising edge of the clock, the data signal setup time to the falling edge of the clock, the data signal hold time to the rising edge of the clock, and the data signal hold time to the falling edge of the clock, as further described below.

[0069] The I / O sensors are configured by setting the configuration signals (prtn_io_sensor_cfg[10:0] configuration bit values). The 11 configuration bits are responsible for three types of functions: four configuration bits (prtn_io_sensor_cfg[3:0]) configure adjustable delay line values ​​that are dynamically changed during margin testing; five configuration bits (prtn_io_sensor_cfg[8:4]) are configured according to the operating frequency (equal to half the data rate) and do not change during margin testing; and two configuration bits (prtn_io_sensor_cfg[10:9]) configure the measurement mode.

[0070] An example of how the five configuration bits (prtn_io_sensor_cfg[8:4]) can be configured according to the operating frequency is shown in the table below.

[0071] [Table 1]

[0072] During the measurement cycle (described in more detail below), the block controller configures the internal adjustable delay line of each I / O sensor using four configurations reserved for this purpose (prtn_io_sensor_cfg[3:0]). This allows up to 16 different delay times to be set for margin measurements. The minimum delay line value is configured by prtn_io_sensor_cfg[3:0] =

[0000] , and the maximum delay line value is configured by prtn_io_sensor_cfg[3:0] =

[11111] .

[0073] Four different margin measurement modes are described in detail below. The first mode to be considered is the measurement of the data signal setup time to the rising clock edge. In this mode, the first multiplexer (Mux1) is controlled to provide the first multiplexer output as the processed data signal (d_in_i), the second multiplexer (Mux2) is controlled to provide the second multiplexer output as the processed positive clock signal (clk_p_i), and the common control signal (C0) is set to a logic low value. The third multiplexer output is irrelevant and can therefore be set to a constant logic low signal (1'b0). As a result, the first state element is configured to sample the delayed data signal with the positive clock signal, and the second state element is configured to sample the data signal with the positive clock signal (i.e., without delay). Thus, the XOR comparison logic gate tests whether the data signal and the delayed data signal are the same when both are sampled by the same rising clock edge.

[0074] Measurement of the data signal setup time to the falling edge of the clock is performed as follows. In this mode, the first multiplexer (Mux1) is controlled to provide the first multiplexer output as the processed data signal (d_in_i), the second multiplexer (Mux2) is controlled to provide the second multiplexer output as the processed negative clock signal (clk_n_i), and the common control signal (C0) is set to a logic low value. The third multiplexer output is irrelevant and can therefore be set to a constant logic low signal (1'b0). As a result, the first state element is configured to sample the delayed data signal with the negative clock signal, and the second state element is configured to sample the data signal with the negative clock signal (i.e., without delay). Thus, the XOR comparison logic gate tests whether the data signal and the delayed data signal are the same when both are sampled by the negative clock rising edge of the same clock.

[0075] Reference is now made to Figure 4, which shows a waveform timing diagram for monitoring margin parameters with reference to setup time. The top waveform shows a clock signal (clk) and indicates a UI (unit interval), which defines the minimum data width. For example, a system using Dual Data Rate (DDR) generates data on the rising and falling edges of the clock, such that the UI is equal to the time interval between the rising and falling edges of the clock. The second waveform is the data signal (d_in). From this, the setup time to the rising edge of the clock (ΔT_S_r) and the setup time to the falling edge of the clock (ΔT_S_f) can be determined. Also shown is a delayed data signal (x_in_d), which is the output from the adjustable delay line, and shows different delay ranges depending on the delay duration set in the adjustable delay line. Also shown is the output comparison signal (X0) for a particular delayed data signal (x_in_d), which in the illustrated case indicates a logic high, thus indicating that the margin is at least the set delay duration. The sensor output signal (SO) corresponds to the sensor fail indication signal (ptrn_io_sensor_fail), which is a sticky bit that remains at a logic high level after the first fail until reset, as further described below.

[0076] Measurement of the hold time of the data signal to the rising edge of the clock is performed as follows. In this mode, the first multiplexer (Mux1) is controlled to provide the first multiplexer output as the processed positive clock signal (clk_p_i), the third multiplexer (Mux3) is controlled to provide the third multiplexer output as the processed data signal (d_in_i), and the common control signal (C0) is set to a logic high value. The second multiplexer output is irrelevant and can therefore be set to a constant logic low signal (1'b0). In this case, the output of the adjustable delay line is the positive delayed clock signal. No data signal is provided as an input to the adjustable delay line. As a result, the first state element is configured to sample the data signal with the positive delayed clock signal. Therefore, the output of the first state element is a delayed data signal with a delay introduced by the sampling. The second state element is configured to sample the data signal with the positive clock signal (i.e., without delay). Thus, the XOR compare logic gate tests whether the data signal sampled by the rising clock edge and the data signal sampled by the delayed rising clock edge (ie, the delayed data signal) are the same.

[0077] Measurement of the data signal hold time to the falling edge of the clock is performed as follows. In this mode, the first multiplexer (Mux1) is controlled to provide the first multiplexer output as the processed negative clock signal (clk_n_i), the third multiplexer (Mux3) is controlled to provide the third multiplexer output as the processed data signal (d_in_i), and the common control signal (C0) is set to a logic high value. The second multiplexer output is irrelevant and can therefore be set to a constant logic low signal (1'b0). In this case, the output of the adjustable delay line is the negative delayed clock signal. A data signal is again not provided as an input to the adjustable delay line. As a result, the first state element is configured to sample the data signal with the negative delayed clock signal. The output of the first state element is again a delayed data signal with a delay introduced by the sampling. The second state element is configured to sample the data signal with the negative clock signal (i.e., without delay). Thus, the XOR compare logic gate tests whether the data signal sampled by the negative clock rising edge and the data signal sampled by the negative delayed clock rising edge (ie, the delayed data signal) are the same.

[0078] Reference is now made to FIG. 5, which illustrates a waveform timing diagram for monitoring margin parameters with reference to hold time. The top waveform shows the clock signal (clk), and the second waveform is the data signal (d_in). From this, the hold time (ΔT_H_f) to the falling edge of the clock and the setup time (ΔT_H_r) to the rising edge of the clock can be determined. The delayed clock signal (x_in_d), which is the output from the adjustable delay line, is also shown, indicating different delay ranges depending on the delay duration set in the adjustable delay line. Also shown is the output comparison signal (X0) for a particular delayed clock signal (x_in_d), which, in the illustrated case, exhibits a logic high, thus indicating that the margin is at least the set delay duration. The sensor output signal (SO) is as described above with reference to FIG. 4, and an example of its generation is described in detail below.

[0079] As mentioned above, two bits of the configuration signal (prtn_io_sensor_cfg) are used to configure the I / O sensor into one of four measurement modes. The first of these bits (prtn_io_sensor_cfg[9]) is a common control signal (C0) that configures the I / O sensor to set up or hold a measurement. When the common control signal (C0, prtn_io_sensor_cfg[9]) is a logic low value ([0]), the I / O sensor is configured into measurement setup mode, and when the common control signal (C0, prtn_io_sensor_cfg[9]) is a logic high value ([1]), the I / O sensor is configured into measurement hold mode. The second of these bits (C1, prtn_io_sensor_cfg

[10] ) determines whether the rising or falling clock edge is used as the reference. If this second bit (C1, prtn_io_sensor_cfg

[10] ) is a logic low value ([0]), the I / O sensor is configured for clock falling (negative) measurement mode, and if the second bit (C1, prtn_io_sensor_cfg

[10] ) is a logic high value ([1]), the I / O sensor is configured for clock rising (positive) measurement mode.

[0080] Using these two configuration bits, the I / O sensor can configure the signal multiplexing arrangement according to the logic equations in the table below.

[0081] [Table 2]

[0082] Returning to the generalized meaning according to the first aspect above, further features may be considered. For example, the comparison circuit may comprise an XOR gate. The comparison signal may then be based on the output of the XOR gate. One input to the XOR gate may be a data signal, and the other input may be a delayed data signal. The adjustable delay line may have a resolution of at least 1 ps. Additionally or alternatively, the adjustable delay line may have at least 16 configurations for duration.

[0083] In certain configurations, a data signal may be provided as an input signal to an adjustable delay line, and the data signal and delayed data signal are sampled according to a clock signal. In other configurations, the data signal is sampled according to a clock signal, and the clock signal is provided as an input signal to an adjustable delay line to provide a delayed clock signal. The delayed data signal may then be the data signal sampled according to the delayed clock signal.

[0084] The delay circuit may further comprise a first state element (e.g., a flip-flop) configured to receive a first state element input signal and provide a first state element output based on the first state element input signal and a first clock input, a second state element (e.g., a flip-flop) configured to receive a second state element input signal and provide a second state element output based on the second state element input signal and a second clock input, and a multiplexing arrangement. The multiplexing arrangement is advantageously configured to selectively apply one of two configurations. In the first configuration, a data signal is applied as an input signal to an adjustable delay line, the output of the adjustable delay line is provided as the first state element input signal, the data signal is provided as the second state element input signal, and clock signals are provided as the first clock input and the second clock input. In a second configuration, the clock signal is applied as an input signal to the adjustable delay line, the output of the adjustable delay line is provided as a first clock input, the data signal is provided as the first state element input signal and the second state element input signal, and the clock signal is provided as the second clock input. The multiplexing arrangement may be further configured to selectively apply as the clock signal (a) a positive clock signal or (b) a negative clock signal that is an inverted positive clock signal.

[0085] In another general sense according to a second aspect (which may be combined with any other aspect disclosed herein), an I / O block may be considered to include a plurality of I / O sensors, each as disclosed herein and configured to receive a respective different data signal from an interconnect portion of a semiconductor IC. Processing logic for each of the plurality of I / O sensors may be located in a common control block. Each I / O sensor may be configured to receive a respective data signal from a different pin of the interconnect portion of the semiconductor IC and, in parallel with other sensors, determine a margin measurement for each pin.

[0086] The I / O blocks may be located on a semiconductor IC, and may then be configured to interface with an external processor to store the determined margin measurements and / or to determine interconnect quality parameters.

[0087] In another general sense, according to a third aspect (which may be combined with any other disclosure herein), there may be provided an I / O monitoring system comprising a plurality of I / O blocks, each I / O block as disclosed herein, each of which may then be controlled by a common I / O controller.

[0088] Some generalized meanings may be considered as a semiconductor IC comprising an I / O block as described herein or an I / O monitoring system as described herein. Methods of manufacturing and / or operating the I / O block, I / O monitoring system, and / or semiconductor IC may also be provided, including corresponding steps of providing and / or configuring I / O sensors as appropriate, as described above.

[0089] The I / O sensor also includes a test verification section including a third state element (FF3), a fourth state element (FF4), an OR gate (OR1), and a fifth state element (FF5). The output comparison signal (X0) is provided as a first input to the OR gate (OR1), whose output is the data input to the fifth state element (FF5). The clock input to the fifth state element (FF5) is the seventh multiplexer output (which, as described above, is a positive clock signal when a rising edge measurement is being performed and a negative clock signal when a falling edge measurement is being performed). The output of the fifth state element (FF5) is provided as a second input to the OR gate (OR1). This output (provided via a buffer) indicates a sensor fail indication signal (ptrn_io_sensor_fail), which is held at a logic high value as soon as the output comparison signal (X0) goes high. This corresponds to the sensor output signal (SO) described above.

[0090] The sensor fail indication signal (ptrn_io_sensor_fail) is one bit from each I / O sensor that indicates that the adjustable delay line configuration is greater than or equal to the pin's margin, i.e., the time difference between data rising and clock rising. As mentioned above, the fail indication is generated by the I / O sensor using a sticky mechanism, i.e., once a fail indication is indicated, it remains at a logic high level until the next I / O sensor reset (as described below). The sensor indication is always relative to the I / O sensor's startup or current configuration mode.

[0091] The third state element (FF3) and the fourth state element (FF4) form a two-stage synchronizer that is used to reset the fifth state element (FF5), thereby resetting the test fail signal (ptrn_io_sensor_fail). The clock input to both the third state element (FF3) and the fourth state element (FF4) is the seventh multiplexer output (as described above). The data input to the third state element (FF3) is a constant logic low signal (1'b0), and the data input to the fourth state element (FF4) is the output of the third state element (FF3). An active-low asynchronous reset signal (ptrn_io_sensor_rst_n) input is also provided as a signal setting input to both the third state element (FF3) and the fourth state element (FF4). The output of the fourth state element (FF4) is provided as a reset signal to the fifth state element (FF5). Thus, the fifth state element (FF5) is used to synchronize the sensor fail indication signal to the high-speed clock. The series configuration of the third state element (FF3) and the fourth state element (FF4) is used to avoid metastability.

[0092] The block controller (prtn_tca_block_ctrl) generates a reset signal (prtn_io_sensor_rst_n) that is distributed to all I / O sensors within the block. The reset signal is related to the PLL divided clock domain used to clock the block controller (prtn_tca_block_ctrl). To do this, the block controller may use the block reset signal (prtn_rst_n) generated by the FC controller (prtn_tca_top_ctrl) and synchronized to the PLL divided clock.

[0093] The reset signal is generated by the block controller asynchronous to the I / O sensor operating clock (10 GHz clock in this illustrative example) and is used as an asynchronous reset in the I / O sensors. Therefore, the assertion of the I / O sensor reset is not synchronized to the 10 GHz clock. The reset should be asserted before any changes to the adjustable delay line configuration. The deassertion of the I / O sensor reset is synchronized within the I / O sensors to the I / O sensor operating clock (10 GHz). The synchronization is performed using a two-stage synchronizer located within each I / O sensor. The reset deassertion time is equal to two 10 GHz clock cycles.

[0094] The I / O sensor is activated by setting the activation signal (prtn_io_sensor_en) to high logic level ([1]). This is done one clock cycle (PLL divided clock cycle) before reset is deasserted. When the I / O sensor stops operating, the activation signal (prtn_io_sensor_en) is set to low logic level ([0]) one clock cycle (PLL divided clock cycle) after reset is asserted.

[0095] Generally, according to a fourth aspect, an input / output (I / O) sensor for a semiconductor three-dimensional (3D) integrated circuit (IC) may be considered. The I / O sensor includes a delay circuit configured to receive a data signal from an interconnection portion (which may be a bidirectional interface) of the semiconductor 3D IC and generate a delayed data signal; and a comparison circuit configured to generate a comparison signal by comparing the data signal with the delayed data signal. The delay circuit includes an adjustable delay line configured to delay an input signal by a set duration. The I / O sensor further includes processing logic configured to set the duration of the adjustable delay line and, based on the comparison signal, determine a margin measurement of the data signal for determining eye pattern parameters. Some or all of the processing logic may be co-located with the rest of the I / O sensor, or some or all of the processing logic may be located remotely from the I / O sensor. Some or all of the processing logic may be shared between two or more I / O sensors. Methods of measuring I / O margins may also be understood that include providing and / or operating features of the I / O sensor described herein.

[0096] Input / output (I / O) blocks with multiple I / O sensors may also be considered. In this case, each I / O sensor may be configured to receive a different data signal, particularly from a different interconnect portion, e.g., a different lane or pin, of a semiconductor 3D IC. When each I / O sensor is configured to receive a different data signal from a different pin of the interconnect portion of the semiconductor 3D IC, each I / O sensor may be configured to determine margin measurements for each pin in parallel with the other sensors. Some or all of the processing logic for each of the multiple I / O sensors of an I / O block is advantageously located in a common control block. The I / O sensors and / or the I / O block may be located on the semiconductor 3D IC. The I / O sensors and / or the I / O block may then be configured to interface with an external processor to store the determined margin measurements and / or to determine eye pattern parameters.

[0097] In a further aspect, an I / O monitoring system may be contemplated that includes multiple input / output (I / O) blocks, each of which may be controlled by a common I / O controller.

[0098] Yet another aspect can be found in a semiconductor three-dimensional (3D) integrated circuit (IC) comprising the input / output (I / O) sensors and / or I / O blocks and / or I / O monitoring systems described herein.

[0099] Referring again to the I / O sensors (optionally in an I / O block, an I / O monitoring system, or a 3D IC), further optional, preferred, and / or advantageous features may be considered.

[0100] The margin measurement may include, for example, one of a data signal setup time to a clock rising edge, a data signal setup time to a clock falling edge, a data signal hold time to a clock rising edge, and a data signal hold time to a clock falling edge.

[0101] For each of the plurality of durations, processing logic may set the adjustable delay line to the respective duration and determine whether the comparison signal for each duration indicates a pass state or a fail state. The processing logic may then identify a minimum duration from the plurality of durations for which the comparison signal indicates a fail state. Optionally, the processing logic may repeat setting the adjustable delay line to each of the plurality of durations and identifying the minimum duration for each of a plurality of measurement cycles. The processing logic may then further determine one or more of the lowest minimum duration across the plurality of measurement cycles, the highest minimum duration across the plurality of measurement cycles, and a sum of the minimum durations across the plurality of measurement cycles.

[0102] Optionally, the adjustable delay line has a resolution for duration of at least 1 ps (optionally 2 ps, or relative to the operating frequency) at the maximum operating frequency, and / or at least 16 (optionally 32) configurations.

[0103] In some embodiments, the comparison circuit comprises an XOR gate, a first input to which may be provided by a data signal (advantageously sampled), and a second input to which may be provided by a delayed data signal.

[0104] In certain modes of operation, a data signal is provided as an input signal to an adjustable delay line, and the data signal and a delayed data signal are sampled according to a clock signal. In other modes of operation, the data signal is sampled according to a clock signal, and the clock signal is provided as an input signal to an adjustable delay line to provide a delayed clock signal. The delayed data signal may then be the data signal sampled according to the delayed clock signal.

[0105] The operating mode may be controlled by a multiplexing arrangement. For example, the delay circuit may further comprise: a first state element configured to receive a first state element input signal and provide a first state element output based on the first state element input signal and a first clock input; a second state element configured to receive a second state element input signal and provide a second state element output based on the second state element input signal and a second clock input; and a multiplexing arrangement configured to selectively apply (i) a data signal as an input signal to an adjustable delay line, where the output of the adjustable delay line is provided as the first state element input signal, the data signal is provided as the second state element input signal, and a clock signal is provided as the first clock input and the second clock input, or (ii) a clock signal as an input signal to the adjustable delay line, where the output of the adjustable delay line is provided as the first clock input, the data signal is provided as the first state element input signal and the second state element input signal, and the clock signal is provided as the second clock input. The multiplexing arrangement may be further configured to selectively apply as the clock signal (a) a positive clock signal or (b) a negative clock signal that is an inverted positive clock signal.

[0106] The present disclosure has now been generally discussed according to several aspects, however, more specific details and other general aspects are revisited below.

[0107] Referring to FIG. 6, a waveform timing diagram of the operation of the die-to-die connectivity monitoring system through a measurement cycle is shown. The measurement cycle defines the activity of the block controller during the measurement period. Each measurement cycle includes multiple [K] delay line cycles. Each delay line cycle includes multiple (16 in one embodiment) measurements, each taken at a different position on the adjustable delay line. The number of measurements per delay line cycle can be, in a more general sense, 2 to 100, or more specifically, 2 to 10, 2 to 20, 2 to 30, 2 to 40, 2 to 50, 5 to 10, 5 to 20, 5 to 30, 5 to 40, 5 to 50, 10 to 20, 10 to 20, 10 to 30, 10 to 40, 10 to 50, 20 to 30, 20 to 40, 20 to 50, 30 to 40, 30 to 50, 40 to 50, or any other subrange from 2 to 100. In other embodiments, the number of measurements per delay line cycle may exceed 100.

[0108] A measurement cycle starts when a measurement command is sent to the block controller (prtn_tca_block_ctrl) and stops when a read cycle is performed. To perform a new measurement cycle, a new measurement command is sent. When the block controller receives a read command, it first disables the I / O sensor by setting the enable signal (ptrn_io_sensor_en) to a logic low level.

[0109] During each adjustable delay line cycle, the adjustable I / O sensor delay line is configured to each of its 16 positions, i.e., the adjustable I / O sensor delay line is changed from its minimum delay value to its maximum delay value. The time interval to stay at each position is defined by the "WIN" parameter. The WIN parameter is configurable to one of 8, 16, 32, and 64, and the time interval is equal to the WIN configuration multiplied by the PLL output time interval divided by the clock cycle time.

[0110] Referring to Figure 7, a waveform timing diagram for activating and resetting the I / O sensor according to Figure 3 is shown. The time to set a new delay line value is the sum of the time it takes for the block controller (prtn_tca_block_ctrl) to reset the fifth state element (FF5) that controls the sensor fail indication signal (ptrn_io_sensor_fail), the time to set a new delay line value (the position of the adjustable delay line), and the guard band time. This is calculated as eight cycles of the PLL divided clock (1 GHz in this example) in the following order: the first cycle [2] to set the active-low asynchronous reset signal (ptrn_io_sensor_rst_n); wait two cycles [4] to reset the sensor fail indication signal (ptrn_io_sensor_fail). The delay line cycle length is equal to [16 × WIN] + [32 × time to set a new adjustable delay line value].

[0111] 8, there is shown a schematic block diagram of an I / O block controller forming part of the I / O block. It comprises a synchronizer, first logic, a memory block, and second logic. The third logic generates an activation signal (ptrn_io_sensor_en), an active-low asynchronous reset signal (ptrn_io_sensor_rst_n), and four configuration bits that make up the adjustable delay line value (prtn_io_sensor_cfg[3:0]).

[0112] The synchronizer receives a 1-bit sensor fail indication signal (ptrn_io_sensor_fail) for each of multiple (in this case 44, [43:0]) different sensors, a PLL (1 GHz) clock signal, and an active-low asynchronous reset signal (ptrn_io_sensor_rst_n), and provides a synchronous sensor fail signal (sensor_fail_sync[43:0]) for each sensor to the first logic. The first logic then determines the minimum delay line position that causes a sensor fail and provides this to the memory block. The memory block should store, for each pin, the minimum delay line position that causes a sensor fail during a full delay line cycle (16 delay line positions executed by 16 WIN intervals). The second logic can be used to read from the memory block to the FC controller.

[0113] When the third logic in the block controller (prtn_tca_block_ctrl) receives the start_measure command, it first enables the I / O sensor by setting the enable signal (ptrn_io_sensor_en) to a logic high value, and then initiates a measurement cycle.

[0114] Four data types are generated by the block controller for each I / O sensor (pin), providing a total of 33 bits (or 31 bits depending on the count_length configuration). The first type is the lower minimum delay line position that caused a sensor fail during the full measurement cycle ([N] × delay line cycles), which requires 5 bits per I / O sensor (memory[4:0]). The second type is the higher minimum delay line position that caused a sensor fail during the full measurement cycle ([N] × delay line cycles), which requires 5 bits per I / O sensor (memory[4:0]). The third type is a validity bit that indicates that the lower minimum delay line position reading (first type) and the higher minimum delay line position reading (second type) correspond to an actual fail indication. Specifically, this bit indicates that the I / O sensor output, i.e., the sensor fail indication signal (prtn_io_sensor_fail), was logic high at least once during the measurement cycle.

[0115] The fourth type is the sum of the minimum delay line positions that will cause a sensor failure during each delay line cycle (one measurement cycle), which requires 14 bits (5 + 9) per I / O sensor for Count_length = 512, or 13 bits (5 + 8) per I / O sensor for Count_length = 256. The fifth type is the number of valid delay line cycles (counts) used in the sum of the minimum delay line values, which requires 9 bits (up to 512 counts) per I / O sensor. The fourth and fifth types are optional and depend on the readout mode (Readout_mode), which can be configured as a normal mode that reads 11 bits per I / O sensor (a total of 44 x 11 = 484 bits, or approximately 61 bytes), a debug mode that reads 33 bits per I / O sensor (a total of 44 x 33 = 1452, or approximately 181 bytes) when Count_length = 512, or 31 bits per I / O sensor (a total of 44 x 31 = 1364, or approximately 171 bytes) when Count_length = 256.

[0116] While executing in the WIN interval, the block controller checks the sensor fail indication signal (prtn_io_sensor_fail[43:0]) of each sensor. The signal is synchronized to the PLL divided clock in the block controller using a synchronizer. When the sensor fail indication signal (prtn_io_sensor_fail) is a logic high value, the block controller stores the value of the delay line position executed during the WIN interval in memory [x], but only if the delay line position is less than the position stored in memory [x].

[0117] The first five bits ([4:0]) of memory [x] store the delay line position, and the sixth bit ([5]) of memory [x] is the valid bit. The valid bit is set to a logic high value the first time the sensor fail indication signal (prtn_io_sensor_fail) of sensor ([x]) is found to be a logic high value. At the end of the delay line cycle, the memory of sensor ([x]) stores the minimum delay line value corresponding to the margin for each pin.

[0118] The block controller (prtn_tca_block_controller) stores the minimum adjustable delay line value that resulted in a fail from all delay line measurement cycles, as well as the maximum value from all minimum adjustable delay line values ​​that resulted in a fail measured across all delay line measurement cycles. It also stores the total of up to 512 delay line cycles, the minimum delay line value measured, and a count of how many measurement cycles were totaled.

[0119] The communication between the block controller (prtn_tca_block_controller) and the I / O sensors within the block provides high fan-out (FO) connectivity. The propagation delays of these signals are advantageously defined to optimize test efficiency, i.e., to optimize the test active time relative to the total test time.

[0120] To ensure the best operation of the I / O sensors, the signals driving them must arrive with a well-defined slope at the input of the I / O sensors. The table below defines the propagation time and signal slope (at the I / O sensor input) for each of the signals (between the block controller and the I / O sensors, optionally in both directions).

[0121] [Table 3]

[0122] Further referring to the generalized meaning above according to any of the aspects, the processing logic may be configured to repeat, for each of a plurality of measurement cycles, setting the adjustable delay line to each of a plurality of durations and identifying the minimum duration. The processing logic may then be configured to further determine one or more of the lowest minimum duration across the plurality of measurement cycles, the highest minimum duration across the plurality of measurement cycles, and a sum of the minimum durations across the plurality of measurement cycles.

[0123] Referring to Figure 9, a schematic circuit diagram of a portion of the I / O block controller of Figure 8 configured for automatic test pattern generation (ATPG) mode is shown. In particular, it comprises two serial state elements (D flip-flops), both clocked by a PLL clock (1 GHz). The first state element has a constant logic high value (1'b1) as its data input and provides its output (Q) as the data input to the second state element. Both state elements have a central active-low reset signal (prtn_rst_n) from the FC controller as their reset input, which is also provided as the first input (for a logic low value) of a multiplexer. The output (Q) of the second state element is provided as the second input (for a logic high value) of the multiplexer.

[0124] Referring to FIG. 10, a schematic circuit diagram of an implementation of an I / O sensor according to the present disclosure for monitoring degradation of a bidirectional or receive-only signal interconnect channel (lane) is shown. This implementation is particularly useful for High Bandwidth Memory 3 (HBM3) semiconductor 3D IC packages. The interconnect signal channel has a near-end (NE) bump (a connection such as a solder pin) and a far-end (FE) bump. Pads at the NE and FE have capacitance (schematically represented by capacitors labeled C-pad). In the FE, which in this example is in the dynamic random access memory (DRAM) portion of the 3D IC, a physical layer (Phy) transmit buffer receives an input (DQ[n]), which is received by an NE (pseudo) differential receive buffer (Diff Rx buffer), which compares the received signal with a threshold voltage (VREF). The output of the NE differential receive buffer is provided as a data input to an I / O sensor, which also receives a clock (clk). In bidirectional channels, the main chip (MC) physical layer (Phy) transmitter also includes a transmit buffer (Tx buffer). The degradation of the transmit signal transition slope (slope-in ​​to slope-out) is shown, which determines the margin. The receive buffer can alternatively be implemented as a CMOS receiver (or another type of receive buffer), in which case there is no need to receive or perform a comparison with the threshold voltage (VREF). This also applies to the other differential receive buffers disclosed below.

[0125] Referring to FIG. 11 , a schematic circuit diagram of an implementation of an I / O sensor according to the present disclosure for monitoring degradation of a transmit-only signal interconnect channel (lane) is shown, which is also particularly suitable for HBM3 3D IC packages. Features common to those of FIG. 10 are not described again for the sake of brevity. Two signal interconnect channels are shown, each with a respective I / O sensor to which the output of the channel's respective NE differential receiver buffer is provided as a data input. In this mode of operation, there is no reference signal, such as a clock signal, that can be used as a comparison for measuring setup or hold times. Therefore, the output of the other channel's NE differential receiver buffer is provided as a clock input to the respective I / O sensor. This means that each I / O sensor measures the setup or hold time between signals from adjacent pins or lanes. In other words, each pin is used as a reference signal for the adjacent pin.

[0126] For example, the reference for the receiver output (Rx[0]) of the first lane is a delayed version of the receiver output (Rx[1]) of the second lane. The delay is given by ΔT. In this case, the data signal of the I / O sensor of the first lane is Rx[0] and the clock signal is Rx[1]+ΔT. The setup time is measured by the I / O sensor as the time difference (Δ) between Rx[1]+ΔT and Rx[0]. Degradation of one of the signals (Rx[0] or Rx[1]) causes a change in the setup time detected by the sensor. It is therefore sensitive to changes in transmit buffer strength and changes in NE bump resistance. ΔT is set to maintain at least one of the following conditions, taking into account the total skew from Rx[0] to Rx[1]: int_Delay ) ≦ Setup_time[0] ≦ IO sensor maximum setup window, and I / O sensor specific delay ≦ Setup_time[1] ≦ I / O sensor maximum setup window.

[0127] Referring to Figure 12, waveform timing for three scenarios for monitoring the degradation of a transmit-only signal interconnect channel is shown. In each case, ΔT is 1.5 × IO_Sensor int_Delay The initial timing relationship is set as follows: The initial timing relationship is determined by receiver random variations and data alignment (D[0] to D[1]). Timing scenarios are used to determine ΔT for proper operation under timing skew from the first lane to the second lane. In the first scenario (a), the timing of the first lane is the same as the timing of the second lane (i.e., Rx[0] = Rx[1]), in the second scenario (b), the timing of the first lane is ahead of the second lane (e.g., Rx[0] - Rx[1] ≥ -20 ps), and in the third scenario (c), the timing of the first lane is behind the second lane (i.e., Rx[0] - Rx[1] ≤ 20 ps).

[0128] Referring to FIG. 13, a schematic circuit diagram of an implementation of an I / O sensor according to the present disclosure for monitoring degradation of differential interconnect receive channels (lanes) is shown, which is also particularly suitable for HBM3 3D IC packages. Features common to those of FIGS. 10 and 11 are not described again for brevity. In the case of transmit-only lanes, since there is no reference signal such as a clock, two single-ended signals Rx_c and Rx_t are used as references to each other after being delayed by ΔT (as in the transmit-only case). The first single-ended signal Rx_c is generated by comparing the signal received from one side of the differential channel with a threshold voltage (VREF), and the second single-ended signal Rx_t is generated by comparing the signal received from the other side of the differential channel with a threshold voltage (VREF). Degradation of one of the signals is detected by the I / O sensor (assuming that degradation does not occur simultaneously for both signals). This can be used for continuous measurement of clock or strobe symmetry (Rx_c-rise to Rx_t-rise).

[0129] Referring to FIG. 14, a schematic circuit diagram of an implementation of an I / O sensor according to the present disclosure for monitoring degradation of a differential interconnect transmit channel (lane) is shown, which is also particularly suitable for an HBM3 3D IC package. It shows a transmit strobe using a differential transmit buffer that receives a data input (D_in) and provides differential transmit outputs (cn, cp). The differential transmit outputs are each provided to respective (pseudo) differential receive buffers (which, as mentioned above, can be implemented using alternative types of receive buffers) that provide data outputs (Rx_c, Rx_t), respectively. The drawing also shows how a single I / O sensor and a multiplexed arrangement of the Rx_c and Rx_t signals can be used in place of two I / O sensors. This can be used to monitor degradation of a differential interconnect receive channel instead of the arrangement of FIG. 13, or to monitor degradation of multiple transmit-only signal interconnect channels (lanes) instead of the arrangement shown in FIG. 11.

[0130] Returning to the generalized meaning above, an I / O block for a semiconductor IC may be considered (which may be combined with any other aspect disclosed herein). The I / O block includes a receive buffer configured to receive a voltage signal from an interconnect portion of the semiconductor IC and provide a receive buffer output, and an I / O sensor disclosed herein. The receive buffer output (which may indicate a logic level) may be provided as a data signal input to a delay circuit of the I / O sensor. The receive buffer may be a differential (or pseudo-differential) receive buffer and may be further configured to compare the received voltage signal with a voltage threshold input and provide a receive buffer output based on the comparison.

[0131] The I / O sensor is beneficially further configured to receive a clock signal input (which may be used in a variety of ways, as described elsewhere herein). In some embodiments, a clock signal related to the received voltage signal may be provided as the clock signal input. This may be used to measure and / or monitor bidirectional or receive-only pins or lanes.

[0132] In some implementations, the (differential) receive buffer is a first (differential) receive buffer configured to receive a first voltage signal from a first interconnect portion of the semiconductor IC and provide a first receive buffer output. The I / O block may then further include a second (differential) receive buffer configured to receive a second voltage signal from a second interconnect portion of the semiconductor IC, optionally compare the received second voltage signal with a voltage threshold input, and, if appropriate, provide a second receive buffer output based on the comparison. In this case, the second receive buffer output, to which a (fixed or adjustable) delay has been applied, may be provided as a clock signal input. This may be used for measuring and / or monitoring transmit-only pins or lanes or differential pins or lanes. For example, the first and second interconnect portions of the semiconductor IC may form a differential channel (although in other embodiments, they may simply be physically and / or logically adjacent).

[0133] In a particular embodiment, the I / O sensor is a first I / O sensor and the clock signal input is a first clock signal input. The I / O block may then further include a second I / O sensor as disclosed herein, and the second receive buffer output is provided as a data signal input to a delay circuit. The second I / O sensor may then be further configured to receive a second clock signal input. The first receive buffer output, with a (fixed or adjustable) delay applied, may then be provided as the second clock signal input.

[0134] In other embodiments, a single I / O sensor may be used to measure the margin. The I / O block may then further comprise a multiplexing arrangement configured to selectively apply (a) the first receive buffer output as the data signal input to the I / O sensor and the second receive buffer output with an applied delay as the clock signal input to the I / O sensor, or (b) the second receive buffer output as the data signal input to the I / O sensor and the first receive buffer output with an applied delay as the clock signal input to the I / O sensor.

[0135] Optionally, the mechanism for holding the output of the fifth state element (FF5) indicating the sensor fail indication signal (ptrn_io_sensor_fail) can be masked. This option can be used to avoid locking the sensor fail indication signal in situations where the data and / or clock are not stable (the unstable time interval can be defined by the protocol). This can be done by adding a control signal to enable sampling by the fifth state element (FF5), for example, by controlling the reset or data input of the fifth state element (FF5).

[0136] In a general sense according to the fifth aspect, there is provided herein an I / O sensor or inter-die connectivity monitoring system that is physically present (embedded) in one IC of a multi-IC module, or multiple such sensors / systems may be physically present in multiple ICs of a multi-IC module, one per IC, or multiple per IC. Such a sensor / system may be useful for any interconnect portion of any IC in the multi-IC module.

[0137] The techniques described herein may be extended to monitoring chip-to-chip (C2C) connectivity and / or degradation. The I / O sensors for C2C monitoring may be based on or may use the I / O sensors for D2D monitoring described herein. Thus, not only is the above description useful for understanding the I / O sensors for C2C monitoring described below, but features of implementations of the I / O sensors for D2D monitoring may also be applied to the I / O sensors for C2C monitoring as well.

[0138] Referring to FIG. 15, a schematic circuit diagram of a C2C interconnect is shown, illustrating I / O sensors for monitoring degradation. The C2C interconnect is between two chips, namely, chip 1 and chip 2. Each chip has a respective transmit signal (DQin) that is provided to a respective transmit (Tx) buffer. The output of the Tx buffer is coupled to a transmit connection pad having a characteristic capacitance represented by a capacitor (C pad). Each chip also receives a respective signal from the other chip at a receive connection pad, which also has a characteristic capacitance represented by a capacitor (C pad). The capacitance (C pad) can be higher than in the case of a D2D interconnect. Each receive connection pad is coupled to a respective receiver (Rx) buffer, which compares the received signal with a reference voltage (VREF) and provides a respective output (DQout). The interconnection between each transmitting and receiving connection pad comprises a solder bump on the transmitting connection pad having a specific resistance (shown as a resistor in the diagram and known as the far-end resistance), a channel, and a solder bump on the receiving connection pad having a specific resistance (shown as a resistor in the diagram and known as the near-end resistance).

[0139] The interconnect is monitored using an agent in each Rx buffer, referred to herein as, for example, a Slew-Rate Tile Connectivity Agent (SRTCA) (in other contexts, when the agent is intended to measure signal slew rate, it may simply be referred to as an "agent" or "circuit"). Each SRTCA receives the signal provided to the Rx buffer along with two reference levels. One of the reference levels is advantageously the reference voltage (VREF) used by the Rx buffer, although this is not required.

[0140] Referring to FIG. 16A, a first block diagram of an I / O sensor for C2C interconnect degradation monitoring is shown, showing the inputs and outputs. The SRTCA receives as inputs a signal input (DQin)—note that this is not the same as DQin shown in FIG. 15 but rather a received version of the DQin signal (after that signal has traversed the channel), a low reference voltage level (VREFL), and a high reference voltage level (VREFH). Typically, VREFL is less than VREFH. The SRTCA provides an output (out) and also receives a control signal. The SRTCA measures the duration between when the signal input is VREFL and when the signal input is VREFH (note that either event can occur first). The slew rate is calculated as measured duration / (VREFH-VREFL) [ps / V].

[0141] Referring to Figure 16B, a second block diagram of an I / O sensor for C2C interconnect degradation monitoring based on a generalized delay time measurement sensor is shown. Specifically, the generalized delay time measurement sensor is advantageously the UTCA I / O sensor described above, particularly with reference to Figure 3. The UTCA sensor has two key inputs: a data signal input (din) and a clock input (clkin), typically from the pin or lane being measured. Essentially, the UTCA output indicates a measurement of the timing interval between the edge of the signal at the UTCA clock input (clkin) and the signal at the data signal input (din).

[0142] An SRTCA can be formed from a UTCA by adding the additional circuitry shown. Specifically, a first receive (Rx) comparator circuit configured to generate a signal based on a comparison of a receive signal input (DQin) with a first given level, in this case a low reference level (VREFL), and a second receive (Rx) comparator circuit configured to generate a signal based on a comparison of the receive signal input (DQin) with a second given level, in this case a high reference level (VREFH). The output of the first Rx comparator circuit is provided as a data signal input for the UTCA, and the output of the second Rx comparator circuit is provided as a clock input for the UTCA. Advantageously, each Rx comparator circuit is configured to generate a signal having an edge when the receive signal input is at the respective given reference level. The output of the UTCA can be understood with reference to FIGS. 4 and 5, as detailed above. Further details of the operation of the SRTCA are provided below. Note that in this configuration, the SRTCA operates on a different clock than the rest of the IC, so additional synchronization can be used.

[0143] Referring to FIG. 17, a simplified schematic diagram of a C2C chip interconnect based on FIG. 15 is shown, illustrating slew rate measurement. For brevity, features also shown in FIG. 15 will not be described again. An example of a binary signal received at the Rx buffer is also shown. This example is for illustrative purposes, and the signal shape may not be typical. As is typical for binary signals, the signal includes rising and falling edges. The duration between these edges reaching multiple reference levels can indicate characteristics of the interconnect. For example, the duration between an edge reaching a first level and an edge reaching a second level can indicate the slew rate. In particular, measuring the duration of an edge at a low reference level (VREFL) and an edge at a high reference level (VREFH) has been found to provide useful information about the interconnect. For example, the slew rate can be proportional to the performance of the interconnect lane. Timing and / or slew rate information can be useful even when the interconnect has high capacitance, resulting in the binary signal containing significant channel coding, allowing communication with a sufficiently low error rate.

[0144] FIG. 18 shows an exemplary eye diagram of a received signal, illustrating I / O sensor measurements. In this example, it can be seen that the duration between a rising edge at the low reference level (VREFL) and a rising edge at the high reference level (VREFH) is 30 ps. For completeness, an additional reference level, the mid reference level (VREFM), is also shown. The I / O sensor may also measure the duration between a rising edge at the low reference level (VREFL) and a rising edge at the mid reference level (VREFM) and / or the duration between a rising edge at the mid reference level (VREFM) and a rising edge at the high reference level (VREFH). These one or more additional durations may be useful for further characterizing the slope shape of the rising edge. The characteristics of the falling edge may be assumed to be the same as those of the rising edge (although this is not necessarily the case), and / or the I / O sensor may be configured to measure one or more durations for the falling edge in some embodiments.

[0145] Thus, I / O sensors are advantageously located on the receiver side of both dies to measure timing (especially lane slew rate) with fine resolution. The I / O sensors may be particularly effective during lane training phases at predefined data rates (faster data rates being preferred). Thus, the I / O sensors may provide one or more of the following: improved visibility for accurate characterization; channel characterization at a system level; values ​​in production, field, and / or mission modes; outlier detection based on hard limits set during new product introduction; outlier detection based on learning models trained on a data analytics platform; lane repair enablement (if relevant); degradation information; time-to-failure (TTF) prediction; and alerts at one or more predefined thresholds. Such advantages are similar to those discussed above, and other advantages as described therein may also apply.

[0146] According to a sixth aspect (which may be combined with any other aspect disclosed herein), generally, there can be considered an input / output (I / O) sensor for a multi-IC module, the I / O sensor comprising: a signal input (DQin) configured to receive a data signal from an interconnect portion of an IC of the multi-IC module; and a duration measurement circuit configured to measure a duration between a first time when the data signal is at a first voltage level (e.g., VREFL) and a second time when the data signal is at a second voltage level (e.g., VREFM or VREFH) different from the first level.

[0147] The I / O sensor may form part of an input / output (I / O) block for the multi-IC module, the I / O block further comprising a receive buffer configured to receive a voltage signal from an interconnection portion of an IC of the multi-IC module and provide a receive buffer output. The receive buffer output may be provided as a signal input to the I / O sensor. In an embodiment, the receive buffer is further configured to receive a reference level input, the reference level input being the first level or the second level. The I / O block is typically located on an IC of the multi-IC module and may be configured to interface with an external processor to store the measured duration. An input / output (I / O) monitoring system comprising multiple I / O blocks according to any of the above may also be considered. Advantageously, the multiple I / O blocks are controlled by a common I / O controller.

[0148] An integrated circuit (IC) that is part of a multi-IC module may also be contemplated, particularly comprising an I / O block or an I / O monitoring system as described herein. A multi-IC module may also be provided that includes a first IC (chip) as described herein, a second IC (chip) as described herein, and an interconnection between the first IC and the second IC, the interconnection comprising one or more lanes, each of the one or more lanes providing an interconnection between a transmit buffer of one of the first IC and the second IC and a receive buffer of the other of the first IC and the second IC.

[0149] Further optional and / or beneficial features of I / O sensors according to this embodiment will now be described in general terms.

[0150] The duration measurement circuit may include a first (Rx) comparator circuit configured to generate a first timing signal having an edge (e.g., a rising edge) when the received data signal is at a first given level, e.g., the first level; a second comparator circuit configured to generate a second timing signal having an edge (e.g., a rising edge) when the received data signal is at a second given level, e.g., the second level; and a timing measurement circuit configured to receive the first timing signal and the second timing signal and measure the time between the (rising) edge of the first timing signal and the (rising) edge of the second timing signal.

[0151] The timing measurement circuit may include a delay circuit configured to receive a first timing signal and generate a delayed data signal, the delay circuit including an adjustable delay line configured to delay the input signal by a set time span, a comparison circuit configured to generate a comparison signal by comparing a second timing signal with the delayed data signal, and timing measurement processing logic configured to set the time span of the adjustable delay line and identify a duration based on the comparison signal. The timing measurement processing logic may be configured to, for each of a plurality of time spans, set the adjustable delay line to the respective time span, determine whether the comparison signal for each time span indicates a pass state or a fail state, and identify a minimum time span from the plurality of time spans for which the comparison signal indicates a fail state.

[0152] In some embodiments, the duration measurement circuit may be further configured to measure the duration between a second time when the data signal is at a second level (e.g., VREFM) and a third time when the data signal is at a third level (e.g., VREFH).

[0153] The I / O sensor may further comprise sensor processing logic (“controller”) configured to determine the slew rate of the data signal from the duration measured by the duration measurement circuitry, or this may be part of the I / O monitoring system.

[0154] Further specific details are provided below, and then additional references to the general meaning according to this sixth aspect are discussed.

[0155] An offset relative to the reference levels in the Rx comparator circuit can cause inaccurate measurement of duration. In particular, the low reference level (VREFL) can be higher than expected, and the high reference level (VREFH) can be lower than expected. Assuming that the characteristics of the falling edge are the same as those of the rising edge, this can be used to correct (or cancel) the offset.

[0156] Referring to FIG. 19, a first variation of the I / O sensor structure incorporating offset cancellation is shown. Like the design of FIG. 16B, this uses a UTCA I / O sensor, but incorporates additional offset cancellation circuitry to enable measurement of both rising and falling edges. The operation of this circuit is described in detail below, while the structure of the circuit is described below. The offset cancellation circuit comprises a first selector or multiplexer set controlled by a first signal (S[0]), a first receive (Rx) comparator circuit, a second receive (Rx) comparator circuit (shown below the first Rx comparator circuit), and a second selector or multiplexer set controlled by a second signal (S[1]). Both the first Rx comparator circuit and the second Rx comparator circuit are fed with the receive signal input (DQin) at one of their inputs.

[0157] The first selector set or multiplexer set can operate in one of two modes: in the first mode (S[0]=[0]), a high reference level (VREFH) is provided as the other input to the first receive (Rx) comparator circuit and a low reference level (VREFL) is provided as the other input to the second receive (Rx) comparator circuit; and in the second mode (S[0]=[1]), a low reference level (VREFL) is provided as the other input to the first receive (Rx) comparator circuit and a high reference level (VREFH) is provided as the other input to the second receive (Rx) comparator circuit. The second selector set or multiplexer set can operate in one of two modes: in a first mode (S[1]=[0]), the output of the second receive (Rx) comparator circuit is provided as a data signal input of the UTCA and the output of the first receive (Rx) comparator circuit is provided as a clock input of the UTCA; and in a second mode (S[1]=[1]), the output of the first receive (Rx) comparator circuit is provided as a data signal input of the UTCA and the output of the second receive (Rx) comparator circuit is provided as a clock input of the UTCA.

[0158] The following table provides an overview of the modes:

[0159] [Table 4]

[0160] The first receive (Rx) comparator circuit and the second receive (Rx) comparator circuit are controlled by a third control signal (S[2]) that controls the polarity of the comparator output signal to enable measurement of rising or falling edges (as indicated by the table above). Each of these circuits operates in one of two modes: in the first mode (S[2]=[0]), the Rx comparator circuits generate a signal having an edge (specifically, an edge transitioning from low level [0] to high level [1]) when the rising edge of the receive signal input (DQin) is at the level provided to the respective Rx comparator circuit (in other words, the output signal is positive [1] when DQin is greater than the reference level and negative [0] when DQin is less than the reference level); and in the second mode (S[2]=[1]), the Rx comparator circuits generate a signal having an edge (specifically, an edge transitioning from low level [0] to high level [1]) when the falling edge of the receive signal input (DQin) is at the level provided to the respective Rx comparator circuit (in other words, the output signal is negative [0] when DQin is greater than the reference level and positive [1] when DQin is less than the reference level).

[0161] Thus, the first control signal (S[0]), the second control signal (S[1]), and the third control signal (S[2]) are used to configure the SRTCA. During operation, two options are possible. In the first option, the first control signal (S[0]) and the second control signal (S[1]) are the same (S[0]=S[1]), in which case the first (upper) receive (Rx) comparator circuit slices the DQin signal with VREFL, and the second (lower) receive (Rx) comparator circuit slices the DQin signal with VREFH. When (S[0]=S[1]=[1]), the output of the first (upper) receive (Rx) comparator circuit is provided as the din input to the timing measurement circuit (UTCA) or adjustable delay line, but when (S[0]=S[1]=[0]), the output of the second (lower) receive (Rx) comparator circuit is provided as the din input to the timing measurement circuit (UTCA) or adjustable delay line.

[0162] In a second option, the first control signal (S[0]) and the second control signal (S[1]) are reversed (S[0]=S[1]!), in which case the first (upper) receive (Rx) comparator circuit slices the DQin signal with VREFH and the second (lower) receive (Rx) comparator circuit slices the DQin signal with VREFL. When (S[1]=[1]), the output of the first (upper) receive (Rx) comparator circuit is provided as the din input to the timing measurement circuit (UTCA) or adjustable delay line, but when (S[1]=[0]), the output of the second (lower) receive (Rx) comparator circuit is provided as the din input to the timing measurement circuit (UTCA) or adjustable delay line.

[0163] This second option can be used to measure the timing of a falling edge signal. As the signal falls and crosses VREFH, the first (upper) receive (Rx) comparator circuit output changes from high to low. As the signal continues to fall and crosses VREFL, the second (lower) receive (Rx) comparator circuit output changes from high to low. In other words, in this case, a negative pulse is generated (as opposed to the positive pulse generated for a rising edge measurement). By setting (S[2]=[1]), the comparator polarity is adjusted as described above so that a positive pulse is generated.

[0164] To cancel offset in rising edge measurement mode, two measurements are taken on the rising edge (S[2]=[0]), both when the first control signal (S[0]) and the second control signal (S[1]) are the same (S[0]=S[1]), with the first measurement taken when (S[0]=S[1]=[0]) and the second measurement taken when (S[0]=S[1]=[1]), so that each comparator is used once per measurement. By averaging the data from the two measurements, the comparator offset is canceled, as described below with reference to FIG. 21. For offset cancellation in the falling edge measurement mode, two measurements are taken on the falling edge (S[2]=[1]), both taken when the first control signal (S[0]) and the second control signal (S[1]) are opposite (S[0]=S[1]!), with the first measurement taken when (S[1]=[1]) and the second measurement taken when (S[1]=[0]), again with each comparator used once per measurement. Again, the two measurements can be averaged to cancel the offset. It may also be possible to perform offset cancellation using the first measurement taken in the rising edge measurement mode and the second measurement taken in the falling edge measurement mode.

[0165] Referring to Figure 20, a second variation of the I / O sensor structure incorporating offset cancellation is shown. This does not implement the UTCA shown with reference to Figure 3, for example, but rather a simplified custom time measurement circuit. The offset cancellation circuit shown is the same as the circuit shown in Figure 19. For brevity, the details of the offset cancellation circuit will not be repeated. The offset cancellation circuit effectively provides two outputs, which are then received as inputs to the rest of the I / O sensor circuit: a data signal (din) and a clock input (clkin).

[0166] The I / O sensor circuit includes a controlled adjustable delay line, a first flip-flop (FF1), a logic arrangement including a NOT gate and a NOR gate, and a second flip-flop (FF4). The adjustable delay line receives a data signal (din) and provides a delayed data signal (DQin_d) as a data input to the first flip-flop (FF1). Both the first flip-flop (FF1) and the second flip-flop (FF4) receive delayed versions of a clock input (clkin) as clock inputs. The delay buffer (Dx) can be used to slightly delay the clock signal (clkin) to compensate for the inherent delay of the delay line; even when the delay line is in an initial (reset) state where no delay is applied, its very presence slightly delays any signal traversing it, typically by 3 to 12 picoseconds (or more in some implementations).

[0167] The output of the first flip-flop (FF1) is fed to a logic arrangement, the output of which is provided as a data input to a second flip-flop (FF4). A NOT gate in the logic arrangement receives the output of the first flip-flop (FF1), the output of which is provided as a first input to a NOR gate. The output of the second flip-flop (FF4) is provided as a second input to the NOR gate. The output of the NOR gate is the output of the logic arrangement, which is provided as a data input to the second flip-flop (FF4). Thus, if the delay applied by the adjustable delay line is the same as the duration between an edge of the data signal (din) and an edge of the clock input (clkin), this will be determined by the output of the second flip-flop (FF4). The delay line delays its input signal until it reaches a "fail" state, i.e., the output of the first flip-flop (FF1) is at a low logic level ([0]), and then the second flip-flop (FF4) captures a high logic level ([1]) until it is reset. By controlling the delay of the adjustable delay line, the duration between an edge of the data signal (din) and an edge of the clock input (clkin) is determined. The delay line position corresponding to fail represents the time interval between the time the DQin signal crosses VREFL and the time the DQin signal crosses VREFH.

[0168] The I / O sensor circuit also includes a reset circuit including a third flip-flop (FF2) and a fourth flip-flop (FF3). Both the third flip-flop (FF2) and the fourth flip-flop (FF3) receive a delayed version of the clock input (clkin) as their clock input. The data input to the third flip-flop (FF2) is a binary logic low level (1'b0). The data input to the fourth flip-flop (FF3) is the output of the third flip-flop (FF2) after passing through a buffer. A reset signal (rst_n) is received at the I / O sensor, and a buffered version (rst_n_buf) is applied to the third flip-flop (FF2) and the fourth flip-flop (FF3) at their inverted set inputs. The buffered version of the reset signal (rst_n_buf) is also provided to the inverted set input of the first flip-flop (FF1). The buffered output of the fourth flip-flop (FF3) is provided as the reset input of the second flip-flop (FF4). This allows for resetting of the I / O sensor, as described above with reference to FIG. 3. Specifically, the third flip-flop (FF2) and the fourth flip-flop (FF3) are used to reset the second flip-flop (FF4) and deassert the reset after two rising edges of the clock. The illustrated reset circuit is provided merely as an example, and those skilled in the art will recognize other reset circuit implementations configured to reset the second flip-flop (FF4) and deassert the reset after one or more rising edges of the clock as suitable for familiar implementations.

[0169] Referring to FIG. 21, an example eye diagram of a received signal is shown, illustrating I / O sensor measurements when offset cancellation is used. The actual duration between when the data signal is at the low reference level (VREFL) and when it is at the high reference level (VREFH) is 28 ps. However, offsets relative to the reference levels cause measurement errors. Therefore, two measurements are taken. The first measurement (M1) is taken on the rising edge; the offset causes the used low reference level (VREFL) to be higher than the actual reference level (by data_cmp_offset, 4 mV) and the used high reference level (VREFL) to be lower than the actual reference level (by clk_cmp_offset, 2 mV). Therefore, the first measurement measures 24 ps, which is shorter than the actual duration. The second measurement (M2) is taken on the falling edge; the offset causes the opposite effect to that of the rising edge; the used low reference level (VREFL) is lower than the actual reference level and the used high reference level (VREFL) is higher than the actual reference level. Therefore, the second measurement is 34 ps, which is longer than the actual duration. The arithmetic mean of the first and second measurements is then determined, resulting in an average measurement of 29 ps, which is close (within tolerance) to the actual duration (28 ps).

[0170] Referring to FIG. 22, a timing diagram for measuring rising edge timing and falling edge timing when using offset cancellation is shown. As discussed above with reference to FIG. 17, the example binary signal received at the Rx buffer shown is for illustrative purposes only, and the signal shape may not be representative. Thus, the I / O sensor measures the rising edge duration (ΔTr) and the falling edge duration (ΔTf). Also shown are the output of the first flip-flop (FF1) indicating delay match and the ptrn_io_sensor_fail signal (the output of the second flip-flop (FF4) in FIG. 20 or the fifth state element (FF5) in FIG. 3) indicating a valid measurement.

[0171] Referring again to the general meaning with reference to the sixth aspect above, further details of the I / O sensor will now be described. For example, the I / O sensor may further include an offset cancellation circuit configured to selectively apply a signal derived from the received data signal to the duration measurement circuit such that, in a first mode, a first given level (of the first comparator circuit) is the first level and a second given level (of the second comparator circuit) is the second level, and in a second mode, the first given level (of the first comparator circuit) is the second level and the second given level (of the second comparator circuit) is the first level. In this manner, the first level and the second level can be switched between the comparator circuits. Optionally, the I / O sensor may further include sensor processing logic configured to control the offset cancellation circuit and the duration measurement circuit to measure a first duration in the first mode of the offset cancellation circuit and to measure a second duration in the second mode of the offset cancellation circuit. This two-measurement approach can be applied when both measurements are rising edge measurements, when both measurements are falling edge measurements, or when one measurement is a rising edge measurement and the other is a falling edge measurement.

[0172] In some embodiments, the offset cancellation circuit comprises a first multiplexing arrangement configured to operate in a first mode (S[0]=[0]) where a first level is provided to the first comparator circuit (as a first given level) and a second level is provided to the second comparator circuit (as a second given level), or in a second mode (S[0]=[1]) where the first level is provided to the second comparator circuit (as a second given level) and a second level is provided to the first comparator circuit (as the first given level); and a second multiplexing arrangement configured to operate in a first mode (S[1]=[0]) in which the output of the first comparator circuit is provided to the timing measurement circuit as a first timing signal and the output of the second comparator circuit is provided to the timing measurement circuit as a second timing signal, or in a second mode (S[1]=[1]) in which the output of the second comparator circuit is provided to the timing measurement circuit as the first timing signal and the output of the first comparator circuit is provided to the timing measurement circuit as the second timing signal. The timing measurement circuit can then be configured to measure the time between an edge of the first timing signal and an edge of the second timing signal.

[0173] Optionally, each of the first comparator circuit and the second comparator circuit is configured to operate in a first mode (S[2]=[0]) in which the respective comparator circuit generates a respective timing signal having an edge when the rising edge of the received data signal is at a respective given level, or in a second mode (S[2]=[1]) in which the respective comparator circuit generates a respective timing signal having an edge when the falling edge of the received data signal is at a respective given level.

[0174] In some embodiments, the timing measurement circuit comprises: a delay circuit configured to receive a first timing signal and generate a delayed data signal, the delay circuit comprising an adjustable delay line configured to delay the input signal by a set time span; a comparison circuit configured to generate a comparison signal by comparing a second timing signal with the delayed data signal; and timing measurement processing logic configured to set the time span of the adjustable delay line and to determine the duration based on the comparison signal.

[0175] In such an embodiment, the comparison circuit may include a first state element (e.g., a flip-flop) configured to receive the delayed data signal and provide a first state element output based on the delayed data signal and a clock input; a logic arrangement including a NOT gate and a NOR gate or an OR gate and configured to provide a logic arrangement output based on the first state element output; and a second state element (e.g., a flip-flop) configured to receive the logic arrangement output and provide a second state element output based on the logic arrangement output and the clock input. The clock input is based on the second timing signal, and the local arrangement is configured to receive the first state element output at the NOT gate, provide the output of the NOT gate as a first input to the NOR gate or the OR gate, and provide the second state element output at a second input to the NOR gate or the OR gate, and the logic arrangement output is the output of the NOR gate or the OR gate. The clock input may be the second timing signal or a delayed version of the second timing signal. The delayed version may be configured to compensate for inherent delays in the delay circuit.

[0176] The comparison circuit advantageously further comprises a third state element (e.g., a flip-flop) configured to receive a low logic level at a third state element data input and to provide a third state element output based on the received low logic level and the clock input, and further configured to receive a reset signal at a third state element state set input, and a fourth state element (e.g., a flip-flop) configured to receive a signal based on the third state element output at a fourth state element data input and to provide a fourth state element output based on the signal received at the fourth state element data input and the clock input, and further configured to receive a reset signal at a fourth state element state set input. The first state element may then be further configured to receive the reset signal at the first state element state set input, and the second state element further configured to receive a signal based on the fourth state element output at a second state element state reset input.

[0177] Referring to FIG. 23, a schematic circuit diagram of a further embodiment of an I / O sensor for measuring multi-phase clocks is shown. Most of this I / O sensor is similar to the I / O sensor shown in FIG. 20, and therefore, to avoid redundancy, the same parts will not be described again below. The main difference resides in the upper left corner of the drawing. Instead of the multiplexing arrangement of FIG. 20, which provides two signals to be compared (d_in and clk_in), a selection or multiplexing arrangement is provided for measuring multi-phase clock signals. In this example, four clock phases (Clk_φ1, Clk_φ2, Clk_φ3, Clk_φ4) are used. Each of these signals is provided at the respective inputs of a first (upper) selector or multiplexer controlled by a first control signal (S[0]) and a second (lower) selector or multiplexer controlled by a second control signal (S[1]). The rest of the circuitry can then be used to measure the time difference between the (rising and / or falling) edges of every two adjacent phases of the multi-phase clock to check whether the phases are properly "aligned" with each other.

[0178] An optimal multiphase clock is expected to have "aligned" phases with equal duty cycles. The circuit of Figure 23 makes it possible to check whether there is indeed an equal time difference between the rising edges of all clock phase signals (four signals in this example). A faulty clock may exhibit what is often called "duty cycle distortion", where the duty cycles of the phases are different and not "aligned".

[0179] 23 can be used to test multi-phase clocks and detect (and quantify) any duty cycle distortion of the phases. Delay lines can be made with specific delay options ("steps") that span the expected time difference between every two adjacent clock phase signals in the absence of distortion (based on knowledge of the particular clock under test).

[0180] Two control signals S[0] and S[1] allow the selection of one phase signal (the phase signal selected by the first selector) to be delayed, while adjacent phase signals are allowed to continue without delay (except for a compensating delay of Dx). A controller (not shown) then compares the output of the second flip-flop (FF4) (which may, for example, indicate a particular time difference between two adjacent phase signals) with what is known to be the correct time difference when the phase signals are properly aligned, and infers whether they are indeed aligned (as well as indicating the amount of distortion in time units).

[0181] The primary use of this circuit is to test the clocking (indicating interconnect quality) of a receiver on one IC of a multi-IC module, however, the circuit can be used in any situation where a multi-phase clock is to be tested.

[0182] Referring to Figure 24, there is shown a schematic circuit diagram of a further embodiment of an I / O sensor or agent that allows for multi-phase clock measurement and measurement of adjustable delays. Some parts of the circuit diagram in Figure 24 are essentially the same as the I / O sensor for multi-phase clock measurement in Figure 23. These parts will not be described again here.

[0183] The implementation of FIG. 24 is particularly applicable to multiphase clock measurements, for example, in systems operating using Quadrature Data Rate (QDR) with respect to the sampling clock. For example, a 32 GT / s data transfer can be sampled with four to eight GHT clock phases, spaced 90 degrees apart. Compared to Dual Data Rate (DDR), which uses two clock phases at half frequency, spaced 180 degrees apart, to sample at twice the data rate with respect to the clock, the smaller phase difference between clocks in a QDR system makes performance significantly more dependent on timing issues. Any deviation from 90 degrees between clock phases will affect link performance, and the complexity of phase generation increases with the number of phases due to systematic and random effects. For this reason, the I / O sensor of FIG. 24 is referred to as a Quadrature Duty Cycle Agent (QDCA). Nevertheless, it will be understood that the additional portions of FIG. 24 may be implemented in conjunction with any other I / O sensor disclosed herein, for example, as shown in FIG.

[0184] A ring oscillator (ROSC) circuit is used to measure the delay. Operating the circuit of FIG. 24 in this manner may be referred to as QDCA oscillator mode. The ROSC circuit comprises an Extended Delay Line (EDL) and a ROSC inverter. The ROSC circuit is controlled by a ROSC pass gate and a ROSC selector, both of which are enabled by a ROSC enable signal, osc_en. When osc_en=[1], the ROSC pass gate and the ROSC selector are enabled, and when osc_en=[0], the ROSC pass gate and the ROSC selector are disabled.

[0185] The output of the ROSC selector is controlled by a mode signal osc_mode. The ROSC circuit can operate in two modes. In the first mode (osc_mode=[1]), the ROSC circuit includes only the extended delay line and the ROSC inverter. In the second mode (osc_mode=[0]), the ROSC circuit includes the I / O sensor adjustable delay line, the extended delay line, and the ROSC inverter. The output of the ROSC selector is provided to a frequency divider that includes a ROSC flip-flop (FF5) and an inverter. The output of the ROSC selector is provided as the clock input to the ROSC flip-flop (FF5), and the inverter is coupled between the ROSC flip-flop (FF5) data output and the ROSC flip-flop (FF5) data input. As a result, the signal at the ROSC flip-flop (FF5) data output is at half the frequency of the output of the ROSC selector.

[0186] The output of the divider is provided to a buffer that provides the oscillator output signal osc_out. The output of a second flip-flop (FF4) provides the quality output qout. The quality output qout is related to the main QDCA measurement, which indicates duty cycle distortion. The oscillator output signal osc_out and the quality output qout are provided as respective inputs to an output selector. The output selector is controlled by a ROSC enable signal osc_en such that when osc_en=[0], the output of the output selector is the quality output qout, and when osc_en=[1], the output of the output selector is the oscillator output signal osc_out. Thus, the output of the output selector provides the agent output ptrn_qdca_out. The ROSC enable signal osc_en is also provided to the inverting control input (labeled Input_phase_dis) of the first (upper) selector or multiplexer in the selection or multiplexing arrangement, which provides for the measurement of the multiphase clock signals. The inverting control input thereby disables the first (upper) selector or multiplexer when osc_en=[1]. In this way, the adjustable delay line can be used either for duty cycle distortion measurement or for delay line measurement. In the latter case, the duty cycle measurement mode is disabled.

[0187] The I / O sensors or agents are therefore controllable by a 14-bit configuration signal ptrn_qdca_cfg (in this exemplary embodiment), where the first 9 bits [8:0] control the adjustable delay line, the next 2 bits [10:9] provide the S[1] signal, the next 2 bits [12:11] provide the S[0] signal, the next bit

[13] provides the mode signal osc_mode, and the last bit

[14] provides the ROSC enable signal osc_en.

[0188] As previously mentioned, the adjustable delay line circuit generates a linear delay in fine steps. The delay provided by the adjustable delay line (D) can be expressed by the following equation:

[0189]

number

[0190] The QDCA oscillator mode allows for the measurement of fine delay line steps in picoseconds. As mentioned above, the QDCA oscillator mode can operate in two configuration modes. The first mode (osc_mode=prtn_qdca_cfg

[13] =[1]), also called fine delay line bypass mode, includes an EDL and a ROSC inverter. The oscillation frequency of the ROSC is then based on the EDL delay. The oscillation period Tosc is twice the delay of the EDL. The second mode (osc_mode=prtn_qdca_cfg

[13] =[0]), also called fine delay line non-bypass mode, includes an EDL and an adjustable delay line. The oscillation frequency of the ROSC in this mode corresponds to the delay of the EDL and the delay of the adjustable fine delay line. In this case, the oscillation period Tosc is twice the sum of the EDL delay and the adjustable delay line delay.

[0191] In a specific example (for illustrative purposes only), the EDL delay may have a value of 0.5 ns, and the expected frequency of ROSC in the first mode may be approximately

[0192]

number

[0193] In operation, the first mode of the ROSC circuit is used to generate a baseline frequency (FB), which in the above illustrative example is 500 MHz. The cycle time is:

[0194]

number

[0195]

number

[0196] Finally, a second mode of the ROSC circuit is used with k set to 1 through n (n=15 in the illustrative example described herein), and F D (k) and extract the fine delay line step duration d(k) according to the following equation:

[0197]

number

[0198] Typical values ​​for d(k) can be between 1 ps and 5 ps, depending on the delay line configuration. Timing measurements determined in this manner can be used to measure clock duty cycle distortion. By accurately determining the delay applied by the adjustable delay line, a picosecond-precision measurement of the time difference between the rising edges of all clock phase signals can be determined. This allows for a quantitative measurement of duty cycle distortion. Such measurements can be useful in determining the degree of duty cycle distortion and / or in determining how to correct or mitigate the duty cycle distortion.

[0199] According to a seventh aspect (which may be combined with any other aspect disclosed herein, particularly the sixth aspect), this generally provides a duty cycle distortion measurement system for a multi-phase clock system, particularly with precision on the order of picoseconds. The duty cycle distortion measurement system may include a duration measurement circuit having an adjustable delay line. The timing measurement circuit may then be configured to measure the time delay provided by the adjustable delay line. This may enable the precision of the duty cycle distortion measurement to be defined (particularly with picosecond precision).

[0200] In this sense, or in other sense, a timing measurement circuit may be provided using a ring oscillator circuit for measuring an adjustable delay line. The ring oscillator circuit generally includes a delay line with a predetermined and / or fixed delay and a logic inverter. The ring oscillator circuit further includes a switch or selector configured to operate the ring oscillator in at least two modes. In a first mode, the frequency of the output of the ring oscillator circuit is based on the predetermined and / or fixed delay. In a second mode, the switch or selector is configured to include an adjustable delay line within the ring oscillator. Then, in the second mode, the frequency of the output of the ring oscillator circuit is based on the predetermined and / or fixed delay and the delay of the adjustable delay line.

[0201] The output of the ring oscillator circuit is optionally provided to a frequency divider, typically configured to divide the frequency by 2. The frequency divider may comprise a flip-flop having an inverter coupled between a data output of the flip-flop and a data input of the flip-flop. The output of the ring oscillator circuit is optionally provided as a clock input to the flip-flop.

[0202] The ring oscillator circuit may form part of an I / O sensor, which may also include any other features of the I / O sensor disclosed herein. An output selector may be provided that may be configured to select between a signal indicative of the adjustable delay line measurement from the ring oscillator circuit and a signal indicative of or based on the duration measurement circuit. The I / O sensor may be configured to select operation of the ring oscillator circuit (e.g., based on an enable signal), with the output of the I / O sensor indicative of the adjustable delay line measurement from the ring oscillator circuit.

[0203] A range of circuit designs and schematics are described herein. It will be understood that these circuit designs may be embodied in electronic (also called "digital") representations (also called "encodings"). The electronic representations may be stored on computer-readable media, particularly those of a non-transitory nature. Suitable electronic representations may include representations in Electronic Computer-Aided Design (ECAD) software, also known as Electronic Design Automation (EDA) software. In this case, portions of the representation may be stored across multiple electronic documents or files, possibly including one or more libraries of ECAD software that provide component details for the circuit. The ECAD representation may provide instructions suitable for manufacturing (also called "fabrication") the circuit represented in the design. In accordance with the present invention, such electronic representations may be provided. Methods of using such electronic representations of electronic circuits as part of the manufacture of the electronic circuit are further contemplated.

[0204] Throughout this disclosure, various embodiments may be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the invention. Accordingly, the description of a range should be considered to have specifically disclosed all the possible subranges as well as individual numerical values ​​within that range. For example, the description of a range such as 1 to 6 should be considered to have specifically disclosed subranges such as 1 to 3, 1 to 4, 1 to 5, 2 to 4, 2 to 6, 3 to 6, etc., as well as individual numbers within that range, e.g., 1, 2, 3, 4, 5, and 6. This is true regardless of the breadth of the range.

[0205] Whenever a range of values ​​is given herein, it is intended to include any recited value (fractional or integer) within the range given. The phrases "ranging / ranges between" a first indicated number and a second indicated number and "ranging from" a first indicated number to a second indicated number are used interchangeably herein and are intended to include the first indicated number and the second indicated number and all fractional and integer numbers therebetween.

[0206] In the description and claims of this disclosure, the words "comprise," "include," and "have," and their forms, are not necessarily limited to the members in the list with which they may be associated. Furthermore, in the event of a conflict between this application and any document incorporated by reference, it is hereby intended that the present application shall control.

[0207] For clarity of reference in this disclosure, the use of nouns as common nouns, proper nouns, named nouns, etc. is not intended to imply that embodiments of the invention are limited to a single embodiment; it should be noted that while many configurations of the disclosed components may be used to describe some embodiments of the invention, other configurations may be derived from these embodiments in different configurations.

[0208] For clarity, not all of the routine features of the implementations described herein are shown and described. Of course, it should be understood that in the development of any such actual implementation, numerous implementation-specific decisions must be made to achieve the developer's specific goals, such as adherence to application- and business-related constraints, and that these specific goals will vary from implementation to implementation and from developer to developer. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking of engineering to those of ordinary skill in the art having the benefit of this disclosure.

[0209] It is expected that, based on the teachings of the present disclosure, one skilled in the art will be able to readily practice the present invention. The description of the various embodiments provided herein is believed to provide sufficient insight and detail into the present invention to enable one skilled in the art to practice the present invention. Furthermore, it is specifically contemplated that the various features and embodiments of the present invention described above can be used alone as well as in various combinations.

[0210] Conventional and / or modern circuit design and layout tools can be used to implement the present invention. The specific embodiments described herein, particularly the various circuit arrangements, measurements, and data flows, are illustrative of example embodiments and should not be construed as limiting the present invention to such specific implementation choices. Thus, multiple examples may be provided for components described herein as a single example. Determination of margin and / or other parameters may be performed, for example, at various parts of the configuration. Other types of eye parameters besides eye width may be determined using margin measurements. Indeed, in some cases, calculation of eye parameters may not be necessary at all. Optionally, the IO sensor can be extended to simultaneously measure two sides of the data eye by implementing a second delay line in the clock signal.

[0211] While circuits and physical structures are generally envisioned, it is fully recognized that in modern semiconductor design and manufacturing, physical structures and circuits may be embodied in computer-readable descriptive forms suitable for use in subsequent design, test, or manufacturing stages, as well as in the resulting manufactured semiconductor integrated circuits. Accordingly, claims directed to conventional circuits or structures may, consistent with their specific language, read computer-readable coding (which may be referred to as a program) and its representations, whether embodied in a medium or combined with a suitable reading function, to enable the fabrication, testing, or design improvement of the corresponding circuits and / or structures. Structures and functions presented as separate components in exemplary configurations may be implemented as combined structures or components. The present invention is intended to include circuits, systems of circuits, related methods, and computer-readable (medium) encodings of such circuits, systems, and methods, all as described herein and defined in the appended claims. As used herein, computer-readable medium includes at least disks, tapes, or other non-transitory magnetic, optical, or semiconductor (e.g., flash memory cards, ROM) media.

[0212] The foregoing detailed description has described only a few of the many possible implementations of the present invention. Therefore, this detailed description is intended for purposes of illustration and not limitation. Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein without departing from the scope and spirit of the present invention. It is only the following claims, including all equivalents, that are intended to define the scope of the present invention. In particular, while the main embodiment is described in the context of a 3D IC, it is believed that the teachings of the present invention may be advantageously used in other types of semiconductor ICs that employ I / O circuitry. Moreover, the techniques described herein may also be applied to other types of circuit applications. Accordingly, other variations, modifications, additions, and improvements may fall within the scope of the present invention, as defined by the following claims.

[0213] Embodiments of the present invention may be used to manufacture, produce, and / or assemble integrated circuits and / or products based on integrated circuits.

[0214] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0215] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowcharts or block diagrams may represent a module, segment, or portion of instructions, which includes one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may be executed in the reverse order, depending on the functionality involved. It should also be noted that each block of the block diagrams and / or flowchart diagrams, and combinations of blocks in the block diagrams and / or flowchart diagrams, may be implemented by a dedicated hardware-based system that performs the specified functions or operations or executes a combination of dedicated hardware and computer instructions.

[0216] The description of various embodiments of the present invention has been presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein have been selected to best explain the principles of the embodiments, practical applications, or technical improvements over technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. An input / output (I / O) sensor for a multi-IC (integrated circuit) module, the I / O sensor comprising: a signal input configured to receive a data signal from an interconnect portion of an IC of the multi-IC module; a duration measurement circuit configured to measure a duration between a first time when the data signal is at a first level and a second time when the data signal is at a second level different from the first level.

2. The duration measurement circuit a first comparator circuit configured to generate a first timing signal having an edge when the received data signal is at a first given level; a second comparator circuit configured to generate a second timing signal having an edge when the received data signal is at a second given level; a timing measurement circuit configured to receive the first timing signal and the second timing signal and measure the time between the edge of the first timing signal and the edge of the second timing signal.

3. The timing measurement circuit a delay circuit configured to receive the first timing signal and generate a delayed data signal, the delay circuit comprising an adjustable delay line configured to delay an input signal by a set time span; a comparison circuit configured to generate a comparison signal by comparing the second timing signal with the delayed data signal; 3. The I / O sensor of claim 2, further comprising: timing measurement processing logic configured to set the time span of the adjustable delay line and to determine the duration based on the comparison signal.

4. The timing measurement processing logic includes: for each of a plurality of time spans, setting the adjustable delay line to the respective time span, and determining whether the comparison signal for the respective time span indicates a pass state or a fail state; The I / O sensor of claim 3 configured to identify a minimum time span from the plurality of time spans for which the comparison signal indicates a fail condition.

5. 5. The I / O sensor of claim 2, further comprising: an offset cancellation circuit configured to selectively apply a signal derived from the received data signal to the duration measurement circuit such that, in a first mode, the first given level is the first level and the second given level is the second level, and in a second mode, the first given level is the second level and the second given level is the first level.

6. The offset cancellation circuit a first multiplexing arrangement configured to operate in a first mode in which the first level is provided to the first comparator circuit and the second level is provided to the second comparator circuit, or in a second mode in which the first level is provided to the second comparator circuit and the second level is provided to the first comparator circuit; and a second multiplexing arrangement configured to operate in a first mode in which the output of the first comparator circuit is provided as a first timing signal to the timing measurement circuit and the output of the second comparator circuit is provided as a second timing signal to the timing measurement circuit, or in a second mode in which the output of the second comparator circuit is provided as the first timing signal to the timing measurement circuit and the output of the first comparator circuit is provided as the second timing signal to the timing measurement circuit.

7. 7. The I / O sensor of claim 6, wherein each of the first comparator circuit and the second comparator circuit is configured to operate in a first mode in which the respective comparator circuit generates a respective timing signal having a positive edge when a rising edge of the received data signal is at the respective given level, or in a second mode in which the respective comparator circuit generates a respective timing signal having a positive edge when a falling edge of the received data signal is at the respective given level.

8. The timing measurement circuit a delay circuit configured to receive the first timing signal and generate a delayed data signal, the delay circuit comprising an adjustable delay line configured to delay an input signal by a set time span; a comparison circuit configured to generate a comparison signal by comparing the second timing signal with the delayed data signal; 8. The I / O sensor of claim 6, further comprising: timing measurement processing logic configured to set the time span of the adjustable delay line and to determine the duration based on the comparison signal.

9. The comparison circuit a first state element configured to receive the delayed data signal and to provide a first state element output based on the delayed data signal and a clock input; a logic arrangement including a NOT gate and a NOR gate or an OR gate, configured to provide a logic arrangement output based on the first state element output; a second state element configured to receive the logic configuration output and to provide a second state element output based on the logic configuration output and the clock input; 9. The I / O sensor of claim 8, wherein the clock input is based on the second timing signal, the local arrangement is configured to receive the first state element output at the NOT gate, provide an output of the NOT gate as a first input to the NOR gate, and provide the second state element output at a second input to the NOR gate, and the logic arrangement output is an output of the NOR gate.

10. 10. The I / O sensor of claim 8 or claim 9, wherein the clock input is the second timing signal or a delayed version of the second timing signal.

11. The comparison circuit a third state element configured to receive a low logic level at a third state element data input and to provide a third state element output based on the received low logic level and the clock input, the third state element further configured to receive a reset signal at a third state element set state input; a fourth state element configured to receive a signal based on the third state element output at a fourth state element data input and to provide a fourth state element output based on the signal received at the fourth state element data input and the clock input, the fourth state element further configured to receive the reset signal at a fourth state element state set input; 11. The I / O sensor of claim 8, wherein the first state element is further configured to receive the reset signal at a first state element state set input, and the second state element is further configured to receive a signal based on the fourth state element output at a second state element state reset input.

12. 12. The I / O sensor of claim 5, further comprising sensor processing logic configured to control the offset cancellation circuit and the duration measurement circuit to measure a first duration in the first mode of the offset cancellation circuit, measure a second duration in the second mode of the offset cancellation circuit, and determine a signal duration based on the measured first and second durations.

13. 13. The I / O sensor of claim 1, wherein the duration measurement circuit is further configured to measure the duration between the second time the data signal is at the second level and a third time the data signal is at a third level.

14. 14. The I / O sensor of claim 1, further comprising sensor processing logic configured to determine a slew rate of the data signal from the duration measured by the duration measurement circuit.

15. 1. An input / output (I / O) block for a multi-IC (integrated circuit) module, the I / O block comprising: a receive buffer configured to receive a voltage signal from an interconnect portion of an IC of the multi-IC module and to provide a receive buffer output; An I / O sensor, a signal input configured to receive a data signal from the receive buffer output; and a duration measurement circuit configured to measure the duration between a first time that the data signal is at a first level and a second time that the data signal is at a second level different from the first level.

16. 16. The I / O block of claim 15, wherein the receive buffer is further configured to receive a reference level input, the reference level input being the first level or the second level.

17. The I / O block of any one of claims 15 to 16, wherein the I / O block is located within the IC of the multi-IC module and is configured to interface with an external processor to store the measured duration.

18. 18. An input / output (I / O) monitoring system comprising a plurality of I / O blocks, each I / O block being as defined in any one of claims 15 to 17, and the plurality of I / O blocks being controlled by a common I / O controller.

19. An integrated circuit (IC) being part of a multi-IC module and comprising an input / output (I / O) block according to any one of claims 15 to 17.

20. A multi-IC module, a first IC that is part of a multi-IC module and that comprises an I / O block according to any one of claims 15 to 17; a second IC that is part of a multi-IC module and that comprises an I / O block according to any one of claims 15 to 17; an interconnect between the first IC and the second IC, the interconnect comprising one or more lanes, each of the one or more lanes providing an interconnect between a transmit buffer of the first IC and the receive buffer of the second IC.

21. 1. An input / output (I / O) sensor for a multi-IC (integrated circuit) module, the I / O sensor comprising: two multiplexers each configured to select a different phase signal from a plurality of phase signals of a multi-phase clock; a duration measurement circuit configured to measure a time difference between an edge of a first one of the selected phase signals and an edge of a second one of the selected phase signals; and a controller configured to measure duty cycle distortion of the multi-phase clock by comparing the measured time difference with known time differences expected from an optimal multi-phase clock.

22. The duration measurement circuit comprises an adjustable delay line, and the I / O sensor comprises:

22. The I / O sensor of claim 21, further comprising a timing measurement circuit configured to measure a time delay provided by the adjustable delay line, thereby defining a precision of the duty cycle distortion measurement.

23. A non-transitory computer readable medium having stored thereon a computer readable encoding of the I / O sensor of any one of claims 1 to 14.

24. A computer readable encoding of the I / O sensor of any one of claims 1 to 14.

25. A non-transitory computer readable medium having stored thereon a computer readable encoding of the I / O sensor of any one of claims 21-22.

26. A computer readable encoding of the I / O sensor of any one of claims 21-22.

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