Void-free stress embedding in semiconductor devices.

Abstract

The present technology includes a semiconductor device with improved stress in a channel region. The semiconductor device includes a substrate, a source region, a drain region, a channel region including at least one channel disposed between the source and drain regions, a first gate region, and a second gate region. The first gate region includes a self-aligned single diffusion break, and the second gate region includes a first gate surrounding the channel between the source and drain regions. The self-aligned single diffusion break also includes a dielectric liner and a stressed metal fill, and the stressed metal fill exhibits a stress of about 350 MPa or greater.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. patent application Ser. No. 63 / 487,507, filed February 28, 2023, entitled "VOID-FREE STRESS INCORPORATION IN SEMICONDUCTOR DEVICES," which is incorporated herein by reference in its entirety.

[0002]

[0002] The present technology relates to methods for semiconductor processing. In particular, the present technology relates to methods for incorporating increased stress within doped regions of semiconductor devices. [Background technology]

[0003]

[0003] Integrated circuits have evolved into complex devices that can contain millions of transistors, capacitors, and resistors on a single chip. During the evolution of integrated circuits, functional density (i.e., the number of interconnected devices per chip area) has generally increased while feature size has decreased. A transistor is a circuit component or element that is often formed on a semiconductor device. Depending on the circuit design, many transistors, as well as capacitors, inductors, resistors, diodes, conductive lines, or other elements, may be formed on a semiconductor device. Integrated circuits incorporate field effect transistors (FETs), which conduct current through a semiconductor channel between a source and a drain in response to a voltage applied to a control gate.

[0004]

[0004] Integrated circuits are made possible by processes that form intricately patterned layers of materials on substrate surfaces. Fabricating patterned materials on substrates requires controlled methods for forming and removing materials. As devices become smaller, film properties can have a greater impact on device performance. As devices become smaller and the industry utilizes more complex patterning schemes, thin film deposition becomes a challenge. Additionally, as material thickness continues to decrease, the as-deposited properties of films can have a greater impact on device performance. These challenges include depositing void-free and stressed films.

[0005]

[0005] Therefore, there is a need for high quality devices and structures with improved mobility, and methods for making such devices. The present technology addresses these and other needs. Summary of the Invention

[0006]

[0006] Embodiments of the present technology include a semiconductor device with improved stress in a channel region. The semiconductor device includes a substrate, a source region, a drain region, a channel region including at least one channel disposed between the source and drain, a first gate region, and a second gate region. The first gate region includes a self-aligned single diffusion break in a p-MOS region, and the second gate region includes a first gate surrounding the channel between the source and drain regions. The self-aligned single diffusion break also includes a dielectric liner and a stressed metal fill. In this case, the stressed metal fill exhibits a compressive stress of about 350 MPa or greater.

[0007] In some embodiments, the channel region has a compressive stress of about 250 MPa or greater. In further embodiments, the semiconductor device also includes a third gate region, where the second gate region is disposed between the first gate region and the third gate region. The third gate region includes a second self-aligned single diffusion break. In further embodiments, the stressed metal fill material is selected from aluminum and aluminum-containing materials, tungsten and tungsten-containing materials, copper and copper-containing materials, titanium and titanium-containing materials, tantalum and tantalum-containing materials, nickel and nickel-containing materials, cobalt and cobalt-containing materials, ruthenium and ruthenium-containing materials, molybdenum and molybdenum-containing materials, metals having a Pilling-Bedworth ratio of about 1.5 or greater, their oxides, or combinations thereof. In further embodiments, the dielectric material liner has a thickness of about 1 nm to about 6 nm. In some embodiments, the channel region includes a plurality of horizontally extending channels. In embodiments, the semiconductor device is a nanosheet field effect transistor or a complementary field effect transistor. In further embodiments, the semiconductor device is a gate-all-around complementary metal oxide semiconductor.

[0008]

[0008] Some embodiments include a second gate region having a tensile-stressed metal fill having a compressive stress of about 350 MPa or greater. In further embodiments, the third gate region includes a dielectric liner and a compressive-stressed metal fill having a compressive stress of about 350 MPa or greater. In further embodiments, the third gate region includes a dielectric liner and a tensile-stressed metal fill. In more embodiments, the self-aligned diffusion break defines a space, where the stressed metal fill and the dielectric liner occupy about 95% or more by volume of the space. In some embodiments, the stressed metal fill is generally void or seam-free. In some embodiments, the stressed metal fill and the dielectric liner occupy about 99% or more by volume of the space of the self-aligned diffusion break. In further embodiments, the stressed metal filling has a compressive stress of about 500 MPa or greater, and the channel region is a p-channel metal oxide semiconductor, and the channel region has a compressive stress of about 350 MPa or greater.

[0009]

[0009] Embodiments of the present technology also include a semiconductor processing system. The semiconductor processing system includes a first processing chamber, a second processing chamber, a third processing chamber, and a system controller. In embodiments, the system controller is configured to: pattern a substrate in the first processing chamber; etch shallow trench isolation in a first gate region of a semiconductor device in the second processing chamber, where the first gate region is a p-MOS region; and line the shallow trench isolation with a dielectric liner and fill the shallow trench isolation with a metal material configured to provide a compressive stress of at least about 350 MPa in the third processing chamber.

[0010]

[0010] Embodiments of the present technology also include a method for forming a semiconductor device with improved stress in a channel region. The method includes etching a shallow trench isolation in a first gate region of the semiconductor device. The semiconductor device includes a substrate, a source region, a drain region, a channel region including at least one channel disposed between the source and drain, a first gate region, and a second gate region. The second gate region includes a first gate surrounding the channel between the source and drain regions. The method includes lining the shallow trench isolation with a dielectric liner. The method also includes filling the lined shallow trench isolation with a metal fill material configured to provide a stress of at least about 350 MPa.

[0011] In some embodiments, the semiconductor device exhibits a first amount of stress in the channel region before etching and filling and a second amount of stress in the channel region after etching and filling, the percentage change from the first amount of stress to the second amount of stress being about 10% or greater. In further embodiments, the semiconductor device includes a third gate region, the second gate region being disposed between the first gate region and the third gate region. In some embodiments, the third gate region is etched during the etching of the first gate region. Alternatively, the third gate region is masked during the etching of the first gate region and is patterned and etched after the etching of the first gate region to form a second shallow trench isolation in the third gate region. In still further embodiments, the shallow trench isolation is filled with a compressively stressed metal fill, and the second shallow trench isolation is filled with a compressively stressed or tensilely stressed metal fill. In some embodiments, the fill metal has a naturally occurring compressive stress or is oxidized after filling. In more embodiments, the method further comprises annealing the semiconductor device after filling.

[0012]

[0012] Such techniques may offer many advantages over conventional techniques. For example, embodiments of the present technique generate a desired level of stress in the channel region of a semiconductor transistor without modifying the composition of the adjacent source and drain regions. In addition, the present technique generates stress in the channel region from existing diffusion breaks, thus allowing more compact devices to be formed with improved stress. The present technique may therefore provide improved stress without requiring additional channels or diffusion breaks with increased size. These and other embodiments, along with their many advantages and features, are described in more detail below and in the accompanying drawings.

[0013]

[0013] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings. [Brief explanation of the drawings]

[0014] [Figure 1]

[0014] A top view of an exemplary processing chamber is shown, in accordance with some embodiments of the present technique. [Figure 2]

[0015] 1 illustrates selected steps in a fabrication method, according to some embodiments of the present technique. [Figure 3A]

[0016] 1 illustrates a cross-sectional view of an exemplary semiconductor structure, in accordance with some embodiments of the present technique. [Figure 3B] 1 illustrates a cross-sectional view of an exemplary semiconductor structure, in accordance with some embodiments of the present technique. [Figure 3C] 1 illustrates a cross-sectional view of an exemplary semiconductor structure, in accordance with some embodiments of the present technique. [Figure 3D] 1 illustrates a cross-sectional view of an exemplary semiconductor structure, in accordance with some embodiments of the present technique. [Figure 3E] 1 illustrates a cross-sectional view of an exemplary semiconductor structure, in accordance with some embodiments of the present technique. [Figure 4]

[0017] 1 illustrates a cross-sectional view of an exemplary semiconductor structure, in accordance with some embodiments of the present technique. [Figure 5]

[0018] 1 illustrates selected steps in a fabrication method, according to some embodiments of the present technique. DETAILED DESCRIPTION OF THE INVENTION

[0015]

[0019] Some of the drawings are included as schematic diagrams. It is understood that the figures are for illustrative purposes and should not be considered to scale unless expressly stated to be to scale. Furthermore, as schematic diagrams, the figures are provided to aid in understanding and may not include all aspects or information compared to realistic depictions and may include material that is emphasized for illustrative purposes.

[0016]

[0020] In the accompanying drawings, similar components and / or features may have the same reference numerals. Furthermore, various components of the same type may be distinguished according to the reference numeral, with a letter distinguishing between the similar components. When only a first reference numeral is used herein, the description is applicable to any of the similar components having the same first reference numeral, regardless of the letter.

[0017]

[0021] The present technology includes electronic devices having one or more self-aligned single diffusion breaks and methods for forming such devices. Such electronic devices may include semiconductor transistors, such as n-channel and p-channel MOSFETs, FinFETs, gate-all-around FETs, and nanosheet FETs, among other transistors, as well as products having such channel regions. In conventional processing methods, the stress level in a transistor channel can be controlled by varying the composition of the semiconductor material in the channel and the composition of the material in the adjacent source and drain regions. In many cases, varying the composition of these doped regions of a transistor to impart a desired amount of stress to the channel region can result in otherwise less desirable transistor performance, such as a lower thermal budget and / or increased resistance at the interface between the contact and the doped region. Controlling the stress in the channel region by varying the composition of the doped region also limits the types of materials that can be used in the doped region. For example, modern PMOS transistors often use doped silicon-germanium (SiGe) semiconductors in the doped region of the transistor. If the Ge-Si ratio becomes too high, defects can occur in the material due to lattice mismatch, reducing the stress in the channel region below acceptable levels.

[0018]

[0022] Another conventional method for increasing stress in a transistor's channel region involves depositing a stressed conductive material in a contact trench above the channel region. The stress from the conductive material is transferred downward to impart the desired stress in the doped material of the channel region. These conventional methods require careful selection and deposition of the conductive material in the contact trench to meet the stress requirements, as well as electrical conductivity, chemical reactivity, hermeticity, thermal budget, and other requirements for the material. In many cases, meeting the stress requirements requires a compromise: selecting a conductive material with less-than-ideal properties in some respects. Altering the deposition method or composition of the stressed material creates additional stress that can degrade the material's performance in other respects, such as electrical conductivity.

[0019]

[0023] Nevertheless, conventional methods have proven increasingly ineffective due to increasingly complex gate and channel surface orientations. That is, gate orientations in multichannel semiconductor nanostructures, such as gate-all-around, complementary FET, nanosheet, and nanowire orientations, to name just a few, hinder the effectiveness of conventional stress application. For example, conventional methods for increasing stress may be able to apply sufficient stress to the top and / or bottom gates, but they are unable to provide the necessary stress to the gate disposed therebetween. Furthermore, due at least in part to poor stress matching in addition to unfavorable surface orientations, multichannel semiconductor nanostructures also exhibit unfavorable hole and / or electron mobilities. Such hole mobility deficiencies are particularly evident compared to conventional gate and favorable channel orientations, such as fin field effect transistors (FinFETs).

[0020]

[0024] Efforts to improve channel strain in multichannel semiconductor nanostructures, particularly those involving source and drain regions formed via epitaxial growth processes, have been underway. However, due to their complex geometries and surface orientations, epitaxial merging consistently suffers from dislocations during and after formation. These dislocations can pull the epitaxially grown material away from the gate and create dislocation seams, leading to channel stress relaxation over time. This has proven problematic, particularly for hole mobility, such as in p-type metal oxide semiconductor (PMOS) regions. Methods to improve epitaxial merging defects have been explored as a way to impart consistent channel stress. However, none of the existing methods have proven sufficient to provide consistent stress, improve electron and hole mobility, or achieve a combination of both.

[0021]

[0025] The present technology overcomes these challenges by providing a consistent stressed channel with improved hole and / or electron mobility. By utilizing one or more self-aligned single diffusion breaks with a thin dielectric stressor film filled with a void-free metal, a desired stress can be provided in the stressed channel region. Additionally, by utilizing a unique combination of a thin dielectric film and a metal fill, void formation in the self-aligned diffusion break can be avoided without requiring further processing of the fill material. In several embodiments of the present technology, stress can be generated by deposition of a stressed material in one or more self-aligned single diffusion breaks adjacent to one or more doped regions of a transistor, such as a channel region. The stressed material can initially impart stress to the one or more self-aligned single diffusion breaks, which can then transfer a portion of that stress to the channel region of the transistor.

[0022]

[0026] While the remainder of the disclosure will routinely identify particular metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductors (CMOS), and their components, it will be readily understood that the devices and methods are equally applicable to other field-effect transistors, their configurations, and processes for forming such devices. Accordingly, the present technology should not be considered limited to use solely with these particular devices or methods. This disclosure will describe one possible semiconductor device, which may include one or more components utilizing one or more self-aligned single diffusion breaks in accordance with embodiments of the present technology, before further variations and modifications to this device in accordance with embodiments of the present technology are described.

[0023]

[0027] FIG. 1 illustrates a top view of a multi-chamber processing system 100 that may be specifically configured to implement aspects or operations according to some embodiments of the present technology. The multi-chamber processing system 100 may be configured to perform one or more manufacturing processes on individual substrates, such as any number of semiconductor substrates, to form semiconductor devices. The multi-chamber processing system 100 may include some or all of the following: a transfer chamber 106, a buffer chamber 108, single-wafer load locks 110 and 112 (or dual load locks may be included), processing chambers 114, 116, 118, 120, 122, and 124, preheat chambers 123 and 125, and robots 126 and 128. The single-wafer load locks 110 and 112 may include a heating element 113 and may be attached to the buffer chamber 108. The processing chambers 114, 116, 118, and 120 may be attached to the transfer chamber 106. The processing chambers 122 and 124 may be attached to the buffer chamber 108. Two substrate transfer platforms 102 and 104 may be positioned between the transfer chamber 106 and the buffer chamber 108 to facilitate transfer between the robots 126 and 128. The platforms 102, 104 may be open to the transfer and buffer chambers, or the platforms may be selectively isolated or sealed from the chambers so that different operating pressures are maintained between the transfer chamber 106 and the buffer chamber 108. The transfer platforms 102 and 104 may each include one or more tools 105, such as for orientation or measurement operations.

[0024]

[0028] The operation of the multi-chamber processing system 100 may be controlled by a computer system 130. The computer system 130 may include any device or combination of devices configured to perform the operations described below. Accordingly, the computer system 130 may be a general-purpose computer configured with a controller or an array of controllers and / or software stored on a non-transitory computer-readable medium that, when executed, can perform the operations described in connection with methods according to embodiments of the present technology. Each of the processing chambers 114, 116, 118, 120, 122, and 124 may be configured to perform one or more processing steps in the fabrication of semiconductor structures. More specifically, the processing chambers 114, 116, 118, 120, 122, and 124 may be equipped to perform numerous substrate processing steps, including dry etching processes, cyclical layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, pre-cleaning, degassing, and orientation, among any number of other substrate processes.

[0025]

[0029] 2 illustrates exemplary steps in a method 200 according to some embodiments of the present technique. The method may be performed in a variety of processing chambers, including the processing chamber 100 described above. Method 200 may include several optional steps that may or may not be specifically associated with some embodiments of methods according to the present technique. For example, many of the steps are described to provide a broader range of structure formations, but are not critical to the technique or may be performed by alternative methods as may be readily understood.

[0026]

[0030] Method 200 may include additional steps before the enumerated steps begin. For example, additional processing steps may include forming structures on a semiconductor substrate, including both the formation and removal of materials. Prior processing steps may be performed in the chamber in which method 200 is performed, or processing may be performed in one or more other processing chambers before transferring the substrate to the semiconductor processing chamber in which method 200 is performed. In either case, method 200 may optionally include providing a semiconductor substrate to a processing region of a semiconductor processing chamber, such as processing chamber 100 described above, or another chamber that may include the components described above. The substrate may be disposed on a substrate support / transfer platform, which may be a pedestal, such as substrate support 104, and which may be mounted within the processing region of a chamber, such as processing region 120 described above. Method 200 describes steps shown generally in FIGS. 3A through 3E, examples of which are described in conjunction with the steps of method 200. It will be understood that Figures 3A-3E show partial schematic views only, and that the semiconductor substrate may be of any size or configuration that further includes the components illustrated in the figures, as well as alternative components, and still benefit from aspects of the present technology.

[0027]

[0031] Method 200 may or may not include optional steps for developing a semiconductor structure into a specific manufacturing process. It should be understood that method 200 may be performed on any number of semiconductor structures 300 or substrates 302, as shown in FIGS. 3A-3E, which include exemplary structures upon which selective deposition materials may be formed. As shown in FIG. 3A, substrate 302 may have several layers of material deposited thereon. Substrate 302 may be any number of materials, such as a base wafer or substrate made of silicon, silicon-containing materials, germanium, other substrate materials, as well as one or more materials that may be formed thereon during semiconductor processing.

[0028]

[0032] Structure 300 may, in embodiments, illustrate a partial view of a substrate that may be used in n-channel and p-channel MOSFETs, FinFETs, gate-all-around FETs, complementary metal-oxide semiconductors, and nanosheet FETs, among other types of semiconductor transistor structures. The layers of material may be fabricated by any number of methods, including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermally enhanced chemical vapor deposition (TECVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), or any other formation technique. In embodiments, plasma-enhanced chemical vapor deposition may be performed in a processing chamber, such as processing chamber 100 described above. The substrate layers may include silicon oxide and silicon nitride, silicon oxide and silicon, silicon nitride and silicon, silicon and doped silicon, or any number of other materials.

[0029]

[0033] As shown in FIG. 3A , a structure 300 is provided that includes a substrate 302 that has already undergone source / drain 304 formation. In some embodiments, the source / drain 304 formation may include epitaxial growth of a doped silicon material, such as silicon-germanium. However, it should be understood that the source / drain regions 304 may be formed from any suitable deposition and patterning process, as the present disclosure does not require rigorous source / drain 304 formation (e.g., attempting to heal epitaxial growth defects) to maintain hole or electron mobility. Additionally, the structure 300 includes multiple gate regions 306 and interlayer dielectric / dummy gate regions 308, which may be formed as known in the art and described above.

[0030]

[0034] In some embodiments, the structure 300 may be a bulk semiconductor substrate. As used herein, the term "bulk semiconductor substrate" refers to a substrate where the entire substrate is composed of a semiconductor material. A bulk semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> The semiconductor substrate 300 may comprise one or more materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In several embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 300 comprises a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 300 comprises one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although some examples of materials from which the substrate may be formed are described herein, any material that can serve as a foundation upon which passive and active electronic devices (e.g., transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic device) may be constructed is within the spirit and scope of the present disclosure.

[0031]

[0035] In embodiments, the semiconductor material may be a doped material, such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. As used herein, the term "n-type" refers to a semiconductor made by doping an intrinsic semiconductor with an electron-donating element during fabrication. The term n-type comes from the negative charge carried by electrons. In n-type semiconductors, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of the wells (or holes). Relative to n-type semiconductors, p-type semiconductors have a higher hole concentration than the electron concentration. In p-type semiconductors, holes are the majority carriers and electrons are the minority carriers. As discussed above, in embodiments, the present technology may provide improved mobility in both p- and n-type semiconductors. However, in embodiments, p-type semiconductors may experience further hole mobility enhancement.

[0032]

[0036] Nevertheless, in step 201, method 200 may include patterning one or more mask layers 310 deposited on top surfaces of source / drain regions 304 and portions of gate regions 306 on substrate 302. For example, in some embodiments, substrate 302 is loaded into load locks 110, 112 and transferred via robots 126, 128 to a process chamber (such as process chamber 114) where a mask deposition process occurs. That is, as shown, one or more mask layers 310 are patterned over five of the seven illustrated gate regions 306, leaving two gate regions 306 exposed. However, as will be explained in more detail below, it should be understood that the patterned mask layer 310 may be positioned or spaced over one or more gate regions 306 as needed to provide the necessary stress to the channel region 316 (as shown more clearly in FIG. 4 ).

[0033]

[0037] 3B, in step 202, method 200 may include etching structure 300. In some embodiments, such step may include transferring substrate 302 to second process chamber 116 configured for an etching process. For example, in one embodiment, one or more of inductively coupled plasma (ICP) etching, reactive ion etching (RIE), or capacitively coupled plasma (CCP) etching are used to form shallow trench isolation or via 312. Furthermore, because mask layer 310 is aligned with gate region 306, shallow trench isolation 312 may be formed within and self-aligned to the gate region and may therefore be considered a self-aligned shallow trench isolation or self-aligned single diffusion break.

[0034]

[0038] After etching structure 300 in step 202, method 200 may include an optional passivation and / or oxidation process following removal of mask layer(s) 310. Nevertheless, etched substrate 302 may be transferred to a third process chamber 118 configured for a deposition and / or fill process, including a chamber for chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermally enhanced chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), etc. For example, in such process chamber 118, in step 203, a dielectric film liner 328 is formed along the perimeter 330 (or outer wall) of self-aligned diffusion break 312, as shown in FIG.

[0035]

[0039] After forming the dielectric film liner in step 203 within the self-aligned diffusion break 312, method 200 may include a fill step 204 of filling the self-aligned diffusion break 312 with metal 314. The fill step 204 may be performed in the same deposition chamber 218, or the substrate 302 may be transferred to an additional process chamber. In some embodiments, the fill may be performed with a stressed metal or may include an unstressed metal, although it will be apparent that either may be configured to provide the necessary stress, either as an inherent feature of the metal or as a feature that may be induced in the metal. For example, when an unstressed metal is used, a further oxidation process may be utilized to impart the necessary stress to the fill metal (such as when using a metal with a high Piling-Bedworth ratio). As shown, the dielectric film liner 328 forms a barrier between the metal fill 314 and the nearby source-drain regions 304, expanding the metal that may be used to form the stressed fill so that the stressed metal does not contact nearby regions.

[0036]

[0040] 3B, the self-aligned diffusion break 312 defines a space from the top surface 332 of the structure to the bottom surface 334 of the diffusion break 312. As will be explained in more detail below, the dielectric liner 328 and stressed metal 314 occupy most or all of the space defined by the self-aligned diffusion break. That is, as described above, the present technique has discovered that by utilizing a thin liner in combination with the stressed metal, few or no seams or voids can form within the self-aligned diffusion break 312 during deposition / fill.

[0037]

[0041] Nevertheless, after formation of the liner 328 and stressed metal fill 314, the substrate 302 may be transferred to a fourth process chamber 120, such as a process chamber configured for polishing, including chemical-mechanical polishing. Accordingly, in step 205, the method 200 may include polishing the structure 300 (e.g., chemical-mechanical polishing the top surface 332 of the structure 300 (FIG. 3D)). A further view of FIG. 3D is shown in FIG. 3E, in which the interlayer dielectric 308 and gate region 306 have been removed for clarity. Additionally, FIG. 4 shows a cross-sectional view of an exemplary embodiment, such as along line A-A' in FIG. 3E. FIG. 4 may more clearly show the source / drain regions 304, the gate region 306, and the channel region 316. As shown, in some embodiments, the structure 300 may have a horizontal gate-all-around orientation, with multiple horizontally extending channels 326 within the channel region 316. For example, in some embodiments, the channel 326 may be generally parallel to the top surface 336 of the substrate 302 .

[0038]

[0042] That is, the present technique has surprisingly discovered that by utilizing a dielectric material to line the periphery 330 of the self-aligned diffusion break(s) 312 and then filling the dielectric-lined diffusion break 312 with a stressed metal fill 314, superior electron and / or hole mobility can be achieved. The same is true even for structures with unfavorable surface orientations. Furthermore, by utilizing a combination of a dielectric material liner and a stressed metal fill within the self-aligned diffusion break(s), the present technique can transfer compressive stress from the stressed material to the nearby channel region without suffering from the channel stress relaxation exhibited in existing techniques.

[0039]

[0043] For example, in the present technology, one or more channel regions 316 (shown more clearly in FIG. 3E and FIG. 4) are increased from a lower stress (a first stress amount) to a higher stress (a second stress amount after deposition and filling as described herein). In embodiments, the percentage change in stress in the channel region 316 from the first stress amount to the second stress amount can be about 0.1% or more, e.g., about 1% or more, about 2% or more, about 5% or more, about 10% or more, about 25% or more, about 50% or more, about 75% or more, about 100% or more, or more, or any range or value therebetween. In further embodiments, the first stress amount in the channel region 316 can be about 10 MPa or less, e.g., about 5 MPa or less, about 1 MPa or less, or less. In further embodiments, the second amount of stress in the channel region 316 can be about 100 MPa or more, e.g., about 200 MPa or more, about 300 MPa or more, about 400 MPa or more, about 500 MPa or more, about 600 MPa or more, or any range or value therebetween.

[0040]

[0044] Additionally, in embodiments, the present technology has found that such stress can be evenly distributed throughout the channel region 316. As mentioned above, previous attempts have utilized stressed materials above and below the channel region. However, conventional techniques may limit stress improvements to the upper side 318 of the channel region 316 and / or the lower side 320 of the channel region 316. Thus, conventional techniques have not been able to provide consistent stress throughout the channel. Conversely, it should be understood that in embodiments, the present technology can have a first channel stress at a first location 322 within the channel region 316 (illustrated adjacent the lower portion 320 of the channel 316 for illustrative purposes only; the first location 322 can be anywhere within the channel region 316) and a second channel stress at a second location 324 within the channel region 316. As shown, the first location 322 can be vertically spaced from the second location 324 for illustrative purposes. However, in some embodiments, the regions may be spaced apart horizontally, or may be spaced apart both vertically and horizontally. Nevertheless, the stress in the first channel may vary from the stress in the second channel by about 30% or less, e.g., about 27.5% or less, about 25% or less, about 22.5% or less, about 20% or less, about 17.5% or less, about 15% or less, about 12.5% ​​or less, about 10% or less, or any range or value therebetween.

[0041]

[0045] Furthermore, as described above, increased stress in the channel region is believed to improve the mobility of charge carriers in the channel, which may also increase the drive current through the channel region. In particular, the increased stress generated in the channel region in embodiments of the present technology may increase the drive current, such as the p-MOS drive current, through the transistor channel by about 1% or more, e.g., about 5% or more, about 10% or more, about 15% or more, about 20% or more, about 25% or more, about 30% or more, about 35% or more, about 40% or more, about 45% or more, about 50% or more, about 55% or more, or any range or value therebetween. In embodiments, increased stress in the channel region can lead to further improvements in hole mobility, such as by about 10% or more, about 20% or more, about 30% or more, about 40% or more, about 50% or more, about 60% or more, about 70% or more, about 80% or more, about 90% or more, about 100% or more, about 110% or more, about 120% or more, about 130% or more, about 140% or more, about 150% or more, or any range or value therebetween. Increased drive current and hole mobility through the channel region can improve transistor performance in several ways, including, but not limited to, improved switching speed and / or reduced power consumption. Embodiments of the present technology can achieve these improvements in semiconductor devices without imposing limitations on the types of materials used in the devices, which may create new processing challenges or otherwise compromise device performance.

[0042]

[0046] Nevertheless, the dielectric liner material can be filled into the self-aligned diffusion break(s) 312 using atomic layer deposition, plasma-enhanced atomic layer deposition, chemical vapor deposition, plasma-enhanced chemical vapor deposition, among other types of deposition techniques. In embodiments, the dielectric film liner 328 can be characterized by a thickness of about 0.5 nm or more, e.g., about 1 nm or more, about 1.5 nm or more, about 2 nm or more, about 2.5 nm or more, about 3 nm or more, about 3.5 nm or more, about 4 nm or more, about 4.5 nm or more, about 5 nm or more, or more. Furthermore, the dielectric film liner 328 can be characterized by a thickness of about 8 nm or less, e.g., about 7 nm or less, about 6 nm or less, about 5 nm or less, about 4.5 nm or less, or less, or any range or value therebetween. Utilizing a dielectric liner within the above ranges can impart high stress to the channel region while avoiding degradation of breakdown voltage. For example, when the dielectric liner thickness is too small (e.g., less than 1 nm, or even 2 nm in some embodiments), there is a high risk of breakdown voltage degradation due to insufficient isolation of the stressed metal fill from the channel region. That is, as the dielectric liner thickness increases, less stress is transferred from the stressed metal fill to the channel region. Therefore, it is important to balance a liner that is thick enough to prevent breakdown voltage degradation without losing the desired stress.

[0043]

[0047] Nevertheless, in some embodiments, the amount of stress in the stressed metal fill and, optionally, the dielectric liner material may depend on the amount of stress to be imparted to the channel region of the semiconductor device as a result of depositing the stressed material. This may, in some embodiments, require determining the amount of stress desired in one or more channel regions 316. The stressed metal fill material may include aluminum and aluminum-containing materials, tungsten and tungsten-containing materials (e.g., tungsten nitride (WN) and tungsten carbide (WC)), copper and copper-containing materials, titanium and titanium-containing materials (titanium nitride (TiN), titanium silicide (TiSi), titanium carbide (TiC), and titanium aluminide (TiAl)), tantalum and tantalum-containing materials (e.g., tantalum nitride (TaN)), nickel and nickel-containing materials (such as nickel silicide (NiSi)), cobalt and cobalt-containing materials, ruthenium and ruthenium-containing materials, molybdenum and molybdenum-containing materials, or combinations thereof.

[0044]

[0048] Additionally or alternatively, suitable metals for use as stress metal fillers include, but are not limited to, metals having a Pilling-Bedworth ratio of about 1.5 or greater, e.g., about 1.75 or greater, e.g., about 2 or greater, e.g., about 2.25 or greater, e.g., about 2.5 or greater, or any range or value therebetween. The Pilling-Bedworth ratio refers to the ratio of the volume of an elementary cell of a metal chalcogenide to the volume of an elementary cell of the corresponding metal-containing film in which the metal chalcogenide is formed. The Pilling-Bedworth ratio is calculated by multiplying V by V. chalc / V metal where V is the volume. To determine the Pilling-Bedworth ratio of a metal chalcogenide, V chalc is equal to the molecular weight of the metal chalcogenide multiplied by the density of the metal chalcogenide, and V metalis equal to the number of atoms of metal per molecule of metal chalcogenide multiplied by the density of the metal chalcogenide. Examples of metal fillers with high Pilling-Bedworth ratios include one or more of Co, Mo, W, Ta, Ti, Ru, Rh, Cu, Fe, Mn, V, Nb, Hf, Zr, Y, Al, Sn, Cr, Os, U, and / or La. That is, as described above, when utilizing materials with high Pilling-Bedworth ratios, the metal can be filled in an unstressed form, and then, when contained within a diffusion break, the unstressed metal oxidizes, expanding the volume of the metal and inducing the necessary compressive stress within the nearby channel.

[0045]

[0049] One or more stressed metal fill materials may be filled into the dielectric material 328-lined self-aligned diffusion break 312 using void-free stressed deposition processes, as known in the art. For example, chemical vapor deposition (CVD) and ALD deposition of these materials may include using any suitable precursor. For example, CVD and ALD may be suitable for deposition utilizing any suitable precursor of the stressed metal fill material. As one example, deposition of a tungsten-containing stressed metal fill material, such as tungsten nitride, may include using a tungsten-containing precursor and a nitrogen-containing precursor. As another example, deposition of a titanium-containing stressed metal fill material may include using a titanium-containing precursor, such as tetrakis(dimethylamino)titanium (TDMAT) or titanium chloride (TiCl4). Deposition of a tantalum-containing stressed metal fill material may include using one or more tantalum-containing precursors, such as pentakis-dimethylaminotantalum (PDMAT) or TaF5. Deposition of the stressed metal fill material including cobalt may include using one or more cobalt-containing precursors, such as tris(2,2,6,6-tetramethyl-3,5-heptanedionato)cobalt, bis(cyclopentadienyl)cobalt, dicobalt hexacarbonylbutylacetylene, etc. In embodiments, deposition of the stressed metal fill material may include one or more co-reactants, if appropriate.

[0046]

[0050] Nevertheless, to deposit the stressed metal 314, the deposition of the stressed metal may be carried out at a temperature of about 150° C. or higher, e.g., about 200° C. or higher, about 250° C. or higher, about 300° C. or higher, about 350° C. or higher, about 400° C. or higher, or higher. Additionally, deposition of the stressed metal material may be carried out at a temperature of about 500° C. or lower, e.g., about 450° C. or lower, or any range or value therebetween.

[0047]

[0051] Additionally, in some embodiments, the metal fill may undergo oxidation after deposition, such as when using metals with high Pilling-Bedworth ratios. Oxidation of the stressed metal fill material may provide the necessary stress or further increase the stress of the metal fill. That is, oxidizing the metal fill may cause the metal fill to expand, increasing the stress within the metal fill. Oxidation of the stressed metal fill material may be achieved using a thermal oxidation process, a plasma oxidation process, or the like. Thus, in some embodiments, the metal fill may include an oxide of the metals described above.

[0048]

[0052] In embodiments, the stressed metal filling may be characterized by a stress of about 350 MPa or greater, e.g., about 400 MPa or greater, about 500 MPa or greater, about 600 MPa or greater, about 700 MPa or greater, about 800 MPa or greater, about 900 MPa or greater, about 1 GPa or greater, or greater, or any range or value therebetween. For purposes of this disclosure, a higher stress material is characterized by a greater absolute value of stress, whether positive or negative, than that of a lower stress material. In the convention used herein, positive stress is characterized by tensile stress, negative stress is characterized as compressive stress, and zero stress (i.e., 0 GPa) is characterized as neutral stress. Positive (i.e., tensile) stress may be characterized by an outward extrusive force that may be generated by expansion of the material. Negative (i.e., compressive) stress may be characterized by an inward tensile force that may be generated by contraction of the material. Thus, as used herein, a "compressive stress" value may refer to a negative absolute value (e.g., a compressive stress of 250 MPa may also be read as -250 MPa), and as used herein, a "tensile stress" value may refer to a positive absolute value (e.g., a tensile stress of 250 MPa refers to 250 MPa).

[0049]

[0053] Regardless of the metal and final stress, in some embodiments, the metal fill undergoes a further annealing process after filling. While the stressed metal and its deposition method may provide a stressed metal fill material with few or no voids, in some embodiments, a further annealing step, such as a microwave annealing process, may further reduce or eliminate any remaining voids without damaging the surrounding structure or the metal fill.

[0050]

[0054] As described above, in some embodiments, the self-aligned diffusion break 312 may be filled with the stressed metal material and the dielectric liner in a manner that is generally considered to be free of voids and / or seams. Thus, in some embodiments, the stressed metal fill and the dielectric liner occupy about 90% by volume or more of the space defined by the self-aligned diffusion break, e.g., about 92% by volume or more, about 94% by volume or more, about 96% by volume or more, about 98% by volume or more, about 99% by volume or more, or any range or value thereof. In some embodiments, the space defined by the self-aligned diffusion break may be completely occupied by the stressed metal fill and the dielectric liner, and no voids or seams may be present. With this technique, even small voids or seams within the self-aligned diffusion break may result in an undesirable reduction in channel stress. For example, voids or seams characterized by a size of about 3 nm or less, such as about 2 nm or less, or about 1 nm or less, can result in a reduction in average channel stress of more than 60%.

[0051]

[0055] In some embodiments, the self-aligned diffusion break may define a channel length L, defined as the distance between the source and drain regions, as shown in FIG. 4 . The channel length L may be characterized by a length of about 35 nm or less, e.g., about 30 nm or less, about 25 nm or less, about 20 nm or less, or any range or value therebetween. The self-aligned diffusion break may be characterized by a high aspect ratio due to the small channel length and large diffusion break depth. Additionally, in some embodiments, only a single self-aligned diffusion break is utilized in structure 300, and not a double diffusion break, yet still imparts the necessary stress, thus allowing for a reduced size while maintaining effectiveness.

[0052]

[0056] Furthermore, although the illustrated embodiments include two single self-aligned diffusion breaks 312 on either side of three gate regions 306 in Figures 3A-3E and two single self-aligned diffusion breaks 312 on either side of a single gate region 306 in Figure 4, it should be understood that the self-aligned diffusion breaks may be positioned with any number of gate regions 306 between pairs of diffusion breaks. For example, one gate region 306, e.g., two gate regions, three gate regions, e.g., four gate regions, e.g., five gate regions, e.g., six gate regions, e.g., seven gate regions, or more gate regions may be positioned between pairs of diffusion breaks depending on the desired stress on the channel region 316 in the structure 300. For example, the number of channel regions 304 disposed between the opposing self-aligned diffusion breaks 312 may be selected to maintain a channel stress of about 350 MPa or more, e.g., about 400 MPa or more, about 450 MPa or more, about 500 MPa or more, about 550 MPa or more, e.g., about 650 MPa or more, e.g., 750 MPa or more, e.g., about 850 MPa or more, e.g., about 950 MPa or more, e.g., about 1000 MPa or more, or more, or any range or value therebetween.

[0053]

[0057] As described above, in some embodiments, the stress imparted by the stressed metal fill can significantly improve mobility and drive current. However, in some embodiments, the improvements described above are specific to hole mobility and p-MOS drive current. Thus, in one or more embodiments, the patterning described above is specific to patterning a single diffusion break in the p-MOS region. For example, with reference to FIG. 5 , in some embodiments where improvements are required in both the p-MOS and n-MOS regions, method 500 can include steps 506 through 510, with step 506 occurring after step 205 of FIG. 2 . That is, as shown, method 500 can include a second patterning step 506. The second patterning step 506 is performed in the same manner as step 201, except that a patterning material is disposed over the n-MOS region. In one such embodiment, substrate 302 can be transferred from processing chamber 120 to processing chamber 114 for the second patterning step. The substrate may then be transferred from processing chamber 114 to etching chamber 116 where etching may occur in step 507. After the second etching process 507, an optional passivation / oxidation step may be performed in step 508, followed by transfer to process chamber 118 for liner deposition / stressed metal fill in step 509, which may be performed in the same or similar manner as etching step 202 and fill step 203, utilizing second patterning step 506. Of course, it should be understood that in some embodiments, method steps 506 through 510 may be performed in whole or in part before steps 201 through 205. Nevertheless, after the second deposition fill step 509, the substrate 302 may be transferred back to processing chamber 120 for a second polishing step 510.

[0054]

[0058] Additionally, stressed metal material 314 as described above can still be used to fill the self-aligned diffusion break 312 lined with the formed dielectric 328. However, a tensile stressed material can be used (or tensile stress can be induced in the stressed metal material) to promote further improvements in the n-MOS region. Deposition of a tensile stressed dielectric material within a single self-aligned diffusion break in the n-MOS region can further improve electron mobility and n-MOS current drive characteristics without adversely affecting hole mobility and p-MOS current drive characteristics as described herein.

[0055]

[0059] Thus, in addition to the improvements described above, increased stress in the channel region can improve the mobility of charge carriers in the channel, thereby increasing the drive current through the n-MOS region. In some examples, the increased stress generated in the channel region by embodiments of the present technology can increase the drive current through the transistor channel by about 1% or more, e.g., about 5% or more, about 10% or more, about 15% or more, about 20% or more, about 25% or more, about 30% or more, about 35% or more, about 40% or more, about 45% or more, about 50% or more, about 55% or more, or more, or any range or value therebetween. The increase in drive current and hole mobility through the channel region can improve the performance of the transistor in several ways, including, but not limited to, improved switching speed and / or reduced power consumption.

[0056]

[0060] In the above description, for purposes of explanation, numerous details are presented in order to facilitate an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details, or with additional details.

[0057]

[0061] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents may be used without departing from the spirit of the embodiments. Additionally, some well-known processes and elements have not been described to avoid unnecessarily obscuring the technology. Therefore, the foregoing description should not be deemed to limit the scope of the technology.

[0058]

[0062] Where a range of values ​​is given, unless the context clearly indicates otherwise, each intervening value between the upper and lower limit of that range is specifically disclosed, to the smallest unit of the lower limit. Any smaller ranges between any stated or unstated intervening value in a stated range, and any other stated or intervening value in that stated range, are also included. The upper and lower limits of such narrower ranges may individually be included or excluded from that range. Each range where either, neither, or both limits are included in this narrower range is also encompassed within the technology, even though there may be specifically excluded limits in the stated range. When a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0059]

[0063] As used in this specification and claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, a reference to "a dielectric material" includes a plurality of such materials, a reference to "a gate region" includes reference to one or more gate regions, and equivalents thereof known to those skilled in the art, and so forth.

[0060]

[0064] Additionally, the terms "comprise(s)," "comprising," "contain(s)," "containing," "include(s)," and "including," when used in this specification and claims, are intended to specify the presence of stated features, integers, components, or operations, but do not exclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

Claims

1. A semiconductor device comprising: substrate, Source region, Drain region, a channel region including at least one channel disposed between the source and the drain; a first gate region including a self-aligned single diffusion break in a p-MOS region, the self-aligned single diffusion break including a dielectric material liner and a stressed metal fill, the stressed metal fill being characterized by a compressive stress of greater than or equal to about 350 MPa; and a second gate region in an n-MOS region including at least a first gate surrounding the channel between the source region and the drain region;

2. 10. The semiconductor device of claim 1, wherein the channel region is characterized by a compressive stress of greater than or equal to about 250 MPa.

3. 10. The semiconductor device of claim 1, further comprising a third gate region, said second gate region being disposed between said first gate region and said third gate region, said third gate region comprising a second self-aligned single diffusion break.

4. 10. The semiconductor device of claim 1, wherein the material of the stressed metal fill is selected from aluminum and aluminum-containing materials, tungsten and tungsten-containing materials, copper and copper-containing materials, titanium and titanium-containing materials, tantalum and tantalum-containing materials, nickel and nickel-containing materials, cobalt and cobalt-containing materials, ruthenium and ruthenium-containing materials, molybdenum and molybdenum-containing materials, oxides of metals having a Pilling-Bedworth ratio of about 1.5 or greater, or combinations thereof.

5. The semiconductor device of claim 3 , wherein the channel region comprises a plurality of horizontally extending channels.

6. 6. The semiconductor device of claim 5, wherein the semiconductor device is a nanosheet field effect transistor or a complementary field effect transistor, and / or the semiconductor device is a gate-all-around complementary metal oxide semiconductor.

7. 10. The semiconductor device of claim 1, wherein the dielectric material liner is characterized by a thickness of about 1 nm to about 6 nm or less.

8. 4. The semiconductor device of claim 3, wherein the third gate region includes a third self-aligned diffusion break, the third self-aligned diffusion break including a compressively stressed metal fill characterized by a compressive stress of greater than or equal to about 350 MPa.

9. 10. The semiconductor device of claim 8, wherein the second self-aligned single diffusion break comprises a dielectric liner and a tensile-stressed metal fill, the tensile-stressed metal fill characterized by a compressive stress of greater than or equal to about 350 MPa.

10. 10. The semiconductor device of claim 1, wherein the self-aligned single diffusion break defines a space, and the stressed metal fill and the dielectric material liner occupy greater than or equal to about 95% by volume of the space.

11. The semiconductor device of claim 10 , wherein the stressed metal filling is generally void or seam free.

12. 12. The semiconductor device of claim 11, wherein the stressed metal fill and the dielectric material liner occupy greater than or equal to about 99% by volume of the space.

13. 1. A semiconductor processing system comprising: a first processing chamber; a second processing chamber; a third processing chamber; and a system controller, the system controller comprising: patterning a substrate in the first processing chamber; etching a shallow trench isolation in a first gate region of a semiconductor device in the second processing chamber, the first gate region being a p-MOS region; and and, in the third processing chamber, lining the shallow trench isolation with a dielectric liner and filling the shallow trench isolation with a metallic material configured to provide a compressive stress of at least about 350 MPa.

14. 1. A method of forming a semiconductor device, comprising: Etching a shallow trench isolation in a first gate region of the semiconductor device, the first gate region being a p-MOS region, the semiconductor device including a substrate, a source region, a drain region, a channel region including at least one channel disposed between the source and the drain, the first gate region, and a second gate region including at least a first gate surrounding the channel between the source region and the drain region; lining the shallow trench isolation with a dielectric liner; and filling the lined shallow trench isolation with a metal configured to provide a compressive stress of about 350 MPa or greater.

15. 15. The method of claim 14, wherein the channel region before the etching is characterized by a first stress and the channel region after the filling is characterized by a second stress, the first stress relative to the second stress being characterized by a percentage change of about 10% or greater.

16. 15. The method of claim 14, wherein the semiconductor device further includes a third gate region, the second gate region being disposed between the first gate region and the third gate region.

17. 17. The method of claim 16, further comprising: etching the third gate region to be etched during the etching of the first gate region; or masking the third gate region during the etching of the first gate region and patterning and etching the third gate region after the etching of the first gate region; and forming a second shallow trench isolation in the third gate region.

18. 18. The method of claim 17, further comprising filling the shallow trench isolation with a compressively stressed metal fill and filling the second shallow trench isolation with a tensile-stressed metal fill or a compressive-stressed metal fill.

19. 15. The method of claim 14, wherein the filled metal has a naturally occurring compressive stress or is oxidized after filling.

20. The method of claim 14 further comprising annealing the semiconductor device after filling.

Images