Metal Core Substrate Based Package Interconnect System

Abstract

The metal core substrate, in which the same metal intra-substrate structure is fabricated with a patterned metal core and the dielectric intra-substrate structure is separated from the patterned metal core, can include interconnect structures deposited on its top and back surfaces. The interconnect structures can include metal interconnect structures patterned therethrough, which can connect with the intra-metal substrate structure to create a metal core substrate-based package interconnect system that includes various electronic, optical, and other types of components within the metal core substrate-based package interconnect system. Multiple metal core substrate-based package interconnect systems can be connected to each other via bonds or contacts. The metal core substrate-based package interconnect system can also include external electronic components connected thereto via contacts.

Description

Detailed Description of the Invention

[0001] [STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT] Not applicable. [Copyright Notice] A portion of this disclosure contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of either the patent document or the patent disclosure, precisely as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights under 37 CFR 1.71(d).

[0002] [Reference to Related Application] This application claims the benefit of Provisional Application No. 63 / 487,345, entitled "SYSTEM ON FOIL," filed February 28, 2023. The benefit under 35 U.S.C. § 119(e) of the U.S. provisional application is hereby claimed, and the aforementioned provisional application is incorporated herein by reference in its entirety. FIELD OF THE INVENTION

[0003] [Background of the invention concept] The present concepts relate to metal core substrate-based package interconnect systems. More particularly, but not exclusively, the present concepts relate to metal core substrate-based package interconnect systems fabricated with various electronic, optical, and other types of components therein. [Description of Related Art]

[0004] The high cost of advancing to the next semiconductor technology node (e.g., 5nm) is changing the role of packaging in the electronics industry. At each new node, Moore's Law historically fulfills the economic and technological promise of scaling density, speed, power, and cost. However, these gains are now slowing, and new packaging solutions are needed to maintain the pace of the economic advantages previously fulfilled by silicon scaling.

[0005] Conductive through-substrate vias are required for almost all advanced packaging applications due to the large number of input / output (I / O) connections required to successfully partition system-on-chip (SoC) designs. This is because SoC designs contain millions of logic gates connected by complex wire networks in the form of multiple buses, complex clock distribution networks, and control signals. Standard device I / O imposes pin-to-pin delays that degrade overall circuit performance. Furthermore, the use of time-domain multiplexing (TDM) with standard I / O to increase virtual pin count by running multiple signals on each I / O can further increase latency, resulting in I / O speeds that can slow down by 4x to 32x or more. The TDM approach also results in higher power consumption. When used to drive hundreds of inter-package connections across PCB traces between multiple chips, standard device I / O pins incur a significant power penalty compared to connecting logic nets on a monolithic die. All of these requirements result in a demand for vias through the substrate.

[0006] Currently, there are three options for achieving feedthroughs in electronic substrates: through-panel vias (TPVs)—electrical conduits through printed circuit boards or organic substrates; through-silicon vias (TSVs)—electrically isolated copper traces through thinned silicon wafers; and through-glass vias (TGVs)—metal-filled holes through glass wafers. Processing techniques for creating conductive center pins for conductive through-vias all use electroplated copper or conductive paste screen-printing processes that use gold, silver, or copper mixed with glass powder and a polymer binder to form a conductive paste.

[0007] One issue with TPVs on printed circuit boards is the minimum resolution of the wires (metal lines), limiting space for larger features. Most printed circuit boards can pattern 4 mil (100 μm) or 3 mil (75 μm) lines and spaces, with the latest technology offering approximately 1.2 mil (30 μm), but at a very high cost. Through-panel via holes are limited to approximately 6 mil (150 μm). These large features primarily limit printed circuit boards to packaged components and do not allow for high-resolution components such as flip-chip dies. Due to the challenges of electroplating copper to fill large perforations in printed circuit boards, TPVs are typically large barrel-coated holes with an opening in the center of the via. An example of a TPV is described in U.S. Patent No. 6,717,071, "Coaxial Via Hole and Process of Fabricating the Same."

[0008] In addition to the high cost of TSVs, they also have low mechanical strength. Because silicon interposers are thinned to form TSVs, they are brittle and prone to cracking and breakage. As silicon interposer packages become larger and are attached to printed circuit boards, the mismatch in coefficient of thermal expansion (CTE) between the silicon interposer and the organic substrate can cause physical cracking or breakage of the bonding bumps. TSVs can also warp, which can hinder manufacturing or assembly and can cause phenomena such as ball grid array (BGA) non-wetting.

[0009] Through-glass vias (TGVs), and to a lesser extent through-silicon vias (TSVs), suffer from a lack of ability to dissipate heat. The glass substrate of a TGV is an insulator, and therefore can only allow heat to escape through the top of the package. TGVs are also inflexible, thus limiting their use in certain applications.

[0010] System-on-Foil, detailed in PCT / US20 / 54245 "System-on-Foil Devices," which is incorporated herein by reference, is a system-level advanced packaging technology designed to address the shortcomings of current 2.5 / 3D packaging architectures. Within System-on-Foil, and all advanced packages, there is a substrate with multiple wiring layers that allows surface-mounted electronic components to communicate with each other.

[0011] However, a problem with using metal substrates for HI is that larger pads and solder bumps attached to wiring layers on the metal substrate can capacitively couple to the substrate, thus limiting the high frequency bandwidth.

[0012] Therefore, there is a need for circuit packages and circuit boards having substrate vias formed in system-on-foil devices.

[0013] There is also a need for a system-on-foil device with through-substrate vias that allow power, ground, and signals to pass between electronic components inside and outside the package.

[0014] There is also a need for a system-on-foil device that allows signals, power, and ground to be routed through the substrate.

[0015] There is also a need for a system-on-foil device having a common metal shell as a substrate and one or more through-via metal pins made from the same metal as the common metal shell.

[0016] There is also a need for a system-on-foil device structure having insulating dielectric through-vias that eliminate capacitive coupling between electronic devices located on either side of the device structure.

[0017] There is also a need for a system-on-foil manufacturing process that eliminates capacitive coupling during the formation of through metal vias (TMVs).

[0018] There is also a need for system-on-a-foil devices that offer lower latency.

[0019] There is also a need for system-on-foil devices that increase bandwidth and data rates (GHz, Gbps).

[0020] Lower power consumption (pJ / bit), higher routing density (lanes per mm / layer), and higher IO density (IO / mm 2 There is also a need for a system-on-foil device that provides

[0021] There is also a need for system-on-foil devices that include interconnect layers of various thicknesses and widths to support high-speed digital, low-speed digital, RF, power, and current densities.

[0022] There is also a need for a system-on-foil device that provides a low impedance power delivery network with a patterned metal core power / ground coplane.

[0023] There is also a need for a system-on-foil device that provides low substrate warpage / high Young's modulus substrates.

[0024] There is also a need for a system-on-foil device that provides rapid heat removal and therefore high thermal conductivity.

[0025] There is also a need for a system-on-foil device that provides a thin dielectric layer between ground and power planes for a power distribution network (PDN).

[0026] There is also a need for a system-on-foil device that provides 50 ohm impedance matching, which cannot be met by deposition methods. [Summary of the inventive concept]

[0027] The present general inventive concept provides semiconductor substrate and / or interposer packaging having through metal vias, and methods of making same. More specifically, but not by way of limitation, the inventive concept relates to semiconductor substrate and / or interposer packaging having through metal vias formed of a metallic material and surrounded by a dielectric material, and methods of making same.

[0028] Additional features and advantages of the present general inventive concepts will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the general inventive concepts.

[0029] The foregoing and / or other features and advantages of the present general inventive concept can be achieved by providing a metal core substrate-based package interconnect system (PIS) comprising: a metal core substrate having intra-metal substrate structures patterned therein using the same metal body as the metal core substrate and a dielectric material patterned therein to separate each of the intra-metal substrate structures from the metal core substrate; and interconnect structures bonded to each of a first surface of the metal core substrate and a second surface of the metal core substrate, each interconnect structure comprising an insulating material patterned with a plurality of metal interconnect structures formed therethrough, at least one of the metal interconnect structures from one interconnect structure being electronically bonded to the at least one intra-metal substrate structure at the first surface of the metal core substrate and at least two metal interconnect structures from the other interconnect structures being electronically bonded to the at least one intra-metal substrate structure at the second surface of the metal core substrate to form at least one package interconnect component (PIC).

[0030] In an exemplary embodiment, at least one package interconnect component is a differential PIC.

[0031] In another exemplary embodiment, at least one package interconnect component is a signal array PIC.

[0032] In yet another exemplary embodiment, at least one of the package interconnect components is a multi-distribution PIC for one of a signal line, a power line, or a ground line.

[0033] In yet another exemplary embodiment, at least one package interconnect component is an optical waveguide PIC.

[0034] In yet another exemplary embodiment, at least one package interconnect component is an array PIC.

[0035] In yet another exemplary embodiment, the insulating material is an inorganic or organic dielectric material.

[0036] In yet another exemplary embodiment, the metal core substrate-based package interconnect system may further include a second metal core substrate-based package interconnect system connected to its top surface by bonding its top surface interconnect structure to the back surface interconnect structure of the second metal core substrate-based package interconnect system such that the metal interconnect structure from the metal core substrate-based package interconnect system is electronically connected to the interconnect structure of the second metal core substrate-based package interconnect system.

[0037] In yet another exemplary embodiment, the metal core substrate-based package interconnect system may further include a third metal core substrate-based package interconnect system connected to the top surface of the second metal core substrate-based package interconnect system via contacts configured to connect metal interconnect structures of the second metal core substrate-based package interconnect system with metal interconnect structures of the third metal core substrate-based package interconnect system.

[0038] In yet another exemplary embodiment, the metal core substrate-based package interconnect system may further include an electronic component attached to the top surface of the third metal core substrate-based package interconnect system via contacts connected to metal interconnect structures patterned therein, wherein the electronic component receives signals via the intra-metal substrate structures patterned in the metal core substrate-based package interconnect system, the second intra-metal substrate structures patterned in the metal core substrate-based package interconnect system, and the third intra-metal substrate structures patterned in the metal core substrate-based package interconnect system.

[0039] In yet another exemplary embodiment, the metal core substrate-based package interconnect system may further include contacts connected to at least two exposed metal interconnect structures patterned within an interconnect structure bonded to the second surface of the metal core substrate, and components attached to the two contacts for receiving signals that pass through the at least two metal intra-substrate structures before passing through the at least two exposed metal interconnect structures.

[0040] The foregoing and / or other features and advantages of the present general inventive concept can also be achieved by providing a metal core substrate-based package interconnect system (PIS) comprising: a first metal core substrate including a metal core, metal intra-substrate structures patterned therein using the same metal body as the metal core, and dielectric intra-substrate structures patterned therein to separate each of the metal intra-substrate structures from the metal core; and a second metal core substrate including a metal core, metal intra-substrate structures patterned therein using the same metal body as the metal core, and dielectric intra-substrate structures patterned therein to separate each of the metal intra-substrate structures from the metal core, wherein at least a portion of a top surface of the second metal core substrate is bonded to at least a portion of a backside surface of the first metal core substrate such that at least one of the intra-metal substrate structures of the first and second metal core substrates are aligned to form at least one single metal intra-substrate structure and at least one single dielectric intra-substrate structure.

[0041] In an exemplary embodiment, the metal core substrate-based package interconnect system (PIS) may further include a cavity formed in at least one of the top surface of the second metal core substrate and the backside surface of the first metal core substrate, and a component embedded in the cavity, the component electrically or optically connected to at least one of the metallic or dielectric intra-substrate structures patterned through one of the first or second metal core substrates.

[0042] In another exemplary embodiment, the metal core substrate-based package interconnect system (PIS) may further include a third metal core substrate having at least a portion of its top surface bonded to at least a portion of the back side of the second metal core substrate such that at least one intra-metal substrate structure of the third and second metal core substrates align to form at least one single intra-metal substrate structure, and a component receives signals via the intra-metal substrate structure connected between the third and second metal core substrates.

[0043] In yet another exemplary embodiment, the metal core substrate-based package interconnect system (PIS) may further include an interconnect structure deposited on the backside of the third metal core substrate and including at least one dielectric interconnect structure and at least one metal interconnect structure patterned therethrough and aligned with and in contact with at least one respective intra-substrate dielectric structure and metallic intra-substrate structure of the third metal core substrate, wherein components receive signals from the second and third metal core substrates through the metallic intra-substrate structures connected to each other and through the at least one metal interconnect structure patterned through the interconnect structure.

[0044] In yet another exemplary embodiment, the metal core substrate-based package interconnect system (PIS) may further include an interconnect structure deposited on at least one of the top surface of the first metal core substrate and the back surface of the second metal core substrate, wherein the at least one interconnect structure includes at least one dielectric interconnect structure and at least one metallic interconnect structure patterned therethrough and in alignment with and contact with at least one corresponding dielectric intra-substrate structure and metallic intra-substrate structure of the metal core substrates on which the interconnect structure is deposited.

[0045] In another exemplary embodiment, the metal core substrate-based package interconnect system (PIS) may further include contacts connected to at least two exposed metal interconnect structures patterned within the interconnect structure bonded to the top surface of the first metal core substrate, and components attached to the two contacts for receiving signals that pass through the first metal core substrate and the second metal core substrate before passing through the at least two exposed metal interconnect structures. [Brief explanation of the drawings]

[0046] These and / or other features and advantages of the inventive concept will become apparent and more readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings.

[0047] [Figure 1] 1 illustrates a metal core substrate based package interconnect system 100 according to an exemplary embodiment of the inventive concept.

[0048] [Figure 2] 2 illustrates a metal core substrate-based package interconnect system 200 according to an exemplary embodiment of the inventive concept.

[0049] [Figure 3] FIG. 3 illustrates a metal core substrate-based package interconnect system 300 according to another exemplary embodiment of the package system components.

[0050] [Figure 4] FIG. 4 illustrates a metal core substrate-based package interconnect system 400 according to another exemplary embodiment of the inventive concept.

[0051] [Figure 5] FIG. 5 illustrates a metal core substrate-based package interconnect system 500 in accordance with yet another exemplary embodiment of the inventive concept.

[0052] [Figure 6] FIG. 6 illustrates a metal core substrate-based package interconnect system 600 in accordance with yet another exemplary embodiment of the inventive concept.

[0053] [Figure 7] FIG. 7 illustrates a metal core substrate-based package interconnect system 700 in accordance with yet another exemplary embodiment of the inventive concept.

[0054] [Figure 8] FIG. 8 illustrates a metal core substrate-based package interconnect system 800 in accordance with yet another exemplary embodiment of the inventive concept.

[0055] [Figure 9] FIG. 9 illustrates a metal core substrate-based package interconnect system 900 in accordance with yet another exemplary embodiment of the inventive concept.

[0056] [Figure 10] FIG. 10 illustrates a metal core substrate-based package interconnect system 1000 according to an exemplary embodiment of the inventive concept.

[0057] [Figure 11] FIG. 11 illustrates a metal core substrate-based package interconnect system 1100 according to yet another exemplary embodiment of the inventive concept.

[0058] [Figure 12A] FIG. 12 illustrates a metal core substrate-based package interconnect system 1200A according to yet another exemplary embodiment of the inventive concept.

[0059] [Figure 12B] FIG. 12 illustrates a metal core substrate-based package interconnect system 1200B according to yet another exemplary embodiment of the inventive concept.

[0060] [Figure 13] FIG. 13 illustrates a metal core substrate based package interconnect system 1300 according to yet another exemplary embodiment of the inventive concept.

[0061] [Figure 14] FIG. 10 illustrates a multi-metal core substrate-based package interconnect system in accordance with yet another exemplary embodiment of the inventive concept.

[0062] [Figure 15] FIG. 10 illustrates a multi-metal core substrate-based package interconnect system in accordance with yet another exemplary embodiment of the inventive concept.

[0063] The drawings illustrate some exemplary embodiments of the inventive concept and should not be considered as limiting its scope, as the overall inventive concept may admit of other equally effective embodiments. The elements and features shown in the drawings are to scale and are intended to clearly illustrate the principles of exemplary embodiments of the inventive concept. In the drawings, reference numerals indicate the same or corresponding, but not necessarily identical, elements throughout the several views. Detailed Description of the Preferred Embodiments

[0064] Reference will now be made in detail to embodiments of the present general inventive concept, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. Hereinafter, embodiments will be described with reference to the drawings to explain the general concept of the present invention. Furthermore, while describing the present general inventive concept, detailed descriptions of related well-known functions or configurations that may obscure the point of the present general inventive concept will be omitted.

[0065] Although the terms "first" and "second" are used herein to describe various elements, it will be understood that these elements are not to be limited by these terms. These terms are used only to distinguish one element from another. Thus, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the teachings of the present disclosure.

[0066] A phrase such as "at least one of," when preceding a list of elements, modifies the entire list of elements, and does not modify any individual element of the list.

[0067] All terms, including descriptive or technical terms, used herein should be interpreted as having meanings that are clear to those skilled in the art. However, the meaning of a term may differ depending on the inventor's intention, legal precedents, the emergence of new technology, etc. In addition, some terms may be arbitrarily selected by the inventor, and in such cases, the meaning of the selected term will be explained in detail in the detailed description of this specification. Therefore, the terms used herein should be defined based on the commonly defined meaning of the term along with the explanation of this entire specification.

[0068] One or more exemplary embodiments of the present general inventive concept are described in detail below with reference to the accompanying drawings.

[0069] Exemplary embodiments of the present general inventive concept are directed to metal core substrate-based package interconnect systems fabricated with various electronic, optical, and other types of components therein, including through metal vias (TMVs), e.g., used to transmit signals, power, or ground through electrically isolated pins; dielectric insulated vias (DIVs), e.g., used to reduce or eliminate capacitive coupling between components / bumps and the metal substrate; power and ground planes, e.g., used to route power and ground by patterning planes within the metal substrate; passive components, e.g., used to fabricate components such as capacitors, resistors, inductors, and other components by using a metal core for at least a portion of each component; and interconnects that support high current density or impedance matching. dielectric cutouts for redistribution layers (RDLs) used to provide additional dielectric thickness beyond that in interconnect layers for target impedance designs; photonic vias and waveguides used to fabricate waveguides in metal core dielectrics; heat spreader channels used to increase convective or conductive heat dissipation by patterning cavities in metal substrates and leaving them empty or filling them with high thermal conductivity materials; microfluidic channels and heat pipes used to remove heat from metal substrates by patterning cavities in metal substrates for microfluidic cooling; and antennas in packages made of the same body as the metal core.

[0070] FIG. 1 illustrates a metal core substrate-based package interconnect system 100 according to an exemplary embodiment of the inventive concept. Referring to FIG. 1, the metal core substrate-based package interconnect system 100 can include a metal core substrate 102. The metal core substrate 102 can be formed from a material selected from the group consisting of a) molybdenum, b) iron, c) titanium, d) chromium, e) tantalum, f) tungsten, g) copper, h) nickel, i) vanadium, j) aluminum, k) cobalt, or any alloy consisting of a) through k). The metal core substrate 102 can be formed by laser ablating the top and back surfaces of a metal core 102a and etching trenches and pockets in the top and back surfaces of the metal core 102a. The etched trenches are preferably formed to form shaped metal pins surrounded by the trenches. The trenches and pockets can then be filled with a dielectric material 102c. Similar processing can be performed on the back side of the metal core 102a to form a metal substrate structure 102b and a dielectric substrate structure 102c, as described in U.S. Patent Application Serial No. 18 / 446,841, filed August 9, 2023, by the assignee of the present patent application.

[0071] After the metal core substrate 102 is fabricated with the intra-metallic and intra-dielectric substrate structures 102b and 102c patterned therein, an interconnect structure 104 can be fabricated on one or both of the top and back surfaces of the metal core substrate 102. The interconnect structure 104 can be formed to include differently shaped dielectric and metal interconnect structures (104a, 104b) that can be aligned with different ones of the intra-metallic and intra-dielectric substrate structures 102b and 102c patterned within the metal core 102a to form continuous transmission lines and, more importantly, various different types of electronic, optical, liquid-based, etc., circuit components within the substrate-based package interconnect system 100, according to various exemplary embodiments of the inventive concepts, as described in detail below with reference to FIGS.

[0072] FIG. 2 illustrates a metal core substrate-based package interconnect system 200 according to an exemplary embodiment of the inventive concept. Referring to FIG. 2, the metal core substrate-based package interconnect system 200 can include a metal core substrate 202, which can be fabricated by a process similar to that for the metal core substrate 102 described with reference to FIG. 1. The metal core substrate 202 can include one or more metal intra-substrate structures 202b formed as straight lines from its top surface to its back surface, each separated by a dielectric intra-substrate structure 202c, which can separate the metal intra-substrate structures 202b from one another, similar to the metal core 102a. Interconnect structures 204, including patterned insulating material 204a and one or more metal interconnect lines 204b, can be fabricated on both the top and back surfaces of the metal core substrate 202. It should be noted that the interconnect structures 204 can be fabricated using inorganic or organic dielectric materials.

[0073] Due to its mechanical, temperature, and chemical compatibility with semiconductor processes, metal core substrates can be made into wafer format for patterning high-fidelity interconnect layers using lithographic patterning processes. As a result, lines and vias within the interconnect structure can be patterned more densely and with finer resolution than is possible with non-wafer patterning techniques. Higher density interconnects allow for an overall reduction in the number of interconnect layers required.

[0074] Additionally, many more vias can be stacked using wafer-based interconnect patterning processes than in traditional substrate build-up processes. Thus, as shown at 210, 220, and 230, the combination of a reduced number of interconnect layers and an increased number of stacked vias can allow interconnects to extend completely vertically through the package, improving performance. This is often not possible with traditional build-up substrates, which require interconnects to be "staggered" side-to-side with another set of stacked vias before continuing down through the substrate core.

[0075] Furthermore, by using wafer-based interconnect patterning techniques, interconnect line roughness can be significantly reduced compared to non-wafer processes, improving transmission line performance.

[0076] Due to the mechanical rigidity of the metal substrate, layer balancing between the top and backside is not required to the same extent as with organic substrate packaging technology.

[0077] In this exemplary embodiment, interconnect structures 204 are deposited on both the top and backside of metal core substrate 202 such that patterned insulating material (also referred to herein as dielectric interconnect structures) 204a and multiple metal interconnect structures 204b are fabricated on the top and bottom sides of metal core substrate 202 to align with dielectric intra-substrate structures 202c and metal intra-substrate structures 202b of metal core substrate 202. More specifically, in this configuration, single-ended electronic transmission line 210 is one example of a package interconnect component that may be formed through metal core substrate-based package interconnect system 200. The single-ended electronic transmission line 210 can start from one contact “C” located on either the top or bottom of the metal core substrate-based package interconnect system 200, connect with a first interconnect structure metal 204b within a first of the interconnect structures 204, traverse the interconnect structure 204, connect with a coaxial metal through via (TMV) 202b, connect with a second metal interconnect structure 204b within the second interconnect structure 204, traverse the second interconnect structure 204, and then terminate at another contact “C” located on the opposite side of the metal core substrate-based package interconnect system 200.

[0078] Coaxial through-metal vias can be formed in the substrate and designed for impedance matching to support high frequency single-ended electronic transmission lines 210. By using the substrate metal as both the inner and outer conductors, these can be formed at higher densities than possible with other substrate technologies. This, when coupled with high density wafer-based interconnects, further supports a reduction in overall package size and layer count.

[0079] Additionally, coaxial through-metal vias provide more area for signal and return currents to flow, especially at high frequencies, improving insertion and return loss compared to non-coaxial vias such as through-silicon, through-glass, and through-package vias. Also, because coaxial through-metal vias are shielded from adjacent vias by the grounded metal core, there is no crosstalk between coaxial through-metal vias, unlike through-silicon, through-glass, and through-package vias.

[0080] Furthermore, differential electronic transmission line 220 is another exemplary embodiment of a package system component that may be formed through metal core substrate-based package interconnect system 200. Differential electronic transmission line 220 may be configured as a combination of signal, power, and / or ground lines. Differential electronic transmission line 220 may start at one of contacts C located on either the top or bottom of metal core substrate-based package interconnect system 200, connect with interconnect structure metal 204b formed on a first one of interconnect structures 204, traverse interconnect structure 204, connect with differential coaxial TMV 202b, traverse differential coaxial TMV 204b, connect with interconnect structure metal 204b formed on a second one of interconnect structures 204, traverse second interconnect structure 204, and terminate at contact C located at the opposite end of metal core substrate-based package interconnect system 200.

[0081] As a result of using substrate metal as both the inner and outer conductors, and therefore supporting higher density differential electronic transmission lines 220, impedance-matching differential through vias can be formed in the substrate at higher densities than competing substrate technologies. This increased density, when coupled with wafer-based interconnects, allows for an overall reduction in package size.

[0082] Furthermore, signal array 230 is another exemplary embodiment of a package system component that may be formed through metal core substrate-based package interconnect system 200. Signal array 230 may start from a plurality of contacts C disposed at one end of metal core substrate-based package interconnect system 200, connect with interconnect structure metal 204b, traverse interconnect structure 204, connect with TMV 202b, traverse metal core substrate 202, connect with interconnect structure metal 204b formed on a second one of interconnect structures 204, traverse interconnect structure 204, and terminate at a plurality of contacts disposed on the opposite side of metal core substrate-based package interconnect system 200.

[0083] The signal array 230 can be used to maximize routing density in a metal core substrate based package interconnect system, allowing for an overall reduction in package size.

[0084] FIG. 3 illustrates a metal core substrate-based package interconnect system 300 according to another exemplary embodiment of a package system component. Referring to FIG. 3 , the metal core substrate-based package interconnect system 300 can include interconnect structures 304 deposited on both the top and back surfaces of the metal core substrate 302, such that a patterned dielectric interconnect structure 304a and a plurality of metal interconnect structures 304b are fabricated on the top and bottom surfaces of the metal core substrate 302 and align with respective ones of the dielectric intra-substrate structures 302c and metal intra-substrate structures 302b of the metal core substrate 302. More specifically, in this configuration, a decoupling circuit 310 is an example of a package interconnect component that can be formed through the metal core substrate-based package interconnect system 300. The decoupling circuit 310 can include a metal interconnect structure 304b formed in a first dielectric interconnect structure 304 fabricated on the top or back surface of the metal core substrate 302. The first dielectric interconnect structure 304 can include a metal interconnect structure 304b, a contact C disposed on the metal interconnect structure 304b, a dielectric interconnect structure 304a formed in the dielectric interconnect structure 304 below the metal interconnect structure 304b, a dielectric intra-substrate structure 302c formed in the metal core substrate 302, and a second dielectric interconnect structure 304 fabricated on the other of the top or back surface of the metal core substrate 302 and configured to mirror the first dielectric interconnect structure 304 with the contact C disposed on the metal interconnect structure 304b formed in the second dielectric interconnect structure 304. The decoupling package interconnect component 310 is formed to reduce capacitive coupling between the contact C (and any associated interconnect metal) and the metal core 302a.

[0085] The decoupling circuit 310 reduces the parasitic capacitance between interconnect structures, such as contacts, and the metal substrate, thereby improving the electronic performance of the package interconnect system for the metal substrate.

[0086] Furthermore, an isolation circuit 320, including a signal line, a power line, or a ground line, is another exemplary embodiment of a package system component that can be formed through the metal core substrate-based package interconnect system 300. The isolation circuit 320 can include a pair of metal interconnect structures 304b extending through the first interconnect structure 304 and connecting with a metal substrate structure 302b, and another metal interconnect structure 304b extending from the metal substrate structure 302b through the second interconnect structure 304 and can have another contact located at its opposite end. The isolation circuit 320 can start at at least one contact C, connect with the interconnect structure metal 304b, pass through the interconnect structure 304, connect with and pass through the substrate plane 302b, connect with at least one other interconnect structure metal 304b of the interconnect structure 304, and pass through the interconnect structure 304, terminating at the at least one contact C. This isolation circuit 320 type interconnect system component can provide multi-port connections from one side of a packaging system to another.

[0087] The multi-distribution signal 320, power PIC, or ground PIC allows for routing of signals, power, or ground within the substrate itself, e.g., distributing power to multiple endpoints. This provides a low-resistivity, isolated conductive path within the substrate that would otherwise have to occur within the interconnect structure layers, thus reducing the required package size and number of interconnect structure layers.

[0088] Additionally, substrate interconnect electronic transmission line 330 is another exemplary embodiment of a package system component that may be formed through metal core substrate-based package interconnect system 300. Substrate interconnect electronic transmission line 330 may include a metal interconnect structure 304b extending through first interconnect structure 304 and connecting with an intra-substrate waveguide 302b formed in metal core substrate 302, and another metal interconnect structure 304b extending from the intra-substrate waveguide 302b through second interconnect structure 304. Substrate interconnect electronic transmission line 330 may start at contact point C, connect with interconnect structure metal 304b, pass through interconnect structure 304, connect with and pass through intra-substrate waveguide 302b, connect with other interconnect structure metal 304b in second interconnect structure 304, pass through interconnect structure 304 and terminate at another contact point C.

[0089] The substrate interconnect electronic transmission line 330 allows for routing of signals within the metal substrate that would otherwise have to occur within an interconnect structure layer, thus reducing the required package size and number of interconnect structure layers. Additionally, the substrate interconnect transmission line 330 can be impedance matched based on its geometry to support high frequency signal transmission.

[0090] 4 illustrates a metal core substrate-based package interconnect system 400 in accordance with another illustrative embodiment of the inventive concept. Referring to FIG. 4, the metal core substrate-based package interconnect system 400 can include interconnect structures 404 deposited on both the top and backside of a metal core substrate 402, allowing patterned dielectric interconnect structures 404a and metallic interconnect structures 404b to be fabricated on the top and backside of the metal core substrate 402 to form package interconnect components, as described in more detail below.

[0091] In the configuration of FIG. 4 , a passive power line 410 is an exemplary embodiment of a package interconnect component that can be formed through the metal core substrate-based package interconnect system 400. The passive power line 410 can include a dielectric intra-substrate structure 404a, a metal interconnect structure 404b, and a metal core 402 portion of the metal core substrate 402. The passive power line 410 starts from a contact C disposed on the metal interconnect structure 404b and passes through the metal interconnect structure 404b (formed as an electrode). The metal interconnect structure 404b can be disposed above or below the grounded metal core 402a, with the dielectric interconnect structure 404a separating the two metal surfaces of the metal interconnect structure 404b and the grounded metal core 402a. The passive power line 410 allows capacitance to be formed between the metal substrate and the interconnect structures above and below, which can be used to achieve electronic performance.

[0092] Alternatively, as shown by reference numeral 420, a power line can incorporate a partially insulating package interconnect component to supply a different power to the metal core 402 and instead use a ground supply from contact C located at the end of the metal interconnect structure 404b formed through the second interconnect structure 402. The power line 420 allows a capacitance to be formed between the metal substrate and the interconnect structure to act as a decoupling capacitor between ground and the supply voltage level.

[0093] Additionally, an anti-pad 430 acting as a signal, power, or ground line is another exemplary package embodiment of a package system component that can be formed to penetrate the metal core substrate-based package interconnect system 300. In this exemplary package interconnect component, the anti-pad 430 can include a metal interconnect structure 404b, a metal substrate structure 402b, and another metal substrate structure 402b, with the anti-pad patterned on the surface / side of one or both metal cores 402a to reduce capacitive coupling between one or more contacts C and the metal core 402. Here, the anti-pad starts at one contact C, connects with the metal interconnect structure 404b of one interconnect structure 404, passes through the interconnect structure 404, connects with the TMV 402b having the anti-pad patterned on the surface / side of the metal core 402a, passes through the TMV 402b, connects with the other of the metal substrate structure 402b, passes through the other interconnect structure 404, and terminates at contact C.

[0094] The anti-pad 430 helps reduce the capacitance between the metal substrate and structures above or below the interconnect system, such as solder balls, bumps, or microbumps.

[0095] 5 illustrates a metal core substrate-based package interconnect system 500 in accordance with yet another illustrative embodiment of the inventive concept. Referring to FIG. 5, the metal core substrate-based package interconnect system 500 may include an interconnect structure 504 deposited on a top surface of a metal core substrate 502, such that patterned dielectric interconnect structures 504a and metallic interconnect structures 504b can be fabricated on the top surface of the metal core substrate 502 to form package interconnect components, as described in more detail below.

[0096] 5 , substrate antenna 510 is an exemplary embodiment of a package interconnect component that may be formed through metal core substrate-based package interconnect system 500. Metal core substrate 502 includes dielectric intra-substrate structures 504a patterned in a stair-like formation, and stepped metal intra-substrate structures 504b may be patterned through metal core substrate 502. Metal interconnect structures 504b extend through interconnect structure 504 to connect to predetermined ones of metal intra-substrate structures 504b to form antenna 510.

[0097] Here, the transmission line starts from junction C, connects to metal interconnect structure 504b, passes through interconnect structure 504, connects to TMV 502b patterned on metal core 502a of metal core substrate 502, and radiates electromagnetic energy from TMV 502b outward. This substrate antenna 510 can also operate in the reverse direction as a receiver.

[0098] The substrate antenna 510 allows for antenna functionality within the substrate itself that would otherwise have to be formed into the interconnect structure or surface mounted. Embedding the antenna within the substrate itself can provide both performance and package size advantages.

[0099] Furthermore, the substrate array 520 is another exemplary embodiment of a package interconnect component that can be formed through the metal core substrate-based package interconnect system 500. In this exemplary package interconnect component, a pair of electronic transmission lines originates from two or more contacts C connected to the metal interconnect structure 504b, crosses the interconnect structure 504, and connects to the TMV array (a pair of metal intra-substrate structures 502b), radiating electromagnetic energy outward from the TMV array. The substrate array 520 can also operate in the reverse direction as a receiver. Furthermore, the antennas 502b in the array may or may not have metal between them. As shown, there is a metal structure 502b between them.

[0100] The substrate array 520 allows antenna functionality within the substrate itself, which would otherwise have to be formed into the interconnect structure or surface mounted. Embedding the antenna array within the substrate itself can offer both performance and package size advantages.

[0101]

[0023] Figure 6 illustrates a metal core substrate-based package interconnect system 600 in accordance with yet another illustrative embodiment of the inventive concept. Referring to Figure 6, the metal core substrate-based package interconnect system 600 may include interconnect structures 604 deposited on the top and backside of a metal core substrate 602, such that patterned dielectric interconnect structures 604a and metallic interconnect structures 604b may be fabricated on the top side of the metal core substrate 602, and optionally on the backside of the metal core substrate 602, to form package interconnect components, as described in more detail below.

[0102] 6, substrate reference portion 610 is an exemplary embodiment of a package interconnect component that may be formed through metal core substrate-based package interconnect system 600. Here, metal interconnect structure 604b is fabricated to be isolated within dielectric interconnect structure 604a of first interconnect structure 604, and a dielectric isolation pocket (DIP) 602c within substrate 602 is patterned in metal core 602a of metal core substrate 602. This configuration results in the formation of a transmission line that emanates from contact C placed in contact with metal interconnect structure 604b, passes through interconnect structure 604 located above DIP 602c using metal core 602a as a ground reference, and terminates at another contact C connected to the same metal interconnect structure 604b.

[0103] The substrate reference 610 can be used to specifically adjust the capacitance and impedance of the interconnect structure up or down by varying the depth and other geometry of the substrate reference relative to the metal substrate surface.

[0104] Alternatively, a different substrate reference portion 620 can be formed having a metal interconnect structure 604b fabricated in the first interconnect structure 604, an intra-substrate dielectric isolation pocket (DIP) 602c patterned in the metal core 602a of the metal core substrate 602, a TMV 602b surrounded by the DIP 602c, and a dielectric interconnect structure 604a extending through the second interconnect structure 604. Here, a transmission line is formed that emanates from a contact C disposed on the metal interconnect structure 604b of the first or second interconnect structure 604, passes through the metal interconnect structure 604b located above or below the DIP 602c, passes through the TMV 602b, passes through the metal interconnect structure 604b formed on the other of the metal interconnect structures 604b located above or below the DIP 602c, and terminates at the second contact C.

[0105] This type of substrate reference 620 allows for tuning of the capacitance and impedance of the interconnect structure passing through the substrate by varying the depth and other geometry of the substrate reference relative to the metal substrate surface.

[0106] 7 illustrates a metal core substrate-based package interconnect system 700 in accordance with yet another illustrative embodiment of the inventive concept. Referring to FIG. 7, the metal core substrate-based package interconnect system 700 may include interconnect structures 704 deposited on the top and backside of a metal core substrate 702, such that patterned dielectric interconnect structures 704a and metallic interconnect structures 704b may be fabricated on the top side of the metal core substrate 702, and optionally on the backside of the metal core substrate 702, to form package interconnect components, as described in more detail below.

[0107] In the configuration of Figure 7, photonic optical waveguide 710 is an exemplary embodiment of a package interconnect component that can be formed through metal core substrate-based package interconnect system 700. Here, a first metal interconnect structure 704b can be fabricated to be isolated within first interconnect structure 704. Second and third metal interconnect structures 704b can be fabricated to extend through interconnect structure 704 and contact metal core 702a of metal core substrate 702, with second and third metal interconnect structures 704b disposed adjacent to each side of first metal interconnect structure 704b, respectively. Here, one contact C is disposed in contact with both first metal interconnect structure 704b and second metal interconnect structure 704b, and a second contact is disposed in contact with both first metal interconnect structure 704b and third metal interconnect structure 704b. In this configuration, an optical waveguide is formed that launches from one contact C, connects with the interconnect system dielectric 704a surrounded by the metal interconnect structure 704b, passes through the interconnect structure 704 while always being surrounded by either the metal core metal 702a and / or the metal interconnect structure 704b, and terminates at the other contact C.

[0108] Photonic optical waveguide 710 in this configuration allows for transmission of photonic signals within interconnect dielectric material encased within interconnect metal.

[0109] Furthermore, the photonic optical waveguide 720 is another exemplary embodiment of a package interconnect component that can be formed through the metal core substrate-based package interconnect system 700. Here, a dielectric intra-substrate structure 702c is formed through the metal core substrate 702. A first metal interconnect structure 704b can be fabricated through the first interconnect structure 704 to contact the metal core 702a on one side of the dielectric intra-substrate structure 702c of the metal core substrate 702, and a second metal interconnect structure 704b can be fabricated through the first interconnect structure 704 to contact the metal core 702a on the opposite side of the dielectric intra-substrate structure 702c of the metal core substrate 702. A contact C can be disposed on the surface of the interconnect structure 704 between the first metal interconnect structure 704b and the second metal interconnect structure 704b. A pair of metal interconnect structures 704b extend through a second interconnect structure 704 disposed on the backside of the metal core substrate 702, with a first metal interconnect structure of the pair 704b contacting the metal core 702a on one side of the dielectric intra-substrate structure 702c of the metal core substrate 702 and a second metal interconnect structure of the pair 704b contacting the metal core 702a on the other side of the dielectric intra-substrate structure 702c of the metal core substrate 702. A contact C is located on the surface of the second interconnect structure 704 between the pair of metal interconnect structures 704b. In this configuration, the photonic optical waveguide 720 can start at one contact C, connect with a dielectric interconnect structure 704a surrounded by two metal interconnect structures 704b, pass through the interconnect structure 704 (always surrounded by either the metal-core metal 702a and / or the metal interconnect structure 704b), connect with and pass through the dielectric intra-substrate structure 702c, connect with the dielectric interconnect structure 704a surrounded by a pair of metal interconnect structures 704b within the second interconnect structure 704, pass through the second interconnect structure 704, and terminate at the other contact C.

[0110] The photonic optical waveguide 720 can also be configured to transmit a photonic signal within the interconnect structure dielectric material, which then travels through the substrate to the photonic optical waveguide on the opposite side, thus enabling optical transmission through the substrate.

[0111] 8 illustrates a metal core substrate-based package interconnect system 800 in accordance with yet another illustrative embodiment of the inventive concept. Referring to FIG. 8, the metal core substrate-based package interconnect system 800 may include interconnect structures 804 deposited on the top and backside of a metal core substrate 802, such that patterned dielectric interconnect structures 804a and metallic interconnect structures 804b may be fabricated on the top side of the metal core substrate 802, and optionally on the backside of the metal core substrate 802, to form package interconnect components, as described in more detail below.

[0112] In the configuration of FIG. 8 , a photonic optical waveguide 810 is an exemplary embodiment of a package interconnect component that can be formed through a metal core substrate-based package interconnect system 800. Here, the metal core substrate 802 can have a dielectric pocket (DIP) 802c fabricated on its top surface. A U-shaped metal interconnect structure 804b can be fabricated within the first interconnect structure 804 such that the bottom of the U-shaped metal interconnect structure 804b contacts the DIP 802c. Also formed within the interconnect structure 804 are two vertical metal interconnect structures 804b that extend from its top surface to the metal core 802a of the metal core substrate 802, one vertical metal interconnect structure 804b fabricated adjacent to each outer side of the U-shaped metal interconnect structure 804b. A contact C can be disposed between one vertical metal interconnect structure 804b and one end of the U-shaped metal interconnect structure 804b, and a second contact C can be disposed between the other vertical metal interconnect structure 804b and the opposite end of the first U-shaped metal interconnect structure 804b. In this configuration, the photonic optical waveguide 810 can start from one contact C, connect to the dielectric interconnect structure 804a surrounded by the two metal interconnect structures 804b, traverse the dielectric interconnect structure 804a, connect to the DIP 802c surrounded by the metal interconnect structure 804b, traverse the DIP 802c, connect to the dielectric interconnect structure 804a surrounded by the metal interconnect structure 804b, traverse it, and terminate at the other contact C.

[0113] Another configuration of photonic optical waveguide 810 allows for transmission of a photonic signal within the interconnect structure dielectric material and then traverses within the substrate without penetrating to another photonic optical waveguide on the same side.

[0114] Furthermore, photonic optical waveguide 820 is another exemplary embodiment of a package interconnect component that can be formed through metal core substrate-based package interconnect system 800. Here, a dielectric isolation pocket (DIP) 802c is formed to extend across the top surface of metal core 802a of metal core substrate 802 and then redirect the metal core 802a downward through a dielectric intra-substrate structure. A first metal interconnect structure 804b can be fabricated through first interconnect structure 804 to contact metal core 802a at one end of DIP 802c, and a second metal interconnect structure 804b can be fabricated through first interconnect structure 804 to contact DIP 802c, then redirect and extend along the entire top surface of DIP 802c until contacting metal core 802a at the opposite end of DIP 802c. A contact C can be disposed between the first metal interconnect structure 804b and the second metal interconnect structure 804b on the surface of the interconnect structure 804. A pair of metal interconnect structures 804b extends through the second interconnect structure 804 disposed on the backside of the metal core substrate 702, with a first metal interconnect structure of the pair 804b contacting the metal core 802a on one side of the DIP 802c and a second metal interconnect structure of the pair 804b contacting the metal core 802a on the opposite side of the DIP 802c. Another contact C can be disposed between the pair of metal interconnect structures 804b and on the surface of the second interconnect structure 804. In this configuration, the photonic optical waveguide 820 can start at one contact C, connect with a dielectric interconnect structure 804a surrounded by two metal interconnect structures 804b, traverse the interconnect structure 804, connect with and traverse the DIP 802c, connect with a dielectric interconnect structure 804a surrounded by a pair of metal interconnect structures 804b within the second interconnect structure 804, traverse the second interconnect structure 804, and terminate at the other contact C.

[0115] Another configuration of photonic optical waveguide 820 allows for transmission of a photonic signal within the interconnect structure dielectric material, which then travels within the substrate and then through the substrate to a photonic optical waveguide within the interconnect structure on the opposite side.

[0116] 9 illustrates a metal core substrate-based package interconnect system 900 in accordance with yet another illustrative embodiment of the inventive concepts. Referring to FIG. 9, the metal core substrate-based package interconnect system 900 may include interconnect structures 904 deposited on the top and backside of a metal core substrate 902, thereby allowing patterned dielectric interconnect structures 904a and metallic interconnect structures 904b to be fabricated on the top and backside of the metal core substrate 902 to form package interconnect components, as described in more detail below.

[0117] In the configuration of FIG. 9 , antenna 910 is an exemplary embodiment of a package interconnect component that can be formed through a metal core substrate-based package interconnect system 900. Here, metal core substrate 902 includes dielectric intra-substrate structure 902c and metal intra-substrate structure 902b patterned on metal core 902a. Metal interconnect structure 904b can be fabricated to extend through interconnect structure 904 deposited on the top surface of metal core substrate 902 and contact intra-metal substrate structure 902b. Another metal interconnect structure 904b can be fabricated to extend through interconnect structure 904 deposited on the backside of metal core substrate 902 and contact the same intra-metal substrate structure 902b. Contact C can be located at the end of metal interconnect structure 704b formed through interconnect structure 904 deposited on the top surface of metal core substrate 902. In this configuration, an electronic transmission line is formed that starts at contact point C, connects with metal interconnect structure 704b, passes through interconnect structure 904, connects with and passes through TMV 902c, connects with and passes through metal interconnect structure 704b formed through interconnect structure 904 deposited on the backside of metal core substrate 902, and radiates electromagnetic energy from antenna 910.

[0118] The antenna 910 may be formed in an interconnect structure above or below the dielectric intra-substrate structure, allowing communication to the antenna from the opposite side of the substrate.

[0119] Furthermore, a different type of antenna 920 is another exemplary embodiment of a package interconnect component that can be formed through the metal core substrate-based package interconnect system 900. Here, the metal core substrate 902 includes a dielectric intra-substrate structure 902c patterned through the metal core 902a, which includes a dielectric insolation pocket (DIP) patterned along the top surface of the metal core 902a and a metal intra-substrate structure 902b patterned through the dielectric intra-substrate structure 902c with the dielectric insolation pocket (DIP) disposed on one side of the metal intra-substrate structure 902b. The metal interconnect structure 904b can be fabricated to extend through the interconnect structure 904 deposited on the top surface of the metal core substrate 902 to the DIP 902c and then extend along the DIP 902c until it contacts the metal intra-substrate structure 902b. Another metal interconnect structure 904b can be fabricated to extend through an interconnect structure 904 deposited on the backside of the metal core substrate 902 and contact the same intra-metal substrate structure 902b. Contact C can be located at the end of the metal interconnect structure 904b formed through the interconnect structure 904 deposited on the top side of the metal core substrate 902.

[0120] In this configuration, an electronic transmission line can start at junction C, connect to and pass through metal interconnect structure 904b formed via interconnect structure 904 deposited on the top surface of metal core substrate 902 using metal core 902 as a ground reference, connect to TMV 902b, connect to and pass through metal interconnect structure 904b formed via interconnect structure 904 deposited on the back surface of metal core substrate 902, and radiate electromagnetic energy from antenna 920.

[0121] The antenna 920 may be formed within an interconnect structure that may be electronically connected via a dielectric intra-substrate structure to an interconnect structure on the other side that may route signals through the package.

[0122] Furthermore, array 930 is yet another exemplary embodiment of package interconnect components that can be formed through a metal core substrate-based package interconnect system 900. Here, metal core substrate 902 includes a dielectric intra-substrate structure 902c patterned through metal core 902a, a pair of metal intra-substrate structures 902b patterned through dielectric intra-substrate structure 902c, and a metal intra-substrate structure 902b disposed between and separated from the pair of metal intra-substrate structures 902b by the dielectric intra-substrate structure 902c. A pair of metal interconnect structures 904b can be fabricated to extend downward through interconnect structures 904 deposited on the top surface of metal core substrate 902 and contact corresponding ones of the metal intra-substrate structures 902b. Another pair of metal interconnect structures 904b can be formed to be patterned through interconnect structures 904 deposited on the back surface of metal core substrate 902 and contact corresponding ones of the metal intra-substrate structures 902b. Contacts C may be located at the end of each of the metal interconnect structures 904 b formed through interconnect structures 904 deposited on top of the metal core substrate 902 .

[0123] In this exemplary package interconnect component, a pair of electronic transmission lines originates from two or more contacts C connected to a metal interconnect structure 904b, traverses the interconnect structure 904, connects to and traverses the TMV array (a pair of metal intra-substrate structures 902b), and connects to a patterned interconnect system metal structure 904b via an interconnect structure 904 deposited on the backside of the metal core substrate 902, allowing electromagnetic energy to radiate outward from the TMV array. The array 930 can also be operated in the reverse direction as a receiver. Furthermore, the antennas 902b in the array may or may not have metal between them. As shown, there is a metal structure 502b between them.

[0124] The antenna array 930 can be formed in an interconnect structure above or below the dielectric substrate structure array, allowing communication to the array from the other side of the substrate. Substrate references, or cutouts in the metal substrate, can be used to adjust the capacitance of the antenna relative to the metal substrate.

[0125] FIG. 10 illustrates a metal core substrate-based package interconnect system 1000 in accordance with an illustrative embodiment of the inventive concept. Referring to FIG. 10, the metal core substrate-based package interconnect system 1000 can include a metal core substrate 1002 formed from a metal core 1002a. The metal core 1002a can be etched (i.e., laser ablated) on its top and back surfaces to form trenches and pockets on the top and back surfaces of the metal core 1002a. The etched trenches are preferably formed to form shaped metal pins surrounded by the trenches. The trenches and pockets can then be filled with a dielectric material 1002c. This same process can be performed on the back surface of the metal core 1002a, forming metal intra-substrate structures 1002b and dielectric intra-substrate structures 1002c therein, thereby electrically isolating one region of the metal core substrate 1002a from the other region of the metal core substrate 1002b.

[0126] Within the electrically isolated region of the metal core substrate 1002, the metal core 1002b can be etched (i.e., laser ablated) on its top and back surfaces to etch trenches in the top and back surfaces of the metal core 1002b. The etched trenches are preferably shaped to form shaped cavities 1002d that are left unfilled to function as ports for electrical or optical connectors.

[0127] An interconnect structure 1004 including a patterned dielectric interconnect structure 1004a and one or more metal interconnect structures 1004b can be fabricated on both the top and back surfaces of a metal core substrate 1002, where the patterned dielectric interconnect structure 1004a is fabricated on the top and bottom surfaces of the metal core substrate 1002 without including any cavities 1002d above or below, and a single metal interconnect structure 1004b is fabricated only on the top surface of the metal core substrate 1002. Here, as illustrated from top to bottom in the central image of Figure 10, metal interconnect structure 1004b traverses over dielectric interconnect structure 1004a deposited over metal core 1002a, then continues over dielectric interconnect structure 1004a deposited over metal core 1002c, then continues over dielectric interconnect structure 1004a deposited over metal core 1002b, and finally traverses dielectric interconnect structure 1004a to connect with metal core 1002b, thereby enabling signal transfer to and from the connector.

[0128] This embodiment allows for the creation of a mechanical connection interface or connector such that an external component or connector can be mechanically seated within a receiving cavity with electrical terminations formed within the metal core-based package interconnect system.

[0129] FIG. 11 illustrates a metal core substrate-based package interconnect system 1100 in accordance with an illustrative embodiment of the inventive concept. Referring to FIG. 11, the metal core substrate-based package interconnect system 1100 can include a metal core substrate 1102 formed from a metal core 1102a. The metal core 1102a can be etched (i.e., laser ablated) on its top and back surfaces to etch trenches and pockets into the top and back surfaces of the metal core 1102a. The etched trenches are preferably formed to form shaped metal pins surrounded by the trenches. The trenches and pockets can then be filled with a dielectric material 1102c. Similar processing can be performed on the back side of the metal core 1102a to form metal intra-substrate structures 1102b and dielectric intra-substrate structures 1102c.

[0130] The metal intra-substrate structures 1102b may be formed from the top surface to the back surface of the metal core substrate 1102, each separated by a dielectric intra-substrate structure 1102c, which may separate the metal intra-substrate structures 1102b from each other and from the metal core 1102a. Interconnect structures 1104 including patterned dielectric interconnect structures 1104a and one or more metal interconnect structures 1104b may be fabricated on both the top and back surfaces of the metal core substrate 1102. Here, some of the patterned dielectric interconnect structures 1104a and metal interconnect structures 1104b are fabricated on the top and bottom surfaces of the metal core substrate 1102 so as to align with some of the dielectric intra-substrate structures 1102c and metal intra-substrate structures 1102b of the metal core substrate 1102. Furthermore, the metal interconnect structures 1104b patterned on both the top and backside interconnect structures 1104 of the metal core substrate 1102 include contacts C connected to their exposed ends for receiving or transmitting signals to or from external devices. In the embodiment of Figure 11, the electronic component EC is connected to two adjacent contacts C connected to the exposed ends of the metal interconnect structures patterned in the interconnect structures 1104 formed on the top surface of the metal core substrate 1102 for receiving at least one of power, signals, or ground. These power, signals, or grounds can be received at contacts C connected to metal interconnect structures 1104b patterned in interconnect structures 1104 formed on the backside of metal core substrate 1102, travel through this metal interconnect structure 1104b, connect with attached intra-metal substrate structure 1102b, travel through this intra-metal substrate structure 1102b, connect with metal interconnect structures 1104b patterned in interconnect structures 1104 formed on the top side of metal core substrate 1102, travel through this metal interconnect structure 1104b, travel through the connected contacts C, and then be received at electronic component EC. Additionally, as shown in FIG. 11 , a second contact C adjacent to the first contact C and located on the other metal interconnect structure 1104b can receive ground from the separated intra-metal substrate structure 1102b.In the multiple different patterned metal core substrates 1102 according to the concepts of the present invention, the multiple different components can receive various signals to be enabled because their intra-metal substrate structures 1102b are connected to metal interconnect structures 1104b patterned in the interconnect structure 1104.

[0131] Metal-core substrate-based package interconnect systems offer substrates with a lower coefficient of thermal expansion (CTE) and higher Young's modulus than traditional substrate materials, which reduces the CTE mismatch between components and the substrate, reduces substrate warpage, and improves the overall reliability of the package.

[0132] 12A illustrates a metal core substrate-based package interconnect system 1200A according to yet another illustrative embodiment of the inventive concept. Referring to FIG. 12A, the metal core substrate-based package interconnect system 1200A can include at least two metal core substrates 1202, each formed of a metal core 1202a having metal sub-substrate structures 1202b and dielectric sub-substrate structures 1202c patterned therein and / or therethrough. These metal core substrates 1202 can be fabricated by surface patterning (i.e., laser ablation or plasma etching), dielectric material filling, and back-grinding, or by a surface and back-patterning and filling process.

[0133] In this exemplary embodiment, two or more metal core substrates 1202 are bonded to each other in a stacked manner. More specifically, the first metal core substrate 1202 (bottom substrate) may be configured to have a metal intra-substrate structure 1202b and a dielectric intra-substrate structure 1202c patterned through the first metal core 1202a. The second metal core substrate 1202 (middle substrate) may be bonded to the top surface of the first metal core substrate 1202 (bottom substrate) and may have a metal intra-substrate structure 1202b and a dielectric intra-substrate structure 1202c patterned through the second metal core 1202a, as well as at least one cavity formed therein for embedding a component therein. In this exemplary embodiment, the cavity is formed through the top surface of the second metal core substrate 1202. The cavity extends across a pair of dielectric structures 1202c and a metal structure 1202b, with the metal structure 1202b patterned between the pair of dielectric structures 1202c. The top of the metal structure 1202b has a contact C for an electronic component (EC) disposed thereon, which receives power via the metal structure 1202b. A third metal core substrate 1202 (top substrate) can be bonded to the top surface of the second metal core substrate 1202 (middle substrate). The third metal core substrate 1202 (top substrate) has the metal structure 1202b and the dielectric structure 1202c patterned therethrough, and has a cavity etched on its backside to align with the cavity etched on the top surface of the second metal core substrate 1202 (middle substrate). This embodiment is configured for cases where the electronic components EC are large enough that they cannot be completely embedded even if a cavity is formed in one metal core substrate 1202. Once the EC is placed in the cavity etched in the second metal core substrate 1202 (middle substrate), the third metal core substrate 1202 (top substrate) can be aligned with the second metal core substrate 1202 (middle substrate) so that the EC can be completely embedded in the two aligned cavities.A second metal core substrate 1202 (middle substrate) and a third metal core substrate 1202 (top substrate) can then be bonded together to form a metal core substrate-based package interconnect system 1200A, including three metal core substrates 1202 bonded together with aligned dielectric and metal substrate structures 1202c and 1202b, and at least one cavity with an embedded EC. The substrates can be bonded together using metal-metal bonding, such as Cu-Cu compression bonding, or solder paste. If the multilayer stack does not require high subsequent process temperatures, conductive polymers can be used to bond the substrates together. Additional electronic components (ECs) and / or contacts C can be disposed on both sides of the metal core substrate-based package interconnect system 1200A. A multilevel system-on-foil stacked interconnect wafer is called a jetty block or jetty board.

[0134] Embodiments of 1200A allow for stacking of metal core substrates to create more complex routing within the resulting stack than would be possible with a single metal core substrate. Additionally, embedded electronic components can be included within the stack.

[0135] 12B illustrates a metal core substrate-based package interconnect system 1200B according to yet another illustrative embodiment of the inventive concept. Referring to FIG. 12B, the metal core substrate-based package interconnect system 1200B can include at least two metal core substrates 1202, each formed of a metal core 1202a having metal sub-substrate structures 1202b and dielectric sub-substrate structures 1202c patterned therein and / or therethrough. These metal core substrates 1202 can be fabricated by surface patterning (i.e., laser ablation or plasma etching), dielectric material filling, and back-grinding, or by a surface and back-surface patterning and filling process.

[0136] In this exemplary embodiment, two or more metal core substrates 1202 are bonded to each other in a stacked manner. More specifically, a first metal core substrate 1202 (bottom substrate) may be configured to have a metal intra-substrate structure 1202b and a dielectric intra-substrate structure 1202c patterned through a first metal core 1202a. A second metal core substrate 1202 (middle substrate) may be bonded to the top surface of the first metal core substrate 1202 (bottom substrate) and configured to have a metal intra-substrate structure 1202b and a dielectric intra-substrate structure 1202c patterned through a second metal core 1202a. In this exemplary embodiment, the dielectric intra-substrate structure 1202c and the metal intra-substrate structure 1202b are exposed on the top surface of the second metal core substrate 1202 (middle substrate), and one of the metal intra-substrate structures 1202b is patterned between a pair of dielectric intra-substrate structures 1202c. The intra-metal substrate structure 1202b has contacts C for an electronic component (EC) disposed thereon, which receives power through the intra-metal substrate structure 1202b. A third metal core substrate 1202 (top substrate) can be bonded to the top surface of the second metal core substrate 1202 (middle substrate). The third metal core substrate 1202 (top substrate) has the intra-metal substrate structure 1202b and the dielectric substrate structure 1202c patterned therethrough, and has a cavity etched into its backside. The cavity is aligned to cover and embed the intra-metal substrate structure 1202b with the contacts and the electronic component (EC) disposed thereon. A second metal core substrate 1202 (middle substrate), a third metal core substrate 1202 (top substrate) can then be bonded together to form a metal core substrate-based package interconnect system 1200A, which includes three metal core substrates 1202 bonded together with aligned dielectric and metal substrate structures 1202c and 1202b, and at least one cavity with an embedded EC. The metal core substrate-based package interconnect system 1200B.

[0137] The 1200B embodiment allows for stacking of metal core substrates to create more complex routing within the resulting stack than would be possible with a single metal core substrate. Additionally, embedded electronic components can be included within the stack.

[0138] FIG. 13 illustrates a metal core substrate-based package interconnect system 1300 according to yet another exemplary embodiment of the inventive concept. Referring to FIG. 13, the metal core substrate-based package interconnect system 1300 can include at least two metal core substrates 1302, each formed with a metal core 1302a having a metal sub-substrate structure 1302b and a dielectric sub-substrate structure 1302c patterned therein and / or therethrough, and the at least two metal core substrates 1032 are bonded together in a stacked manner. The metal core substrate 1202 can be fabricated by surface patterning (i.e., laser ablation or plasma etching), dielectric material filling, and back-grinding, or by a surface and back-patterning and filling process. In this exemplary embodiment, three metal core substrates 1302 are directly bonded together in a stacked manner. Furthermore, interconnect structures 1304 can be deposited on both the top and bottom core substrates 1302. The interconnect structures 1304 deposited on the top and bottom core substrates 1302 may include dielectric interconnect structures 1304a and metal interconnect structures 1304b patterned therein and / or through them. As shown, predetermined ones of the dielectric interconnect structures 1304a and metal interconnect structures 1304b may be connected to predetermined ones of the dielectric intra-substrate structures 1302c and metal intra-substrate structures 1302b of the metal core substrate 1302 to form electrical traces extending through the metal core substrate 1302 and the interconnect structures 1304. Additionally, one of the plurality of metal core substrates 1302 may have at least one etched cavity that accommodates a corresponding electronic component (EC), with at least one EC electronically connected to and receiving signals from at least one metal intra-substrate structure 1302b. In an exemplary embodiment, at least one EC may receive electronic signals via the interconnected metal interconnect structures 1304b and metal intra-substrate structure 1302b.The interconnect structures 1304 deposited on the top and / or bottom core substrates 1302 can have external components electronically connected to the metal interconnect structures 1304b patterned therein via contacts connected to the external components and the metal interconnect structures 1304b.

[0139] Embodiments of 1300 allow for stacking of metal core substrates to create more complex routing within the resulting stack than is possible with a single metal core substrate. Additionally, embedded electronic components can be included within the stack. The stack can be fabricated in wafer format so that wafer-based interconnect structures can be patterned on the top and backside, allowing for additional routing capacity and attachment of surface components.

[0140] 14 illustrates a multi-metal core substrate-based package interconnect system according to yet another illustrative embodiment of the inventive concept. Referring to FIG. 14 , the multi-metal core substrate-based package interconnect system may include a plurality of metal core substrate-based package interconnect systems 1400 joined to one another at respective interconnect structures 1404. More specifically, each metal core substrate-based package interconnect system 1400 may include interconnect structures 1404 deposited on both the top and back surfaces of the metal core substrate 1402, such that patterned dielectric interconnect structures 1404 a and metal interconnect structures 1404 b of the interconnect structures 1404 are fabricated on the top and bottom surfaces of the metal core substrate 1402 to connect with the dielectric intra-substrate structures 1402 c and metal intra-substrate structures 1402 b of the metal core substrate 1402, respectively. The dielectric interconnect structures 1404a and metal interconnect structures 1404b of the interconnect structure 1404 are fabricated on the top and bottom surfaces of the metal core substrate 1402 to connect with the dielectric intra-substrate structures 1402c and metal intra-substrate structures 1402b of the metal core substrate 1402, respectively.

[0141] Embodiments of 1400 allow for stacking of multiple metal core substrate-based package interconnect systems to create more complex routing and capabilities than is possible with a single metal core substrate-based package interconnect system. Electronic components can be attached to either the top or bottom interconnect structure.

[0142] 15 illustrates a metal core substrate-based package interconnect system according to yet another exemplary embodiment of the inventive concept. Referring to FIG. 15, the metal core substrate-based package interconnect system can include multiple metal core substrates 1502 and multiple interconnect structures 1504 bonded together in various orders to form at least a portion of a first metal core substrate-based package interconnect system 1500a. More specifically, according to this exemplary embodiment, two metal core substrates 1502 can be directly bonded together such that at least one dielectric isolation pocket (DIP) 1502c is formed therebetween to form an enclosed DIV 1502c, and patterned metal intra-substrate structures 1502b and dielectric intra-substrate structures 1502c are formed within the two interconnected metal core substrates 1502.

[0143] On opposing surfaces of the two metal core substrates 1502 (surfaces of the metal core substrates 1502 that are not bonded to each other), interconnect structures 1504 can be deposited, including metal interconnect structures 1504b connected to intra-metal substrate structures 1502b of both metal core substrates 1502 and dielectric interconnect structures 1504c patterned between the metal interconnect structures 1504b. Some of the metal interconnect structures 1504b patterned on one of the interconnect structures 1504 can have contacts C connected thereto. Connected to the contacts can be intra-metal substrate structures 1502b of a second metal core substrate-based package interconnect system 1500b, which has a metal core substrate 1502 and interconnect structures 1504 deposited on its top and back surfaces. Thus, signals, power, and ground can pass through the intra-metallic substrate structures 1502b of the two directly bonded metal core substrates 1502, the metal interconnect structures 1504b of the interconnect structure 1504 deposited on the metal core substrate 1502, the contacts, and the metal interconnect structures 1504b and intra-metallic substrate structures 1502b of the second metal core substrate-based package interconnect system 1500. Furthermore, additional contacts C can be connected to at least one of the metal interconnect structures 1504b exposed on the top surface of the second metal core substrate-based package interconnect system 1500b. Additional electronic components EC can be connected to these contacts C.

[0144] The interconnect structure 1504 located on the other side of the two joined metal core substrates 1502 of the first metal core substrate-based package interconnect system 1500a may include an additional metal core substrate 1502 and an interconnect structure 1504 connected thereto, and the metal substrate structure 1502b and the metal interconnect structure are connected to each other.

[0145] Here, one package interconnect system is used as a substrate to support the connection of at least one other package interconnect system, acting as a package. The advantage is that both the substrate and the package have the same metal core and therefore the same CTE, minimizing the formation of thermomechanical stresses and improving reliability.

[0146] While several embodiments of the present general inventive concept have been shown and described, those skilled in the art will understand that changes can be made to these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the appended claims and their equivalents.

Claims

1. 1. A metal core substrate-based package interconnect system (PIS), comprising: a metal core substrate having intra-metal substrate structures patterned therein using the same metal body as the metal core substrate and a dielectric material patterned therein to separate each of the intra-metal substrate structures from the metal core substrate; interconnect structures bonded to each of the first surface of the metal core substrate and the second surface of the metal core substrate, each interconnect structure comprising an insulating material patterned with a plurality of metal interconnect structures formed therethrough, at least one of the metal interconnect structures from one interconnect structure being electronically bonded to at least one intra-metal substrate structure at the first surface of the metal core substrate, and at least two metal interconnect structures from the other interconnect structure being electronically bonded to at least one intra-metal substrate structure at the second surface of the metal core substrate to form at least one package interconnect component (PIC); A metal core substrate based package interconnect system (PIS) comprising:

2. The metal core substrate-based package interconnect system (PIS) of claim 1 , wherein said at least one package interconnect component is a differential PIC.

3. The metal core substrate based package interconnect system (PIS) of claim 1 , wherein said at least one package interconnect component is a signal array PIC.

4. 10. The metal core substrate based package interconnect system (PIS) of claim 1, wherein the at least one package interconnect component is a multi-distribution PIC for one of a signal line, a power line, or a ground line.

5. The metal core substrate-based package interconnect system (PIS) of claim 1 , wherein said at least one package interconnect component is an optical waveguide PIC.

6. The metal core substrate-based package interconnect system (PIS) of claim 1 , wherein said at least one package interconnect component is an array PIC.

7. The metal core substrate-based package interconnect system (PIS) of claim 1 , wherein the insulating material of at least one of the interconnect structures is formed of an inorganic dielectric material or an organic dielectric material.

8. a second metal core substrate-based package interconnect system connected on its top surface by bonding the interconnect structures on its top surface to the backside interconnect structures of the second metal core substrate-based package interconnect system, such that the metal interconnect structures from the metal core substrate-based package interconnect system are electronically connected to the interconnect structures of the second metal core substrate-based package interconnect system; 10. The metal core substrate-based package interconnect system of claim 1, further comprising:

9. a third metal core substrate-based package interconnect system connected to a top surface of the second metal core substrate-based package interconnect system via contacts configured to connect metal interconnect structures of the second metal core substrate-based package interconnect system to metal interconnect structures of the third metal core substrate-based package interconnect system; 10. The metal core substrate-based package interconnect system of claim 8, further comprising:

10. an electronic component attached to the top surface of said third metal core substrate-based package interconnect system via contacts connected to metal interconnect structures patterned therein; 10. The metal core substrate-based package interconnect system of claim 9, further comprising: an intra-metal substrate structure patterned in the metal core substrate-based package interconnect system; a second intra-metal substrate structure patterned in the metal core substrate-based package interconnect system; and a third intra-metal substrate structure patterned in the metal core substrate-based package interconnect system.

11. contacts connected to at least two exposed metal interconnect structures patterned within the interconnect structure bonded to the second surface of the metal core substrate; a component attached to the two contacts for receiving a signal that passes through at least two metal intra-substrate structures before passing through the at least two exposed metal interconnect structures; 10. The metal core substrate-based package interconnect system of claim 1, further comprising:

12. 1. A metal core substrate-based package interconnect system (PIS), comprising: a first metal core substrate including a metal core, metal intra-substrate structures patterned therein using the same metal body as the metal core, and dielectric intra-substrate structures patterned therein to separate each of the metal intra-substrate structures from the metal core; a second metal core substrate including a metal core, metal intra-substrate structures patterned therein using the same metal body as the metal core, and dielectric intra-substrate structures patterned therein to separate each of the metal intra-substrate structures from the metal core, wherein at least a portion of the top surface of the second metal core substrate is bonded to at least a portion of the backside surface of the first metal core substrate such that the at least one of the metal intra-substrate structures of the first and second metal core substrates are aligned to form at least one single metal intra-substrate structure and at least one single dielectric intra-substrate structure; A metal core substrate based package interconnect system (PIS) comprising:

13. a cavity formed in at least one of the top surface of the second metal core substrate and the back surface of the first metal core substrate; a component embedded in the cavity, the component electrically or optically connected to at least one of the intra-metallic or intra-dielectric substrate structures patterned through one of the first or second metal core substrates; 13. The metal core substrate-based package interconnect system (PIS) of claim 12, further comprising:

14. a third metal core substrate having at least a portion of its top surface bonded to at least a portion of the backside surface of the second metal core substrate such that the at least one intra-metal substrate structure of the third and second metal core substrates are aligned to form at least one single intra-metal substrate structure, and the component receives signals via the intra-metal substrate structure connected between the third and second metal core substrates; 14. The metal core substrate-based package interconnect system (PIS) of claim 13, further comprising:

15. an interconnect structure comprising: at least one dielectric interconnect structure deposited on the backside of the third metal core substrate; and at least one metal interconnect structure patterned therethrough and aligned with and in contact with at least one respective intra-substrate dielectric structure and metallic intra-substrate structure of the third metal core substrate; further comprising the components receive signals from the second and third metal core substrates through the metal substrate structures connected to each other and through the at least one metal interconnect structure patterned through the interconnect structure; 15. The metal core substrate based package interconnect system (PIS) of claim 14.

16. an interconnect structure deposited on at least one of the top surface of the first metal core substrate and the backside of the second metal core substrate; wherein the at least one interconnect structure comprises at least one dielectric interconnect structure and at least one metal interconnect structure patterned therethrough and in alignment with and contacting at least one corresponding dielectric and metal intra-substrate structure of the metal core substrate on which the interconnect structure is deposited.

13. The metal core substrate based package interconnect system (PIS) of claim 12.

17. contacts connected to at least two exposed metal interconnect structures patterned within an interconnect structure bonded to the top surface of the first metal core substrate; components attached to the two contacts for receiving signals passing through the first metal core substrate and the second metal core substrate before passing through the at least two exposed metal interconnect structures; 20. The metal core substrate-based package interconnect system of claim 16, further comprising:

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