Semiconductor structure, method of forming same, and semiconductor device

Abstract

The present disclosure relates to a semiconductor structure, a method for forming the same, and a semiconductor device, the semiconductor structure including a stacked structure, a semiconductor layer on the stacked structure, a channel structure extending through the stacked structure into the semiconductor layer, a contact structure extending along a stacking direction of the stacked structure, and a first soldering structure and a second soldering structure, wherein the first soldering structure penetrates the semiconductor layer and is connected to the contact structure, and the second soldering structure is connected to the semiconductor layer.

Description

[Technical Field]

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to semiconductor structures, methods of forming the same, and semiconductor devices. [Background technology]

[0002] 3D memory is a new type of flash memory in which multiple layers of data storage cells are stacked vertically to overcome the limitations of 2D or planar flash memory. 3D memory has excellent precision, supports higher capacity in a smaller footprint, has low cost and low power consumption, and can fully meet various requirements.

[0003] However, 3D memory still faces many challenges. Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides a semiconductor structure, a method for forming the same, and a semiconductor device to solve the problem of relatively high complexity and cost of both the semiconductor structure and its technological process due to the special requirements of various conductive via structures and solder pads on materials within the semiconductor structure.

[0005] To solve the above problems, the technical solutions of the present disclosure are implemented as follows: [Means for solving the problem]

[0006] The present disclosure provides a semiconductor structure comprising: A laminated structure; a semiconductor layer on the laminated structure; a channel structure extending through the stack structure into the semiconductor layer; a contact structure extending along a stacking direction of the stacked structure; a first soldering structure and a second soldering structure; Including, The first soldering structure is connected to the contact structure through the semiconductor layer, and the second soldering structure is connected to the semiconductor layer. A semiconductor structure is provided.

[0007] In an example of the present disclosure, each of the first soldering structure and the second soldering structure includes a first portion and a second portion on the first portion, the size of the second portion in the first direction being larger than the size of the first portion in the first direction, and the first direction being perpendicular to the stacking direction.

[0008] In an example of the present disclosure, the size of the first portion in the first direction is a first size, the size of the first portion in the stacking direction is a second size, and the ratio of the second size to the first size is less than 1:5.

[0009] In the examples of the present disclosure, the first and second portions are integrally formed.

[0010] In the example of the present disclosure, the portion of the channel structure that extends into the semiconductor layer has a size of less than 200 nm in the stacking direction.

[0011] In the examples of the present disclosure, the top surface of the semiconductor layer immediately above the channel structure is flush with the top surface of the semiconductor layer immediately above the stack structure.

[0012] In the examples of the present disclosure, the top surface of the semiconductor layer directly above the channel structure is higher than the top surface of the semiconductor layer directly above the stack structure.

[0013] In the examples of the present disclosure, the material of the first soldering structure and the material of the second soldering structure both include aluminum.

[0014] In examples of the present disclosure, the semiconductor structure further includes an isolation structure located between at least the first soldering structure and the semiconductor layer.

[0015] In an example of the present disclosure, the stacked structure includes alternating stacked first material layers and insulating layers, and has a third portion and a fourth portion arranged side by side in a direction perpendicular to the stacking direction; a contact structure extends through the third portion, and a channel structure extends through the fourth portion; the first material layer in the third portion includes a sacrificial layer, and the first material layer in the fourth portion includes a conductive layer.

[0016] In an example of the present disclosure, the channel structure includes a functional layer located within the stacked structure and a channel layer located within the stacked structure and extending into the semiconductor layer, the functional layer covering the sidewalls of the channel layer within the stacked structure.

[0017] In order to solve the above problem, the present disclosure provides a semiconductor device including a first semiconductor structure and the semiconductor structure described in any one of the above examples, the first semiconductor structure is located on one of two opposite sides of the semiconductor structure, away from the semiconductor layer in the stacking direction, and is connected to the semiconductor structure by hybrid bonding; A semiconductor device is also provided.

[0018] In the examples of the present disclosure, the first semiconductor structure comprises: It includes peripheral circuitry connected to contact structures within the semiconductor structure.

[0019] To solve the above problems, the present disclosure provides a method for forming a semiconductor structure, comprising: providing a stack structure, a contact structure, and a channel structure, wherein the channel structure penetrates and protrudes above the stack structure, and the contact structure extends along a stacking direction of the stack structure; forming a semiconductor layer on the stack structure and the channel structure from a side where the channel structure protrudes above the stack structure; forming a first soldering structure and a second soldering structure, the first soldering structure penetrating the semiconductor layer and connecting with the contact structure, and the second soldering structure connecting with the semiconductor layer; The present invention further provides a method of forming the ion beam comprising:

[0020] In an example of the present disclosure, the step of forming a semiconductor layer on the stack structure and the channel structure includes: forming a semiconductor material layer on each of the stack structure, the channel structure, and the contact structure, wherein an upper surface of the semiconductor material layer directly above the channel structure and the contact structure is higher than an upper surface of the semiconductor material layer directly above the stack structure; removing a portion of the semiconductor material layer to form a first opening exposing the contact structure, and a remaining portion of the semiconductor material layer forming the semiconductor layer; Includes:

[0021] In an example of the present disclosure, the step of forming a semiconductor layer on the stack structure and the channel structure includes: planarizing the semiconductor material layer before forming the first opening so that an upper surface of the semiconductor material layer immediately above the channel structure is flush with an upper surface of the semiconductor material layer immediately above the stack structure; Further includes:

[0022] In an example of the present disclosure, the method includes forming an isolation layer covering the sidewalls and bottom of the first opening and the semiconductor layer; removing at least a portion of the isolation layer on a bottom of the first opening to expose a contact structure; and removing a portion of the isolation layer on the semiconductor layer to form a second opening through which the semiconductor layer is exposed, with a remaining portion of the isolation layer forming the isolation structure. Further includes:

[0023] In an example of the present disclosure, the step of forming the first soldering structure and the second soldering structure includes: After forming the isolation structure, forming a first soldering structure in at least the first opening and forming a second soldering structure in at least the second opening, each of the first soldering structure and the second soldering structure including a first portion and a second portion on the first portion, the first portion of the first soldering structure being located in the first opening and the second portion of the second soldering structure being located in the second opening. Includes:

[0024] In an example of the present disclosure, the step of providing a stack structure, a contact structure, and a channel structure includes: forming a stack structure, a contact structure, and a channel structure on a base structure, wherein the base structure includes a substrate and a first semiconductor layer between the substrate and the stack structure, and the channel structure extends into the first semiconductor layer, or the base structure includes a substrate, and the channel structure extends into the substrate; removing the base structure to expose a portion of the channel structure; Includes:

[0025] In an example of the present disclosure, the channel structure includes a channel layer and a functional layer surrounding the channel layer, and after removing the base structure to expose a portion of the functional layer, the method includes: removing the exposed portion of the functional layer after removing the base structure to expose a portion of the channel layer; Further includes:

[0026] To make the objects, features, and advantages of the present disclosure clearer and easier to understand, specific implementations of the present disclosure will be described in detail below with reference to the drawings. [Brief explanation of the drawings]

[0027] [Figure 1] 1A-1C are schematic diagrams of semiconductor structures in some examples. [Figure 2A] 1 is a first diagram showing a cross section along lines AA′ and BB′ of a semiconductor structure in an example of the present disclosure. [Figure 2B]1 is a top view of a semiconductor structure provided in an example of the present disclosure. [Figure 3A] 1 is a structural schematic diagram of a first portion and a second portion provided in an example of the present disclosure. FIG. [Figure 3B] 1 is a structural schematic diagram of a first portion and a second portion provided in an example of the present disclosure. FIG. [Figure 4] FIG. 2 is a second diagram showing a cross section along lines AA′ and BB′ of a semiconductor structure in an example of the present disclosure. [Figure 5] FIG. 3 is a third diagram showing a cross section along lines AA′ and BB′ of a semiconductor structure in an example of the present disclosure. [Figure 6] 1 is a flowchart of a method for forming a semiconductor structure provided in an example of the present disclosure. [Figure 7] 2A to 2C are cross-sectional views taken along lines AA′ and BB′ of a process for forming a semiconductor structure provided in an example of the present disclosure. [Figure 8] 2A to 2C are cross-sectional views taken along lines AA′ and BB′ of a process for forming a semiconductor structure provided in an example of the present disclosure. [Figure 9] 2A to 2C are cross-sectional views taken along lines AA′ and BB′ of a process for forming a semiconductor structure provided in an example of the present disclosure. [Figure 10] 2A to 2C are cross-sectional views taken along lines AA′ and BB′ of a process for forming a semiconductor structure provided in an example of the present disclosure. [Figure 11] 2A to 2C are cross-sectional views taken along lines AA′ and BB′ of a process for forming a semiconductor structure provided in an example of the present disclosure. [Figure 12] 2A to 2C are cross-sectional views taken along lines AA′ and BB′ of a process for forming a semiconductor structure provided in an example of the present disclosure. [Figure 13] 2A to 2C are cross-sectional views taken along lines AA′ and BB′ of a process for forming a semiconductor structure provided in an example of the present disclosure. [Figure 14] 2A to 2C are cross-sectional views taken along lines AA′ and BB′ of a process for forming a semiconductor structure provided in an example of the present disclosure. [Figure 15]2A to 2C are cross-sectional views taken along lines AA′ and BB′ of a process for forming a semiconductor structure provided in an example of the present disclosure. [Figure 16] 2A to 2C are cross-sectional views taken along lines AA′ and BB′ of a process for forming a semiconductor structure provided in an example of the present disclosure. [Figure 17] 2A to 2C are cross-sectional views taken along lines AA′ and BB′ of a process for forming a semiconductor structure provided in an example of the present disclosure. [Figure 18] 2A to 2C are cross-sectional views taken along lines AA′ and BB′ of a process for forming a semiconductor structure provided in an example of the present disclosure. [Figure 19] 2A to 2C are cross-sectional views taken along lines AA′ and BB′ of a process for forming a semiconductor structure provided in an example of the present disclosure. [Figure 20] 2A to 2C are cross-sectional views taken along lines AA′ and BB′ of a process for forming a semiconductor structure provided in an example of the present disclosure. [Figure 21] 2A to 2C are cross-sectional views taken along lines AA′ and BB′ of a process for forming a semiconductor structure provided in an example of the present disclosure. [Figure 22] 2A to 2C are cross-sectional views taken along lines AA′ and BB′ of a process for forming a semiconductor device provided in an example of the present disclosure. [Figure 23] 2A to 2C are cross-sectional views taken along lines AA′ and BB′ of a process for forming a semiconductor device provided in an example of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0028] To make the above objects, features, and advantages of the present disclosure more apparent and easier to understand, specific implementations of the present disclosure will be described in detail below with reference to the drawings.

[0029] Numerous details are set forth in the following description to provide a thorough understanding of the present disclosure, but the present disclosure may be implemented in other implementations different from those described herein and is therefore not limited by the specific examples disclosed below.

[0030] As used in this application and in the claims, terms such as "a," "an," and / or "the" may include the plural instead of only the singular, unless the context clearly dictates otherwise. In general, the terms "including" and "comprising" only indicate that the explicitly recited steps and elements are inclusive, but do not constitute an exclusive list; other steps or elements may also be included in the method or apparatus.

[0031] In the detailed description of the examples of the present disclosure, cross sections showing device structures are not drawn to scale and are partially exaggerated for ease of explanation. The figures are merely illustrative and do not limit the scope of the present disclosure in any way. In addition, the three-dimensional spatial dimensions of length, width, and depth may be involved in actual fabrication.

[0032] For ease of description, spatial relationship terms such as "under," "below," "lower," "beneath," "above," and "on" may be used herein to describe the relationship of one element or feature to another element or feature in the drawings. It should be understood that these spatial relationship terms are intended to include orientations of the device in use or operation other than that shown in the drawings. For example, if a device were turned upside down, an element described as being "below," "under," or "beneath" another element or feature would instead have an orientation of being "above" that other element or feature. Thus, the exemplary terms "beneath" and "under" can include both an orientation of "below" and "above." The device may be oriented differently (rotated 90 degrees or to other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. Furthermore, when a layer is referred to as being located "between" two layers, it should be understood that it may be the only layer located between them, or that there may be one or more other layers located between the two layers.

[0033] In the context of this application, a structure in which a first feature is located "on" a second feature as described above may include instances in which the first feature and the second feature are formed in direct contact with each other, or may include instances in which an additional feature is formed between the first feature and the second feature, such that the first feature and the second feature do not need to be in direct contact with each other.

[0034] Furthermore, it should be noted that when terms such as "first," "second," etc. are used to define a portion, they are intended only to distinguish one portion from another portion, and unless otherwise stated, the above terms do not have any special meaning and cannot be construed as limitations on the scope claimed by this application.

[0035] As used herein, the term "3D memory" refers to a semiconductor device having vertically oriented strings of memory cell transistors (referred to herein as "memory strings," such as NAND strings) on a laterally oriented substrate, such that the memory strings extend perpendicular to the substrate. As used herein, the term "vertical / vertically" means nominally perpendicular to the sides of the substrate.

[0036] As used herein, the term "substrate" refers to a material onto which subsequent layers of material are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or left unpatterned. Furthermore, substrates can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0037] As used in this application, the term "layer" refers to a portion of material that includes a region having a thickness. A layer can extend throughout an underlying or overlying structure, or may have an extent that is smaller than the extent of the underlying or overlying structure. Furthermore, a layer can be a homogeneous or heterogeneous region of a continuous structure that has a thickness that is smaller than the thickness of the continuous structure. For example, a layer can be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal surfaces at the top and bottom surfaces. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer and can include one or more layers therein and / or have one or more layers on, above, and / or below it. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which contacts, interconnect lines, and / or vias are formed) and one or more dielectric layers.

[0038] Flowcharts are used herein to illustrate operations performed by systems according to examples of the present application. It should be understood that the operations described above and below do not necessarily have to be performed in the exact order. Instead, various steps may be processed in reverse order or simultaneously. It should be noted that other operations may be added to these processes, or one or more operations may be deleted from these processes.

[0039] In some examples, as shown in FIG. 1 , the channel structure of the semiconductor structure includes a functional layer and a channel layer, and the functional layer covers a portion of the sidewall of the channel layer. In some examples, during the process of forming the channel structure, it is difficult to control the depth of the portion of the channel structure that extends beyond the stacked structure within a small range. As a result, the portion of the channel layer that is not covered by the finally formed functional layer has a relatively large height in the Z direction. The semiconductor structure further includes a contact structure, a gate line slit (GLS) structure, and a channel structure. The semiconductor layer covers an upper portion of the gate line slit structure and is covered by an isolation layer thereon. When the height of the upper portion of the channel structure and the height of the upper portion of the semiconductor layer above the gate line slit structure are much lower than the height of the upper portion of the isolation layer, a first conductive via structure that penetrates the isolation layer and connects to the contact structure, a second conductive via structure that penetrates the isolation layer and connects to the semiconductor layer above the gate line slit structure, and / or a third conductive via structure that penetrates the isolation layer and connects to the semiconductor layer above the channel structure may be disposed to pad out the contact structure and the channel structure. The "top" in the above means the highest point of the semiconductor structure in the Z direction. A first pad may be disposed on the top of the first conductive via structure, a second pad may be disposed on the top of the second conductive via structure, and a third pad may be disposed on the top of the third conductive via structure.

[0040] It should be understood that because the portion of the channel layer not covered by the functional layer has a relatively large height in the Z direction in the semiconductor structure described above, the isolation layer has a relatively large thickness in the Z direction. Furthermore, each of the conductive via structures described above may have a relatively large aspect ratio. Furthermore, the conductive via structure has a conductive material filled therein. Aluminum has poor step coverage, making it unsuitable for conductive via structures with a relatively large aspect ratio, such as that shown in FIG. 1 . While tungsten can be considered for filling vias with a relatively large aspect ratio, it is relatively expensive. Furthermore, since the pads can also be used in the testing phase, a metal material that is resistant to deformation can be selected, and the material used for the various pads may be aluminum. Due to the special requirements for the conductive via structures and pad materials in the semiconductor structure described above, the semiconductor structure and its processing procedures are complex and require high processing costs.

[0041] To solve one or more of the above problems, a semiconductor structure is provided in an example of the present disclosure with reference to FIGS. 2A and 2B. The semiconductor structure includes a stacked structure 100, a semiconductor layer 110 on the stacked structure 100, a channel structure 210 extending in the Z direction through the stacked structure 100 into the semiconductor layer 110, and a contact structure 220 extending along the stacking direction (i.e., the Z direction) of the stacked structure 100. FIG. 2A is a cross-sectional view of the semiconductor structure taken along lines AA′ and BB′ in FIG. 2B provided in the present disclosure, and FIG. 2B is a top view of the semiconductor structure provided in the present disclosure. In FIGS. 2A and 2B, the numbers of the channel structures 210, contact structures 220, and gate line slit structures 230 are merely examples and do not correspond to one another. A contact region is also included in FIG. 2B. The contact region includes a plurality of word line contact structures 221 configured to pad out word lines in the stacked structure 100. FIG. 2B further includes a first soldering structure 310 configured to pad out the contact structure 220 and a second soldering structure 320 configured to pad out the channel structure 210.

[0042] In some examples, the channel structure 210 includes a functional layer disposed in the stack structure 100 and a channel layer disposed in the stack structure 100 and extending into the semiconductor layer 110, where the functional layer covers sidewalls of the channel layer in the stack structure 100. A portion of the channel layer extending into the semiconductor layer 110 is not covered by the functional layer. A height of the portion of the channel layer extending into the semiconductor layer 110 in the Z direction is less than a preset value.

[0043] In some examples, the functional layer includes a blocking layer, a trapping layer, and a tunneling layer. The material of the channel layer includes, but is not limited to, polysilicon.

[0044] In some examples, the portion of the channel structure 210 that extends into the semiconductor layer 110 has a size in the stacking direction that is less than 200 nm, i.e., the first preset value is 200 nm.

[0045] It should be noted that the first preset values ​​given in the above examples are merely examples and are not used to limit the specific values ​​of the first preset values ​​in the examples of the present disclosure.

[0046] 2A further includes a first soldering structure 310 that penetrates the semiconductor layer 110 and is connected to the contact structure 220, and a second soldering structure 320 that is connected to the semiconductor layer 110. The first soldering structure 310 is configured to pad out the contact structure 220, and the second soldering structure 320 is configured to pad out the channel structure 210. It should be noted that the second soldering structure 320 is configured to pad out the channel structure 210 indirectly via the semiconductor layer 110, rather than directly pad out the channel structure 210.

[0047] In some embodiments, the material of the semiconductor layer 110 includes, but is not limited to, polysilicon. The semiconductor layer 110 can be used as a source layer.

[0048] It should be understood that in the example of the present disclosure, based on the relatively small size of the portion of the channel structure 210 extending into the semiconductor layer 110 along the stacking direction and the relatively small size of the semiconductor layer 110 along the stacking direction, the first soldering structure 310 is made to be in direct contact with the contact structure 220, and the second soldering structure 320 is made to be in direct contact with the semiconductor layer 110. That is, without the need to form tungsten-filled contact structures between the first soldering structure 310 and the contact structure 220 and between the second soldering structure 320 and the semiconductor layer 110, padding of the contact structure 220 and the channel structure 210 can be directly achieved by the second soldering structure 320 and the first soldering structure 310, resulting in a simplified semiconductor structure, saving corresponding process steps, and reducing process costs.

[0049] In some examples, the material of the first soldering structure 310 and the material of the second soldering structure 320 may each include aluminum, but the materials of the first soldering structure 310 and the second soldering structure 320 are not limited thereto.

[0050] In some examples, as shown in FIGS. 3A and 3B, each of the first soldering structure 310 and the second soldering structure 320 includes a first portion 301 and a second portion 302 on the first portion 301, and the size of the second portion 302 in a first direction (i.e., the X direction) is larger than the size of the first portion 301 in the first direction, and the first direction is perpendicular to the stacking direction (i.e., the Z direction).

[0051] In some examples, the size of the first portion 301 in the first direction is a first size, the size of the first portion 301 in the stacking direction is a second size, and the ratio of the second size to the first size is less than 1:5.

[0052] It should be noted that, as shown in Figure 3A, the first portion 301 may have an inverted trapezoidal shape, and the first size taken at different heights along the Z direction may have different values, which may be the minimum size of the inverted trapezoid in the X direction, i.e., the size of the bottom of the first portion 301 in the X direction in Figure 3A. In some examples, as shown in Figure 3B, the first portion 301 may have a rectangular shape, and the first size taken at different heights along the Z direction may be the same, and the first size may be the size of the rectangle in the X direction at any height along the Z direction.

[0053] In some examples, the first portion 301 and the second portion 302 may be integrally formed, which may simplify the process flow, save process time, reduce process costs, and reduce the complexity of the wiring process.

[0054] In the example of the present disclosure, first portion 301 and second portion 302 use the same conductive material, including but not limited to aluminum.

[0055] In some examples, as shown in FIG. 4, the top surface of the semiconductor layer 110 directly above the channel structure 210 is higher than the top surface of the semiconductor layer 110 directly above the stacked structure 100.

[0056] In the example of the present disclosure, the top surface of the semiconductor layer 110 has an irregular morphology related to the profile of the portion of the channel structure 210 that protrudes above the stack structure 100 .

[0057] Specifically, the semiconductor layer 110 having an irregularly shaped top surface can be formed by depositing a semiconductor material on the sidewalls and top surface of the stacked structure 100 and the channel structure 210 using a deposition / epitaxial growth process, and has the same thickness in the Z direction. Because the channel structure 210 protrudes above the stacked structure 100, the top surface of the semiconductor layer 110 directly above the channel structure 210 is higher than the top surface of the semiconductor layer 110 directly above the stacked structure 100.

[0058] 4, the semiconductor structure further includes a gate line slit structure 230 extending through the stack structure 100 into the semiconductor layer 110. It may be understood that the top surface of the semiconductor layer 110 directly above the gate line slit structure 230 may be higher than the top surface of the semiconductor layer 110 directly above the stack structure 100.

[0059] In some particular examples, the material of the gate line slit structure 230 may be one or more of a dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride, and a semiconductor material, such as polysilicon.

[0060] In some examples, as shown in FIG. 2A, the top surface of the semiconductor layer 110 directly above the channel structure 210 is flush with the top surface of the semiconductor layer 110 directly above the stack structure 100.

[0061] Specifically, in a corresponding formation process, a semiconductor layer 110 having an upper surface with an irregular morphology as shown in FIG. 4 may be first formed, and then the upper surface may be planarized by chemical mechanical polishing (CMP), thereby finally obtaining a semiconductor layer 110 having a flat surface in the X direction as shown in FIG. 2A.

[0062] 2, the stacked structure 100 includes alternating stacked first material layers 101 and insulating layers 102, and has a third portion 100b (e.g., a contact region) and a fourth portion 100a (e.g., an array region) arranged side by side in a direction perpendicular to the stacking direction. The contact structure 220 penetrates the third portion 100b, and the channel structure 210 penetrates the fourth portion 100a. The first material layer 101 in the third portion 100b includes a sacrificial layer, and the first material layer 101 in the fourth portion 100a includes a conductive layer.

[0063] In the example of the present disclosure, the conductive layer in the fourth portion 100a may be formed by replacing a sacrificial layer, during which the sacrificial layer in the third portion 100b is not replaced, and the contact structure 220 in the third portion 100b may provide support for the stacked structure 100.

[0064] In some specific examples, the material used for the conductive layer may include one or more of conductive materials such as tungsten, cobalt, copper, aluminum, and metal silicides. The material used for the sacrificial layer may include, but is not limited to, silicon nitride. The material used for the insulating layer 102 may include, but is not limited to, silicon oxide.

[0065] In some examples, as shown in FIG. 2A, the semiconductor structure further includes an isolation structure 120 located between at least the first soldering structure 310 and the semiconductor layer 110.

[0066] In examples of the present disclosure, the isolation structure 120 is configured to separate the first soldering structure 310 from the semiconductor layer 110, such that the first soldering structure 310 and the second soldering structure 320 can pad out the contact structure 220 and the channel structure 210, respectively. In some particular examples, the material of the isolation structure 120 may include, but is not limited to, silicon oxide.

[0067] An example of the present disclosure provides a semiconductor device including a first semiconductor structure 400, as shown in FIG. 5, and a semiconductor structure according to any of the examples above.

[0068] The first semiconductor structure 400 is located on one of two opposite sides of the semiconductor structure, the side farther from the semiconductor layer 110 in the stacking direction, and is connected to the semiconductor structure by hybrid bonding.

[0069] In some examples, the first semiconductor structure 400 comprises: The semiconductor structure includes peripheral circuitry connected to contact structures 220 within the semiconductor structure.

[0070] In some examples, the semiconductor structure includes a first bonding layer located on two opposing sides of the semiconductor structure away from the semiconductor layer 110 along the Z direction. The first semiconductor structure 400 further includes a second bonding layer. The first and second bonding layers can be bonded through a hybrid bonding process.

[0071] In some examples, the first semiconductor structure 400 and the semiconductor structure provided in the examples of the present disclosure can be bonded by a fusion bonding process or a direct wafer bonding process, with the side of the substrate away from the stacked structure 100 facing upward after bonding.

[0072] In the examples of the present disclosure, a memory array wafer including the stacked structure 100 is bonded to the first semiconductor structure 400 including peripheral circuits, and then a subsequent backside pad-out process is performed from the side of the substrate away from the stacked structure 100. However, in some other examples, the memory array wafer and the first semiconductor structure 400 including peripheral circuits may be bonded after the backside pad-out process is performed, or only the memory array wafer may be formed and the backside pad-out process may be performed on the memory array wafer.

[0073] In some implementations, as shown in FIG. 5 , the contact structure 220 may be connected to peripheral circuits in the first semiconductor structure 400 through interconnect structures in the interconnect layer 410. The peripheral circuits may include complementary metal-oxide-semiconductor (CMOS) devices and metal-oxide-semiconductor (MOS) devices. The CMOS and MOS devices in the peripheral circuits may be electrically padded out through the interconnect structures, the contact structure 220, and the first soldering structure 310. The first soldering structure 310 may be configured to receive a first voltage transmitted to the peripheral circuits through the contact structure 220. The second soldering structure 320 may be configured to receive a second voltage received by the semiconductor layer 110 and transferred to the plurality of channel structures 210 as a source voltage. By using an isolation structure 120 between the first soldering structure 310 and the semiconductor layer 110, the first soldering structure 310 and the second soldering structure 320 do not interfere with each other.

[0074] An example of the present disclosure provides a method for forming a semiconductor structure. Figure 6 is a flowchart of the method for forming a semiconductor structure provided in an example of the present disclosure. As shown in Figure 6, the method for forming a semiconductor structure includes the following steps: Step S10: Providing a stack structure, a contact structure, and a channel structure, wherein the channel structure penetrates the stack structure and protrudes above the stack structure, and the contact structure extends in a stacking direction of the stack structure. Step S20: A semiconductor layer is formed on the stacked structure and the channel structure from the side where the channel structure protrudes above the stacked structure. Step S30: Form a first soldering structure and a second soldering structure, the first soldering structure being connected to the contact structure through the semiconductor layer, and the second soldering structure being connected to the semiconductor layer.

[0075] 7 to 19 are structural diagrams illustrating a process for forming a semiconductor structure provided in an example of the present disclosure. Hereinafter, a method for forming a semiconductor structure provided in an example of the present disclosure will be described in detail with reference to FIGS.

[0076] Referring to FIG. 7, step S10 is performed to provide a stacked structure 100, a contact structure 220, and a channel structure 210, wherein the channel structure 210 penetrates the stacked structure 100 and protrudes above the stacked structure 100, and the contact structure 220 extends in the stacking direction of the stacked structure 100.

[0077] In some examples, the stacked structure 100 includes a third portion 100b (e.g., a contact region) and a fourth portion 100a (e.g., an array region) arranged side by side in a direction perpendicular to the stacking direction. The third portion 100b includes a sacrificial layer 101b and an insulating layer 102 arranged in order along the Z direction. The fourth portion 100a includes a conductive layer 101a and an insulating layer 102 arranged in order along the Z direction.

[0078] In some specific examples, a base structure may first be provided, which may include a first region and a second region arranged side by side in the X direction. The process of forming the stacked structure 100 includes using a deposition process to form an insulating layer 102 and a sacrificial layer 101b alternately stacked along the Z direction on both the first region and the second region, forming a gate line slit (GLS), then removing the sacrificial layer 101b on the second region while leaving the sacrificial layer 101b on the first region, and depositing a conductive layer 101a at the position where the sacrificial layer 101b was removed on the second region. As a result, a third portion 100b of the stacked structure 100 is formed on the first region, and a fourth portion 100a of the stacked structure 100 is formed on the second region. In some specific examples, the method further includes filling the gate line slit to form a gate line slit structure 230.

[0079] 7 is merely an example, and the present disclosure is not limited thereto. It should be understood that the number of sacrificial layers 101b is the same as the number of conductive layers 101a.

[0080] In examples of the present disclosure, deposition processes include, but are not limited to, chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0081] In the example of the present disclosure, the channel structure 210 includes a functional layer and a channel layer, where the functional layer covers a portion of the sidewall of the channel layer. The top surface of the functional layer is flush with the top surface of the laminated structure 100, and the channel layer protrudes above the top surface of the laminated structure 100. The channel structure 210 is formed by etching an initial channel structure. The initial channel structure includes an initial functional layer and a channel layer, where the initial functional layer covers the sidewall and top surface of the channel layer. To form the functional layer, a portion of the initial functional layer on the laminated structure 100 is removed.

[0082] In examples of the present disclosure, the material of the contact structure 220 may be one or more of conductive materials such as tungsten, cobalt, copper, aluminum, and metal suicides.

[0083] The present disclosure provides various examples of methods for forming a semiconductor layer, a first soldering structure, and a second soldering structure. Figures 8 to 13 are structural schematic diagrams of the processes for forming the semiconductor layer, the first soldering structure, and the second soldering structure provided in the present disclosure. Hereinafter, methods for forming the semiconductor layer, the first soldering structure, and the second soldering structure provided in the examples of the present disclosure will be described in detail with reference to Figures 6 and 8 to 13.

[0084] 8 and 9, step S20 is performed to form a semiconductor layer 110 on the stacked structure 100 and the channel structure 210 from the side where the channel structure 210 protrudes above the stacked structure 100. The material of the semiconductor layer 110 includes at least one of polysilicon, polycrystalline germanium, and polycrystalline silicon germanium.

[0085] In some examples, referring to FIGS. 8 and 9, forming the semiconductor layer 110 on the stack structure 100 and the channel structure 210 includes: 8 on the stacked structure 100, the channel structure 210, and the contact structure 220 by a deposition process while the top surface of the semiconductor material layer 111 is not flat, and the thickness of the semiconductor material layer 111 in the Z direction remains the same because the semiconductor material layer 111 is formed conformally with the channel structure 210 and the contact structure 220. Because the channel structure 210 and the contact structure 220 protrude above the stacked structure 100, the top surface of the semiconductor material layer 111 directly above the channel structure 210 and the top surface of the semiconductor material layer 111 directly above the contact structure 220 are higher than the top surface of the semiconductor material layer 111 directly above the stacked structure 100. A portion of the semiconductor material layer 111 directly above the contact structure 220 is removed, and in some instances, at least a portion of the contact structure 220 above the top surface of the stacked structure 100 may also be removed, resulting in a first opening 501 being formed to expose the contact structure 220, with the remaining portion of the semiconductor material layer 111 forming the semiconductor layer 110, as shown in FIG.

[0086] Referring to FIG. 10, step S30 is performed to form a first soldering structure 310 that penetrates the semiconductor layer 110 and connects to the contact structure 220, and a second soldering structure 320 that connects to the semiconductor layer 110.

[0087] The first soldering structure 310 is configured to pad out the contact structure 220, and the second soldering structure 320 is configured to pad out the channel structure 210. The conductive material used in the first soldering structure 310 and the second soldering structure 320 may include, but is not limited to, aluminum.

[0088] In the example of the present disclosure, a solder layer may be first formed on the semiconductor layer 110, and then the solder layer may be processed by lithography and etching to form the first soldering structures 310 and the second soldering structures 320. Note that the number of first soldering structures 310 and second soldering structures 320 in FIG. 10 is merely exemplary, and the present disclosure is not specifically limited thereto.

[0089] 11 to 13, in some examples, the method further includes using a deposition process to form an isolation layer 121 covering the sidewalls and bottom of the first opening 501 and the semiconductor layer 110, as shown in FIG. 11, where the isolation layer 121 covers the entire semiconductor layer 110. Materials used for the isolation layer 121 include, but are not limited to, silicon oxide.

[0090] At least a portion of the isolation layer 121 on the bottom of the first opening 501 is removed using an etching process to expose the contact structure 220, and a portion of the isolation layer 121 on the semiconductor layer 110 is removed to form a second opening 502 through which the semiconductor layer 110 is exposed, so that the remaining portion of the isolation layer 121 forms the isolation structure 120 as shown in FIG. 12.

[0091] It should be noted that the number of first openings 501 and second openings 502 in FIG. 12 is merely an example, and the present disclosure does not specifically limit this.

[0092] In some examples, referring to FIGS. 12 and 13, forming the first soldering structure 310 and the second soldering structure 320 includes: After forming the isolation structure 120, forming at least a first soldering structure 310 in the first opening 501 using a deposition process and forming at least a second soldering structure 320 in the second opening 502 using a deposition process, where the top surfaces of both the first soldering structure 310 and the second soldering structure 320 are higher than the top surface of the isolation structure 120. Each of the first soldering structure 310 and the second soldering structure 320 includes a first portion 301 and a second portion 302 on the first portion 301, where the first portion 301 of the first soldering structure 310 is located in the first opening 501 and the first portion 301 of the second soldering structure 320 is located in the second opening 502.

[0093] In the examples of the present disclosure, the first portion 301 and the second portion 302 may be integrally formed.

[0094] In the above example, it can be understood that the method of directly forming the opening 501, and therefore the semiconductor layer 110, without performing a planarization process after forming the semiconductor material layer 111 can save process flow and save process time.

[0095] 14 to 19 are other structural schematic diagrams of the process for forming the semiconductor layer, first soldering structure, and second soldering structure provided in the present disclosure. Hereinafter, the method for forming the semiconductor layer, first soldering structure, and second soldering structure provided in the examples of the present disclosure will be described in detail with reference to FIG. 6 and FIG. 14 to FIG. 19.

[0096] 14 to 16, step S20 is performed to form the semiconductor layer 110 on the stacked structure 100 and the channel structure 210 from the side where the channel structure 210 protrudes above the stacked structure 100.

[0097] In some examples, referring to FIGS. 14-16, forming the semiconductor layer 110 on the stack structure 100 and the channel structure 210 may include: The method further includes planarizing the semiconductor material layer 111 shown in FIG. 14 before forming the first opening 501 so that after planarization, the top surface of the semiconductor material layer 111 directly above the channel structure 210 is flush with the top surface of the semiconductor material layer 111 directly above the stacked structure 100, as shown in FIG. 15. As shown in FIG. 15, a portion of the semiconductor material layer 111 directly above the contact structure 220 is removed to form a first opening 501 to expose the contact structure 220, and the remaining portion of the semiconductor material layer 111 forms the semiconductor layer 110, as shown in FIG. 16.

[0098] In the examples of the present disclosure, the semiconductor material layer 111 can be formed by a deposition process and then etched to form the semiconductor layer 110, which is finally crystallized by a laser to form the laser crystallized semiconductor layer 110, such as laser crystallized polysilicon.

[0099] In some examples, the semiconductor material layer 111 may also be crystallized by a laser to form a laser-crystallized semiconductor material layer 111, which is then etched to form a laser-crystallized semiconductor layer 110.

[0100] Referring to FIG. 19, step S30 is performed to form a first soldering structure 310 that penetrates the semiconductor layer 110 and is connected to the contact structure 220, and a second soldering structure 320 that is connected to the semiconductor layer 110.

[0101] The first soldering structure 310 is configured to pad out the contact structure 220, and the second soldering structure 320 is configured to pad out the channel structure 210. The conductive material used in the first soldering structure 310 and the second soldering structure 320 may include, but is not limited to, aluminum.

[0102] 17 to 19, in some examples, the method further includes using a deposition process to form an isolation layer 121 covering the sidewalls and bottom of the first opening 501 and the semiconductor layer 110, as shown in FIG. 17, where the isolation layer 121 covers the entire semiconductor layer 110. Materials used for the isolation layer 121 include, but are not limited to, silicon oxide.

[0103] As shown in FIG. 18 , an etching process is used to remove at least a portion of the isolation layer 121 on the bottom of the first opening 501 to expose the contact structure 220, and a portion of the isolation layer 121 on the semiconductor layer 110 to form a second opening 502, through which the semiconductor layer 110 is exposed, and the remaining portion of the isolation layer 121 forms the isolation structure 120.

[0104] It should be noted that the number of first openings 501 and second openings 502 in FIG. 18 is merely an example, and the present disclosure does not specifically limit this.

[0105] 19 , forming the first soldering structure 310 and the second soldering structure 320 includes, after forming the isolation layer 120, using a deposition process to form at least the first soldering structure 310 in the first opening 501 and using a deposition process to form at least the second soldering structure 320 in the second opening 502, wherein top surfaces of both the first soldering structure 310 and the second soldering structure 320 are higher than a top surface of the isolation structure 120. Each of the first soldering structure 310 and the second soldering structure 320 includes a first portion 301 and a second portion 302 on the first portion 301. The first portion 301 of the first soldering structure 310 is located in the first opening 501, and the first portion 301 of the second soldering structure 320 is located in the second opening 502.

[0106] The first soldering structure 310 and the second soldering structure 320 may also be used for testing and for connection to other external components or semiconductor structures. In some examples, the size of the second portion 302 in the X direction is larger than the size of the first portion 301 in the X direction, which can increase the area for contacting other components and therefore reduce the possibility of poor contact between the other components and the soldering structures.

[0107] In the example of the present disclosure, the first portion 301 and the second portion 302 are integrally formed. The soldering layer covering the isolation structure 120 may be formed on the isolation structure 120 using a deposition process and then recessed to form trenches therein to form the first soldering structure 310 and the second soldering structure 320.

[0108] In the example of the present disclosure, the conductive material used for the first soldering structure 310 and the second soldering structure 320 may be aluminum. The first soldering structure 310 and the second soldering structure 320 may be formed in a single deposition process, reducing process costs. The first soldering structure 310 and the second soldering structure 320 may be configured to pad out the contact structure 220 and the channel structure 210, respectively, thus avoiding padding out the contact structure 220 and the channel structure 210 using conductive via structures with high aspect ratios, which are difficult to form by etching and may also limit the type of conductive material filled in the vias.

[0109] In some examples, providing the stacked structure 100, the contact structure 220, and the channel structure 210 may include: 20 and 21, the method includes forming a stacked structure 100, a contact structure 220, and a channel structure 210 on a base structure 600. The base structure 600 includes a substrate 610 and a first semiconductor layer 620 between the substrate 610 and the stacked structure 100, with the channel structure 210 extending within the first semiconductor layer 620. Alternatively, the base structure 600 includes the substrate 610, and the channel structure 210 extends within the substrate 610. The base structure 600 is removed to expose a portion of the channel structure 210 .

[0110] 20, the base structure 600 may include a substrate 610 and a first semiconductor layer 620. The channel structure 210 extends within the first semiconductor layer 620.

[0111] 21, the base structure 600 can include a substrate 610. The channel structure 210 extends within the substrate 610.

[0112] The substrate 610 may be a single-material semiconductor material substrate (e.g., a silicon substrate, a germanium substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon substrate), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0113] Materials used for the first semiconductor layer 620 include, but are not limited to, polysilicon, polycrystalline germanium, and polycrystalline silicon germanium.

[0114] Examples of the present disclosure further provide methods of forming semiconductor devices, which are further described in connection with FIGS.

[0115] In some examples, a first semiconductor structure 400 including peripheral circuitry (not shown in FIG. 22 ) as shown in FIG. 22 may be first provided and then bonded to the structure shown in FIG. 20 or 21 on the side of the structure away from the base structure 600 in the Z direction, with the base structure 600 facing up as shown in FIG. 22 . Subsequently, the substrate 610 and the first isolation layer between the substrate 610 and the first semiconductor layer 620 are removed by an etching process as shown in FIG. 20 , or the substrate 610 is removed by an etching process as shown in FIG. 21 to form the structure shown in FIG. 23 . Thereafter, the first semiconductor layer 620 shown in FIG. 23 is removed, and then the semiconductor layer, first contact structure, and second contact structure are formed using the method for forming a semiconductor structure described above to form a semiconductor device. Note that FIGS. 7-21 may further include a first semiconductor structure (not shown).

[0116] In some other examples, after forming the semiconductor layer, the first soldering structure, and the second soldering structure using the above-described method for forming a semiconductor structure, the first semiconductor structure can be bonded to the semiconductor structure on a side away from the semiconductor layer in the Z direction to form a semiconductor device.

[0117] In some examples, the channel structure 210 includes a channel layer and a functional layer surrounding the channel layer, and after removing the base structure 600 to expose a portion of the functional layer, the method includes: After removing the base structure 600, the method further includes removing the exposed portion of the functional layer to expose a portion of the channel layer.

[0118] In some examples, the channel structure 210 can be formed by etching an initial channel structure 211 including an initial functional layer and a channel layer, as shown in Figure 20 or 21. After removing the base structure 600, a portion of the initial functional layer above the top of the stacked structure 100 is exposed and can be removed using an etching process to form the functional layer and expose a portion of the channel layer.

[0119] Although the present disclosure has been described with reference to specific examples, those skilled in the art should understand that the examples are configured to illustrate the present disclosure only, and that equivalent modifications or substitutions can be made without departing from the spirit of the present disclosure. Accordingly, all changes and modifications made to the examples, as long as they are within the spirit of the present disclosure, are within the scope of the claims of this application. [Explanation of symbols]

[0120] 10 Semiconductor Structures 11 channel structure 12 Functional Layers 13 Semiconductor layer 14 Channel Layer 15 Separation layer 16 Contact structure 17a First conductive via structure 17b Second conductive via structure 17c Third conductive via structure 18 Gate line slit (GLS) structure 19a First Pad 19b Second Pad 100 laminated structure 100a Fourth Part 100b Third Part 101 first material layer 101a Conductive layer 101b Sacrificial layer 102 Insulating layer 110 Semiconductor layer 111 semiconductor material layer 120 Separation structure 121 Separation layer 210 channel structure 220 contact structure 230 Gate line slit structure 301 First Part 302 Second Part 310 First soldering structure 320 Second soldering structure 400 First Semiconductor Structure 501 First Opening 502 Second Opening 600 base structure 610 PCB 620 First semiconductor layer

Claims

1. 1. A semiconductor structure comprising: A laminated structure; a semiconductor layer on the laminated structure; a channel structure extending through the stack structure into the semiconductor layer; a contact structure extending along a stacking direction of the stacked structure; a first soldering structure and a second soldering structure; Equipped with the first soldering structure is connected to the contact structure through the semiconductor layer, and the second soldering structure is connected to the semiconductor layer; Semiconductor structure.

2. 2. The semiconductor structure of claim 1, wherein each of the first soldering structure and the second soldering structure comprises a first portion and a second portion on the first portion, the size of the second portion in a first direction being larger than the size of the first portion in the first direction, and the first direction being perpendicular to the stacking direction.

3. 3. The semiconductor structure of claim 2, wherein a size of the first portion in the first direction is a first size, a size of the first portion in the stacking direction is a second size, and a ratio of the second size to the first size is less than 1:

5.

4. The semiconductor structure of claim 2 , wherein the first portion and the second portion are integrally formed.

5. The semiconductor structure according to claim 1 , wherein a portion of the channel structure extending into the semiconductor layer has a size of less than 200 nm in the stacking direction.

6. The semiconductor structure of claim 1 , wherein a top surface of the semiconductor layer directly above the channel structure is flush with a top surface of the semiconductor layer directly above the stack structure.

7. The semiconductor structure of claim 1 , wherein a top surface of the semiconductor layer directly above the channel structure is higher than a top surface of the semiconductor layer directly above the stack structure.

8. 2. The semiconductor structure of claim 1, wherein the material of the first soldering structure and the material of the second soldering structure both comprise aluminum.

9. The semiconductor structure of claim 1 , further comprising an isolation structure located between at least the first soldering structure and the semiconductor layer.

10. 2. The semiconductor structure of claim 1, wherein the stacked structure includes alternating first material layers and insulating layers, and includes a third portion and a fourth portion arranged side by side in a direction perpendicular to the stacking direction; the contact structure passes through the third portion, and the channel structure passes through the fourth portion; the first material layer in the third portion includes a sacrificial layer, and the first material layer in the fourth portion includes a conductive layer.

11. 2. The semiconductor structure of claim 1, wherein the channel structure comprises a functional layer located within the stacked structure and a channel layer located within the stacked structure and extending into the semiconductor layer, the functional layer covering a sidewall of the channel layer within the stacked structure.

12. A semiconductor device comprising a first semiconductor structure and the semiconductor structure of any one of claims 1 to 11, the first semiconductor structure is located on one of two opposite sides of the semiconductor structure, away from the semiconductor layer in the stacking direction, and is connected to the semiconductor structure by hybrid bonding; Semiconductor devices.

13. The first semiconductor structure comprises: peripheral circuitry connected to the contact structure within the semiconductor structure; The semiconductor device of claim 12 , comprising:

14. 1. A method of forming a semiconductor structure, comprising: providing a stack structure, a contact structure, and a channel structure, wherein the channel structure penetrates the stack structure and protrudes above the stack structure, and the contact structure extends along a stacking direction of the stack structure; forming a semiconductor layer on the stacked structure and the channel structure from a side where the channel structure protrudes above the stacked structure; forming a first soldering structure and a second soldering structure, the first soldering structure penetrating the semiconductor layer and connecting with the contact structure, and the second soldering structure connecting with the semiconductor layer; A forming method comprising:

15. The step of forming the semiconductor layer on the stack structure and the channel structure includes: forming a semiconductor material layer over the stack structure, the channel structure, and the contact structure, wherein an upper surface of the semiconductor material layer directly above the channel structure and an upper surface of the semiconductor material layer directly above the contact structure are higher than an upper surface of the semiconductor material layer directly above the stack structure; removing a portion of the semiconductor material layer to form a first opening exposing the contact structure, with the remainder of the semiconductor material layer forming the semiconductor layer; The method of claim 14 , comprising:

16. The step of forming the semiconductor layer on the stack structure and the channel structure includes: planarizing the semiconductor material layer so that the top surface of the semiconductor material layer directly above the channel structure is flush with the top surface of the semiconductor material layer directly above the stack structure before forming the first opening. The method of claim 15 further comprising:

17. forming an isolation layer covering the sidewalls and bottom of the first opening and the semiconductor layer; removing at least a portion of the isolation layer on the bottom of the first opening to expose the contact structure; removing a portion of the isolation layer over the semiconductor layer to form a second opening, through which the semiconductor layer is exposed and a remainder of the isolation layer forms an isolation structure; The method of claim 15 further comprising:

18. The step of forming the first soldering structure and the second soldering structure includes: forming the first soldering structure in at least the first opening and the second soldering structure in at least the second opening after forming the isolation structure, wherein each of the first soldering structure and the second soldering structure comprises a first portion and a second portion on the first portion, the first portion of the first soldering structure being located in the first opening and the second portion of the second soldering structure being located in the second opening.

20. The method of claim 17, comprising:

19. The step of providing the stack structure, the contact structure, and the channel structure comprises: forming the stack structure, the contact structure, and the channel structure on a base structure, the base structure comprises a substrate and a first semiconductor layer between the substrate and the stack structure, and the channel structure extends within the first semiconductor layer; or the base structure comprises a substrate, and the channel structure extends within the substrate; Steps and removing the base structure to expose a portion of the channel structure; The method of claim 14 , comprising:

20. The channel structure includes a channel layer and a functional layer surrounding the channel layer, and after removing the base structure to expose a portion of the functional layer, the method includes: removing the exposed portion of the functional layer after removing the base structure to expose a portion of the channel layer; 20. The method of claim 19, further comprising:

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