Linked list data structure, data processing method therefor, recording medium, and electronic device

Abstract

The present application relates to a linked list data structure and its data processing method, recording medium, and electronic device, which includes a RAM, an empty address management unit, and a multi-headed linked list, and the multi-headed linked list includes a control unit, a write operation sublist indication unit, a read operation sublist indication unit, and n sublists, and the sublists include a sublist length unit, a write pointer unit, and a read pointer unit. Based on the linked list data structure, the present application enables the n-headed linked list to issue a read command every clock cycle and output data every clock cycle.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to a Chinese patent application bearing application number 2023102331281 and entitled "Linked list data structure and data processing method therefor, recording medium, and electronic device," filed with the State Intellectual Property Office of the People's Republic of China on March 13, 2023, the entire contents of which are incorporated herein by reference.

[0002] The present application relates to the technical field of reading and writing linked list data, and more particularly to a linked list data structure, a data processing method thereof, a computer-readable recording medium, and an electronic device. [Background technology]

[0003] Linked list data structures are often used in digital circuit design. As shown in Figure 1, in a linked list data structure, each piece of data is followed by a pointer, which points to the address of the next piece of data. Typically, both the data and the pointer are stored in RAM (Random Access Memory), and the pointer is the address of the data in RAM. When reading a piece of data from RAM, the data and its corresponding pointer are read at the same time. Therefore, the address where the next piece of data and its corresponding pointer are located in RAM can be identified based on the pointer corresponding to the piece of data, and the RAM can be accessed based on this address to read the next piece of data and its corresponding pointer.

[0004] Because RAM typically has read delays, a traditional linked list data structure typically requires three to four clock cycles to read the result after issuing a read request. Therefore, after reading one piece of data, it takes three to four clock cycles for the address of the next piece of data to be known and the read can begin. This creates a problem: data read efficiency is low for linked list data structures. Figure 2 specifically illustrates the traditional linked list data structure. In Figure 2, a read command for address A0 is issued at time T0. Data D0 is obtained at time T3, three clock cycles later. At the next clock cycle, T4, the address of the next piece of data, A1, is obtained based on data D0, and a read command is issued. Three more clock cycles are then required to obtain the next piece of data, D1. In Figure 2, it takes an average of four clock cycles to read one piece of data. This performance is insufficient for many high-bandwidth designs, which typically require one piece of data to be read per clock cycle. For example, if the system clock is 1GHz and the data width is 512 bits, if one piece of data is output in four clock cycles, the system bandwidth will be 128Gbps, but if one piece of data is output in one clock cycle, the system bandwidth will reach 512Gbps. Summary of the Invention

[0005] An object of the present application is to provide a linked list data structure, a data processing method therefor, a computer-readable recording medium, and an electronic device.

[0006] In order to achieve the above object, a first aspect of the present application provides a linked list data structure, the linked list data structure including a RAM, a free address management unit, and a multi-headed linked list, the multi-headed linked list including a control unit, a write operation sublist indication unit, a read operation sublist indication unit, and n sublists, n being a positive integer of 2 or more, the sublists including a control unit, a sublist length unit, a write pointer unit, and a read pointer unit, the RAM including a plurality of data units and a plurality of pointer storage units corresponding one-to-one to the plurality of data units, each data unit and its corresponding one pointer storage unit sharing the same address in the RAM, the data unit is used to store data; The pointer unit is used to store an address, and when one data unit stores the i-th data of one sublist, the pointer unit corresponding to the one data unit is used to store the address of the data unit where the i+1-th data of the one sublist is located; the free address management unit is used to manage free addresses in the RAM, and when receiving a free address read request from the control unit, to output one free address to the control unit; The write operation sublist indication unit is used to store a sublist number of a write target sublist, and the write target sublist is a sublist into which data to be written is to be written; The read operation sublist indication unit is used to store a sublist number of a sublist to be read, and the sublist number of the sublist to be read is a sublist where the data to be read is located; The sublist length unit is used to store sublist length information, and the sublist length information is the number of data currently stored in the sublist; the write pointer unit is used to store the address in the RAM of the currently written data in the multi-headed linked list; the read pointer unit is used to store the address in the RAM of the next data to be read from the multi-headed linked list; When the control unit receives a data write request, it identifies a write target sublist based on the sublist number stored in the write operation sublist instruction unit, and performs a data write operation based on the free address, the sublist length information stored in the sublist length unit of the write target sublist, and the address stored in the write pointer unit; when the control unit receives a data read request, it identifies a read target sublist based on the sublist number stored in the read operation sublist instruction unit, and performs a data read operation based on the address stored in the read pointer unit of the read target sublist.

[0007] According to the linked list data structure provided in the first aspect of the present application, when storing n consecutive data, one data is written to one sublist in one clock cycle, and the n data are written sequentially to each of the n sublists of the n-head linked list in successive n clock cycles, completing the writing of the n data. Therefore, when subsequently reading the n consecutive data, one data is read from each sublist in one clock cycle, and data is read from each of the n sublists in successive n clock cycles to obtain the n data. In this way, the n-head linked list makes it possible to issue a read command in each clock cycle and output data in each clock cycle.

[0008] A second aspect of the present application provides a data processing method for the above linked list data structure, the method including: when the control unit receives a data write request, performing a data write operation; performing the data write operation, Obtaining data to be written based on the data write request; reading out a sublist number stored in the write operation sublist instruction unit, identifying a write target sublist based on the sublist number stored in the write operation sublist instruction unit, and obtaining sublist length information stored in a sublist length unit of the write target sublist and an address stored in a write pointer unit of the write target sublist; Sending an empty address read request to the empty address management unit and receiving one empty address returned from the empty address management unit; writing the data to be written to a data unit corresponding to the free address in the RAM; determining whether to write the free address to a pointer storage unit in the RAM corresponding to the address stored in a write pointer unit of the sublist to be written, based on sublist length information stored in a sublist length unit of the sublist to be written; updating the sublist number stored in the write operation sublist instruction unit to the sublist number of the next sublist to be written; updating the address stored in the write pointer unit of the write target sublist to the free address; and updating sublist length information stored in a sublist length unit of the sublist to be written based on the number of data currently stored in the sublist to be written.

[0009] A data processing method according to a second aspect of the present invention is implemented based on the linked list data structure according to the first aspect of the present invention. When storing n consecutive data, one data item is written to one sublist in one clock cycle, and the n data items are sequentially written to each of the n sublists of the n-head linked list in n consecutive clock cycles, completing the writing of the n data items. Correspondingly, when subsequently reading the n consecutive data items, one data item is read from each sublist in one clock cycle, and data is sequentially read from each of the n sublists in n consecutive clock cycles to obtain the n data items. In this way, the n-head linked list allows a read command to be issued in each clock cycle, and data to be output in each clock cycle.

[0010] A third aspect of the present application provides a computer-readable recording medium having a computer program stored therein, the computer program being executed by a processor to realize the data processing method described in the second aspect of the present application.

[0011] A fourth aspect of the present application provides an electronic device including a processor, a memory, and a computer program stored in the memory and executable by the processor, which, when executed by the processor, realizes the data processing method described in the second aspect of the present application.

[0012] A fifth aspect of the present application provides a chip including a processor and a memory, The processor calls up and executes a computer program from the memory, and a device incorporating the chip is used to execute the data processing method according to the second aspect of the present application.

[0013] A sixth aspect of the present application provides a computer program product, the computer program product including associated program instructions which, when executed, result in the data processing method according to the second aspect of the present application.

[0014] A seventh aspect of the present application provides a computer program comprising program instructions which, when executed on an electronic device, cause the computer device to perform the data processing method according to the second aspect of the present application.

[0015] In an eighth aspect of the present application, there is provided an apparatus, the apparatus may include at least one processor, and associated program instructions, when executed by the at least one processor, cause the apparatus to implement the data processing method according to the second aspect of the present application.

[0016] Other features and advantages of the present application are described in the following specification.

[0017] In order to more clearly describe the embodiments of the present invention or the technical solutions of the prior art, the drawings necessary for describing the embodiments or the prior art will be briefly described. The drawings described below are only shown in the embodiments of the present invention, and it is clear that those skilled in the art can obtain drawings of other embodiments based on these drawings without any creative efforts. [Brief explanation of the drawings]

[0018] [Figure 1] FIG. 1 is a schematic diagram of a linked list data structure in the prior art. [Figure 2] FIG. 1 is a schematic diagram of a data reading process of a linked list data structure in the prior art; [Figure 3] FIG. 2 is a schematic diagram of a linked list data structure in one embodiment of the present application; [Figure 4] FIG. 1 is a schematic diagram of the process of reading and writing a linked list data structure in one embodiment of the present application; [Figure 5]1 is a flowchart illustrating a data write operation according to an embodiment of the present application. [Figure 6] FIG. 1 is a schematic diagram of a data writing process for one multi-headed linked list in an embodiment of the present application. [Figure 7] 1 is a flowchart illustrating a data read operation according to an embodiment of the present application. DETAILED DESCRIPTION OF THE INVENTION

[0019] The detailed description of the drawings is intended as an illustration of the presently preferred embodiments of the present application and is not intended to represent the only form in which the present application can be implemented. It is to be understood that the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the present application.

[0020] One embodiment of the present application provides a linked list data structure. Referring to FIG. 3, the linked list data structure of this embodiment includes a RAM, an empty address management unit, and a multi-headed linked list. The multi-headed linked list includes a control unit, a write operation sublist indication unit, a read operation sublist indication unit, and n sublists, where n is a positive integer greater than or equal to 2, and each of the n sublists includes a sublist length unit, a write pointer unit, and a read pointer unit. The RAM includes a plurality of data units and a plurality of pointer storage units that correspond one-to-one to the plurality of data units, and any data unit and its corresponding pointer storage unit share the same address in the RAM.

[0021] The data unit is used to store data, and specifically, one data unit stores one piece of data.

[0022] The pointer storage units are used to store addresses, for example, one pointer storage unit stores one address. When one data unit is used to store the i-th data of one sublist, the pointer storage unit corresponding to this one data unit is used to store the address of the data unit where the (i+1)-th data of this one sublist is located, that is, the address stored in the pointer storage unit is used to represent the relationship between two data.

[0023] The free address management unit manages free addresses in the RAM, and is used to output one free address to the control unit when a free address read request is received from the control unit.

[0024] The write operation sublist indication unit is used to store the sublist number of a write target sublist, where the write target sublist is the sublist to which the data to be written is to be written. Specifically, the write operation sublist indication unit provides a write target sublist indication, and the control unit knows which sublist the data to be currently written needs to be written to based on the indication of the write operation sublist indication unit. For a multi-headed linked list, only one piece of data is written to that one sublist in each clock cycle, and if data needs to be written in the next clock cycle, the data is written to the next sublist in the next clock cycle.

[0025] The read operation sublist indication unit is used to store the sublist number of the read target sublist, which is the sublist where the data to be read is located. Specifically, the read operation sublist indication unit provides a read target sublist indication, and the control unit knows which sublist the data to be currently read is stored in based on the indication of the read operation sublist indication unit. For a multi-headed linked list, only one piece of data is read from one sublist in each clock cycle, and if data needs to be read in the next clock cycle, the data is read from the next sublist in the next clock cycle, and the reading of data corresponds one-to-one to the writing order of the data.

[0026] The sublist length unit is used to store sublist length information, and the sublist length information is the number of data that the sublist currently stores.

[0027] The write pointer unit is used to store the address where the currently written data in the multi-headed linked list resides in the RAM, and specifically, the address stored in the write pointer unit is updated after the data has been written. The read pointer unit is used to store the address where the next data to be read from the multi-headed linked list is stored in the RAM, and specifically, the address stored in the read pointer unit is updated after the data has been read. When the control unit receives a data write request, it identifies a write target sublist based on the sublist number stored in the write operation sublist instruction unit, and performs a data write operation based on the free address, the sublist length information stored in the sublist length unit of the write target sublist, and the address stored in the write pointer unit; when the control unit receives a data read request, it identifies a read target sublist based on the sublist number stored in the read operation sublist instruction unit, and performs a data read operation based on the address stored in the read pointer unit of the read target sublist. The linked list data structure of this embodiment can include one or more multi-head linked lists, with each multi-head linked list having the same structure and operating principle. Therefore, this embodiment will be described using one multi-head linked list, and the number of sublists n in each multi-head linked list is determined by the time required to read the linked list data. For example, in the multi-head linked list read process shown in FIG. 4, the value of n is set to 4. This is because if a data read request is issued in T8 clock cycles and data at address A8 in the first sublist is read, the data at address A8 is returned in T11 clock cycles, meaning that it takes four clock cycles to read one piece of data. Therefore, the number of sublists n in the multi-head linked list is set to 4 so that data can be read in each clock cycle. Generally, reading one piece of data requires 3 to 4 clock cycles, so n can be set to 3 or 4, specifically determined by the time required to read the data.

[0028] Continuing to refer to FIG. 4, in this embodiment, when writing data, the data is written to each sublist sequentially, i.e., data D0 is written to address A0 of the first sublist at clock cycle T0, data D1 is written to address A1 of the second sublist at clock cycle T1, data D2 is written to address A2 of the third sublist at clock cycle T2, and data D3 is written to address A3 of the second sublist at clock cycle T3.

[0029] When reading data, data is read sequentially from each sublist, i.e., data at address A8 is read from the first sublist in clock cycle T8, data at address A9 is read from the second sublist in clock cycle T9, data at address A10 is read from the third sublist in clock cycle T10, and data at address A11 is read from the fourth sublist in clock cycle T11. Then, data D8 at address A8 is also returned in clock cycle T11, and data at address A12 can be read again from the first sublist in clock cycle T12.

[0030] According to the above, in this embodiment, through the duplication of sublists, one multi-headed linked list can issue a read command in each clock cycle and output one piece of data in each clock cycle. That is, in Figure 4, in the eight clock cycles T11 to T18, data is output in each clock cycle, thereby improving the data read efficiency of the linked list data structure and solving the technical problem of the low data read efficiency of the conventional linked list data structure.

[0031] In the linked list data structure of this embodiment, the free address management unit may be a FIFO device, and when one address in the RAM becomes free, the free address may be written to the FIFO device.

[0032] Specifically, the FIFO device operates on the principle of first-in, first-out (First Input, First Output), meaning that the free address written to the FIFO device first is output first. That is, in one clock cycle, the free address management unit receives one free address read request from the control unit and outputs one free address in RAM for use in writing data. Assuming the RAM storing linked list data has a depth of 1024, when initializing the linked list, 0, 1, 2, ..., 1023 are written sequentially to the free address management unit, indicating that all of these RAM addresses are initially free and available for allocation.

[0033] In the linked list data structure of this embodiment, the write operation sublist indication unit, the read operation sublist indication unit, and the sublist length unit may be registers.

[0034] Specifically, the function of a register is to store binary codes, and it is composed of a combination of flip-flops with storage functions. Since one flip-flop can store one bit of binary code, a register that stores n-bit binary codes must be composed of n flip-flops. For example, in the case of a multi-headed linked list containing four sublists, the registers of its write operation sublist indication unit and read operation sublist indication unit must represent four binary codes from 0 to 3, namely 00, 01, 10, and 11.

[0035] Based on the linked list data structure of the above embodiment, another embodiment of the present application provides a data processing method for a linked list data structure, the method including: performing a data write operation when the control unit receives a data write request. As shown in FIG. 5, performing the data write operation includes the following steps: Step S11: Obtain the data to be written based on the data write request. Step S12: The sublist number stored in the write operation sublist instruction unit is read, the write target sublist is identified based on the sublist number stored in the write operation sublist instruction unit, and the sublist length information stored in the sublist length unit of the write target sublist and the address stored in the write pointer unit of the write target sublist are obtained. Step S13: A free address read request is sent to the free address management unit, and one free address returned from the free address management unit is received. Step S14: The data to be written is written to the data unit corresponding to the empty address in the RAM. Step S15: Based on the sublist length information stored in the sublist length unit of the sublist to be written, it is determined whether or not to write the free address to the pointer storage unit in the RAM corresponding to the address stored in the write pointer unit of the sublist to be written. Step S16: The sublist number stored in the write operation sublist instruction unit is updated to the sublist number of the next sublist to be written. Step S17: The address stored in the write pointer unit of the write target sublist is updated to the free address. Step S18: Based on the number of data currently stored in the sublist to be written, the sublist length information stored in the sublist length unit of the sublist to be written is updated. Specifically, the sublist length information is equal to the number of data items currently stored in the sublist. That is, if no data items have been written, the sublist length information is 0. After the first data item is written, the sublist length information is updated to 1. Each time data items are written, the sublist length information is updated by incrementing it by 1.

[0036] In the data processing method of this embodiment, step S15 may include the following. Based on the sublist length information stored in the sublist length unit of the write target sublist, it is determined whether the data to be written is the first data to be written to the write target sublist, and if it is the first data, it is determined that the pointer storage unit corresponding to the address stored in the write pointer unit of the write target sublist in the RAM is empty, and if it is not the first data, it writes the empty address to the pointer storage unit corresponding to the address stored in the write pointer unit of the write target sublist in the RAM.

[0037] Specifically, referring to Figure 6, Figure 6 shows the data writing process of one multi-headed linked list. In Figure 6, data D0, D1, D2, and D3 are sequentially stored in four data units (RAM) of four sublists. At this time, when data D0, D1, D2, and D3 are stored in the four sublists, they are all the first data to be stored in the sublists. At this time, after the data unit operation of the sequential / sublist of data D0 / D1 / D2 / D3 / / is completed, the contents of the pointer storage unit corresponding to the data unit are not updated. At this time, the address of the next data to be written to the sublist is not yet known and cannot be pointed to, so the contents of the pointer storage unit should be empty.

[0038] When the first sublist receives another write request for data D4, the sublist length information at this point is 1, and the acquired free address is 4. Then, data D4 is stored in the data unit of RAM corresponding to the previously acquired free address 4, and at the same time, the value of free address 4 is stored in the pointer storage unit of the address (address 0) stored in the write pointer unit of the sublist. That is, the data unit at address 0 stores data D0, and the pointer storage unit stores address 4. After that, the content stored in the write pointer unit of the sublist is updated from address 0 to address 4, and the write pointer unit of the sublist points to address 4, indicating that data has now been written up to the data unit at address 4.

[0039] In the data processing method of this embodiment, if the sublist to be written into which the data to be written is to be written is the i-th sublist among the n sublists, the corresponding next sublist to be written is the i+1-th sublist, and if the sublist to be written into which the data to be written is to be the n-th sublist among the n sublists, the corresponding next sublist to be written may be the 1st sublist.

[0040] Specifically, referring to Figure 4, data is written to the n sublists in the order of their sublist numbers, with the corresponding sublist selected and data written to it at each clock cycle, and the n sublists are cycled through. In Figure 4, data can be written to and stored in each sublist once every n clock cycles.

[0041] The data processing method of this embodiment may further include, when the control unit receives a data read request, performing a data read operation. As shown in FIG. 7, performing the data read operation includes the following steps: Step S21: A sublist to be read is identified based on the sublist number stored in the read operation sublist instruction unit, and the address stored in the read pointer unit of the sublist to be read is obtained. Step S22: The data in the data unit corresponding to the address stored in the read pointer unit in the RAM and the address in the pointer storage unit are read. Specifically, when reading data, the data of the data unit and the address of the corresponding pointer storage unit are also read, and the use of the address of the pointer storage unit will be described in the subsequent steps. Step S23: The read data is output. Specifically, the data read request is output to the request source that issued the data read request. Step S24: The sublist number stored in the read operation sublist instruction unit is updated to the sublist number of the next sublist to be read. Step S25: The address stored in the read pointer unit is updated to the read address.

[0042] In the data processing method of this embodiment, performing the data read operation may further include the following steps: Step S26: When the data in the data unit and the address in the pointer storage unit at one address in the RAM are read, the read address is written to the free address management unit.

[0043] Specifically, after the data and pointer address of one address in the RAM are read, this one address is released and written back to the free address management unit so that it can be subsequently used.

[0044] In the data processing method of this embodiment, when the sublist to be read in which the data to be read is located is the i-th sublist among the n sublists, the corresponding next sublist to be read is the i+1-th sublist, where 1≦i≦n−1; and when the sublist to be read in which the data to be read is located is the n-th sublist among the n sublists, the corresponding next sublist to be read may be the 1st sublist.

[0045] Specifically, referring to Figure 4, corresponding to the data storage, data reading from the n sublists is also used in each clock cycle in the order of the sublist numbers, and the n sublists are cycled through. In Figure 4, each sublist can read data once every n clock cycles.

[0046] Note that the method of this embodiment is realized based on the linked list data structure of the above embodiment, and therefore, the contents not described in detail in the method of this embodiment can be obtained by referring to the linked list data structure of the above embodiment, and will not be repeated here.

[0047] Another embodiment of the present application provides a computer-readable recording medium having a computer program stored therein, the computer program realizing the data processing method for a linked list data structure described in the above embodiment when executed by a processor.

[0048] Specifically, the computer-readable recording medium may include any entity or recording medium capable of carrying the computer program instructions, such as a USB memory, a mobile hard disk, a magnetic disk, an optical disk, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier wave signal, a telecommunications signal, and a software distribution medium.

[0049] Another embodiment of the present application provides an electronic device including a processor, a memory, and a computer program stored in the memory and executable on the processor, which, when executed by the processor, implements the data processing method for a linked list data structure described in the above embodiment.

[0050] The electronic device may further include a bus connecting different components (including the memory and the processor). The memory may include a computer-readable medium in the form of a volatile memory, such as a random access memory (RAM) and / or a cache memory. The memory may also include at least one program product, which has a set (e.g., at least one) program module configured to perform the functions of each embodiment of the present application. The electronic device may also communicate with one or more external devices (e.g., a keyboard, a pointing device, a display, etc.), and may further communicate with one or more devices that allow a user to interact with the electronic device and / or any device (e.g., a network card) that allows the electronic device to communicate with one or more other computing devices; such communication may occur via an input / output (I / O) interface; and the electronic device may also communicate with one or more networks (e.g., a local area network (LAN), a wide area network (WAN), and / or a public network such as the Internet) via a network adapter.

[0051] Another embodiment of the present application provides a chip including a processor and a memory, The processor is used to call up and execute a computer program from the memory, causing a device equipped with the chip to execute the data processing method.

[0052] Another embodiment of the present application provides a computer program product, the computer program product including associated program instructions that, when executed, implement the above data processing method.

[0053] Another embodiment of the present application provides a computer program comprising program instructions which, when executed on an electronic device, cause the computing device to perform the above data processing method.

[0054] Another embodiment of the present application provides an apparatus, which may include at least one processor, and associated program instructions executed by the at least one processor cause the apparatus to implement the data processing method.

[0055] Although the embodiments of the present application have been described above, the above description is illustrative and not exhaustive, and is not limited to the disclosed embodiments. Many updates and modifications will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used in this specification are selected to best explain the principles, practical applications, or technical improvements in the market of the embodiments, or to enable other ordinary skilled in the art to understand the embodiments disclosed herein.

Claims

1. 1. A linked list data structure comprising: The memory device includes a RAM, a free address management unit, and a multi-headed linked list, the multi-headed linked list including a control unit, a write operation sublist indication unit, a read operation sublist indication unit, and n sublists, n being a positive integer of 2 or more, the sublists including a sublist length unit, a write pointer unit, and a read pointer unit, the RAM including a plurality of data units and a plurality of pointer units corresponding one-to-one to the plurality of data units, and any one data unit and one corresponding pointer unit share one address in the RAM, the data unit is used to store data; The pointer unit is used to store an address, and when one data unit stores the i-th data of one sublist, the pointer unit corresponding to the one data unit is used to store the address of the data unit in which the i+1-th data of the one sublist is located; the free address management unit is used to manage free addresses in the RAM, and when receiving a free address read request from the control unit, to output one free address to the control unit; The write operation sublist indication unit is used to store a sublist number of a write target sublist, and the write target sublist is a sublist into which data to be written is to be written; The read operation sublist indication unit is used to store a sublist number of a sublist to be read, and the sublist number of the sublist to be read is a sublist where the data to be read is located; The sublist length unit is used to store sublist length information, and the sublist length information is the number of data currently stored in the sublist; the write pointer unit is used to store the address at which currently written data in the multi-headed linked list resides in the RAM; the read pointer unit is used to store the address at which the next data to be read from the multi-headed linked list is located in the RAM; a control unit that, when receiving a data write request, identifies a write target sublist based on the sublist number stored in the write operation sublist indication unit, and executes a data write operation based on the free address, sublist length information stored in the sublist length unit of the write target sublist, and an address stored in the write pointer unit; and, when receiving a data read request, identifies a read target sublist based on the sublist number stored in the read operation sublist indication unit, and executes a data read operation based on the address stored in the read pointer unit of the read target sublist.

2. 2. The linked list data structure of claim 1, wherein the free address management unit is a FIFO device, and when an address in the RAM becomes free, the free address is written to the FIFO device.

3. 2. The linked list data structure of claim 1, wherein the write operation sublist indication unit, the read operation sublist indication unit, and the sublist length unit are registers.

4. 1. A data processing method comprising: The method is used for a linked list data structure according to any one of claims 1 to 3, and includes the control unit performing a data write operation when it receives a data write request; performing the data write operation, obtaining data to be written based on the data write request; reading out a sublist number stored in the write operation sublist instruction unit, identifying a write target sublist based on the sublist number stored in the write operation sublist instruction unit, and obtaining sublist length information stored in a sublist length unit of the write target sublist and an address stored in a write pointer unit of the write target sublist; Sending an empty address read request to the empty address management unit and receiving one empty address returned from the empty address management unit; writing the data to be written to a data unit corresponding to the free address in the RAM; determining whether to write the free address to a pointer unit in the RAM corresponding to the address stored in a write pointer unit of the sublist to be written, based on sublist length information stored in a sublist length unit of the sublist to be written; updating the sublist number stored in the write operation sublist instruction unit to the sublist number of the next sublist to be written; updating the address stored in the write pointer unit of the write target sublist to the free address; updating sublist length information stored in a sublist length unit of the sublist to be written based on the number of data currently stored in the sublist to be written.

5. Determining whether to write the free address to a pointer unit in the RAM corresponding to the address stored in a write pointer unit of the sublist to be written based on sublist length information stored in a sublist length unit of the sublist to be written, 5. The data processing method according to claim 4, further comprising: determining whether the data to be written is the first data to be written to the write target sublist based on sublist length information stored in a sublist length unit of the write target sublist; if the data is the first data, identifying a pointer unit in the RAM corresponding to an address stored in a write pointer unit of the write target sublist as empty; and if the data is not the first data, writing the empty address to a pointer unit in the RAM corresponding to an address stored in the write pointer unit of the write target sublist.

6. When the sublist to be written into which the data to be written is to be written is the i-th sublist among the n sublists, the corresponding next sublist to be written is the i+1-th sublist; 5. The data processing method according to claim 4, wherein when the sublist to be written into which the data to be written is to be written is the nth sublist among the n sublists, the corresponding next sublist to be written is the first sublist.

7. 1. A data processing method comprising: The method is used for a linked list data structure according to any one of claims 1 to 3, and includes the control unit performing a data read operation when it receives a data write request; performing the data read operation, Identifying a read target sublist based on a sublist number stored in the read operation sublist indication unit, and obtaining an address stored in a read pointer unit of the read target sublist; reading data in a data unit and an address in a pointer unit corresponding to the address stored in the read pointer unit in the RAM; Outputting the read data; updating the sublist number stored in the read operation sublist instruction unit to the sublist number of the next sublist to be read; updating the address stored in the read pointer unit to the read address.

8. Performing the data read operation further comprises:

8. The data processing method according to claim 7, further comprising, when data in a data unit and an address in a pointer unit of one address in the RAM are read, writing the read address to the free address management unit.

9. When the sublist to be read in which the data to be read is located is the i-th sublist among the n sublists, the corresponding next sublist to be read is the i+1-th sublist, where 1≦i≦n−1; 8. The data processing method according to claim 7, wherein when the sublist to be read in which the data to be read is located is the nth sublist among the n sublists, the corresponding next sublist to be read is the first sublist.

10. A computer-readable recording medium, A computer-readable recording medium, characterized in that a computer program is stored in the computer-readable recording medium, and when the computer program is executed by a processor, the data processing method according to any one of claims 4 to 9 is realized.

11. 1. An electronic device comprising: An electronic device comprising a processor, a memory, and a computer program stored in the memory and executable by the processor, wherein when the processor executes the program, the electronic device realizes the data processing method according to any one of claims 4 to 9.

12. A chip, a processor and a memory, The processor calls and executes a computer program from the memory, and a device equipped with the chip is used to execute the data processing method according to any one of claims 4 to 9.

13. 1. A computer program product comprising: The computer program product comprises associated program instructions, the associated program instructions, when executed, resulting in the data processing method of any one of claims 4 to 9.

14. A computer program comprising: A computer program comprising program instructions which, when executed on an electronic device, cause the computer device to carry out the data processing method of any one of claims 4 to 9.

15. 1. An apparatus comprising: The apparatus may include at least one processor, characterised in that associated program instructions, when executed by the at least one processor, cause the apparatus to implement the data processing method of any one of claims 4 to 9.

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