3D dynamic random access memory (DRAM) and method for fabricating 3D-DRAM

Abstract

The three-dimensional (3D) dynamic random access memory (DRAM) includes a substrate and a plurality of nanosheet transistors vertically stacked on a surface of the substrate. Each of the nanosheet transistors has a gate, a source, and a drain. A plurality of bit lines are connected to corresponding drains of the nanosheet transistors on one side of the plurality of nanosheet transistors. A plurality of capacitors are vertically stacked on the substrate, extend parallel to the surface of the substrate, and are connected to corresponding sources of the plurality of nanosheet transistors on the other side of the plurality of nanosheet transistors.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 420,179, filed October 28, 2022, and U.S. Provisional Application No. 63 / 438,083, filed January 10, 2023. The entire disclosures of the above-referenced applications are incorporated herein by reference. [Technical Field]

[0002] The present disclosure relates to memory, and more particularly to 3D dynamic random access memory (3D-DRAM) and methods for fabricating 3D-DRAM. [Background technology]

[0003] The background description provided herein is intended to present the contents of the present disclosure generally. Work by the presently named inventors within the scope of what is described in this Background section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure.

[0004] Dynamic random access memory (DRAM) stores each bit of data in a memory cell. Each memory cell contains a capacitor and one or more transistors. The memory is typically based on metal-oxide-semiconductor (MOS) technology. Advanced DRAM is typically processed with two transistors per active area (e.g., FinFET-based). The transistor gate is connected (or contacted) to a word line. The drain is contacted to a bit line. A storage node contact connects the transistor source to the memory cell's vertical metal capacitor. Current 3D DRAM architectures are experiencing scaling saturation due to the high aspect ratios required for contact and capacitor processing. Summary of the Invention

[0005] A three-dimensional (3D) dynamic random access memory (DRAM) includes a substrate and a plurality of nanosheet transistors vertically stacked on the surface of the substrate, each nanosheet transistor having a gate, a source, and a drain. The 3D DRAM includes a first staircase, a plurality of bit line contacts, a plurality of bit lines connected to corresponding drains of the nanosheet transistors in the first staircase by the plurality of bit line contacts, a plurality of second staircases, a plurality of third staircases, a plurality of capacitor contacts, and a plurality of storage node contacts including first ends connected to corresponding sources of the plurality of nanosheet transistors. A plurality of capacitors are vertically stacked on the substrate and extend parallel to the surface of the substrate. First ends of the plurality of capacitors located adjacent to the plurality of nanosheet transistors are connected to first ends of corresponding plurality of capacitor contacts in corresponding plurality of second staircases. Second ends of the plurality of capacitor contacts are connected to second ends of corresponding plurality of storage node contacts in corresponding plurality of third staircases.

[0006] In other features, the first staircase comprises a two-dimensional (2D) staircase. The first staircase descends in first and second orthogonal directions relative to a surface of the substrate. At least a portion of the first staircase extends below the surface of the substrate. The first staircase and the plurality of bit lines are disposed on one side of the plurality of nanosheet transistors. The plurality of second staircases, the plurality of third staircases, and the capacitor are disposed on the opposite side of the plurality of nanosheet transistors.

[0007] In other features, the capacitor contact is J-shaped and has multiple vertical lengths across the surface of the substrate. The multiple second steps are alternately arranged between the multiple third steps. The multiple second steps descend in a direction toward the multiple nanosheet transistors. The multiple third steps ascend in a direction toward the multiple nanosheet transistors. The gates of the multiple nanosheet transistors include forked sheet gates corresponding to word lines.

[0008] The three-dimensional (3D) dynamic random access memory (DRAM) includes a substrate and a plurality of nanosheet transistors vertically stacked on a surface of the substrate. Each of the nanosheet transistors has a gate, a source, and a drain. A plurality of bit lines are connected to corresponding drains of the nanosheet transistors on one side of the plurality of nanosheet transistors. A plurality of capacitors are vertically stacked on the substrate, extend parallel to the surface of the substrate, and are connected to corresponding sources of the plurality of nanosheet transistors on the other side of the plurality of nanosheet transistors.

[0009] In other features, a plurality of bit lines are connected to corresponding drains of the nanosheet transistors in the first staircase by a plurality of bit line contacts.

[0010] In other features, the 3D DRAM includes a plurality of second staircases, a plurality of third staircases, a plurality of capacitor contacts, and a plurality of storage node contacts including first ends connected to corresponding sources of the plurality of nanosheet transistors, wherein the first ends of the plurality of capacitors located adjacent to the plurality of nanosheet transistors are connected to the first ends of the corresponding plurality of capacitor contacts in the corresponding plurality of second staircases, and the second ends of the plurality of capacitor contacts are connected to the second ends of the corresponding plurality of storage node contacts in the corresponding plurality of third staircases.

[0011] In other features, the first staircase comprises a two-dimensional (2D) staircase. The first staircase descends in first and second orthogonal directions relative to the surface of the substrate. At least a portion of the first staircase extends below the surface of the substrate. The capacitor contact is J-shaped and has multiple vertical lengths across the surface of the substrate. The multiple second staircases are interleaved with the multiple third staircases.

[0012] In other features, the plurality of second steps descend in a direction toward the plurality of nanosheet transistors, and the plurality of third steps ascend in a direction toward the plurality of nanosheet transistors, wherein gates of the plurality of nanosheet transistors comprise forked sheet gates corresponding to word lines.

[0013] A method for fabricating a three-dimensional (3D) dynamic random access memory (DRAM) includes alternately depositing first and second layers on a surface of a substrate, patterning active areas of a plurality of nanosheet transistors in the alternating first and second layers, patterning fork-sheet gates of the plurality of nanosheet transistors, selectively doping portions of the plurality of nanosheet transistors, and forming a first staircase that provides a plurality of connection locations to a plurality of bit line contacts on one side of the plurality of nanosheet transistors, and a plurality of second staircases that provide a plurality of connection locations to a plurality of storage node contacts on the opposite side of the plurality of nanosheet transistors.

[0014] In other features, the first staircase descends in first and second orthogonal directions relative to a surface of the substrate. The method includes forming a plurality of capacitors opposite the plurality of nanosheet transistors. The plurality of capacitors are stacked vertically on the substrate and extend parallel to the surface of the substrate.

[0015] In other features, the method includes forming a plurality of third steps between the plurality of second steps to provide connection locations for first ends of the plurality of capacitors. The plurality of second steps ascend in a direction toward the plurality of nanosheet transistors, and the plurality of third steps descend in a direction toward the plurality of nanosheet transistors. The method includes patterning a plurality of capacitor contacts connecting the first ends of the plurality of capacitors to the plurality of storage node contacts. The plurality of capacitor contacts are J-shaped and have a plurality of vertical lengths across the surface of the substrate.

[0016] In other features, the method includes patterning and depositing a plurality of bit lines connected to a corresponding plurality of bit line contacts, wherein at least a portion of the first step extends below a surface of the substrate.

[0017] A three-dimensional (3D) dynamic random access memory (DRAM) includes a substrate and a first array of nanosheet transistors arranged in a first vertical stack on the substrate. The first array comprises N levels of rows, each comprising M nanosheet transistors. A second array of nanosheet transistors is arranged in a second vertical stack on the substrate, the second array comprising N levels of rows, each comprising M nanosheet transistors, where M and N are integers greater than 1. N bit line layers are stacked and vertically aligned with the nanosheet transistors of the first and second arrays of N levels. First sides of channels of M nanosheet transistors in each of the nanosheet transistors of the first array of N levels are connected to first sides of corresponding N bit line layers, and first sides of channels of M nanosheet transistors in each of the nanosheet transistors of the second array of N levels are connected to second sides of corresponding N bit line layers, such that each of the N bit line layers is connected to 2×M nanosheet transistors.

[0018] In other features, a first vertical bit line of the N vertical bit lines is connected to a first vertical bit line layer of the N bit line layers, and the remaining N vertical bit lines are connected to one of the N bit line layers, extend through one or more of the N bit line layers, and are isolated from one or more of the N bit line layers. 2M vertical word lines are connected to the gates of the nanosheet transistors of the first array and the nanosheet transistors of the second array.

[0019] In other features, M of the 2M vertical word lines are each connected to the gates of a first array of vertically aligned nanosheet transistors, and M of the 2M vertical word lines are each connected to the gates of a second array of vertically aligned nanosheet transistors.

[0020] In other features, 2M vertical word lines surround the gates of corresponding first array nanosheet transistors and second array nanosheet transistors. Bridges in the first array connect first sides of the N bit line layer channels to the first array nanosheet transistors. The bridges in the first array include N levels of rows, each including M bridges. Bridges in the second array connect second sides of the N bit line layer channels to the second array nanosheet transistors, the bridges in the second array including N levels of rows, each including M bridges.

[0021] In other features, a first array of capacitors is connected to a second side of the channels of the nanosheet transistors of the first array, the first array of capacitors including N levels of rows each including M capacitors;

[0022] In other features, a second array of capacitors connected to the second sides of the channels of the nanosheet transistors of the second array, the second array of capacitors including N levels of rows each including M capacitors; a first array of bridges connecting the first array of capacitors to the second sides of the channels of the nanosheet transistors of the first array; a first array of bridges including N levels of rows each including M bridges;

[0023] a second array of bridges connecting the capacitors of the second array to second sides of the channels of the nanosheet transistors of the second array, the bridges of the second array including N levels of rows each including M bridges;

[0024] In other features, the capacitors of the first array comprise metal-isolator-metal capacitors, the capacitors of the first array comprising an inner metal layer connected to the second sides of the channels of the nanosheet transistors of the first array, an isolator layer surrounding the inner metal layer, and an outer layer surrounding the inner metal layer.

[0025] A method for fabricating a three-dimensional (3D) dynamic random access memory (DRAM) includes: arranging a first array of nanosheet transistors in a first vertical stack on a substrate, the first array comprising N levels of rows each including M nanosheet transistors; arranging a second array of nanosheet transistors in a second vertical stack on the substrate, the second array comprising N levels of rows each including M nanosheet transistors, where M and N are integers greater than 1; stacking and vertically aligning N bit line layers with the nanosheet transistors of the N levels of the first and second arrays; connecting first sides of channels of the M nanosheet transistors in each of the nanosheet transistors of the first array of N levels to first sides of the N bit line layers and connecting first sides of channels of the M nanosheet transistors in each of the nanosheet transistors of the second array of N levels to second sides of the N bit line layers, such that each of the N bit line layers is connected to 2×M nanosheet transistors.

[0026] In other features, the method includes connecting the first N vertical bit lines to one of the N bit line layers and connecting the remaining N vertical bit lines to one of the N bit line layers, the vertical bit lines extending through and being isolated from the one or more of the N bit line layers.

[0027] In other features, the method includes connecting 2M vertical word lines to gates of the nanosheet transistors of the first array and the nanosheet transistors of the second array. In other features, the method includes connecting M of the 2M vertical word lines to gates of vertically aligned nanosheet transistors of the first array, respectively. In other features, the method includes connecting M of the 2M vertical word lines to gates of vertically aligned nanosheet transistors of the second array, respectively. The 2M vertical word lines surround the gates of corresponding nanosheet transistors of the first array and the nanosheet transistors of the second array.

[0028] In other features, the method includes connecting first sides of the N bit line layer channels to the nanosheet transistors of a first array using bridges of a first array, the bridges of the first array including N levels of rows each including M bridges. The method includes connecting second sides of the N bit line layer channels to the nanosheet transistors of a second array using bridges of a second array, the bridges of the second array including N levels of rows each including M bridges.

[0029] In other features, the method includes connecting a first array of capacitors to second sides of the channels of the first array of nanosheet transistors, the first array of capacitors including N levels of rows each including M capacitors. The method includes connecting a second array of capacitors to second sides of the channels of the second array of nanosheet transistors, the second array of capacitors including N levels of rows each including M capacitors.

[0030] In other features, the method includes connecting the capacitors of the first array to the second sides of the channels of the nanosheet transistors of the first array using bridges of a first array, the bridges of the first array including N levels of rows each including M bridges. In other features, the method includes connecting the capacitors of the second array to the second sides of the channels of the nanosheet transistors of the second array using bridges of a second array, the bridges of the second array including N levels of rows each including M bridges.

[0031] In other features, the capacitors of the first array comprise metal-isolator-metal capacitors, the capacitors of the first array comprising an inner metal layer connected to the second sides of the channels of the nanosheet transistors of the first array, an isolator layer surrounding the inner metal layer, and an outer layer surrounding the inner metal layer.

[0032] Further areas of applicability of the present disclosure will become apparent from the detailed description, claims, and drawings. The detailed description and specific examples are intended for purposes of illustration only and are not intended to limit the scope of the present disclosure. [Brief explanation of the drawings]

[0033] The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein:

[0034] [Figure 1A] FIG. 1A is a cross-sectional view of an example 2D DRAM cell.

[0035] [Figure 1B] FIG. 1B is a cross-sectional view of the example 2D DRAM cell of FIG. 1A rotated in a first plane.

[0036] [Figure 1C] FIG. 1C is a cross-sectional view of the example 2D DRAM cell of FIG. 1B rotated in a second plane.

[0037] [Figure 2A] FIG. 2A is a perspective view of an example of a 3D DRAM integrated circuit according to the present disclosure. [Figure 2B] FIG. 2B is a perspective view of an example of a 3D DRAM integrated circuit according to the present disclosure. [Figure 2C] FIG. 2C is a perspective view of an example of a 3D DRAM integrated circuit according to the present disclosure.

[0038] [Figure 3A] FIG. 3A is a perspective view of an example of 2D staircases, alternating up and down staircases, and capacitor contacts in a 3D DRAM according to the present disclosure. [Figure 3B] FIG. 3B is a perspective view of an example of 2D staircases, alternating up and down staircases, and capacitor contacts in a 3D DRAM according to the present disclosure. [Figure 3C] FIG. 3C is a perspective view of an example of 2D staircases, alternating up and down staircases, and capacitor contacts in a 3D DRAM according to the present disclosure.

[0039] [Figure 4] FIG. 4 is a flowchart of an example method for fabricating a 3D DRAM according to the present disclosure.

[0040] [Figure 5A] FIG. 5A is a perspective view illustrating an example of active area patterning and cladding according to the present disclosure. [Figure 5B] FIG. 5B is a perspective view illustrating an example of active area patterning and cladding according to the present disclosure. [Figure 5C] FIG. 5C is a perspective view illustrating an example of active area patterning and cladding according to the present disclosure.

[0041] [Figure 6A] FIG. 6A is a perspective view illustrating an example of patterning a word line or fork sheet gate according to the present disclosure. [Figure 6B]FIG. 6B is a perspective view illustrating an example of patterning word lines or fork sheet gates according to the present disclosure. [Figure 6C] FIG. 6C is a perspective view illustrating an example of patterning word lines or fork sheet gates according to the present disclosure. [Figure 6D] FIG. 6D is a perspective view illustrating an example of patterning word lines or fork sheet gates according to the present disclosure.

[0042] [Figure 7A] FIG. 7A is a perspective view illustrating an example of the replacement of sacrificial SiGe with a dielectric material according to the present disclosure. [Figure 7B] FIG. 7B is a perspective view illustrating an example of replacing sacrificial SiGe with a dielectric material according to the present disclosure. [Figure 7C] FIG. 7C is a perspective view illustrating an example of replacing sacrificial SiGe with a dielectric material according to the present disclosure.

[0043] [Figure 8A] FIG. 8A is a perspective view illustrating an example of further formation of a first step (first direction) and a plurality of second steps according to the present disclosure. [Figure 8B] FIG. 8B is a perspective view illustrating an example of further formation of a first step (first direction) and a plurality of second steps according to the present disclosure. [Figure 8C] FIG. 8C is a perspective view illustrating an example of further formation of a first step (first direction) and a plurality of second steps according to the present disclosure. [Figure 8D] FIG. 8D is a perspective view illustrating an example of further formation of a first step (first direction) and a plurality of second steps according to the present disclosure. [Figure 8E] FIG. 8E is a perspective view illustrating an example of further formation of a first step (first direction) and a plurality of second steps according to the present disclosure. [Figure 8F] FIG. 8F is a perspective view illustrating an example of further formation of a first step (first direction) and a plurality of second steps according to the present disclosure. [Figure 8G]FIG. 8G is a perspective view illustrating an example of further formation of a first step (first direction) and a plurality of second steps according to the present disclosure. [Figure 8H] FIG. 8H is a perspective view illustrating an example of further formation of a first step (first direction) and a plurality of second steps according to the present disclosure.

[0044] [Figure 9A] FIG. 9A is a perspective view illustrating an example of further forming a first step in a second direction according to the present disclosure. [Figure 9B] FIG. 9B is a perspective view illustrating an example of further forming the first step in a second direction according to the present disclosure. [Figure 9C] FIG. 9C is a perspective view illustrating an example of further forming the first step in a second direction according to the present disclosure. [Figure 9D] FIG. 9D is a perspective view illustrating an example of further forming the first step in a second direction according to the present disclosure. [Figure 9E] FIG. 9E is a perspective view illustrating an example of further forming the first step in a second direction according to the present disclosure. [Figure 9F] FIG. 9F is a perspective view illustrating an example of further forming the first step in a second direction according to the present disclosure. [Figure 9G] FIG. 9G is a perspective view illustrating an example of further forming the first step in a second direction according to the present disclosure. [Figure 9H] FIG. 9H is a perspective view illustrating an example of further forming the first step in a second direction according to the present disclosure.

[0045] [Figure 10A] FIG. 10A is a perspective view illustrating an example of horizontal capacitor formation according to the present disclosure. [Figure 10B] FIG. 10B is a perspective view illustrating an example of horizontal capacitor formation according to the present disclosure. [Figure 10C] FIG. 10C is a perspective view illustrating an example of horizontal capacitor formation according to the present disclosure. [Figure 10D]FIG. 10D is a perspective view illustrating an example of horizontal capacitor formation according to the present disclosure. [Figure 10E] FIG. 10E is a perspective view illustrating an example of horizontal capacitor formation according to the present disclosure. [Figure 10F] FIG. 10F is a perspective view illustrating an example of horizontal capacitor formation according to the present disclosure. [Figure 10G] FIG. 10G is a perspective view illustrating an example of horizontal capacitor formation according to the present disclosure. [Figure 10H] FIG. 10H is a perspective view illustrating an example of horizontal capacitor formation according to the present disclosure. [Figure 10I] FIG. 10I is a perspective view illustrating an example of horizontal capacitor formation according to the present disclosure.

[0046] [Figure 11A] FIG. 11A is a perspective view showing an example of forming a plurality of third steps between a plurality of second steps according to the present disclosure. [Figure 11B] FIG. 11B is a perspective view showing an example of forming a plurality of third steps between a plurality of second steps according to the present disclosure. [Figure 11C] FIG. 11C is a perspective view illustrating an example of forming a plurality of third steps between a plurality of second steps according to the present disclosure. [Figure 11D] FIG. 11D is a perspective view showing an example of forming a plurality of third steps between a plurality of second steps according to the present disclosure. [Figure 11E] FIG. 11E is a perspective view showing an example of forming a plurality of third steps between a plurality of second steps according to the present disclosure. [Figure 11F] FIG. 11F is a perspective view illustrating an example of forming a plurality of third steps between a plurality of second steps according to the present disclosure. [Figure 12A] FIG. 12A is a perspective view showing an example of forming a plurality of third steps between a plurality of second steps according to the present disclosure. [Figure 12B] FIG. 12B is a perspective view showing an example of forming a plurality of third steps between a plurality of second steps according to the present disclosure. [Figure 12C] FIG. 12C is a perspective view illustrating an example of forming a plurality of third steps between a plurality of second steps according to the present disclosure. [Figure 12D] FIG. 12D is a perspective view illustrating an example of forming a plurality of third steps between a plurality of second steps according to the present disclosure. [Figure 12E] FIG. 12E is a perspective view illustrating an example of forming a plurality of third steps between a plurality of second steps according to the present disclosure. [Figure 12F] FIG. 12F is a perspective view illustrating an example of forming a plurality of third steps between a plurality of second steps according to the present disclosure. [Figure 12G] FIG. 12G is a perspective view illustrating an example of forming a plurality of third steps between a plurality of second steps according to the present disclosure. [Figure 12H] FIG. 12H is a perspective view illustrating an example of forming a plurality of third steps between a plurality of second steps according to the present disclosure. [Figure 12I] FIG. 12I is a perspective view showing an example of forming a plurality of third steps between a plurality of second steps according to the present disclosure.

[0047] [Figure 13A] FIG. 13A is a perspective view illustrating an example of a bridge (capacitor contact) and bit line according to the present disclosure. [Figure 13B] FIG. 13B is a perspective view illustrating an example of a bridge (capacitor contact) and bit line according to the present disclosure. [Figure 13C] FIG. 13C is a perspective view illustrating an example of a bridge (capacitor contact) and bit line according to the present disclosure. [Figure 13D] FIG. 13D is a perspective view illustrating an example of a bridge (capacitor contact) and bit line according to the present disclosure. [Figure 13E] FIG. 13E is a perspective view illustrating an example of a bridge (capacitor contact) and bit line according to the present disclosure. [Figure 13F]FIG. 13F is a perspective view illustrating an example of a bridge (capacitor contact) and bit line according to the present disclosure.

[0048] [Figure 14A] FIG. 14A is a plan view illustrating an example of a bit line shared by multiple write lines, transistors, and capacitors according to the present disclosure. [Figure 14B] FIG. 14B is a plan view illustrating an example of a bit line shared by multiple write lines, transistors, and capacitors according to the present disclosure.

[0049] [Figure 15A] FIG. 15A is a perspective view of an example of a 3D DRAM having a stack of transistors and bit lines connected to the transistors according to the present disclosure. [Figure 15B] FIG. 15B is a perspective view of an example of a 3D DRAM having a stack of transistors, bit lines connected to the transistors, according to the present disclosure. [Figure 15C] FIG. 15C is a perspective view of an example of a 3D DRAM having a stack of transistors and bit lines connected to the transistors according to the present disclosure.

[0050] [Figure 15D] FIG. 15D is a perspective view illustrating an example of a multi-bridge connection between bit lines and transistors, and capacitors and transistors according to the present disclosure.

[0051] [Figure 15E] FIG. 15E is a perspective view illustrating an example capacitor according to the present disclosure.

[0052] [Figure 16] FIG. 16 is a perspective view of an example of a multi-bridge of a 3D DRAM according to the present disclosure.

[0053] [Figure 17]FIG. 17 is a perspective view of an example of a sacrificial silicon layer drilled with vertical via landings at different heights according to the present disclosure. [Figure 18A] FIG. 18A is a perspective view of an example of a sacrificial silicon layer drilled with vertical via landings at different heights according to the present disclosure. [Figure 18B] FIG. 18B is a perspective view of an example of a sacrificial silicon layer drilled with vertical via landings at different heights according to the present disclosure. [Figure 18C] FIG. 18C is a perspective view of an example of a sacrificial silicon layer drilled with vertical via landings at different heights according to the present disclosure. [Figure 18D] FIG. 18D is a perspective view of an example of a sacrificial silicon layer drilled with vertical via landings at different heights according to the present disclosure. [Figure 18E] FIG. 18E is a perspective view of an example of a sacrificial silicon layer drilled with vertical via landings at different heights according to the present disclosure.

[0054] [Figure 19] FIG. 19 is a perspective view of an example of a multi-bridge in process according to the present disclosure.

[0055] [Figure 20] FIG. 20 is a flowchart of an example method for fabricating a 3D DRAM according to the present disclosure.

[0056] [Figure 21A] FIG. 21A is a perspective view illustrating an example of active area patterning according to the present disclosure. [Figure 21B] FIG. 21B is a perspective view illustrating an example of active area patterning according to the present disclosure.

[0057] [Figure 22A] FIG. 22A is a perspective view illustrating an example of gate patterning according to the present disclosure. [Figure 22B] FIG. 22B is a perspective view illustrating an example of gate patterning according to the present disclosure.

[0058] [Figure 23A] FIG. 23A is a perspective view showing an example of nanosheet separation according to the present disclosure. [Figure 23B] FIG. 23B is a perspective view showing an example of nanosheet separation according to the present disclosure. [Figure 23C] FIG. 23C is a perspective view showing an example of nanosheet separation according to the present disclosure. [Figure 23D] FIG. 23D is a perspective view showing an example of nanosheet separation according to the present disclosure.

[0059] [Figure 24A] FIG. 24A is a perspective view illustrating an example of multi-bridge formation according to the present disclosure. [Figure 24B] FIG. 24B is a perspective view illustrating an example of multi-bridge formation according to the present disclosure. [Figure 24C] FIG. 24C is a perspective view illustrating an example of multi-bridge formation according to the present disclosure. [Figure 24D] FIG. 24D is a perspective view illustrating an example of multi-bridge formation according to the present disclosure. [Figure 24E] FIG. 24E is a perspective view illustrating an example of multi-bridge formation according to the present disclosure. [Figure 24F] FIG. 24F is a perspective view illustrating an example of multi-bridge formation according to the present disclosure. [Figure 24G] FIG. 24G is a perspective view illustrating an example of multi-bridge formation according to the present disclosure. [Figure 24H] FIG. 24H is a perspective view illustrating an example of multi-bridge formation according to the present disclosure.

[0060] [Figure 25A] FIG. 25A is a perspective view illustrating another example of multi-bridge formation according to the present disclosure. [Figure 25B] FIG. 25B is a perspective view illustrating another example of multi-bridge formation according to the present disclosure. [Figure 25C] FIG. 25C is a perspective view illustrating another example of multi-bridge formation according to the present disclosure. [Figure 25D] FIG. 25D is a perspective view illustrating another example of multi-bridge formation according to the present disclosure.

[0061] [Figure 26A] FIG. 26A is a perspective view illustrating an example of bit line patterning according to the present disclosure. [Figure 26B] FIG. 26B is a perspective view illustrating an example of bit line patterning according to the present disclosure. [Figure 26C] FIG. 26C is a perspective view illustrating an example of bit line patterning according to the present disclosure. [Figure 26D] FIG. 26D is a perspective view illustrating an example of bit line patterning according to the present disclosure. [Figure 26E] FIG. 26E is a perspective view illustrating an example of bit line patterning according to the present disclosure. [Figure 26F] FIG. 26F is a perspective view illustrating an example of bit line patterning according to the present disclosure.

[0062] [Figure 27A] FIG. 27A is a perspective view illustrating an example of a capacitor process according to the present disclosure. [Figure 27B] FIG. 27B is a perspective view illustrating an example of a capacitor process according to the present disclosure. [Figure 27C] FIG. 27C is a perspective view illustrating an example of a capacitor process according to the present disclosure. [Figure 27D] FIG. 27D is a perspective view illustrating an example of a capacitor process according to the present disclosure. [Figure 27E] FIG. 27E is a perspective view illustrating an example of a capacitor process according to the present disclosure. [Figure 27F] FIG. 27F is a perspective view illustrating an example of a capacitor process according to the present disclosure. [Figure 27G] FIG. 27G is a perspective view illustrating an example of a capacitor process according to the present disclosure. [Figure 27H] FIG. 27H is a perspective view illustrating an example of a capacitor process according to the present disclosure.

[0063] [Figure 28] FIG. 28 is a perspective view illustrating an example of gate isolation according to the present disclosure.

[0064] [Figure 29A] FIG. 29A is a perspective view illustrating an example of forming a top contact to a bitline according to the present disclosure. [Figure 29B] FIG. 29B is a perspective view illustrating an example of forming a top contact to a bitline according to the present disclosure. [Figure 29C] FIG. 29C is a perspective view illustrating an example of forming a top contact to a bitline according to the present disclosure. [Figure 29D] FIG. 29D is a perspective view illustrating an example of forming a top contact to a bitline according to the present disclosure. [Figure 29E] FIG. 29E is a perspective view illustrating an example of forming a top contact to a bitline according to the present disclosure.

[0065] [Figure 30A] FIG. 30A is a perspective view illustrating an example of the formation of word lines and capacitor formation according to the present disclosure. [Figure 30B] FIG. 30B is a perspective view illustrating an example of the formation of word lines and capacitor formation according to the present disclosure.

[0066] [Figure 31A] FIG. 31A illustrates a 3D DRAM with some outer layers omitted for purposes of illustration according to the present disclosure. [Figure 31B] FIG. 31B illustrates a 3D DRAM with some outer layers omitted for purposes of illustration according to the present disclosure. [Figure 31C] FIG. 31C illustrates a 3D DRAM with some outer layers omitted for purposes of illustration according to the present disclosure.

[0067] In the drawings, reference numbers may be reused to refer to similar and / or identical elements. DETAILED DESCRIPTION OF THE INVENTION

[0068] The 3D-DRAM architecture according to the present disclosure rotates (and stacks) 2D DRAM cells in two planes to overcome the patterning challenges of current designs. The 3D-RAM architecture includes horizontal nanosheet transistors (e.g., two transistors per bit). The 3D-RAM architecture places storage node contacts and drain contacts on each side of the nanosheet transistor. The 3D-RAM architecture includes 2D staircases that allow bit lines to connect to corresponding drains of the nanosheet transistors. The 3D-RAM architecture also includes alternating (i.e., alternating) up-and-down staircases that connect horizontally stacked capacitors to the horizontal storage node contacts.

[0069] These features enable the implementation of 3D-RAM architectures using horizontal nanosheet transistors. The 3D-RAM architectures described herein can be processed using existing materials and processes already developed for advanced logic / memory (compared to other FinFET-based transistor 3D-NAND designs that have not yet been fully developed).

[0070] As will be appreciated, the following description is presented using specific materials and integration steps to provide a further understanding of 3D DRAM architectures according to the present disclosure, however, 3D DRAM architectures according to the present disclosure are not limited to these examples and other materials and / or other integration steps may be used without departing from the scope of the present disclosure.

[0071] 1A, a memory cell 50 for a 2D DRAM is shown. The memory cell 50 includes a vertically extending capacitor 54, a source 56, a storage node contact 58, a drain 62, and a gate 66. The memory cell 50 is arranged with the capacitor 54 extending upward from the memory cell 50. Further improvements can be achieved by moving from 2D DRAM to 3D DRAM. However, the implementation of 3D DRAM has been difficult to achieve.

[0072] 1B and 1C, a 3D DRAM integrated circuit according to the present disclosure rotates the 2D DRAM memory cell shown in FIG. 1A in two orthogonal directions. In FIG. 1B, the memory cell 50 of the 2D DRAM of FIG. 1A is rotated 90 degrees (e.g., the Z-plane is rotated from vertical to horizontal), and then multiple memory cells 50 are stacked. However, the arrangement of FIG. 1B requires materials with different selectivities to the etching chemistries used to enable deep lateral etches and different lateral recesses.

[0073] In Figure 1C, the memory cell 50 of the 2D DRAM is rotated 90 degrees to a second orientation (e.g., the x-plane is rotated from vertical to horizontal). The capacitor 54 extends horizontally. As can be seen, etching can be performed vertically rather than laterally (at a different etch rate). However, this arrangement makes it more difficult to form contacts to the gate, drain, and source of the nanosheet transistor.

[0074] 2A-2C, features of a 3D DRAM integrated circuit (IC) are shown. The 3D DRAM IC includes capacitors 54 that run horizontally and are connected to storage node contacts 58 by bridges (or capacitor contacts 110). The capacitor contacts 110 connect the capacitors 54 to the storage node contacts 58 using alternating up and down staircases, as described further below. A bit line 128 is connected to the drain 122 of the nanosheet transistor 118 through a 2D staircase by a bit line contact. A fork gate or word line 132 is connected to the gate of the nanosheet transistor 118.

[0075] As can be seen, the 3D DRAM architecture includes multiple 2D DRAM cells stacked twice with a 90-degree rotation. Multiple alternating up-and-down staircases allow the capacitor 54 (here horizontal) to connect to the storage node contact 58 and source 56 of the nanosheet transistor. The storage node contact 58 and drain 122 are located on different sides of the nanosheet transistor 118.

[0076] 3A-3C, a first staircase, multiple second staircases, multiple third staircases, and contacts in a 3D DRAM integrated circuit are shown. In FIG. 3A, a first staircase 140 allows a bit line 128 to connect with a bit line contact 141 that is connected to the drain 122 of a nanosheet transistor 118. In FIGS. 3B and 3C, multiple second staircases 144 provide connection locations to a capacitor 54. Multiple third staircases 142 allow a capacitor contact 110 to connect to a capacitor 54 and a storage node contact 58. In some examples, the highest capacitor contacts the lowest storage node contact, and vice versa.

[0077] 4, a method 300 for fabricating a 3D DRAM integrated circuit is shown. At 310, active area patterning and cladding is performed (e.g., as described below in FIGS. 5A-5C). At 314, word line (or fore-sheet gate) patterning is performed (e.g., an example is described below in FIGS. 6A-6D).

[0078] At 318, a SiGe substitution is performed (e.g., an example is described below in Figures 7A-7D). At 320, a dopant source optionally dopes a portion of the nanosheet transistor. At 322, a first step is defined in a first direction, and a plurality of second steps are defined (e.g., an example is described below in Figures 8A-8H). At 326, the first step is further defined in a second direction perpendicular to the first direction (e.g., an example is described below in Figures 9A-9H). At 330, a horizontal capacitor is formed (e.g., an example is described below in Figures 10A-10I). At 334, a plurality of third steps are defined between the plurality of second steps (e.g., an example is described below in Figures 11A-12G). At 338, bridges (capacitor contacts) and bitlines are defined (eg, an example is described below in Figures 13A-13F).

[0079] 5A-5C, active area patterning and insulating layer deposition are shown. In FIG. 5A, alternating silicon (Si) layers 414 and silicon germanium (SiGe) layers 416 (collectively, alternating Si / SiGe layers 418) are deposited on a Si substrate 410. The silicon germanium (SiGe) layers 416 act as sacrificial layers. An insulating layer 420 (e.g., silicon nitride (SiN)) is deposited on the last Si layer of the alternating Si / SiGe layers 418.

[0080] In Figure 5B, the insulating layer 420 and alternating Si / SiGe layers 418 are patterned using lithography and one or more etching steps into horizontal capacitor shapes 430 and fork seat shapes 434. In Figure 5C, an oxide layer 424 (e.g., SiO2, etc.) is deposited around the insulating layer 420 and alternating Si / SiGe layers 418 after patterning.

[0081] 6A-6D, the patterning of word lines (or forked sheet gates) is shown. For illustrative purposes, FIGS. 6A-6C are shown as cross sections of the memory cell of FIG. 5C. In FIG. 6A, vertical gate trenches 440 are created in insulating layer 420 and alternating Si / SiGe layers 418 using lithography and etching steps.

[0082] 6B, a selective lateral etch of the SiGe layers 416 in the alternating Si / SiGe layers 418 is performed through the vertical gate trench 440 to create a lateral opening 444. The lateral etch is selective, etching substantially more of the SiGe layers 416 compared to the silicon layers 414 in the alternating Si / SiGe layers 418.

[0083] In Figure 6C, gate metal 450 (e.g., tungsten W) for the word lines is deposited in the lateral openings 444. In Figure 6D, polishing, such as chemical mechanical polishing (CMP), may be performed after deposition.

[0084] 7A-7C, the replacement of sacrificial SiGe with a dielectric is shown. In FIG. 7A, an etch is performed to open storage node contacts 490 and drain contacts 492 (corresponding to dotted lines 460 and 464 in FIG. 6D, respectively). In FIG. 7B, a lateral etch recess is performed to remove SiGe layer 416 between silicon layer 414 at storage node contacts 490 and drain contacts 492. In FIG. 7C, oxide 470 deposition is performed.

[0085] 8A-8H, resist patterning and etching / resist trim loops are used to form a first staircase on one side of a nanosheet transistor and multiple second staircases on the other side of the nanosheet transistor. In FIG. 8A, a resist layer 510 is deposited on a substrate. In FIGS. 8B-8G, sequential etching of the nitride and oxide layers is performed to expose a first staircase step (which now descends in a first direction) and multiple second staircase steps. In FIG. 8B, selected portions of the resist layer 510, insulating layer 420, and oxide layer 424 are etched to expose a first staircase step 514 and multiple second staircase steps 518 (located on each side of the nanosheet transistor). The multiple second staircases 518 are spaced apart transversely to the ascending / descending direction.

[0086] 8C-8G, selected portions of resist layer 510, insulating layer 420, and oxide layer 424 are sequentially etched to define additional steps in first staircase 514 and additional steps in the plurality of second staircases 518. In FIG. 8G, after the final steps in first staircase 514 and plurality of second staircases 518 are defined, a nitride layer is deposited over first staircase 514 and plurality of second staircases 518, as shown in FIG. 8H. As can be seen, first staircase 514 and plurality of second staircases 518 descend in a direction away from the nanosheet transistor.

[0087] 9A-9H, further processing of the first staircase 514 step is shown. More specifically, the first staircase 514 step is further etched downward in a second direction perpendicular to the first direction (thus, the first staircase becomes a 2D staircase). In FIG. 9A, a resist layer 540 is patterned and deposited on the nitride layer 530 in areas other than the first staircase 514. In FIG. 9B, the nitride layer 530 above the first staircase 514 is removed. In FIG. 9C, a resist layer 540 is deposited. In FIG. 9D, patterning and etching of the resist layer 540 is performed to define the first staircase 514 step 548 in the second direction.

[0088] In Figure 9E, etching of resist layer 540 is performed to define step 550 of first staircase 514. In Figure 9F, patterning and etching of resist layer 540 is performed to define step 552 of first staircase 514. In Figure 9G, patterning and etching of resist layer 540 is performed to define step 554 of first staircase 514 (and expose drain contact 492). In Figure 9H, patterning and etching of resist layer 540 is performed to define step 554 of first staircase 514. As can be seen in Figure 9H, steps 548, 550, 552, 554, and 556 transition downward in first and second orthogonal directions (e.g., x and y directions).

[0089] 10A-10I, horizontal capacitor formation is shown. In FIG. 10A, an insulating layer 580 (e.g., a nitride layer, etc.) is deposited and polished. In FIGS. 10B and 10C, an etching layer 590 is deposited on the insulating layer 580, and a trench opening 604 for the horizontal capacitor is etched. In FIG. 10D, the trench opening 604 is further etched to expose the sides of the silicon layer 414 and the SiGe layer 416. In FIG. 10E, the SiGe layer 416 between the silicon layer 414 is laterally etched and removed. In FIG. 10F, a capacitor material 620 (e.g., titanium nitride, etc.) is deposited and polished to fill the trench opening 610.

[0090] In Figure 10G, trenches 624 are etched. In the steps of Figures 10B-10F, SiGe layer 416 has been replaced with capacitor material 620. In Figure 10H, silicon layer 414 between the layers of capacitor material 620 is laterally etched. In Figure 10I, oxide layer 424 is deposited in trenches 624 and polished.

[0091] 11A-12G, a plurality of third steps are defined between (or interleaved with) the plurality of second steps 518. In FIG. 11A, a resist layer 710 is deposited and patterned on the oxide layer 424 and insulating layer 580 above the first steps 514 and the plurality of second steps 518. Openings are formed in the resist layer 710 by lithography and etching. In FIGS. 11C and 11D, the oxide layer 424 and insulating layer 580 are etched to expose the top surfaces of a pair of horizontal capacitors (e.g., capacitor material 620). In FIGS. 11E and 11F, the resist layer 710 is removed.

[0092] 12A-12I, a resist pattern and etching / resist trim loops are used to define the plurality of third steps. In FIGS. 12A and 12B, a resist layer 750 is formed on a portion of the insulating layer 580 above the horizontal capacitor (e.g., capacitor material 620) and on the area above the plurality of second steps 518. In FIGS. 12C-12G, the resist layer 750 is sequentially removed, and the steps of the plurality of third steps 760 are sequentially etched. As can be seen, the plurality of third steps 760 descend in a direction toward the nanosheet transistor, exposing connection locations for the horizontal capacitor. The resist layer 750 is removed.

[0093] 13A-13F, bridge and bit line processing is shown. In FIG. 13A, an insulating layer 580 is deposited and polished. In FIG. 13B, a resist layer 810 is deposited, creating a pattern 814 for the bridge (or capacitor contact) and bit line (connecting to the bit line or drain contact). In FIG. 13C, the bridge and bit line are etched through the pattern 814. In FIG. 13D, metal is deposited to form the bridge (or capacitor contact) 820 and bit line 824, and the resist layer 810 is removed. In FIGS. 13E and 13F, additional cross sections are shown.

[0094] Referring now to Figures 14A and 14B, a portion of another example of a 3D DRAM is shown. As described above, bit lines are located on opposite sides of the nanosheet transistors, and a gate-forked-sheet design is used. Additional modifications include the use of gate-all-around nanosheet transistors, wider capacitors, and an increased number of transistors per bit line. In Figure 14A, a bit line 910 is shared by multiple transistors 920 and capacitors 926. The capacitors 926 are wider (compared to conventional designs). The capacitors 926 are connected to a first side of the channel of the transistors 920. Word lines 924 are connected around the gate terminal of the transistors 920. The bit lines 910 are connected to a second side of the channel of the transistors 920. In Figure 14B, each of the bit lines 910 can be connected to multiple terminals of multiple transistors 920 located symmetrically on each side of it in multiple levels.

[0095] 15A-17B, additional features of a 3D DRAM are shown. In FIG. 15A, a stack of transistors 920 includes a gate connected to a vertically extending word line 924. In FIG. 15B, the silicon channel 954 of the transistor 920 is shown in the gate metal. An isolator layer 956 (high-k layer) is disposed between the silicon channel 954 of the transistor 920 and the gate metal (or word line 924). In FIGS. 15A and 15C, vertical bit line contacts 910-C extend to different heights and connect to bit line layers 910-L extending in spaced-apart parallel planes. In some examples, 28 layers of capacitors are used. In some examples, there are six 28 layer capacitors 926 in each row per unit cell on either side of the unit cell (e.g., 28 x 6 x 2 = 336 transistors per unit cell).

[0096] In FIG. 15C, the vertical bit line contacts 910-C pass through insulating portions 960 of the bit line layers 910-L to prevent shorting and then connect to the corresponding bit line layers 910-L. In some examples, the bit line layers 910-C are positioned between two rows of transistors, as shown in FIG. 14B. In some examples, there are 28 bit line layers 910-L. Each bit line layer 910-L is penetrated by a bit line contact 910-C that connects to the other bit line layers 910-L (contact is prevented by insulating portions 960). In some examples, each bit line layer 910-L contacts 12 transistors, and there is one bit line contact 910-C per bit line layer 910-L. The horizontal bit lines 910-H are connected to the vertical bit line contacts 910-C, which are connected to the bit line layers 910-L.

[0097] 15A and 15D, multibridge 943 connects bitline layer 910-L to a first side of the channel of transistor 920, and multibridge 945 connects a second side of the channel of transistor 920 to capacitor 926. In some examples, the gate length is greater than 30 nm to avoid short channel effects.

[0098] 15E, the capacitors 926 can comprise an array 970 of metal-isolator-metal capacitors. For example, an inner metal layer 972 includes a conductor such as titanium nitride (TiN), an isolator layer 974 includes a material with a high dielectric constant, and an outer layer 976 includes a conductor such as TiN. In some examples, the outer layer 976 is grounded by contact 940 in FIG. 15A. In some examples, there are 28 layers of capacitors 926, six in each row per unit cell on both sides of the unit cell (e.g., 28 x 6 x 2 = 336 capacitors per unit cell).

[0099] The metal-isolator-metal capacitance increases as the length L of the capacitor 926 increases, the diameter d of the inner metal layer 972 increases, the thickness of the isolator decreases, and the dielectric constant of the isolator increases. In some examples, the capacitance of the metal-isolator-metal capacitor is greater than 5 femtofarads (fF), and the length L defines the allowable footprint for the 3D DRAM.

[0100] 16-18E, additional features of the 3D DRAM are shown. In FIG. 16, a multibridge 943, a transistor 920, a multibridge 945, and a capacitor 926 extend from each side of a stack of sacrificial silicon layers 990 (replaced by bitline layers 910-L). In FIGS. 17-18D, the sacrificial silicon layer 990 is drilled with two arrays of vias (corresponding to bitline contacts 910-C) located at different heights in the stack of sacrificial silicon layers 990. The silicon material in the sacrificial silicon layer 990 is replaced with a conductive material through the vias to form the bitline contacts 910-C, as described further below. In FIG. 18E, the bitline contact bank including the bitline contacts 910-C accommodates the very dense areas of the 3D DRAM architecture.

[0101] 19, multibridges 943 and 945 have multiple functions. Multibridge 943 allows bitline layer 910-L to contact a first side of the channel of transistor 920. Multibridge 945 also allows a second side of the channel of transistor 920 to contact capacitor 926. In addition, multibridges 943 and 945 act as a silicon etch stop layer when replacing silicon at 927 (future location of capacitor 926) during fabrication of bitline contact 910-C and capacitor 926.

[0102] Referring now to Figure 20, a method 1000 for fabricating the 3D DRAM of Figures 14-19 is shown. At 1010, active area patterning is performed. At 1014, gates are formed. At 1018, nanosheet transistor isolation is performed. At 1020, multi-bridges are formed. At 1022, bitline contact bank patterning is performed. At 1026, capacitors are processed. At 1030, gates are isolated. At 1034, top contact and bitline formation is performed. At 1038, wordline and capacitor ground formation is performed.

[0103] 21A and 21B, active area patterning is shown. In some examples, silicon layers 414 and silicon germanium layers 416 are alternately deposited on a silicon substrate 410 and patterned in a manner similar to that shown in FIGS. 5A-5C and described above.

[0104] 22A and 22B, the initial formation of the gate (word line 924) is performed. The formation of the gate or word line 924 includes creating a trench, oxide etching and SiGe recess, depositing an isolator layer 956, and filling with a metal gate.

[0105] 23A and 23D, isolation of transistor 920 is performed. Referring now to FIGS. 23A and 23B, oxide removal is performed. A mask 921 is deposited to maintain the mechanical integrity of the pillars. In FIG. 23C, a lateral etch of silicon germanium layer 416 is performed. In FIG. 23D, oxide cladding 923 is deposited.

[0106] 24A-24H, a first method for forming multibridges 943 and 945 is shown. In FIGS. 24A and 24B, trenches 1010 are patterned on each side of the channel of transistor 920, and an etch of oxide 1012 (selectively etching the oxide and leaving the silicon) is performed to expose silicon bridges 1014 (which will ultimately correspond to multibridges 943 and 945, respectively) at different vertical levels. In FIGS. 24C and 24D, a metal conformal deposition of a transition metal 1020 (e.g., cobalt (Co), nickel (Ni), etc.) is performed. Gas-phase doping can be used to introduce dopants into the silicon bridges and extensions. In FIGS. 24E and 24F, a salicide process (e.g., annealing) is performed to form an alloy of silicon and the transition metal, creating multibridges 943 and 945. In Figures 24G and 24H, removal of the transition metal 1020 (other than the alloy that forms the multi-bridges 943 and 945) is performed.

[0107] 25A-25C, a second method for forming multibridges 943 and 945 is shown. In FIG. 25A, trenches 1050 are patterned on each side of the channel of transistor 920. An etch of oxide 1012 and silicon in trench 1050 is performed. In FIG. 25B, selective deposition of conductors 1060 (e.g., in-situ doped SiGe epitaxy) on silicon with a confluence front is used to form multibridges 943 and 945. In some examples, when SiGe epitaxy is used, the capacitor lines are 100-oriented to allow faster lateral growth (compared to horizontal growth between transistors 920 or between sacrificial silicon in bitline layers or capacitor locations).

[0108] Referring now to Figures 26A-26F, patterning of bit line contacts 910-C, which form bit line contact banks, is performed. In Figure 26A, a hole array 1100 (e.g., a 4x7 hole array) is patterned in nitride layer 1104. In Figures 26B and 26C, etching of vias 1106 is performed (defining vertical bit lines 910-C) through oxide 1108 and silicon 1112 (within silica (future locations of bit line layers 910-L)) to different etching depths (in other words, different landing heights on future bit line layers 910-L). In Figure 26D, isolation spacers (insulating portions 960) for vias 1106 are deposited in vias 1106. In Figure 26E, removal of silicon (corresponding to bit line layers 910-L) is performed using wet etching, stopping at multi-bridges 943 and 945. In Figure 26F, vias 1106 and other cavities are filled with a conductive material (eg, to form vertical bitlines 910-C and bitline layers 910-L).

[0109] 27A-27H, the capacitor is processed. In FIG. 27A, a trench 1210 is opened and an etch of oxide 1108 is performed. In FIG. 27B, an etch of silicon layer 414 is performed to form a recess 1218. In FIG. 27C, a cavity expansion is performed using an oxide isotropic etch to increase the diameter of recess 1218 relative to the inner metal layer 972 of capacitor 926.

[0110] In Figure 27D, metal 1222 is deposited in recess 1218 to form inner metal layer 972 of capacitor 926. For example, one or more conformal deposition and anisotropic etch cycles are performed. In Figure 27E, oxide deposition and an oxide-selective etch to TiN are performed. In Figure 27F, oxide removal is performed. In Figure 27G, an isolator layer 974 having a high dielectric constant k is deposited on inner metal layer 972 of capacitor 926. In Figure 27H, an outer layer 976 of capacitor 926 is deposited on isolator layer 974.

[0111] 28, the gate or word lines are isolated or cut. Trenches 1240 are etched in the gate metal between the nanosheet transistors and filled with dielectric 1242.

[0112] 29A-30B, horizontal bitline contacts 910-H for bitlines 910-C are formed. In FIGS. 29A and 29B, horizontal bitline contacts 1310 (e.g., six horizontal bitline contacts) are formed, and the bitlines are rerouted above the capacitors 926. In FIG. 29C, horizontal bitline contacts 1314 (across the horizontal bitline contacts 1310 and in parallel planes) are patterned (e.g., seven horizontal bitlines) and implemented. In FIG. 29D, additional horizontal bitline contacts 1318 (e.g., six horizontal bitline contacts) are formed (above the horizontal bitline contacts) and rerouted above the capacitors 926. In FIG. 29E, horizontal bitline patterning (e.g., seven horizontal bitlines) is implemented. In FIGS. 30A and 30B, wordlines 924 and capacitor ground (contacts 940) formation to the outer layer 976 of the capacitors 926 are implemented.

[0113] Referring now to Figures 31A-31C, a 3D DRAM is shown with some layers removed to reveal the underlying structure.

[0114] The foregoing description is merely exemplary in nature and is not intended to limit the disclosure, its application, or uses in any way. The broad teachings of the present disclosure can be embodied in a variety of forms. Accordingly, while the present disclosure includes specific examples, the true scope of the disclosure should not be limited to such examples, as other modifications will become apparent upon review of the drawings, the specification, and the following claims. It should be understood that one or more steps in a method may be performed in a different order (or simultaneously) without altering the principles of the disclosure. Furthermore, although each embodiment is described above as having specific features, any one or more of these features described with respect to any embodiment of the present disclosure may be implemented in other embodiments and / or combined with any features of the other embodiments (even if such combination is not explicitly described). In other words, the described embodiments are not mutually exclusive, and substituting one or more embodiments for one another is within the scope of the present disclosure.

[0115] Spatial and functional relationships between elements (e.g., modules, circuit elements, semiconductor layers, etc.) are described using various terms such as "connected," "engaged," "coupled," "adjacent," "next to," "on," "above," "below," and "disposed." Also, when a relationship between a first element and a second element is described in the above disclosure, unless expressly described as "direct," the relationship may be a direct relationship where no other intervening elements exist between the first element and the second element, or an indirect relationship where one or more intervening elements (spatial or functional) exist between the first element and the second element. As used herein, the phrase "at least one of A, B, and C" should be interpreted in the sense of a logical (A or B or C) using a non-exclusive logical OR, and not in the sense of "at least one of A, at least one of B, and at least one of C."

Claims

1. 1. A three-dimensional (3D) dynamic random access memory (DRAM), comprising: A substrate; a plurality of nanosheet transistors vertically stacked on the surface of the substrate, each of the nanosheet transistors comprising a gate, a source, and a drain; The first staircase and a plurality of bit line contacts; a plurality of bit lines connected to the corresponding drains of the nanosheet transistors in the first staircase by the plurality of bit line contacts; a plurality of second staircases; a plurality of third staircases; a plurality of capacitor contacts; a plurality of storage node contacts, the storage node contacts including first ends connected to the sources of the corresponding ones of the nanosheet transistors; a plurality of capacitors vertically stacked on the substrate and extending parallel to the surface of the substrate; Equipped with First ends of the capacitors located adjacent to the nanosheet transistors are connected to first ends of the capacitor contacts corresponding to the second steps; second ends of the capacitor contacts are connected to second ends of the storage node contacts corresponding to the third steps; 3D-DRAM.

2. 2. The 3D-DRAM according to claim 1, The first staircase comprises a two-dimensional (2D) staircase.

3. 2. The 3D-DRAM according to claim 1, The first staircase descends in first and second orthogonal directions relative to the surface of the substrate.

4. 2. The 3D-DRAM according to claim 1, At least a portion of the first step extends below the surface of the substrate.

5. 2. The 3D-DRAM according to claim 1, The 3D-DRAM, wherein the first staircase and the plurality of bit lines are disposed on one side of the plurality of nanosheet transistors.

6. 5. The 3D-DRAM according to claim 4, The 3D-DRAM, wherein the plurality of second steps, the plurality of third steps, and the capacitor are arranged on opposite sides of the plurality of nanosheet transistors.

7. 2. The 3D-DRAM according to claim 1, The capacitor contact is J-shaped and has multiple vertical lengths across the surface of the substrate.

8. 2. The 3D-DRAM according to claim 1, The plurality of second steps are alternately arranged between the plurality of third steps.

9. 9. The 3D-DRAM according to claim 8, the second steps descend in a direction toward the nanosheet transistors, The third steps rise in a direction toward the nanosheet transistors. 3D-DRAM.

10. 2. The 3D-DRAM according to claim 1, The gates of the plurality of nanosheet transistors comprise fork-sheet gates corresponding to word lines.

11. 1. A three-dimensional (3D) dynamic random access memory (DRAM), comprising: A substrate; a plurality of nanosheet transistors vertically stacked on the surface of the substrate, each of the nanosheet transistors comprising a gate, a source, and a drain; a plurality of nanosheet transistors; a plurality of bit lines connected to the corresponding drains of the nanosheet transistors on one side of the plurality of nanosheet transistors; a plurality of capacitors vertically stacked on the substrate, extending parallel to a surface of the substrate, and connected to the sources of the corresponding nanosheet transistors on opposite sides of the plurality of nanosheet transistors; A 3D-DRAM comprising:

12. 12. The 3D-DRAM according to claim 11, The first staircase and Multiple bit line contacts and Furthermore, the plurality of bit lines are connected to the corresponding drains of the nanosheet transistors in the first staircase by the plurality of bit line contacts; 3D-DRAM.

13. 13. The 3D-DRAM according to claim 12, a plurality of second staircases; a plurality of third staircases; a plurality of capacitor contacts; a plurality of storage node contacts, the storage node contacts including first ends connected to the sources of the corresponding ones of the nanosheet transistors; Furthermore, First ends of the capacitors located adjacent to the nanosheet transistors are connected to first ends of the capacitor contacts corresponding to the second steps; second ends of the capacitor contacts are connected to second ends of the storage node contacts corresponding to the third steps; 3D-DRAM.

14. 13. The 3D-DRAM according to claim 12, The first staircase comprises a two-dimensional (2D) staircase.

15. 13. The 3D-DRAM according to claim 12, The first staircase descends in first and second orthogonal directions relative to the surface of the substrate.

16. 13. The 3D-DRAM according to claim 12, At least a portion of the first step extends below the surface of the substrate.

17. 14. The 3D-DRAM according to claim 13, The capacitor contact is J-shaped and has multiple vertical lengths across the surface of the substrate.

18. 14. The 3D-DRAM according to claim 13, The plurality of second steps are alternately arranged between the plurality of third steps.

19. 19. The 3D-DRAM according to claim 18, the second steps descend in a direction toward the nanosheet transistors, The third steps rise in a direction toward the nanosheet transistors. 3D-DRAM.

20. 12. The 3D-DRAM according to claim 11, The gates of the plurality of nanosheet transistors comprise fork-sheet gates corresponding to word lines.

21. 1. A method for fabricating a three-dimensional (3D) dynamic random access memory (DRAM), comprising: depositing alternating first and second layers on a surface of a substrate; patterning a plurality of nanosheet transistor active areas in the alternating first and second layers; patterning the fork sheet gates of the plurality of nanosheet transistors; Selectively doping a portion of the plurality of nanosheet transistors; forming a first staircase that provides a plurality of connection locations to a plurality of bit line contacts on one side of the plurality of nanosheet transistors, and a plurality of second staircases that provide a plurality of connection locations to a plurality of storage node contacts on an opposite side of the plurality of nanosheet transistors.

22. 22. The method of claim 21, The method, wherein the first step descends in first and second orthogonal directions relative to the surface of the substrate.

23. 22. The method of claim 21, The method further comprises forming a plurality of capacitors on opposite sides of the plurality of nanosheet transistors.

24. 22. The method of claim 21, The method of claim 1, wherein the plurality of capacitors are stacked vertically on the substrate and extend parallel to the surface of the substrate.

25. 24. The method of claim 23, The method further includes forming a plurality of third steps between the plurality of second steps to provide connection locations for first ends of the plurality of capacitors.

26. 26. The method of claim 25, The method, wherein the second steps ascend in a direction toward the nanosheet transistors, and the third steps descend in a direction toward the nanosheet transistors.

27. 25. The method of claim 24, The method further comprising patterning a plurality of capacitor contacts connecting the first ends of the plurality of capacitors to the plurality of storage node contacts.

28. 28. The method of claim 27, The method, wherein the plurality of capacitor contacts are J-shaped and have multiple vertical lengths across the surface of the substrate.

29. 28. The method of claim 27, The method further comprising patterning and depositing a plurality of bit lines connected to a corresponding plurality of bit line contacts.

30. 22. The method of claim 21, At least a portion of the first step extends below the surface of the substrate.

31. 1. A three-dimensional (3D) dynamic random access memory (DRAM), comprising: A substrate; a first array of nanosheet transistors arranged in a first vertical stack on the substrate, the first array comprising N levels of rows each including M nanosheet transistors; a second array of nanosheet transistors arranged in a second vertical stack on the substrate, the second array comprising N levels of rows each containing M nanosheet transistors, where M and N are integers greater than 1; N bit line layers stacked and vertically aligned with the nanosheet transistors of the first and second arrays of the N levels; Equipped with Each of the N bit line layers is connected to 2×M nanosheet transistors, such that first sides of channels of the M nanosheet transistors in each of the nanosheet transistors of the first array of N levels are connected to first sides of corresponding N bit line layers, and first sides of channels of the M nanosheet transistors in each of the nanosheet transistors of the second array of N levels are connected to second sides of corresponding N bit line layers; 3D DRAM.

32. 32. The 3D DRAM of claim 31, N vertical bit lines Furthermore, a first vertical bit line of the N vertical bit lines is connected to a first bit line layer of the N bit line layers; the remaining N vertical bit lines are connected to one of the N bit line layers, extend through one or more of the N bit line layers, and are isolated from one or more of the N bit line layers; 3D DRAM.

33. 33. The 3D DRAM of claim 32, The 3D DRAM further comprises 2M vertical word lines connected to the gates of the nanosheet transistors of the first array and the nanosheet transistors of the second array.

34. 34. The 3D DRAM of claim 33, M of the 2M vertical word lines are respectively connected to gates of vertically aligned nanosheet transistors of the first array; M of the 2M vertical word lines are respectively connected to the gates of vertically aligned nanosheet transistors of the second array; 3D DRAM.

35. 35. The 3D DRAM of claim 34, The 2M vertical word lines surround the gates of corresponding nanosheet transistors of the first array and nanosheet transistors of the second array.

36. 33. The 3D DRAM of claim 32, a first array of bridges connecting the first sides of the channels of the N bit line layers to the nanosheet transistors of the first array, the first array of bridges including N levels of rows each including M bridges; a second array of bridges connecting the second sides of the channels of the N bit line layers to nanosheet transistors of the second array, the second array of bridges including N levels of rows each including M bridges; The 3D DRAM further comprises:

37. 33. The 3D DRAM of claim 32, a first array of capacitors connected to second sides of the channels of the first array of nanosheet transistors, the first array of capacitors including N levels of rows, each including M capacitors; a second array of capacitors connected to second sides of the channels of the second array of nanosheet transistors, the second array of capacitors including N levels of rows, each including M capacitors; The 3D DRAM further comprises:

38. 38. The 3D DRAM of claim 37, a first array of bridges connecting the first array of capacitors to the second sides of the channels of the first array of nanosheet transistors, the first array of bridges including N levels of rows, each including M bridges; a second array of bridges connecting the second array of capacitors to the second sides of the channels of the second array of nanosheet transistors, the second array of bridges including N levels of rows each including M bridges; The 3D DRAM further comprises:

39. 38. The 3D DRAM of claim 37, The 3D DRAM, wherein the first array of capacitors comprises a metal-isolator-metal capacitor.

40. 38. The 3D DRAM of claim 37, The first array of capacitors comprises: an inner metal layer connected to the second side of the channel of the nanosheet transistors of the first array; an isolator layer surrounding the inner metal layer; an outer layer surrounding the inner metal layer; 3D DRAM comprising:

41. 1. A method for fabricating a three-dimensional (3D) dynamic random access memory (DRAM), comprising: disposing a first array of nanosheet transistors in a first vertical stack on a substrate, said first array comprising N levels of rows each including M nanosheet transistors; disposing a second array of nanosheet transistors in a second vertical stack on the substrate, the second array comprising N levels of rows each containing M nanosheet transistors, where M and N are integers greater than 1; stacking and vertically aligning N bit line layers with the first and second arrays of nanosheet transistors in the N levels; connecting first sides of channels of the M nanosheet transistors in each of the nanosheet transistors of the first array of the N levels to first sides of the N bit line layers, and connecting first sides of channels of the M nanosheet transistors in each of the nanosheet transistors of the second array of the N levels to second sides of the N bit line layers, such that each of the N bit line layers is connected to 2×M nanosheet transistors. A method comprising:

42. 42. The method of claim 41 further comprising: connecting a first of the N vertical bit lines to one of the N bit line layers; connecting the remaining N vertical bit lines to one of the N bit line layers, the remaining N vertical bit lines extending through one or more of the N bit line layers and being isolated from one or more of the N bit line layers.

43. 43. The method of claim 42, The method further includes connecting 2M vertical word lines to the gates of the nanosheet transistors of the first array and the nanosheet transistors of the second array.

44. 44. The method of claim 43, further comprising: connecting M of the 2M vertical word lines to gates of vertically aligned nanosheet transistors of the first array, respectively; connecting M of the 2M vertical word lines to gates of nanosheet transistors in the second array that are respectively vertically aligned.

45. 45. The method of claim 44, The method, wherein the 2M vertical word lines surround the gates of corresponding nanosheet transistors of the first array and nanosheet transistors of the second array.

46. 43. The method of claim 42, further comprising: using a first array of bridges to connect the first sides of the channels of the N bit line layers to the nanosheet transistors of the first array, the bridges of the first array including N levels of rows each including M bridges; The method comprises using bridges of a second array to connect the second sides of the channels of the N bit line layers to nanosheet transistors of the second array, wherein the bridges of the second array include N levels of rows, each including M bridges.

47. 43. The method of claim 42, further comprising: a first array of capacitors is connected to a second side of the channel of the nanosheet transistor of the first array, the first array of capacitors including N levels of rows each including M capacitors; connecting a second array of capacitors to a second side of the channel of the second array of nanosheet transistors, wherein the second array of capacitors includes N levels of rows, each including M capacitors.

48. 48. The method of claim 47, further comprising: using a first array of bridges to connect the capacitors of the first array to the second sides of the channels of the nanosheet transistors of the first array, the bridges of the first array including N levels of rows each including M bridges; A method comprising: using a second array of bridges to connect capacitors of the second array to the second sides of the channels of nanosheet transistors of the second array, the bridges of the second array including N levels of rows each including M bridges.

49. 48. The method of claim 47, The method, wherein the first array of capacitors comprises metal-isolator-metal capacitors.

50. 48. The method of claim 47, The first array of capacitors comprises: an inner metal layer connected to the second side of the channel of the nanosheet transistors of the first array; an isolator layer surrounding the inner metal layer; an outer layer surrounding the inner metal layer; A method comprising:

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