Flip Chip Assembly

Abstract

A flip-chip assembly (1) for integrated solid-state quantum circuits is disclosed. The assembly includes a first chip (10) including a first semiconductor substrate (12), the first semiconductor substrate (12) including a plurality of spin defects (13), the plurality of spin defects (13) coupled by spin-spin interactions, the plurality of spin defects (13) hosting a plurality of quantum bits. The assembly includes a second chip (20) including a second semiconductor substrate (22) bonded to the first chip (10). The second chip (20) includes a plurality of control structures (24) and readout structures (26), and the first semiconductor substrate (12) is a diamond substrate. This document also teaches fabrication of the flip-chip assembly.

Description

[Technical Field]

[0001] explanation CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority from European Patent Application No. 23386003.0, filed January 20, 2023.

[0002] FIELD OF THE INVENTION This document describes a method and assembly of integrated solid-state quantum circuits (ISSQC) having semiconductor substrates and readout structures, control structures and semiconductor device interconnects using flip-chip technology. [Background technology]

[0003] Background of the Invention An integrated solid-state quantum circuit (ISSQC) is an integrated circuit that can address, control, and sense the quantum state of solid-state qubits for applications in quantum technology and quantum computing. An integrated solid-state quantum circuit also includes a semiconductor substrate (or a semiconductor device that hosts multiple qubits), a control structure that can manipulate the qubits, and a readout structure used to control the control structure. The readout structure can also be used to collect optical, electrical, or magnetic signals from the qubits, and spin defects exist within the semiconductor substrate.

[0004] The qubits are addressed and manipulated using at least one of optical, electric, and magnetic fields.

[0005] The control structures are used to deliver optical, electric and / or magnetic fields, as well as to control, initialize, manipulate and read out the spin state of a given qubit within a semiconductor substrate.

[0006] Readout structures are, for example, analog circuits, digital circuits, transistors, logic devices, sensor devices, light emitting devices and light collecting devices.

[0007] The central components of the ISSQC, such as the semiconductor substrate, control structures, and readout structures, can be fabricated by two approaches: in the first approach, the central components of the ISSQC are directly integrated into one device (monolithic fabrication process), for example using a bottom-up fabrication process; in the second approach, the central components of the ISSQC are fabricated separately in separate devices and integrated onto the ISSQC at a later stage (e.g., flip-chip assembly).

[0008] prior art Monolithic fabrication processes are known approaches for on-chip integration of semiconductor waveguides, transistors, semiconductor quantum processors, and photon sources, and have been described in several publications.

[0009] For example, US Patent No. 11,171,225 (University of Toronto) describes a monolithically integrated semiconductor quantum processor.

[0010] KD Jons et al., “Monolithic on-chip integration of semiconductor waveguides, beam splitters and single-photon sources,” J. Phys. D: Appl. Phys. 48 085101 (2015), describes the monolithic on-chip integration of semiconductor waveguides, beam splitters, and single-photon sources.

[0011] According to the prior art, monolithic manufacturing processes suffer from a lack of flexibility in circuit design, which can result in poorer isolation between manufactured components. Additionally, quality control tests can be performed on manufactured components within an ISSQC only when the entire ISSQC is assembled. These quality control tests can indicate, for example, a lack of signal from multiple qubits readout from control structures within the device. A drawback of monolithic manufacturing processes is the difficulty of determining the reason for a lack of signal from a qubit. This lack of signal can be related to a problem during the manufacturing of the qubit or a problem during the manufacturing of the semiconductor device (e.g., misalignment of the semiconductor device).

[0012] However, no known prior art document discloses a monolithic manufacturing process for the central components of the ISSQC, such as the semiconductor substrate (eg, diamond substrate), the control structure, and the readout structure.

[0013] Another approach for the fabrication of the central components of the ISSQC is the separate fabrication of separate devices for each central component. Separate fabrication processes allow for separate optimization of the fabrication of the semiconductor substrate (with the qubits) and the semiconductor device hosting the control structures and associated circuitry. This separate fabrication allows for optimization of the semiconductor substrate, for example, by selection of material properties, atomic-scale fabrication of the qubits, dopant optimization, or even by different materials, for increased efficiency of the semiconductor device.

[0014] Separate fabrication of the ISSQC's central components allows for the use of established techniques and materials for the development of semiconductor devices, including control structures and integrated circuits (ICs). Separate fabrication can, for example, exploit the capabilities of established CMOS technology. Separate fabrication also allows for the ability to parallelize different steps of the fabrication process.

[0015] Separate fabrication of the central components of the ISSQC also allows for separate testing of the semiconductor substrates prior to integration of the entire ISSQC. Electromagnetic compatibility (EMC) testing, fabrication testing, and signal transmission testing can be applied separately to the control and readout structures. Separate fabrication therefore allows for the determination of potential problems with coupling to or lack of signal from the qubits. The presence of qubits in the first semiconductor substrate with expected coherence properties and satisfied coupling can also be determined.

[0016] A drawback of separate fabrication approaches is the demands on interconnection technology, especially when multiple spin defects are present: spin defects (e.g., qubits) must be addressed in one-, two-, or three-dimensional configurations.

[0017] The prior art teaches the fabrication of diamond-based devices hosting NV centers for quantum technology and quantum coupling applications. The production of diamond-based devices uses the fabrication of control structures (e.g., coils, transmission lines, etc.) either directly on the diamond substrate or on a separate material / device.

[0018] For example, Tim Schroder et al. "Quantum nanophotonics in diamond," Journal of the Optical Society of America B 33, B65 (2016) reports recent developments in diamond nano- and microphotonic structures for efficient light collection, coupling of color centers to nanocavities, complex integration of diamond devices with other material systems, and a wide range of fabrication methods that enable complex photonic diamond systems.

[0019] John F. Barry et al. "Sensitivity optimization for NV-diamond magnetometry" Rev. Mod. Phys. 92, 015004 (2020) discloses methods to enhance the sensitivity of broadband ensemble-NV diamond magnetometers, improving the spin dephasing time, readout fidelity, and material properties of the host diamond.

[0020] Emilie Bourgeois et al. "Photoelectric Detection and Quantum Readout of Nitrogen-Vacancy Center Spin States in Diamond", Adv. Optical Mater. 8, 1902132 (2020) discloses a method for readout of the electron spin states of negatively charged nitrogen-vacancy (NV) point defects in diamond based on photoelectric detection of NV magnetic resonance.

[0021] H. Zhang et al. "Selective addressing of solid-state spins at the nanoscale via magnetic resonance frequency encoding" npj Quantum Information 3,31 (2017) describes nanoscale magnetic resonance frequency encoding to achieve site-selective addressing and coherent control of four-site arrays of NV spins.

[0022] Christopher Foy et al. "A CMOS-integrated quantum sensor based on nitrogen-vacancy centers" Nature Electronics 2, 284 (2019) discloses NV-based quantum sensing integrated with complementary metal-oxide-semiconductor (CMOS) technology to create a compact and scalable platform.

[0023] Mikhail Y. Shalaginov et al. "On-Chip Single-Layer Integration of Diamond Spins with Microwave and Plasmonic Channels", ACS Photonics 7, 2018 (2020) discloses an on-chip integrated structure for nitrogen-vacancy (NV) spin-based applications, implemented within a single material layer with one patterning step.

[0024] MI Ibrahim et al. "A Scalable Quantum Magnetometer in 65nm CMOS with Vector-Field Detection Capability," 2019 IEEE International Solid-State Circuits Conference - (ISSCC), 2019, pp. 458-461, doi: 10.1109 / ISSCC.2019.8662434 discloses a CMOS-NV quantum sensor with a highly scalable microwave delivery structure and a Talbot effect-based optical filter with an amplified green-to-red suppression ratio.

[0025] However, both direct and separate fabrication currently use wire bonds or direct device contacts to achieve interconnection between the semiconductor substrate and the control structures. It would therefore be advantageous to develop an architecture that allows for direct interconnection between the semiconductor substrate and the control and readout structures.

[0026] Quantum devices and technologies based on solid-state qubits require optical and / or magnetic and electric fields to initialize, manipulate and / or read out the spin state of the qubits.

[0027] One known solution that allows for the connection of two different semiconductor substrates is flip-chip technology. Flip-chip technology provides solutions to different manufacturing challenges related to the assembly process, for example, by using flip-chip solder bumping, compression, fusion, or thermal bonding. Flip-chip technology allows for the vertical integration of different semiconductor substrates and control structures into hybrid integrated circuits, enabling a scalable manufacturing approach.

[0028] Several prior art documents are known that describe the use of flip-chip technology for ISSQC. For example, International Patent Application WO2022008792A1 (IQM Technology) discloses a quantum computing circuit including two chips stacked together in a flip-chip configuration and attached to each other by bump bonding including bonding bumps. The first chip is made of aluminum oxide, copper, and palladium, and the second chip is made of a different material from the first chip to avoid unwanted interactions between the qubits and other circuit elements of the quantum processor.

[0029] US Patent 10355193B2 (IBM) describes a qubit flip-chip assembly that includes qubits formed on a first chip and an optically transmissive path formed on a second chip. The two chips are joined using solder bumps. The optically transmissive path can provide optical access to the qubits on the first chip. The first chip has a semiconductor substrate made from a highly resistive silicon wafer.

[0030] US Patent Application 20040182914 (Emcore) discloses a p-type contact for flip-chip bonding, in which the p-type III-nitride layer of a III-nitride flip-chip light-emitting diode die is in electrical contact with a bonding pad.

[0031] US Patent Application No. 6262489B1 (Delphi) discloses a method and assembly for mounting IC semiconductor devices to a substrate using flip-chip technology.

[0032] US Patent Application US7049704B2 (Intel) disclosed a package that allows both electrical and optical coupling between one or more integrated circuits and a printed circuit board that has optical waveguide structures in addition to electrical connections.

[0033] US Patent Application US6265775B1 (Micron) discloses a flip-chip semiconductor die bonded to a counter substrate such as a silicon wafer.

[0034] Matsumae T et al. “Low-temperature direct bonding of InP and diamond substrates under atmospheric conditions”. Sci Rep. 2021 May 27;11(1):11109. doi: 10.1038 / s41598-021-90634-4. PMID: 34045611; PMCID: PMC8159945 discloses an InP substrate directly bonded onto a diamond heat spreader for efficient heat dissipation.

[0035] R. Ishihara et al., "3D Integration Technology for Quantum Computer based on Diamond Spin Qubits," 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2021, pp. 14.5.1-14.5.4, doi: 10.1109 / IEDM19574.2021.9720552, discloses a quantum chip with multiple optically coupled modules, each containing a single diamond-based spin defect.

[0036] International Patent Application WO2020254040A1 (IBM) discloses a flip-chip assembly including a Josephson junction providing a quantum bit, the Josephson junction being disposed on a substrate which may comprise diamond.

[0037] U.S. Patent Application 2019 / 0165238 A1 (IBM) discloses a flip-chip assembly including a first chip and a second chip joined using solder bumps, where an optical transmission path disposed on the second chip can provide optical access to quantum bits disposed on the first chip.

[0038] The use of diamond substrates for quantum chips is known, for example, from German patent application DE 10 20 20 12 5 183 A1 (Quantum Tech GmbH), which discloses a scalable quantum computer based on a diamond substrate with impurity centers with CMOS circuitry.

[0039] International patent application WO2021051163A1 (ANU) discloses a quantum information processing device having a diamond substrate, an assembly, an arrangement, a system, and a sensor. Summary of the Invention [Problem to be solved by the invention]

[0040] One of the challenges in using flip-chip technology for the fabrication of ISSQC is connecting the diamond substrate to the semiconductor device without wire bonds. An additional challenge with flip-chip technology for ISSQC is controlling the physical properties of the connection between the quantum substrate and the semiconductor device. [Means for solving the problem]

[0041] Brief Summary of the Invention This document teaches a flip-chip assembly for integrated solid-state quantum circuits. The flip-chip assembly includes a first chip including a first semiconductor substrate. The first semiconductor substrate includes a plurality of spin defects, the plurality of spin defects being coupled by spin-spin interactions, and the plurality of spin defects (13) host a plurality of qubits. The flip-chip assembly further includes a second chip including a second semiconductor substrate bonded to the first chip. The second chip includes a plurality of control structures and readout structures. The first semiconductor substrate is a diamond substrate. The diamond substrate can be a monolithic diamond substrate, i.e., includes a single substrate made of diamond.

[0042] The use of a second chip structure allows control and readout structures to be easily fabricated on the second chip and connected to the qubits in the first chip by flip-chip bonding. The assembly and methods described herein can therefore avoid wire bonds, allowing for small form factors and vertical integration. Vertical integration allows for connection of qubits in the diamond substrate to the control and readout structures.

[0043] The plurality of qubits in the first semiconductor substrate include a plurality of spin defects. The first semiconductor substrate may further include impurities selected from at least one of boron, aluminum, gallium, indium, thallium, nihonium, nitrogen, phosphorus, arsenic, antimony, bismuth, beryllium, and lithium. These impurities help stabilize the charge of the qubits and may also affect the coherence properties of the qubits.

[0044] In a further embodiment, the readout structure is integrated into a third chip.

[0045] The second semiconductor substrate may, for example, comprise a transparent material that allows for the fabrication of optical waveguides in the second semiconductor substrate.

[0046] This document also describes a method for fabricating an integrated solid-state quantum circuit. The method includes providing a first chip including a first semiconductor substrate, the first semiconductor substrate including a plurality of spin defects. The plurality of spin defects are coupled by spin-spin interactions. The plurality of spin defects (13) host a plurality of qubits. The first semiconductor substrate is a diamond substrate. The method also includes fabricating a plurality of control and readout structures on a second semiconductor substrate, followed by aligning the first chip to the second chip. Finally, the first chip is bonded to the second chip, thereby forming a flip-chip assembly.

[0047] The spin defects are fabricated, for example, by atomic-scale fabrication in a first semiconductor substrate, and the activation, creation, and / or transformation of the spin defects is controlled by chemical, electrical, thermal, optical procedures, or ion irradiation.

[0048] The bonding of the first chip to the second chip is performed by at least one of metal-to-semiconductor bonding, metal-to-metal bonding, solder bump bonding or adhesive bonding, thermal compression bonding, vacuum bonding, eutectic-fusion bonding, or anodic bonding.

[0049] In a further embodiment, a plurality of control structures and readout structures are developed on a third chip.

[0050] After bonding, the method includes testing the flip-chip assembly and verifying the alignment and bonding of the first chip to the second or third chip.

[0051] Finally, the method includes packaging the flip-chip assembly for at least one of thermal management, electrical shielding, magnetic shielding, and / or radiation shielding.

[0052] The complete ISSQC method and flip-chip assembly allows for decoupling of manufacturing processes between and on separate semiconductor substrates. The complete ISSQC method and flip-chip assembly allows for avoiding the need for wire bonds. The method and assembly of this document lead to smaller scale chips. Flip-chip technology offers the possibility of vertical integration of semiconductor substrates, thereby helping to reduce the overall area occupied by readout and control structures. The reduced overall area allows for improved thermal management.

[0053] The assemblies and methods presented herein also allow for the separation of the difficulty of creating solid-state qubits in semiconductor materials (i.e., diamond) from the difficulty of creating control structures and devices that include the control and readout structures. [Brief explanation of the drawings]

[0054] [Figure 1] Figure 1 shows the flip chip assembly of ISSQC using flip chip technology. [Figure 2] Figure 2 shows an alternative concept for the method and assembly of ISSQC using flip-chip technology. [Figure 3] FIG. 3 shows an alternative concept for flip-chip assembly with a first transparent semiconductor substrate. [Figure 4] FIG. 4 shows an alternative concept for flip-chip assembly with a second transparent semiconductor substrate. [Figure 5] FIG. 5 shows an alternative concept of flip-chip assembly with a light emitting device integrated into a second transparent semiconductor substrate. [Figure 6] FIG. 6 shows an alternative concept of flip-chip assembly with a light emitting device on one side of a first semiconductor substrate. [Figure 7]FIG. 7 shows an alternative concept of flip-chip assembly having a light-emitting device and a third chip including electrical-interface routings (e.g., an interposer) between one or more control structures and another or multiple others. [Figure 8] Figure 8 shows the assembly process for ISSQC. DETAILED DESCRIPTION OF THE INVENTION

[0055] Detailed Description of the Invention The present invention will now be described based on the figures. It will be understood that the embodiments and aspects of the invention described herein are examples only and do not limit the scope of protection of the claims in any way. The invention is defined by the claims and their equivalents. It will be understood that features of one aspect or embodiment of the invention can be combined with features of different aspects or aspects and / or embodiments of the invention.

[0056] FIG. 1 illustrates a first embodiment of the present invention. FIG. 1 shows an ISSQC flip-chip assembly 1 using flip-chip technology. The flip-chip assembly 1 includes a first chip 10 having a first semiconductor substrate 12 and a second chip 20 having a second semiconductor substrate 22. The flip-chip assembly 1 includes flip-chip bond interconnects 32 connecting the first chip 10 to the second chip 20. The second semiconductor substrate 22 includes a control structure 24 and a readout structure 26.

[0057] First semiconductor substrate 12 is referred to as the "front-end-of-line" (FEOL) portion of the manufacturing process, with FEOL being the first portion of flip-chip assembly 1. First semiconductor substrate 12 has a plurality of spin defects 13. In one embodiment, the plurality of spin defects 13 are bulk spin defects 13 located within semiconductor substrate 12 (as shown in FIG. 1 ), although this is not a limitation of the present invention. In another embodiment, the plurality of spin defects 13 are surface spin defects 13 located at or on a top surface 14 of first semiconductor substrate 12. In yet a further embodiment, the plurality of spin defects 13 is a combination of bulk spin defects 13 and surface spin defects 13.

[0058] The first semiconductor substrate 12 is made of diamond. The diamond substrate may be a monolithic diamond substrate, i.e., comprise a single substrate made of diamond. The spin defects 13 may be pre-existing in the first semiconductor substrate 12. The spin defects 13 may be grown or created on the top surface 14 of the first semiconductor substrate 12, or in an epitaxial layer or bulk material of the first semiconductor substrate 12. The spin defects 13 may also be grown or created in the first semiconductor substrate 12. The spin defects 13 are referred to as "in-grown defects" and may be manufactured through atomic-scale fabrication, incorporated during the growth of the first semiconductor substrate 12, or created by particle and / or light irradiation and / or ion implantation.

[0059] The spin defects 13 can be coupled by spin-spin interactions, which include interactions between electron spins associated with the spin defects 13. The spin-spin interactions include interactions between electron spins and nuclear spins associated with the spin defects 13.

[0060] The spin-spin interaction (magnetic dipole-dipole interaction) is the inverse of the cube, i.e., 1 / r 3where r is the defect distance between interacting electron spins. As the defect distance between interacting ones of the spin defects 13 increases, the spin-spin interaction decreases rapidly. A defect distance of << 20 nm allows for strong coupling between the spin defects 13, and the spin-spin interaction enables high-fidelity, high-speed quantum computing on qubits (see below) associated with the spin defects 13. The coupling strength can be given in frequency. A defect distance << 20 nm allows for coupling strengths in the >> kHz, e.g., up to the MHz range.

[0061] During fabrication of semiconductor device 12, fabrication of spin defects 13 can be controlled, for example, by atomic-scale fabrication, such that the defect distance is within a predetermined range. In one example, the predetermined range of defect distances between spin defects 13 includes values ​​of 20 nm or less. In another example, the range includes values ​​of 10 nm or less. In further examples, the range includes values ​​of about 5 nm, values ​​of 3 nm or more and 7 nm or less, or values ​​of 4 nm or more and 6 nm or less, etc.

[0062] Controlling the defect distance of the spin defects 13 during fabrication, for example by atomic-scale fabrication, allows for control of the interaction of electron spins in the spin defects 13, i.e., the interaction of the spin magnetic moments of electrons in the spin defects 13. This interaction is governed by the following equation: 3 (see above), allowing for entanglement of interacting electron spins.

[0063] In a non-limiting example, the spin defects 13 are NV centers or carbon-13 (C-13) in diamond. The spin defects 13 function as (or are associated with) quantum bits. The spin states of the electron spin and / or nuclear spin are associated with the NV center to provide the quantum bit. The nuclear spin can be associated with a nitrogen atom or a carbon atom. The spin defects 13 can be initialized and addressed optically, electrically, or magnetically. The quantum bit can be entangled by spin-spin interactions that couple the spin defects 13.

[0064] In an alternative embodiment, the spin defects 13 are impurities or dopant elements 15 in the first semiconductor substrate 12, as will be explained below.

[0065] The qubits or solid-state qubits in the first semiconductor substrate 12 can be addressed and manipulated using at least one of optical, electric, and magnetic fields. The optical, electric, or magnetic fields are transmitted between the first semiconductor substrate 12 and the control structure 24 of the second semiconductor substrate 22, as will be described below. In one embodiment, solid-state qubits exist for nitrogen-vacancy (NV) centers in diamond and for carbon isotopes that possess non-zero nuclear spin. Other elements, such as Si or other group 4 elements, can create similar spin defects 13, such as silicon-vacancy centers (SiV), in the diamond of the first semiconductor substrate 12.

[0066] The activation, creation and transformation of spin defects 13 can be controlled by chemical, electrical, optical, or thermal procedures (eg, annealing), although this is not a limiting aspect of the present invention.

[0067] Nitrogen vacancy (NV) centers can be created by introducing nitrogen into the diamond lattice. One non-limiting example of vacancy creation is irradiation, such as ion irradiation, electron radiation, proton irradiation, or laser light irradiation. In an alternative embodiment, nitrogen is introduced into the diamond lattice during the growth of the diamond (e.g., the first semiconductor substrate 12), or incorporated through implantation or diffusion from the top surface 14 of the diamond. The diffusion of nitrogen into the diamond lattice can be activated and / or assisted by chemical, electrical, or thermal and optical annealing, but this is not a limitation of the present invention.

[0068] The manufacturing process of the first semiconductor substrate 12 may include the introduction of impurities or dopant elements 15 into the first semiconductor substrate 12. The dopant elements 15 are electron donor and acceptor impurities. Such additional elements (e.g., dopant elements 15) can adjust the electrical, optical, and structural material properties of the first semiconductor substrate 12, as well as the properties of the solid-state quantum bits within the first semiconductor substrate 12. The electron donor and acceptor impurities are atomic elements that possess electron spin and / or nuclear spin. The dopant elements 15 can be controlled and manipulated by external (electrical, optical, magnetic) fields. The dopant elements 15 can be activated and / or diffused within the first semiconductor substrate 12 by thermal annealing, optical annealing, or by ion implantation.

[0069] Non-limiting examples of acceptor impurities are boron, aluminum, gallium, indium, thallium, and nihonium. Non-limiting examples of donor impurities are nitrogen, phosphorus, arsenic, antimony, bismuth, beryllium, and lithium. Dopant elements 15 enable charge stabilization of negatively charged NV centers in diamond. Dopant elements 15 can also affect the coherence properties of the electron spin state of the NV centers.

[0070] Adjusting the concentration of the added dopant elements 15 in the first semiconductor substrate 12 allows for control of the material properties of the first semiconductor substrate 12. A fixed number of qubits are assumed to be at known positions and known depths within the first semiconductor substrate 12.

[0071] 1 is referred to as the "back-end-of-line (BEOL)" portion of ISSQC manufacturing. Second semiconductor substrate 22 includes a plurality of control structures 24 and readout structures 26. Control structures 24 and readout structures 26 are developed in or on separate semiconductor substrates, for example, on second semiconductor substrate 22.

[0072] However, this does not limit the embodiment of the invention, and the control structure 24 and the readout structure 26 can be developed on a third chip 30, as shown in Figure 7. The second semiconductor substrate 22 and the third chip 30 are made of silicon, in a non-limiting example. According to this embodiment, the optical device 16 is integrated into the third chip 30.

[0073] The control structures 24 or control field structures are, for example, DC / AC magnetic fields (coils, microcoils, MW / RF antennas), transmission lines 29, magnetic structures, and DC / AC electric fields (electrodes). The control structures 24 are used not only to generate optical, electric, and / or magnetic fields, but also to control, initialize, manipulate, and read out the spin state of a given qubit in the first semiconductor substrate 12.

[0074] The readout structure 26 is, for example, a memory device, a logic device, a communication device, a sensor, an optical device, a capacitor, a FET, a current amplifier, a CMOS logic IC.

[0075] According to one embodiment, the second semiconductor substrate 22 has a front surface 22a and a back surface 22b. The front surface 22a and the back surface 22b of the second semiconductor substrate 22 may include a transparent substrate 25, a transmission line 29, a planar and / or vertical electrode structure, and a readout structure 26.

[0076] The second semiconductor substrate 22 has flip-chip bonding interconnects 32 on its front side 22a configured for bonding the second chip 20 to the first chip 10, as shown in Figures 1-6. The flip-chip bonding interconnects 32 include, for example, metal contacts, insulating layers (dielectrics), magnetic structures, metal levels, and bonding sites for flip-chip technology and for connecting the chip to the package.

[0077] The optical device 16 shown in Figures 3-7 is used for emitting and / or delivering and / or detecting an optical field to / from the first semiconductor substrate 12 or to / from the second semiconductor substrate 22. In one embodiment, the optical device 16 enables the emission of an optical field and can be, but is not limited to, an LED diode, a laser diode, or a diode pumped solid state (DPSS). In a further embodiment, the optical device 16 enables the delivery of an optical field and can be, but is not limited to, a fiber or a waveguide. In a further embodiment, the optical device 16 enables the detection of an optical field and can be, but is not limited to, light meters, photometers, photodetectors, photodiodes, etc. In still further embodiments, the optical device 16 can include an optical filter, such as, but not limited to, a notch filter, a high bandpass filter, or a low bandpass filter.

[0078] 3, optical device 16 emits and / or delivers an optical field through first semiconductor substrate 12. In a non-limiting example, at least a portion of first semiconductor substrate 12 is transparent to visible and near-infrared light wavelengths.

[0079] Figure 4 illustrates an alternative concept of flip-chip assembly 1 having a transparent substrate 25. Transparent substrate 25 is transparent to visible and near-infrared wavelengths of light, allowing an optical signal, such as an optical field coming from first semiconductor substrate 12, to be transmitted and collected through flip-chip assembly 1. In the example of Figure 4, the optical field is emitted from optical device 16 through transparent substrate 25 and through second semiconductor substrate 22.

[0080] The optical device 16 can be developed on a separate substrate or can be integrated with the flip-chip assembly 1 by stacking and packaging. Figure 5 shows a flip-chip assembly 1 having an optical device 16 integrated or fabricated in a second semiconductor substrate 22.

[0081] Figure 6 shows flip-chip assembly 1 illuminated from one side of first semiconductor substrate 12 by optical device 16. Optical device 16 activates spin defects 13 in first semiconductor substrate 12 by emitting an optical field. Optical device 16 is then used to read out the qubits from flip-chip assembly 1. According to the embodiment of Figure 6, first semiconductor substrate 12 is transparent to visible and near-infrared light wavelengths.

[0082] The transmission lines 29 are used to transmit and collect optical, electromagnetic (AC / DC current, MW / RF signals), and radio-frequency (radio-frequency) fields through the flip-chip assembly 1. By way of non-limiting example, the transmission lines 29 are transparent or semi-transparent to allow for the optical transmission of visible or near-infrared optical signals. Optical, radio-frequency, microwave, and electromagnetic (AC / DC current, MW / RF signals) signals generated within the first semiconductor substrate 12 can be transmitted through the transmission lines 29 to the second semiconductor substrate 22 via readout structures 26 (e.g., electrodes) on the second semiconductor substrate 22 that are connected to the control field structures 24.

[0083] The transmission line 29 can be provided on either the front surface 22a of the second semiconductor substrate 22 or on the top surface 14 of the first semiconductor substrate 12, but this is not a limitation of the present invention. In one example, Figure 1 shows the transmission line 29 provided on the first semiconductor substrate 12, with some of the control structures 24 developed on the front surface 22a of the second semiconductor substrate 22. In another example, Figure 2 shows the transmission line 29 provided on the second semiconductor substrate 22, with some of the control structures 24 developed on the top surface 14 of the first semiconductor substrate 12.

[0084] Electrode structures and readout structures 26 on the front surface 22 a of the second semiconductor substrate 22 allow current to flow between the first semiconductor substrate 12 and the second semiconductor substrate 22 through the flip-chip assembly 1 .

[0085] In an alignment step, the top surface 14 of the first semiconductor substrate is aligned with the associated features of the second semiconductor substrate 22. Verification of the alignment can be performed by in situ optical, magnetic, and electrical measurements suitable for registering the positions of the qubits, for example, by optical imaging and nuclear and electron spin magnetic resonance spectroscopy techniques.

[0086] The final steps in the fabrication of flip chip assembly 1 may include the materials (e.g., flip chip bonding interconnects 32) and / or surface treatments necessary to achieve the interconnection between first semiconductor substrate 12 and second semiconductor substrate 22.

[0087] The flip-chip bond interconnects 32 enable interconnection between at least one of the surfaces (e.g., top surface 14) of the first semiconductor substrate and at least one of the structural or device surfaces (e.g., front surface 22a and back surface 22b) of the second semiconductor substrate 22. The flip-chip bond interconnects 32 include solder pads, metal pads, adhesive active areas, or surface active areas, but this is not a limitation of the present invention.

[0088] Flip-chip bonding interconnects 32 are used for bonding the flip-chip assembly 1 and can be implemented by, for example, metal-to-semiconductor bonding, metal-to-metal bonding, solder bump or adhesive bonding, thermal compression bonding, vacuum bonding, eutectic-fusion bonding, and anodic bonding. Eutectic bonding is already used in the semiconductor industry to create electrical contacts (e.g., ohmic contacts, Schottky contacts).

[0089] In one embodiment, the ISSQC manufacturing process includes a testing and packaging step. The testing step of the flip-chip assembly 1 is used to verify the alignment and bonding of the control structure 24, readout structure 26, top surface 14 of the first semiconductor substrate 12, and front surface 22a and back surface 22b of the second semiconductor substrate 22. The packaging step is a process in which the flip-chip assembly 1 is packaged in a protective structure that provides thermal management, magnetic shielding, and electrical shielding over a preferred frequency range.

[0090] In the packaging step, bonding a cap wafer to the flip chip assembly 1 may provide the required protection in preparation for subsequent process steps. Sealing the ISSQC at the cap wafer level may provide a higher level of cleanliness, so that testing and packaging steps can be performed before dicing.

[0091] In an alternative embodiment, the fabrication of the second semiconductor substrate 22 having the control structures 24 and readout structures 26 is separated from the fabrication of the first semiconductor substrate 12. In this alternative embodiment, shown in Figure 2, the control structures 24 (e.g., microcoils, contacts, electrode structures) are fabricated directly on the top surface 14 of the first semiconductor substrate 12. According to this embodiment, the readout structures 26 and flip-chip bonded interconnects 32 are fabricated on the second semiconductor substrate 12.

[0092] FIG. 8 shows a flow diagram for a method of fabricating an integrated solid-state quantum circuit.

[0093] In step S101, a first chip 10 is provided. In step S102, a first semiconductor substrate 12 is fabricated on the first chip 10. The first semiconductor substrate 12 is made of diamond.

[0094] In step S103, spin defects 13 are fabricated in the first semiconductor substrate 12 through one of atomic-scale fabrication, particle irradiation, ion implantation, or laser irradiation. As previously described, the spin defects 13 can be grown on the top surface 14 of the first semiconductor substrate 12, or can be distributed within the bulk of the first semiconductor substrate 12. The activation, creation, and conversion of all of the spin defects 13, or at least some of the spin defects 13 into qubits, can be controlled by chemical, electrical, optical, or thermal procedures (e.g., annealing).

[0095] In step S104, dopant elements 15 are introduced into the first semiconductor substrate 12. The introduction of dopant elements 15 in step S104 can be performed before or simultaneously with step S103.

[0096] In step S105, a second chip 20 is provided on which a plurality of control structures 24 and readout structures 26 are fabricated in step S106. In an alternative embodiment, the control structures 24 are fabricated on the top surface 14 of the first semiconductor substrate 12, and the transmission lines 29 are fabricated on the back surface 22b of the second semiconductor substrate 22. The readout structures 26 are fabricated on the second semiconductor substrate 22.

[0097] In step S107, transmission lines 29 are fabricated on the second semiconductor substrate 22. In an alternative embodiment, the transmission lines 29 are fabricated on the first semiconductor substrate 12. The transmission lines 29 allow electromagnetic fields to be transmitted and collected through the flip-chip assembly 1. Optical signals, radio frequency signals, and microwave signals can be transmitted through the transmission lines 29.

[0098] The transmission line 29 is fabricated using, for example, metal deposition, sputtering, evaporation, CVD, optical lithography, photolithography, e-beam lithography, and soft lithography.

[0099] In step S108, flip-chip bonded interconnects 32 are added to the second semiconductor substrate 22. The flip-chip bonded interconnects 32 enable interconnection between at least one surface of the first semiconductor substrate 12 and at least one surface (e.g., the front surface 22a or the back surface 22b) of the second semiconductor substrate 22. To achieve the flip-chip bonded interconnects 32, solder pads, metal pads, adhesive activation areas, or surface activation areas can be used.

[0100] In step S109, the surfaces of the first chip 10 and the second chip 20 are aligned to establish control and readout of individual or multiple quantum bits in the first semiconductor substrate 12. In an alternative embodiment, the surface of the second chip 20 and / or the surface of the third chip 30 are aligned to the first chip 10, as shown in FIG.

[0101] In step S110, the first chip 10 is bonded to the second chip 20 using at least one of flip-chip bonding, solder bump or adhesive bonding, thermocompression bonding, vacuum bonding, eutectic fusion bonding, and anodic bonding.

[0102] In the assembly step S111, the flip chip assembly 1 is assembled.

[0103] In a testing step S112, the flip-chip assembly 1 is tested to verify successful alignment of the control structure 24, the transmission line 29, and bonding of the surfaces of the first and second chips 10 with the surfaces of the control structure 24 and the readout structure 26. Step S112 is an optional step, and the flip-chip assembly 1 can be packaged (in step S113) immediately after step S111, if necessary. It will also be understood that the assembly step S111 and the testing step S112 can be performed in parallel.

[0104] In packaging step S113, flip chip assembly 1 is packaged in a protective structure that provides thermal management and magnetic, electrical, and radiation shielding of flip chip assembly 1 from external field sources. According to one example, packaging step S113 can be an optional step. [Explanation of symbols]

[0105] 1: Flip chip assembly 10: First chip 12: First semiconductor substrate 13:Spin defect 14: Upper surface of first semiconductor substrate 15: Dopant element 16: Optical devices 20: Second chip 22: Second semiconductor substrate 22a:Front 22b: Back 25: Transparent substrate 24: Control Structures 26: Readout structure 29: Transmission line 30: Third chip 32: Flip-chip bonded interconnect

Claims

1. A flip-chip assembly (1) of an integrated solid-state quantum circuit comprising: A first chip (10) including a first semiconductor substrate (12), The first semiconductor substrate (12) includes a plurality of spin defects (13); the plurality of spin defects (13) are coupled by spin-spin interactions; the plurality of spin defects (13) hosting a plurality of qubits; A first chip (10); a second chip (20) including a second semiconductor substrate (22) bonded to the first chip (10), The second chip (20) includes a plurality of control structures (24) and readout structures (26); a second chip (20); Including, A flip-chip assembly (1), wherein the first semiconductor substrate (12) is a diamond substrate.

2. The flip chip assembly (1) of claim 1, wherein the plurality of spin defects (12) comprises surface spin defects and / or bulk spin defects.

3. 3. The flip chip assembly of claim 1, wherein the first semiconductor substrate (12) further comprises an impurity selected from at least one of boron, aluminum, gallium, indium, thallium, nihonium, nitrogen, phosphorus, arsenic, antimony, bismuth, beryllium, and lithium.

4. 2. The flip chip assembly of claim 1, wherein the readout structure (26) is integrated into a third chip (30).

5. 10. The flip chip assembly of claim 1, wherein the second semiconductor substrate (20) comprises a transparent material.

6. 1. A method of fabricating an integrated solid-state quantum circuit, comprising: Providing a first chip (10) including a first semiconductor substrate (12), The first semiconductor substrate (12) includes a plurality of spin defects (13); the plurality of spin defects (13) are coupled by spin-spin interactions; the plurality of spin defects (13) host a plurality of qubits; the first semiconductor substrate (12) is a diamond substrate; fabricating a plurality of control structures (24) and readout structures (26) on a second semiconductor substrate (22); aligning the first chip (10) with the second chip (20); and b. bonding the first chip (10) to the second chip (20), thereby forming a flip chip assembly (1).

7. The method of claim 6, further comprising atomic-scale fabrication of the plurality of spin defects (13) in the first semiconductor substrate (12).

8. 8. The method of claim 7, wherein the activation, creation, and / or transformation of the plurality of spin defects (13) is controlled by chemical, electrical, thermal, optical procedures, or ion irradiation.

9. 7. The method of claim 6, wherein bonding of the first chip (10) to the second chip (20) is performed by at least one of metal-to-semiconductor bonding, metal-to-metal bonding, solder bump bonding, adhesive bonding, thermocompression bonding, vacuum bonding, eutectic fusion bonding, or anodic bonding.

10. The method of claim 6, wherein the plurality of control structures (24) and readout structures (26) are developed on a third chip (30).

11. 7. The method of claim 6, further comprising testing the flip chip assembly (1), wherein testing the flip chip assembly (1) comprises verifying alignment and bonding of the first chip (10) and the second chip (20).

12. The method of claim 6, further comprising aligning at least one of a third chip (30) or the second chip (20) to the first chip (10).

13. 7. The method of claim 6, further comprising packaging the flip chip assembly (1) with at least one of thermal management or electrical shielding, magnetic shielding, or radiation shielding.

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