MEMORY SYSTEM, METHOD AND CONTROLLER

Abstract

A method for reducing power consumption in a memory system includes determining (602), by a controller of the memory system, that a condition is met based on a plurality of commands received by the memory system during a first period of time, wherein a frequency or voltage applied to one or more processors of the controller is reduced (604) by the controller in response to determining that the condition is met.

Description

[Technical Field]

[0001] The present disclosure relates to memory devices, memory systems, and methods for controlling power consumption in flash memories. [Background technology]

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Various operations, such as program (write) operations and read operations, can be performed by flash memory. The operations performed by flash memory can affect the power consumption of the flash memory. Summary of the Invention

[0003] The present disclosure relates to a memory system, a method, and a controller for reducing power consumption in a memory system. One exemplary method includes determining, by a controller of the memory system, that a condition is met based on a plurality of commands received by the memory system during a first period of time. A frequency or voltage applied to one or more processors of the controller is reduced by the controller in response to determining that the condition is met.

[0004] Although generally described as computer-implemented software embodied on a tangible medium that processes and transforms respective data, some or all of the aspects may be computer-implemented methods or may further be included in respective systems or other devices for performing the described functions. Details of these and other aspects and implementations of the present disclosure are set forth in the accompanying drawings and description below. Other features, objects, and advantages of the present disclosure will be apparent from the specification and drawings, and from the claims. [Brief explanation of the drawings]

[0005] [Figure 1] FIG. 1 illustrates a block diagram of an example of a system having a memory device in accordance with some aspects of the present disclosure. [Figure 2] 1 illustrates a diagram of an example memory system in accordance with some aspects of the present disclosure. [Figure 3] 1 illustrates a diagram of an example memory controller coupled to a power management controller in accordance with some aspects of the present disclosure. [Figure 4] 1 illustrates an example workflow for changing a core frequency or core voltage applied to a processor of a memory controller in a memory system, in accordance with some aspects of the present disclosure. [Figure 5] 1 illustrates an example of changes in power consumption associated with different memory device operations after changes in core frequency and core voltage, according to some aspects of the present disclosure. [Figure 6] 1 illustrates an example flowchart of a method for reducing power consumption in a memory system in accordance with some aspects of the present disclosure.

[0006] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION OF THE INVENTION

[0007] This specification relates to a memory system, method, and controller for reducing power consumption in a memory system. In some cases, memory devices in a memory system, such as NAND flash memory devices, can perform operations including sequential reads and sequential writes of data. A sequential read or write operation of a memory device is an operation in which data is read from or written to a memory device sequentially. The power consumption of the memory system due to sequential read or write operations of memory devices in the memory system may increase as the speed of the sequential read or write operations increases. To avoid excessive power consumption during sequential read or write operations, a memory controller of the memory system that controls the memory devices in the memory system can change the core frequency or core voltage applied to the processor of the memory controller to reduce the power consumption of the memory system while maintaining a high speed of the sequential read or write operations. Changing the core frequency or core voltage can also help avoid excessive temperature of the memory devices during sequential read or write operations.

[0008] FIG. 1 illustrates a block diagram of an example system 100 having a memory device according to some aspects of the present disclosure. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG. 1 , the system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of the electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 108 may be configured to transmit data to and receive data from the memory device 104.

[0009] The memory device 104 can be any memory device disclosed in this disclosure. According to some implementations, the memory controller 106 is coupled to the memory device 104 and the host 108 and configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some implementations, the memory controller 106 is designed to operate in a low-duty-cycle environment, such as a Secure Digital (SD) card, a CompactFlash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, and mobile phones. In some implementations, the memory controller 106 is designed to operate in a high-duty-cycle environment, such as a solid-state drive (SSD) or embedded multimedia card (eMMC) used as data storage for mobile devices such as smartphones, tablets, and laptop computers, and enterprise storage arrays. The memory controller 106 can be configured to control operations of the memory device 104, such as read, erase, and program operations. Memory controller 106 may also be configured to manage various functions related to data stored or to be stored in memory device 104, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, memory controller 106 is further configured to process error correcting codes (ECC) on data read from or written to memory device 104. Any other suitable functions, such as formatting memory device 104, may also be performed by memory controller 106.

[0010] The memory controller 106 can communicate with an external device (e.g., the host 108) according to a particular communication protocol. For example, the memory controller 106 may communicate with the external device via at least one of a variety of interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.

[0011] The memory controller 106 and one or more memory devices 104 can be incorporated into various types of storage devices and can be included in the same package, such as a universal flash storage (UFS) package or an eMMC package. That is, the memory system 102 can be implemented and packaged in different types of end electronic products. In some implementations, the memory system 102 can be implemented and packaged in an SSD, such as a client SSD or an enterprise SSD. Client SSDs can be used in electronic devices such as personal computers, digital cameras, smartphones, and mobile devices. Enterprise SSDs can be used in enterprise environments such as data centers or servers.

[0012] 2 shows a diagram of an example memory system 200. The memory system 200 includes a memory controller 202, a volatile memory device 206, non-volatile memory devices 208, 210, and 212, and a power management controller 204. The memory controller 202 is described in more detail in FIG. 3. The memory controller 202 is coupled to the volatile memory device 206, the non-volatile memory devices 208, 210, and 212, and the power management controller 204. In some implementations, the volatile memory device 206 can be used to cache data that can be accessed by the memory controller 202. In some implementations, the memory device 206 can be a non-volatile memory device.

[0013] In some implementations, memory controller 202 controls operations performed by non-volatile memory devices 208, 210, and 212. Exemplary operations may include sequential read operations, sequential write operations, idle operations, and other operations. Other operations may include random read operations and random write operations. Memory controller 202 may change a core frequency or a core voltage applied to a processor within memory controller 202. Figure 4 illustrates an example of a workflow for changing a core frequency or a core voltage applied to a processor of a memory controller within a memory system.

[0014] In some implementations, the memory controller 202 can send commands to the power management controller 204 to enable the power management controller 204 to change the core voltage applied to the processor within the memory controller 202 .

[0015] FIG. 3 shows a diagram 300 of an example of a memory controller coupled to a power management controller. Memory controller 302 may correspond to memory controller 202 of FIG. 2. Memory controller 302 includes tightly coupled memories 304 and 312, a main CPU 306, another CPU 314, a shared memory 316, and a phase-locked loop (PLL) frequency adjustment module 308. Main CPU 306 and another CPU 314 are processors within memory controller 302 for supporting operation of memory devices controlled by memory controller 302. Other CPU 314 may include one or more secondary CPUs controlled by main CPU 306. Memory controller 302 is coupled to power management controller 310. Tightly coupled memory 304 is coupled to main CPU 306, and tightly coupled memory 312 is coupled to other CPU 314. Tightly coupled memory 304 includes a command sequence mode determination module 318, a frequency and voltage change module 320, and a CPU synchronization module 322. The tightly coupled memory 312 includes a CPU synchronization module 324 and a command group counter module 326 .

[0016] In some implementations, the command sequence mode determination module 318 can determine a command sequence mode associated with the main CPU 306. The command sequence modes can include a sequential read mode, a sequential write mode, an idle mode, and other modes. In the sequential read mode, the main CPU 306 supports sequential read operations of the memory device controlled by the memory controller 302. In the sequential write mode, the main CPU 306 supports sequential write operations of the memory device controlled by the memory controller 302. In the idle mode, the main CPU 306 supports idle operations of the memory device controlled by the memory controller 302, in which the main CPU 306 receives no commands or few commands from the host. In other modes, the main CPU 306 supports other operations of the memory device controlled by the memory controller 302. Examples of other operations can include random read operations and random write operations.

[0017] In some implementations, the frequency and voltage change module 320 can change the core frequency or core voltage applied to the main CPU 306 and the other CPUs 314. The CPU synchronization module 322 can perform synchronization operations for the main CPU 306, where the main CPU 306 finishes its current command and waits for the main CPU 306 and the other CPUs 314 to complete their core frequency or core voltage change before continuing to process a new command or task.

[0018] In some implementations, the CPU synchronization module 324 can perform synchronization operations for the other CPUs 314, which finish their current commands and wait for the main CPU 306 and the other CPUs 314 to complete core frequency changes or core voltage changes before continuing to process new commands or tasks.

[0019] In some implementations, the command group counter module 326 can count and monitor the number of commands associated with each command sequence mode and received by the memory controller 302 during a particular period of time. The main CPU 306 can use the monitored number of commands associated with each command sequence mode to determine when to change the core frequency or core voltage applied to the main CPU 306 and the other CPUs 314.

[0020] In some implementations, the main CPU 306 can control a PLL frequency adjustment module 308 coupled to the main CPU 306 to change the core frequencies applied to the main CPU 306 and the other CPUs 314. A shared memory 316 is coupled to both the main CPU 306 and the other CPUs 314 for storing data shared between the main CPU 306 and the other CPUs 314.

[0021] In some implementations, the main CPU 306 can control a power management controller 310 coupled to the main CPU 306 to change the core voltage applied to the main CPU 306 and the other CPUs 314. The power management controller 310 can correspond to the power management controller 204 of Figure 2. The main CPU 306 can send commands to the power management controller 310 to change the core voltage applied to the main CPU 306 and the other CPUs 314.

[0022] FIG. 4 illustrates an example workflow 400 for changing the core frequency or core voltage applied to a processor of a memory controller in a memory system.

[0023] At 402, a primary processor of a memory controller in a memory system determines that conditions are met for changing a core frequency or core voltage applied to one or more processors of the memory controller. In some implementations, the memory controller, e.g., memory controller 302 of FIG. 3, can be a system-on-chip (SOC). The one or more processors can include a primary processor, e.g., main CPU 306 of FIG. 3, and one or more secondary processors, e.g., other CPU 314 of FIG. 3.

[0024] In some implementations, to determine whether the condition is met, the main processor first monitors the number of commands received by the memory controller for sequential reads, e.g., sequential read commands with a command size of 128 KB, and the number of commands received by the memory controller for sequential writes, e.g., sequential write commands with a command size of 128 KB, during a certain period (e.g., a first period). For example, the period can be 1 second.

[0025] In some implementations, if the monitored number of sequential read commands received by the memory controller during the period is greater than a read threshold, the main processor determines that a condition is met for changing a core frequency or core voltage applied to one or more processors of the memory controller, which may be reduced to a target frequency or target voltage, respectively, to reduce power consumption associated with read and / or write operations of memory devices controlled by the memory controller.

[0026] In some implementations, if the monitored number of sequential write commands received by the memory controller during the period is greater than a write threshold, the main processor determines that a condition is met for modifying a core frequency or core voltage applied to one or more processors of the memory controller, which may be reduced to a target frequency or target voltage, respectively, to reduce power consumption associated with read and / or write operations of memory devices controlled by the memory controller.

[0027] In some implementations, if the monitored number of combined sequential write commands and the monitored number of sequential write commands received by the memory controller during the period are greater than a total threshold, the main processor determines that a condition is met for changing a core frequency or a core voltage applied to one or more processors of the memory controller, which may be reduced to a target frequency or target voltage, respectively, to reduce power consumption associated with read and / or write operations of memory devices controlled by the memory controller.

[0028] In some implementations, the read threshold, write threshold, or total threshold may be predetermined based on the read or write performance that the main processor can support without incurring excessive power consumption in the memory system. For example, the core frequency applied to the main CPU is 800 MHz, and the read performance that the main processor can support is 30% of a maximum read speed of 14 GB per second. The read threshold may then be set to 14 GB * 0.3 / (128 * 1024), which is approximately 32,000 commands per second. As another example, the write performance that the main processor can support is 30% of a maximum write speed of 10 GB per second. The read threshold may then be set to 10 GB * 0.3 / (128 * 1024), which is approximately 23,000 commands per second.

[0029] In some implementations, to avoid an excessive number of frequency or voltage changes within a certain period of time, the main processor may also monitor a delay time duration (e.g., a second period of time) as an additional condition for determining whether to change the core frequency or core voltage. For example, if a period equivalent to the delay time duration has not elapsed since the core frequency or core voltage was last changed, the main processor will not change either the core frequency or core voltage even if the condition is met. If the condition is met after a period equal to the delay time duration has elapsed since the core frequency or core voltage was last changed, the main processor may change the core frequency or core voltage.

[0030] In some implementations, the main processor may also check the garbage collection state of each memory device controlled by the memory controller as another condition for determining whether to change the core frequency or core voltage. For example, during the garbage collection process of a memory device controlled by the memory controller, the main processor may increase the core frequency or core voltage regardless of whether the other conditions above are met. As another example, if none of the memory devices controlled by the memory controller are in a garbage collection state, the main processor may determine whether to change the core frequency or core voltage based on the other conditions above.

[0031] In some implementations, if the main processor determines that the memory device controlled by the memory controller is not in one of a sequential read mode, a sequential write mode, or a garbage collection mode, the main processor does not change the core frequency and core voltage.

[0032] At 404, the main processor changes the core frequency to the target frequency or the core voltage to the target voltage after determining that the conditions for changing the core frequency or the core voltage are met. In some implementations, the target frequency and the target voltage can be predetermined based on testing and calculation. For example, the target frequency can be predetermined so that the read and write performance of a memory device controlled by the memory controller, such as an SSD, is not affected by the target frequency. The target frequency can be a frequency lower than the core frequency. In another example, the target voltage can be predetermined so that the target voltage can support the stability of a memory device controlled by the memory controller.

[0033] Table 1 below includes example target frequencies and target voltages for different input / output (I / O) command sequence cases. The example target frequencies and target voltages can be further adjusted based on testing the read and write performance of memory devices controlled by the memory controller.

[0034] [Table 1]

[0035] In some implementations, to change the core frequency to a target frequency or the core voltage to a target voltage, each of the one or more processors may first perform a synchronization operation. During the synchronization operation, each processor may first finish processing its current command and then wait for the process of changing the frequency and voltage to be completed for the processor. This wait state for each of the one or more processors may be a common designated state. Code for each processor to perform the synchronization operation may be stored in tightly coupled memory, such as tightly coupled memory 304 for main CPU 306 or tightly coupled memory 312 for other CPU 314 in FIG. 3 .

[0036] In some implementations, after each CPU finishes processing its current command during synchronous operation, the main processor can change the core frequency to the target frequency by modifying a phase-locked loop (PLL) register, such as the PLL frequency adjustment module 308 in Figure 3. The target frequency can be lower than the core frequency to reduce power consumption associated with read and / or write operations of memory devices controlled by the memory controller.

[0037] In some implementations, after reducing the core frequency, the main processor can change the core voltage to a target voltage by sending a corresponding command to a power management integrated circuit (PMIC) for voltage change. The target voltage can be lower than the core voltage to reduce power consumption associated with read and / or write operations of memory devices controlled by the memory controller.

[0038] In some implementations, after the main processor has changed both the core frequency and the core voltage, each CPU can finish the synchronization function and then continue processing new tasks.

[0039] 5 illustrates an example of the change in power consumption associated with different memory device operations after changing the core frequency and core voltage. For a sequential read operation in this example, the SOC core voltage changes from 0.8V to 0.78V, and the SOC core frequency changes from 1200MHz to 800MHz, resulting in a change in SOC power consumption from 18W to 16W. For a sequential write operation in this example, the SOC core voltage changes from 0.8V to 0.78V, and the SOC core frequency changes from 1200MHz to 800MHz, resulting in a change in SOC power consumption from 24W to 22W. For an idle operation in this example, the SOC core voltage changes from 0.8V to 0.76V, and the SOC core frequency changes from 1200MHz to 400MHz, resulting in a change in SOC power consumption from 6W to 4W. For the other operations in this example, the SOC core voltage and SOC core frequency are not changed, resulting in no change in SOC power consumption.

[0040] 6 illustrates an example flowchart 600 of a method for reducing power consumption in a memory system according to some aspects of the present disclosure. At 602, a controller of the memory system determines that a condition is met based on a plurality of commands received by the memory system during a first period of time.

[0041] At 604, the controller reduces the frequency or voltage applied to one or more processors of the controller in response to determining that the condition is met.

[0042] Certain aspects of the subject matter described herein may be implemented as a memory system including a memory device and a controller coupled to the memory device, the controller configured to perform operations including determining, based on a plurality of commands received by the memory system during a first period of time, that a condition is met, and reducing a frequency or voltage applied to one or more processors of the controller in response to determining that the condition is met.

[0043] The memory system may include one or more of the following features.

[0044] In some implementations, the multiple commands include at least one of sequential write commands or sequential read commands.

[0045] In some implementations, the operations further include determining that a second period of time has elapsed since the frequency or voltage applied to the one or more processors of the controller was last reduced, and reducing the frequency or voltage applied to the one or more processors of the controller includes reducing the frequency or voltage applied to the one or more processors of the controller in response to determining that the condition is met and that the second period of time has elapsed since the frequency or voltage applied to the one or more processors of the controller was last reduced.

[0046] In some implementations, reducing the frequency or voltage applied to one or more processors of the controller includes reducing the frequency applied to one or more processors of the controller followed by reducing the voltage applied to one or more processors of the controller.

[0047] In some implementations, the first period of time is immediately prior to the time when the frequency or voltage applied to one or more processors of the controller is reduced.

[0048] In some implementations, the memory system is in a sequential write mode, a sequential read mode, or an idle mode.

[0049] In some implementations, before reducing the frequency or voltage applied to one or more processors of the controller, the operations further include, in response to determining that the condition is met, completing all current tasks of the one or more processors and synchronizing each of the one or more processors to a common specified state.

[0050] In some implementations, after reducing the frequency or voltage applied to one or more processors of the controller, the operations further include executing a new task on the one or more processors.

[0051] In some implementations, reducing the frequency applied to the one or more processors includes reducing the frequency applied to the one or more processors using a phase-locked loop (PLL) register in the controller.

[0052] In some implementations, the one or more processors include a main processor and one or more secondary processors, and the memory system further includes a power management integrated circuit (PMIC) coupled to the controller, and reducing the voltage applied to the one or more processors includes determining, by the main processor, one or more commands based on a plurality of parameters monitored by the one or more processors, and sending, by the main processor, the one or more commands to the PMIC to reduce the voltage applied to the one or more processors.

[0053] In some implementations, before reducing the frequency or voltage applied to the one or more processors of the controller, the operations further include determining that the memory system is not in a garbage collection mode, and reducing the frequency or voltage applied to the one or more processors of the controller includes reducing the frequency or voltage applied to the one or more processors of the controller in response to determining that the condition is met and the memory system is not in garbage collection.

[0054] In some implementations, the conditions include an amount of commands received by the memory system during a first period of time greater than a threshold, a ratio of the threshold to the first period of time greater than or equal to 32,000, and the first period of time being greater than or equal to 1 second.

[0055] Certain aspects of the subject matter described herein may be implemented as a method, the method including determining, by a controller of a memory system, that a condition is met based on a plurality of commands received by the memory system during a first period of time, wherein a frequency or voltage applied to one or more processors of the controller is reduced by the controller in response to determining that the condition is met.

[0056] The method can include one or more of the following features.

[0057] In some implementations, the multiple commands include at least one of sequential write commands or sequential read commands.

[0058] In some implementations, the method further includes determining that a second period of time has elapsed since the frequency or voltage applied to the one or more processors of the controller was last reduced, and reducing the frequency or voltage applied to the one or more processors of the controller includes reducing the frequency or voltage applied to the one or more processors of the controller in response to determining that the condition is met and that the second period of time has elapsed since the frequency or voltage applied to the one or more processors of the controller was last reduced.

[0059] In some implementations, reducing the frequency or voltage applied to one or more processors of the controller includes reducing the frequency applied to one or more processors of the controller followed by reducing the voltage applied to one or more processors of the controller.

[0060] In some implementations, before reducing the frequency or voltage applied to one or more processors of the controller, the method further includes, in response to determining that the condition is met, completing all current tasks of the one or more processors and synchronizing each of the one or more processors to a common specified state.

[0061] In some implementations, after reducing the frequency or voltage applied to one or more processors of the controller, the method further includes executing a new task on the one or more processors.

[0062] In some implementations, reducing the frequency applied to the one or more processors includes reducing the frequency applied to the one or more processors using a phase-locked loop (PLL) register in the controller.

[0063] In some implementations, the one or more processors include a main processor and one or more secondary processors, and the memory system further includes a power management integrated circuit (PMIC) coupled to the controller, and reducing the voltage applied to the one or more processors includes determining, by the main processor, one or more commands based on a plurality of parameters monitored by the one or more processors, and sending, by the main processor, the one or more commands to the PMIC to reduce the voltage applied to the one or more processors.

[0064] In some implementations, before reducing the frequency or voltage applied to the one or more processors of the controller, the method further includes determining that the memory system is not in a garbage collection mode, and reducing the frequency or voltage applied to the one or more processors of the controller includes reducing the frequency or voltage applied to the one or more processors of the controller in response to determining that the condition is met and the memory system is not in garbage collection.

[0065] In some implementations, the conditions include an amount of commands received by the memory system during a first period of time greater than a threshold, a ratio of the threshold to the first period of time greater than or equal to 32,000, and the first period of time being greater than or equal to 1 second.

[0066] Certain aspects of the subject matter described herein can be implemented as a controller of a memory system configured to perform operations including determining, by the controller, that a condition is met based on a plurality of commands received by the memory system during a first period of time, and reducing, by the controller, a frequency or voltage applied to one or more processors of the controller in response to determining that the condition is met.

[0067] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of what may be claimed, but rather as descriptions of features that may be specific to particular implementations. Certain features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations, separately, or in any subcombination. Furthermore, while the features described above may be described as working in a particular combination and initially claimed as such, one or more features from a claimed combination may, in some cases, be deleted from the combination, and the claimed combination may be directed to a subcombination or a variation of the subcombination.

[0068] As used in this disclosure, the terms "a," "an," or "the" are used to include one or more unless the context clearly dictates otherwise. The term "or" is used to refer to a non-exclusive "or" unless otherwise specified. The phrase "at least one of A and B" is synonymous with "A, B, or A and B." Furthermore, phrases or terms used in this disclosure, unless otherwise defined, are for descriptive purposes only and not for limiting purposes. The use of section headings is intended to aid in the reading of the document and should not be construed as limiting. Information associated with a section heading may occur within or outside of that particular section.

[0069] As used in this disclosure, the term "about" or "approximately" may allow for some variation in a value or range, for example, within 10%, within 5%, or within 1% of a stated value or the limits of a stated range.

[0070] As used in this disclosure, the term "substantially" refers to a majority or majority, such as at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or more.

[0071] Values ​​expressed in range format should be interpreted flexibly to include not only the numerical values ​​explicitly recited as the limits of the range, but also all individual numerical values ​​or subranges subsumed within that range, as if each numerical value and subrange were explicitly recited. For example, a range of "0.1% to about 5%" or "0.1% to 5%" should be interpreted to include about 0.1% to about 5%, as well as individual values ​​(e.g., 1%, 2%, 3%, and 4%) and subranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%) within the stated range. "X to Y" is equivalent to "about X to about Y" unless otherwise specified. Similarly, the term "X, Y, or Z" is equivalent to "about X, about Y, or about Z," unless otherwise specified.

[0072] Specific implementations of the present subject matter have been described. Other implementations, modifications, and permutations of the described implementations are within the scope of the following claims, as will be apparent to those skilled in the art. Although operations may be shown in the drawings or claims in a particular order, such operations need not be performed in the particular order shown, or in sequential order, to achieve desirable results, or even that all of the operations shown be performed (although some operations may be considered optional). In particular situations, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and performed as deemed appropriate.

[0073] Furthermore, the separation or integration of the various system modules and components in the above-described implementations may not be required in all implementations, and the described components and systems may generally be integrated together or packaged into multiple products.

[0074] Accordingly, the foregoing exemplary implementations do not define or limit this disclosure, and other changes, substitutions, and alterations are also possible without departing from the spirit and scope of this disclosure.

Claims

1. 1. A memory system comprising: a memory device; a controller coupled to the memory device, determining that a condition is met based on a plurality of commands received by the memory system during a first period of time; reducing a frequency or voltage applied to one or more processors of the controller in response to determining that the condition is met; and a controller configured to perform operations including: A memory system comprising:

2. 2. The memory system of claim 1, wherein the plurality of commands includes at least one of a sequential write command and a sequential read command.

3. The operation is determining that a second period of time has elapsed since the frequency or the voltage applied to the one or more processors of the controller was last reduced; Further comprising: Reducing the frequency or the voltage applied to the one or more processors of the controller may include: reducing the frequency or the voltage applied to the one or more processors of the controller in response to determining that the condition is met and that the second period of time has elapsed since the frequency or the voltage applied to the one or more processors of the controller was last reduced.

3. The memory system of claim 1, comprising:

4. 4. The memory system of claim 1, wherein reducing the frequency or the voltage applied to the one or more processors of the controller comprises reducing the frequency applied to the one or more processors of the controller and then reducing the voltage applied to the one or more processors of the controller.

5. 5. The memory system of claim 1, wherein the first period of time is immediately before the moment when the frequency or the voltage applied to the one or more processors of the controller is reduced.

6. The memory system of claim 1 , wherein the memory system is in a sequential write mode, a sequential read mode, or an idle mode.

7. Before reducing the frequency or the voltage applied to the one or more processors of the controller, the operation In response to determining that the condition is met, completing all current tasks on said one or more processors; and synchronizing each of said one or more processors to a common designated state; The memory system of claim 1 , further comprising:

8. After reducing the frequency or the voltage applied to the one or more processors of the controller, the operation comprises: executing a new task on said one or more processors; The memory system of claim 1 , further comprising:

9. 9. The memory system of claim 1, wherein reducing the frequency applied to the one or more processors comprises reducing the frequency applied to the one or more processors using a phase-locked loop (PLL) register in the controller.

10. the one or more processors comprising a primary processor and one or more secondary processors, and the memory system further comprising a power management integrated circuit (PMIC) coupled to the controller, wherein reducing the voltage applied to the one or more processors comprises: determining, by the main processor, one or more commands based on a plurality of parameters monitored by the one or more processors; sending, by the main processor, the one or more commands to the PMIC to reduce the voltage applied to the one or more processors; 10. The memory system of claim 1, comprising:

11. Before reducing the frequency or the voltage applied to the one or more processors of the controller, the operation determining that the memory system is not in garbage collection mode; Further comprising: Reducing the frequency or the voltage applied to the one or more processors of the controller may include: reducing the frequency or the voltage applied to the one or more processors of the controller in response to determining that the condition is met and the memory system is not in garbage collection.

11. The memory system of claim 1, comprising:

12. 12. The memory system of claim 1, wherein the conditions include an amount of the plurality of commands received by the memory system during the first period of time being greater than a threshold, a ratio of the threshold to the first period of time being greater than or equal to 32,000, and the first period of time being greater than or equal to 1 second.

13. determining, by a controller of a memory system, that a condition is met based on a plurality of commands received by the memory system during a first period of time; reducing, by the controller, a frequency or voltage applied to one or more processors of the controller in response to determining that the condition is satisfied; A method comprising:

14. The method of claim 13 , wherein the plurality of commands includes at least one of sequential write commands or sequential read commands.

15. determining that a second period of time has elapsed since the frequency or the voltage applied to the one or more processors of the controller was last reduced; Further comprising: Reducing the frequency or the voltage applied to the one or more processors of the controller may include: reducing the frequency or the voltage applied to the one or more processors of the controller in response to determining that the condition is met and that the second period of time has elapsed since the frequency or the voltage applied to the one or more processors of the controller was last reduced.

15. The method of claim 13 or 14, comprising:

16. 16. The method of claim 13, wherein reducing the frequency or the voltage applied to the one or more processors of the controller comprises reducing the frequency applied to the one or more processors of the controller and then reducing the voltage applied to the one or more processors of the controller.

17. Before reducing the frequency or the voltage applied to the one or more processors of the controller, the method comprises: In response to determining that the condition is met, completing all current tasks on said one or more processors; and synchronizing each of the one or more processors to a common designated state; 17. The method of any one of claims 13 to 16, further comprising:

18. After reducing the frequency or the voltage applied to the one or more processors of the controller, the method further comprises: executing a new task on said one or more processors; 18. The method of any one of claims 13 to 17, further comprising:

19. 19. The method of claim 13, wherein reducing the frequency applied to the one or more processors comprises reducing the frequency applied to the one or more processors using a phase-locked loop (PLL) register in the controller.

20. the one or more processors comprising a primary processor and one or more secondary processors, and the memory system further comprising a power management integrated circuit (PMIC) coupled to the controller, wherein reducing the voltage applied to the one or more processors comprises: determining, by the main processor, one or more commands based on a plurality of parameters monitored by the one or more processors; sending, by the main processor, the one or more commands to the PMIC to reduce the voltage applied to the one or more processors; 20. The method of any one of claims 13 to 19, comprising:

21. Before reducing the frequency or the voltage applied to the one or more processors of the controller, the method comprises: determining that the memory system is not in garbage collection mode; Further comprising: Reducing the frequency or the voltage applied to the one or more processors of the controller may include: reducing the frequency or the voltage applied to the one or more processors of the controller in response to determining that the condition is met and the memory system is not in garbage collection.

21. The method of any one of claims 13 to 20, comprising:

22. 22. The method of claim 13, wherein the conditions include an amount of the plurality of commands received by the memory system during the first period of time being greater than a threshold, a ratio of the threshold to the first period of time being greater than or equal to 32,000, and the first period of time being greater than or equal to 1 second.

23. A controller for a memory system, comprising: determining, by the controller, that a condition is met based on a plurality of commands received by the memory system during a first period of time; reducing, by the controller, a frequency or voltage applied to one or more processors of the controller in response to determining that the condition is satisfied; a controller configured to perform operations including:

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