Semiconductor chamber parts using advanced coating technology

Abstract

The present technology is generally directed to semiconductor processing systems and methods. The systems and methods include a chamber having multiple chamber components, such as a pedestal, a lid stack, a face plate, an electrode, and a showerhead. The face plate is supported by the lid stack and defines a plurality of first apertures. The showerhead is positioned between the face plate and the pedestal and defines a plurality of second apertures. In the systems and methods, the face plate, the showerhead, the lid stack, the pedestal, or a combination thereof includes a coating of yttrium fluoride, yttrium oxyfluoride, or both yttrium fluoride and yttrium oxyfluoride having a thickness greater than 10 μm on at least a portion of the respective chamber component or combination thereof.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. patent application Ser. No. 18 / 181,077, filed Mar. 9, 2023, entitled "SEMICONDUCTOR CHAMBER COMPONENTS WITH ADVANCED COATING TECHNIQUES," the entire contents of which are incorporated herein by reference.

[0002]

[0002] The present technology relates to semiconductor systems, processes, and apparatus. More particularly, the present technology relates to systems that form or include coatings on chamber components. [Background technology]

[0003]

[0003] Integrated circuits are realized by processes that create intricately patterned layers of material on a substrate surface. Creating patterned materials on a substrate requires a controlled method for removing exposed material. Chemical etching is used for a variety of purposes, including transferring a photoresist pattern to an underlying layer, thinning a layer, or narrowing the lateral dimensions of features already present on a surface. It is often desirable to have an etching process that etches some materials faster than others, for example, to facilitate the pattern transfer process. Such an etching process is said to be selective to the first material. Due to the variety of materials, circuits, and processes, etching processes have been developed that are selective to a variety of materials.

[0004] Etching processes are sometimes referred to as wet or dry, depending on the materials used in the process. Wet HF etching preferentially removes silicon oxide over other dielectrics and materials. However, wet processes can have difficulty penetrating some confined trenches and sometimes deform the remaining material. Wet processes can also damage chamber components. For example, HF etchants can chemically attack chamber components made of metals, such as aluminum alloys. Dry etching, which is performed in a localized plasma formed within the substrate processing region, can penetrate more confined trenches and is less likely to deform the fragile remaining structures. However, localized plasma can damage the substrate due to electric arcs that occur when the localized plasma discharges. The localized plasma and plasma effluents can also damage chamber components.

[0005]

[0005] Therefore, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. The present technique addresses the above needs and others. Summary of the Invention

[0006]

[0006] Embodiments of the present technology are generally directed to a semiconductor processing system. The system includes a chamber having multiple chamber components, such as a pedestal, a lid stack, a faceplate, and a showerhead. In the system, the pedestal is configured to support a semiconductor substrate. In the system, the faceplate is supported by the lid stack and defines a plurality of first apertures. In embodiments, the showerhead is positioned between the faceplate and the pedestal and defines a plurality of second apertures. In the system, the faceplate, the showerhead, the lid stack, the pedestal, or a combination thereof includes a coating of yttrium fluoride, yttrium oxyfluoride, or both yttrium fluoride and yttrium oxyfluoride having a thickness greater than 10 μm or less than about 100 nm on at least a portion of the respective chamber component or combination thereof.

[0007] In embodiments, the faceplate, the showerhead, or both the faceplate and the showerhead define a chamber-facing surface, the surface having an exposed surface area, and about 80% or more of the exposed surface area includes a coating of yttrium fluoride, yttrium oxyfluoride, or both yttrium fluoride and yttrium oxyfluoride. In more embodiments, about 90% or more of the exposed surface area of ​​the faceplate, the showerhead, or both the faceplate and the showerhead includes a coating of yttrium fluoride, yttrium oxyfluoride, or both yttrium fluoride and yttrium oxyfluoride. Further, in embodiments, the coating of yttrium fluoride, yttrium oxyfluoride, or both yttrium fluoride and yttrium oxyfluoride has a thickness of about 50 μm or greater on at least a portion of the respective chamber component or combination thereof. Additionally or alternatively, in embodiments, the plurality of first open pores, the plurality of second open pores, or a combination thereof, define an open surface having an open surface area, and about 70% or more of the open surface area comprises a coating of yttrium fluoride, yttrium oxyfluoride, or both yttrium fluoride and yttrium oxyfluoride. In further embodiments, the coating of yttrium fluoride, yttrium oxyfluoride, or both yttrium fluoride and yttrium oxyfluoride on the open surface further comprises yttrium oxide, YOFx, or a combination thereof.

[0008]

[0008] Embodiments of the present technology also include a method for coating a component of a semiconductor processing chamber. The method includes positioning a component having an exposed surface in the chamber. The method includes depositing a coating including yttrium oxide on at least a portion of the exposed surface. The method includes exposing the coating to a high-power plasma treatment at a power of about 2 Watts or greater and a pressure of 500 mTorr. The method includes flowing a fluorine-containing precursor into the chamber in a high-power plasma process, forming a plasma from the fluorine-containing precursor to generate plasma effluents, and contacting a surface of the coating with the plasma effluents. The method includes converting at least a portion of the yttrium oxide in the coating to yttrium fluoride, yttrium oxyfluoride, or both yttrium fluoride and yttrium oxyfluoride.

[0009] In embodiments, the plasma further comprises hydrogen, ammonia, helium, argon, or a combination thereof. In more embodiments, the fluorine-containing precursor comprises nitrogen trifluoride. Further embodiments include methods in which the yttrium oxide is deposited by atomic layer deposition, plasma spray, electron beam, chemical vapor deposition, physical vapor deposition, plasma-enhanced chemical vapor deposition, or a combination thereof. In more embodiments, the yttrium oxide is deposited by a combination of atomic layer deposition and plasma spray or electron beam. Additionally or alternatively, in embodiments, the component defines a plurality of apertures, each aperture having an exposed aperture surface, and the coating is deposited on at least a portion of the exposed aperture surface. In further embodiments, the high-power plasma process comprises a power of about 10 watts to about 3000 watts, a pressure of about 1 Torr to about 15 Torr, and a voltage of about 10 volts to about 1000 volts. In embodiments, the high-power plasma process is carried out for a time sufficient to convert at least about 50% by weight of the yttrium oxide to yttrium fluoride, yttrium oxyfluoride, or both yttrium fluoride and yttrium oxyfluoride. In further embodiments, the high-power plasma process is carried out for at least about 1 hour. In even more embodiments, the high-power plasma process is carried out for a period sufficient to achieve a coating thickness of about 1 μm or greater.

[0010]

[0010] Embodiments of the present technology are also generally directed to a method for coating one or more components of a semiconductor processing chamber. The method includes positioning a plurality of chamber components having exposed surfaces within the semiconductor processing chamber. Included are methods in which the components are a faceplate defining a plurality of first apertures and a showerhead defining a plurality of second apertures. The method includes depositing a coating comprising yttrium oxide on at least a portion of the exposed surfaces of the plurality of chamber components. The method includes converting at least a portion of the yttrium oxide to yttrium fluoride, yttrium oxyfluoride, or both yttrium fluoride and yttrium oxyfluoride within the semiconductor processing chamber.

[0011] In embodiments, the plurality of chamber components further includes a lid stack supporting the faceplate and a pedestal configured to support the semiconductor substrate. In more embodiments, the method is performed under pressure. In further embodiments, the semiconductor processing chamber further includes a first electrode and a second electrode, the first electrode and the second electrode configured to provide at least about 2 watts of power during conversion.

[0012] Such techniques may offer many advantages over conventional systems and techniques. For example, embodiments of the present technology may protect even hard-to-reach areas of a chamber, such as increasingly small faceplate or showerhead apertures, from any number of corrosive processes. Additionally, coatings formed on the substrate support and / or other components may be maintained over hundreds or thousands of wafers due to increased coating density, potentially increasing throughput, and may be maintained in highly corrosive atmospheres. These and other embodiments, along with their many advantages and features, are described in more detail below and in the accompanying drawings.

[0013] A further understanding of the nature and advantages of the techniques of the present disclosure may be realized by reference to the remaining portions of the specification and the drawings. [Brief explanation of the drawings]

[0014] [Figure 1] 1 illustrates a top view of an exemplary processing system in accordance with some embodiments of the present technique. [Figure 2A]

[0015] 1 shows a schematic cross-sectional view of an exemplary processing chamber in accordance with an embodiment of the present technique; [Figure 2B]

[0016] 2B shows a detailed view of a portion of the processing chamber shown in FIG. 2A in accordance with an embodiment of the present technique. [Figure 3]

[0017] FIG. 1 illustrates a bottom view of an exemplary showerhead in accordance with an embodiment of the present technique. [Figure 4]

[0018] 1 illustrates exemplary steps in a method according to some embodiments of the present technology. [Figure 5]

[0019] 1A-C show schematic partial cross-sectional views of exemplary chamber components according to some embodiments of the present technique. DETAILED DESCRIPTION OF THE INVENTION

[0015]

[0020] Some figures are included as schematic diagrams. It is understood that the figures are for illustrative purposes and should not be considered to scale unless expressly stated to be to scale. Furthermore, as schematic diagrams, the figures are provided to aid in understanding and may not include all aspects or information compared to realistic depictions and may include material that is emphasized for illustrative purposes.

[0016]

[0021] In the accompanying drawings, similar components and / or features may have the same reference numerals. Furthermore, various components of the same type may be distinguished according to the reference numeral, with a letter distinguishing between the similar components. When only a first reference numeral is used in this specification, the description is applicable to any of the similar components having the same first reference numeral, regardless of the letter.

[0017]

[0022] Semiconductor processing can involve several steps that produce intricately patterned materials on a substrate. These steps can include several formation and removal processes that may utilize corrosive or erosive materials. These corrosive or erosive materials include plasma-enhanced materials formed remotely or at the substrate level. While etchants may preferentially etch substrate materials, chemical etchants may also contact other components within the chamber. Etchants can chemically attack components, and depending on the process being performed, plasma effluents may impinge on one or more components and erode material. Chemical and physical damage caused by etchants to chamber components can increase wear over time, increasing chamber replacement costs and downtime. Additionally, chamber contamination can occur from chamber substrate-reactive species particles formed by erosion of the chamber walls. As a non-limiting example, in some localized or wafer-level plasma processes, a showerhead or manifold may act as a ground electrode to generate the plasma in the substrate processing region. In this case, the substrate support or some other component may act as a plasma-generating electrode. Plasma species may impinge on the showerhead, which acts as a ground electrode, and metallic species forming the showerhead may be released into the plasma. If such metallic contaminants come into contact with the substrate, they may cause a short circuit during operation. Deposition processes can also use plasma-enhanced processes to form or deposit material on the substrate, which may also be deposited on chamber components.

[0018]

[0023] While conventional techniques have struggled to limit both corrosion and erosion of chamber components, they tend to periodically replace components due to damage caused by one or both of these corrosion and erosion mechanisms. Consequently, some conventional designs involve periodically replacing showerheads or coating them with impingement-resistant ceramic materials (e.g., yttrium oxide-based coatings). Attempts have been made to improve ceramic-based coatings using high-quality deposition techniques, such as electron beam or plasma spraying. However, while such coatings may perform well against some impingement and erosion, they do not adequately withstand chemical reactions with plasma effluent species or contact with high-energy plasma species. This exposure can still result in coating erosion or corrosion, especially in areas where the coating is poorly formed or where high-energy plasmas (e.g., capacitively coupled plasmas) are present.

[0019]

[0024] Furthermore, such coatings can reduce the amount of process gas or plasma present, especially during the first few substrates after the process begins. For example, ceramic coatings (such as yttrium oxide-based coatings) absorb plasma species and desorb hydrogen, causing the coating to delaminate and change composition after initial exposure to the process plasma. As a result, the properties of the film deposited on the first few substrates are significantly less than ideal due to the coating's interaction with the process plasma, a phenomenon often referred to as the "first wafer effect."

[0020]

[0025] Furthermore, chamber components can contain increasingly small features, such as showerheads and / or faceplates containing numerous apertures for delivering species through the chamber, as well as difficult-to-access connections, holes, lid stacks, and more. If a coating cannot completely coat all aperture sidewalls and all exposed surfaces, plasma species that may originate remotely can cause the same problems as closely-occurring species. Furthermore, if the holes are not small enough, localized plasma can leak through them and damage other upstream components. However, many line-of-sight coating systems cannot completely coat holes if the holes are small enough. Therefore, ceramic-based coatings have had difficulty adequately coating these small features. Even deposition methods that produce high-quality coatings, such as electron beam and plasma spraying, are inadequate for coating holes and features, especially as their dimensions continue to shrink. Additionally, these coating methods limit the deposition thickness of coatings to less than 10 μm, resulting in insufficient thickness and density for many high-energy processes. Attempts have been made to improve coverage of small features using atomic layer deposition (ALD). However, ALD is further limited in deposition thickness because the yttrium oxide coating thickness is less than 500 nm. As a result, existing chamber components have difficulty in long-term, stable operation in plasma environments, especially high-energy environments.

[0021]

[0026] The present technology overcomes these and other problems by applying a high-quality pre-halogenated coating to chamber components prior to substrate processing. For example, chamber components can be fully coated on surfaces exposed within a semiconductor processing chamber. Furthermore, the coating can be characterized by increased thickness and / or density, which not only improves resistance to both chemical and high-power plasma systems but also allows the components to be used for processing multiple wafers before the coating is reapplied. Furthermore, because the coating is already at least partially halogenated, the "first wafer effect" is significantly reduced, if not eliminated, eliminating the need for "seasoning" the chamber and substrates. Furthermore, the unique methods presented herein allow coatings from the present technology to be applied in situ within an assembled semiconductor processing chamber (e.g., a chamber utilized for processing substrates). Thus, the chamber and components therein can be easily recoated without removing the unit from the processing stream. Additionally, such a process can improve coverage of the exposed surfaces of the chamber and components, reducing the risk of corrosion and erosion during processing.

[0022]

[0027] While the remainder of the disclosure will routinely identify particular etching and deposition processes that utilize the disclosed technology, it will be readily understood that the systems and methods are equally applicable to deposition and cleaning processes that may be performed in the described chambers or other chambers. Correspondingly, the technology should not be viewed as limited to use with any particular etching process or etching chamber. Furthermore, while an exemplary chamber is described to provide a foundation for the technology, it should be understood that the technology is applicable to substantially any semiconductor processing chamber capable of performing the steps described.

[0023]

[0028] 1 illustrates a top view of one embodiment of a processing system 100 comprising a deposition chamber, an etch chamber, a bake chamber, and a cure chamber, according to an embodiment. In the figure, a pair of front opening unified pods (FOUPs) 102 provide substrates of various sizes, which are received by a robot arm 104 and placed in a low-pressure holding area 106, and then placed in one of the substrate processing chambers 108a-108f located in tandem sections 109a-109c. A second robot arm 110 can be used to transfer substrate wafers from the holding area 106 to the substrate processing chambers 108a-108f and vice versa. Each substrate processing chamber 108a-108f may be equipped to perform several substrate processing steps, including cyclic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), etching, pre-cleaning, degassing, alignment, and other substrate processes. The substrate processing chambers 108a-108f may include one or more system components for deposition, annealing, curing, and / or etching. Any one or more of the processes described herein may be performed in one or more chambers separate from the fabrication system shown in various embodiments. It will be understood that additional configurations of the chambers 108a-108f are contemplated by the system 100.

[0024]

[0029] 2A shows a cross-sectional view of an exemplary processing chamber system 200 having a separated plasma generation region within the processing chamber. During coating according to the present technique, process gases may flow into a first plasma region 215 through a gas injector assembly 205. A remote plasma system (RPS) 201 may optionally be included in the system and may process a first gas. The first gas then travels through the gas injector assembly 205. The injector assembly 205 may include two or more separate gas supply channels; if a second channel (not shown) is included, the second channel may bypass the RPS 201.

[0025]

[0030] Chamber components such as a cooling plate 203, a faceplate 217, an ion suppressor 223, a showerhead 225, and a pedestal 265 having a substrate 255 disposed thereon are shown, and each may be included according to an embodiment. The cooling plate and faceplate may, in some embodiments, serve as sides of a lid assembly, also referred to as a lid stack. The pedestal 265 may have heat exchange channels through which a heat exchange fluid flows to control the temperature of the substrate. The heat exchange channels may operate to heat and / or cool the substrate or wafer during processing. The wafer support platter of the pedestal 265, which may comprise aluminum, ceramic, or a combination thereof, may also be resistively heated and reach relatively high temperatures (e.g., from below about 100°C to above about 1100°C) using embedded resistive heating elements.

[0026]

[0031] The face plate 217 may be pyramidal, conical, or another similar structure that is narrow at the top and widens toward the bottom. The face plate 217 may also be flat, as shown, and may include multiple through channels used to distribute process gases. Depending on the use of the RPS 201, plasma-generating gases and / or plasma-excited species may pass through multiple holes in the face plate 217 shown in FIG. 2B to be more uniformly delivered into the first plasma region 215.

[0027]

[0032] An exemplary configuration may include gas inject assembly 205 communicating with gas feed region 258 separated from first plasma region 215 by faceplate 217 such that gases / species enter first plasma region 215 through holes in faceplate 217. Structural and operational features may be selected to prevent bulk backflow of plasma from first plasma region 215 back into feed region 258, gas inject assembly 205, and fluid delivery system 210. Faceplate 217 or the conductive top of the chamber and showerhead 225 are shown with insulating ring 220 positioned between these features, which allows an AC potential to be applied to faceplate 217 relative to showerhead 225 and / or ion suppressor 223. Insulating ring 220 may be positioned between faceplate 217 and showerhead 225 and / or ion suppressor 223, which allows for the formation of a capacitively coupled plasma (CCP) in the first plasma region. Baffles (not shown) may additionally be located within first plasma region 215 or otherwise coupled to gas injection assembly 205 to affect the flow of fluid entering this region through gas injection assembly 205.

[0028]

[0033] The ion suppressor 223 can include a plate or other geometry defining a plurality of apertures throughout its structure, configured to suppress the migration of ionic-charged species exiting the first plasma region 215 while allowing uncharged neutral or radical species to pass through the ion suppressor 223 and enter the activated gas supply region between the suppressor and the showerhead. In embodiments, the ion suppressor 223 can be or include a perforated plate with various aperture configurations. These uncharged species can include highly reactive species that are carried through the apertures with a less reactive carrier gas. As described above, migration of ionic species through the apertures can be reduced, and in some cases, completely prevented. Controlling the amount of ionic species passing through the ion suppressor 223 advantageously allows for improved control of the gas mixture that comes into contact with the underlying wafer substrate, which in turn allows for improved control of the deposition and / or etching characteristics of the gas mixture. For example, adjusting the ion concentration of the gas mixture can significantly change the etch selectivity (e.g., SiNx:SiOx etch ratio, Si:SiOx etch ratio, etc.) In alternative embodiments where deposition is performed, the balance between conformal and flowable style deposition of the dielectric material can also be shifted.

[0029]

[0034] The plurality of apertures in the ion suppressor 223 may be configured to control the passage of the activated gas (i.e., ionic species, radical species, and / or neutral species) through the ion suppressor 223. For example, the aspect ratio of the apertures (i.e., diameter to length of the aperture) and / or the geometry of the apertures may be controlled to reduce the flow rate of ionic charged species in the activated gas passing through the ion suppressor 223. The apertures in the ion suppressor 223 may include a tapered portion facing the plasma excitation region 215 and a cylindrical portion facing the showerhead 225. The cylindrical portion may be shaped and sized to control the flow rate of ionic species passing to the showerhead 225. As an additional means of controlling the flow rate of ionic species through the ion suppressor 223, an adjustable electrical bias may be applied to the ion suppressor 223.

[0030]

[0035] The ion suppressor 223 can function to reduce or eliminate the amount of ionic charged species that travel from the plasma generation region to the substrate. Uncharged neutral and radical species can still pass through the apertures in the ion suppressor and react with the substrate. Note that complete removal of ionic charged species within the reaction region around the substrate may not be achieved in some embodiments. In certain cases, ionic species are intended to reach the substrate to perform etching and / or deposition processes. In such cases, the ion suppressor can help control the concentration of ionic species within the reaction region at a constant level that supports the process.

[0031]

[0036] The showerhead 225, in combination with the ion suppressor 223, can prevent the plasma present in the first plasma region 215 from directly exciting gases in the substrate processing region 233, while still allowing excited species to migrate from the chamber plasma region 215 into the substrate processing region 233. In this manner, the chamber can be configured to prevent the plasma from contacting the substrate 255 being etched. This can advantageously protect various intricate structures and films patterned on the substrate, which may be damaged, misaligned, or otherwise distorted if the generated plasma directly contacts them. Furthermore, allowing the plasma to contact or approach the substrate level can increase the rate of etching performed by oxide species. Correspondingly, if the exposed area of ​​material is an oxide, maintaining the plasma away from the substrate can further protect this material.

[0032]

[0037] The processing system may further include a power supply 240 electrically connected to the processing chamber. The power supply 240 supplies power to the faceplate 217, the ion suppressor 223, the showerhead 225, and / or the pedestal 265 to generate a plasma in the first plasma region 215 or the processing region 233. The power supply may be configured to supply an adjustable amount of power to the chamber according to the process being performed. Such a configuration may enable the use of an adjustable plasma in the process being performed. Unlike remote plasma units, which often have an on or off function, an adjustable plasma may be configured to supply a specific amount of power to the plasma region 215 and / or the substrate processing region 233. This, in turn, may enable the development of specific plasma characteristics that may dissociate precursors in specific ways, thereby enhancing the etch profile produced by those precursors.

[0033]

[0038] A plasma can be ignited in either the chamber plasma region 215 above the showerhead 225, or the substrate processing region 233 below the showerhead 225, or in both the chamber plasma region 215 and the substrate processing region 233. A plasma can exist in the chamber plasma region 215, for example, to generate radical precursors from an inflow of fluorine-containing precursors or other precursors. An AC voltage, typically in the radio frequency ("RF") range, can be applied between a conductive top portion of the processing chamber, such as the faceplate 217, and the showerhead 225 and / or ion suppressor 223 to ignite a plasma in the chamber plasma region 215 during deposition. The RF power source can generate a high RF frequency of 13.56 MHz, but can also generate other frequencies, either alone or in combination with the 13.56 MHz frequency.

[0034]

[0039] FIG. 2B shows a detailed view 253 of features that affect the distribution of process gas through face plate 217. As shown in FIGS. 2A and 2B, the intersection of face plate 217, cooling plate 203, and gas inject assembly 205 defines gas delivery region 258. Gas delivery region 258 may be supplied with process gas from gas inject assembly 205. Gas may fill gas delivery region 258 and flow through apertures 259 in face plate 217 to first plasma region 215. Apertures 259 may be configured to direct flow in a substantially single direction, allowing process gas to flow into processing region 233 but partially or completely preventing backflow into gas delivery region 258 after traversing face plate 217.

[0035]

[0040] As shown, face plate 217 defines a plurality of apertures 259. It should be apparent that, although apertures 259 of any shape are contemplated, regardless of shape, each aperture 259 defines an exposed aperture surface 260 that extends around the interior periphery of each aperture 259 from a first side 261 of face plate 217 to a second side 262 of face plate 217, and that this surface is exposed to or in fluid communication with first plasma region 215 and gas inject assembly 205. Furthermore, in an embodiment, exposed aperture surfaces 260 of all apertures 259 may define the aperture surface area of ​​face plate 217.

[0036]

[0041] A gas delivery assembly such as showerhead 225 for use in processing chamber section 200, which may also be referred to as a dual channel showerhead (DCSH), is described in more detail in the embodiment depicted in Figure 3. A dual channel showerhead may provide an etching process that limits interaction with chamber parts and other etchants before being delivered to the processing region by isolating the etchant outside of the processing region 233.

[0037]

[0042] The showerhead 225 may include an upper plate 214 and a lower plate 216. The plates may be bonded together to define a space 218 between the plates. The plates may be bonded to provide a first aperture 219 through the upper and lower plates and a second aperture 221 through the lower plate 216. The formed channel may be configured to provide fluid access from the space 218 through the lower plate 216 only through the second aperture 221, and the first aperture 219 may be fluidly isolated from the space 218 between the plates and the second aperture 221. The space 218 may be fluidly accessible through a side of a gas supply assembly that includes the showerhead 225. However, it should be understood that in an embodiment, only a single type of aperture 219 may be defined through the showerhead 225, and / or the apertures 219 and 221 may be collectively referred to as “showerhead apertures.” Furthermore, in embodiments, both the first aperture 219 and the second aperture 221 may extend completely or partially through the showerhead 225 to provide fluid access between the first plasma region 215 and the processing region 233. Furthermore, in embodiments, the showerhead 225 may be formed from only one plate.

[0038]

[0043] Nevertheless, as shown, the showerhead 225 defines a plurality of apertures 219 / 221. While apertures 219 / 221 of any shape are contemplated, it will be apparent that, regardless of shape, each aperture 219 / 221 defines an exposed aperture surface 263 that extends around the periphery of each aperture 219 / 221 from a first side 264 of the showerhead 225 to a second side 266 of the showerhead 225, and that this aperture surface is exposed to or in fluid communication with the first plasma region 215 and the processing region 233. Furthermore, in embodiments, the exposed aperture surfaces 263 of all of the apertures 219 / 221 may define an aperture surface area of ​​the showerhead 225.

[0039]

[0044] FIG. 3 illustrates a bottom view of a showerhead 325 for use in a processing chamber, according to an embodiment. The showerhead 325 may correspond to the showerhead 225 illustrated in FIG. 2A. The through-holes 365, which represent the first apertures 219, can have multiple shapes and configurations to control and influence the flow rate of precursors through the showerhead 225. The small holes 375, which represent the second apertures 221, can be distributed approximately evenly over the surface of the showerhead, even between the through-holes 365. These small holes 375 can aid in more uniform mixing of the precursors as they exit the showerhead compared to other configurations.

[0040]

[0045] 4 illustrates exemplary steps of a method 400 according to some embodiments of the present technique. The method may be performed in a variety of processing chambers, including the processing chamber 100 described above. Method 400 may include several optional steps, which may or may not be specifically associated with some embodiments of the method according to the present technique. For example, many of the steps are described to provide a broader range of structure formations, but are not critical to the technique or may be performed by alternative methods as may be readily understood.

[0041]

[0046] Method 400 may include additional steps prior to the initiation of the recited steps. For example, the additional processing steps may include forming or providing chamber components. Pre-processing steps may be performed within the chamber in which method 400 is performed, or processing may be performed in one or more other processing chambers prior to providing or installing one or more chamber components within the semiconductor processing chamber in which method 400 is performed. Nevertheless, method 400 may optionally include providing one or more chamber components to a processing region of semiconductor processing system 100, such as processing chambers 108a-108f described above, or other chambers that may include the components described above. Chamber components may be deposited within one or more processing chambers 108a-108f, such as the processing region 120 of the chamber described above. Method 400 describes steps shown generally in FIGS. 5A-5C, examples of which are described in conjunction with the steps of method 400. It should be understood that Figures 5A-5C are only partially schematic, and that one or more chamber components may include additional components as illustrated in the figures, as well as alternative components of any size or configuration that can still benefit from aspects of the present technology.

[0042]

[0047] 5A-5C illustrate a chamber component 500 that may be coated in accordance with embodiments of the present technology. As discussed above, the chamber component 500 may be any one or more chamber components having a surface exposed to the interior of a semiconductor processing chamber, such as the process system 100 or processing chamber system 200 described above. Thus, in embodiments, the chamber component 500 may be one or more of the cooling plate 203, faceplate 217, ion suppressor 223, showerhead 225, pedestal 265 (alone or including a substrate support), and / or baffles, feeds, inlets, exhausts, and their supports, etc. That is, in embodiments, the chamber component 500 may be any one or more components used in a plasma processing chamber. In an embodiment, chamber component 500 may be assembled within processing chamber 108a-108f or a processing chamber of processing system 200 (e.g., for an in situ process, as described in further detail below), or may be placed within processing chamber 108a-108f, such as on a support within the processing chamber (e.g., for an ex situ process), in step 405.

[0043]

[0048] 5A, a chamber component 500 can include a surface 501. The exposed surface 501 can include multiple features, such as grooves, apertures, features, etc., depending on the particular chamber component 500. In some embodiments, the chamber component 500 can include multiple apertures 520 (FIG. 5B), as described above, such as when the chamber component 500 is a faceplate and / or showerhead.

[0044]

[0049] 5A-5C show schematic cross-sectional views of an exemplary corrosion- and erosion-resistant coating deposited on a chamber component 500 in accordance with some embodiments of the present technology. The figures show exemplary diagrams of various coating configurations intended to illustrate possible coating applications encompassed by embodiments of the present technology, which may include applying coatings to multiple components within the chamber system 200 or other components that may benefit from a corrosion-resistant coating. It should be understood that additional and alternative coating applications may be used during step 410, as discussed in more detail below. The application of the coating, such as the number of layers and the types of layers formed, may depend on the type of component to which the coating is applied and the component's configuration. For example, if the component includes one or more apertures, the coating may include two or more layers or two or more applications (without forming a boundary between layers) of a ceramic material, such as yttrium oxide, to completely cover the exposed surfaces of the chamber component, including the exposed surfaces of each of the one or more apertures. The exemplary chamber component 500 provided in FIGS. 5A-5C may be illustrative of any of the chamber components previously described.

[0045]

[0050] In some embodiments, the chamber component 500 may be fabricated from aluminum, chromium, magnesium, nickel, alloys thereof, combinations thereof, or the like. Even when the chamber component 500 comprises a high-purity metal alloy, the alloy often contains impurities of various alloying metals. For example, aluminum alloys generally contain trace amounts of nickel, copper, iron, manganese, and chromium. In some embodiments, the following elements may be present as impurities in the aluminum alloy in the following weight percent ranges: nickel in the range of about 0.001% to about 0.5%, iron in the range of about 0.001% to about 0.25%, copper in the range of about 0.15% to about 0.35%, manganese in the range of about 0.001% to about 0.2%, zinc in the range of about 0.001% to about 0.15%, chromium in the range of about 0.04% to about 0.28%, titanium in the range of about 0.001% to about 0.06%, and magnesium in the range of about 0.8% to about 1.2%. Optionally, the total amount of other impurities present in the aluminum alloy may be about 0.15% by weight or less.

[0046]

[0051] The illustrations of Figures 5A-5C also include a coating according to the present technology applied to an exposed surface 501 of a chamber component 500. While the illustrations show a coating applied to only one surface of the chamber component, it should be understood that the coating may be included on all exposed surfaces of the chamber component (either the surface facing the chamber or the surface exposed to the chamber as described above) and is shown covering only the depicted surface for illustrative purposes. The corrosion- and erosion-resistant coating can be configured to resist corrosion and erosion and protect the component 500 from reactive etchants, including halogen-containing wastewater, gases, etchants, or deposition processes. For example, the corrosion- and erosion-resistant coating can be configured to protect the component 500 from etchants or gases, even in high-power processes such as CCP processes.

[0047]

[0052] Thus, in embodiments, the yttrium oxide-containing coating 510 may be deposited on the exposed surface 501 of the component 500 in step 410. The yttrium oxide-containing coating 510 may extend over the exposed surface 501 of the component 500. Because the yttrium oxide-containing coating 510 is not the final coating of the present technology, no predetermined thickness or expensive coating technique is required. That is, additional steps, described in more detail below, are utilized to convert the coating to a halogen-containing coating, improving the coating thickness and / or density during conversion. Thus, in embodiments, the yttrium oxide-containing coating 510 may be formed by thermal spraying, ALD, CVD, PVD, PECVD, combinations thereof, etc., as known in the art.

[0048]

[0053] The yttrium oxide-containing coating 510 may extend around the periphery of the chamber component 500 to achieve a coating thickness of about 5 nm or more (e.g., about 10 nm or more, e.g., about 50 nm or more, e.g., about 100 nm or more, e.g., about 250 nm or more, e.g., about 500 nm or more, e.g., about 750 nm or more, e.g., about 1 μm or more, e.g., about 2 μm or more, e.g., about 3 μm or more, e.g., about 4 μm or more, e.g., about 5 μm or more, e.g., about 6 μm or more, e.g., about 7 μm or more, e.g., about 8 μm or more, e.g., about 9 μm or more, e.g., up to 10 μm, or any range or value therebetween). That is, as discussed above and known in the art, existing deposition methods for yttrium oxide are limited to less than 500 nm for ALD coating methods and less than 10 μm for electron beam methods, which are insufficient to protect against erosion and corrosion in highly corrosive environments and / or high-energy plasma systems over long periods of time.

[0049]

[0054] However, as described above, the thickness of the yttrium oxide-containing coating 510 may not be critical, as thickness and / or density may be improved in accordance with the present technique. Nevertheless, in embodiments, when a chamber component 500 has small-sized features or apertures 520, two or more coating methods may be utilized to provide the yttrium oxide-containing coating 510 on substantially all exposed surfaces of the chamber component and multiple other components. That is, the present technique converts the underlying yttrium oxide-containing coating 510 into a more robust halogen-containing coating, as described below. Therefore, the yttrium oxide-containing coating 510 should be formed on all exposed surfaces on which it is desired to form the halogenated coating of the present technique. Thus, in embodiments, electron beam, thermal spray, etc. may be utilized to form a high-thickness, high-quality yttrium oxide-containing coating 510 on planar surfaces (and / or line-of-sight exposed surfaces) of the component, and ALD processes, etc. may be utilized to deposit on small features or apertures 520 (and / or non-line-of-sight exposed surfaces).

[0050]

[0055] Regardless of the method or methods used, in embodiments, one or more exposed surfaces of one or more chamber components 500 may define an exposed surface area (e.g., the surface area of ​​all exposed surfaces that are coated) where at least about 50% (e.g., about 60% or more, e.g., about 70% or more, e.g., about 80% or more, e.g., about 85% or more, e.g., about 90% or more, e.g., about 95% or more, e.g., about 97.5% or more, e.g., about 99% or more, or any range or value therebetween) of the exposed surface area has the yttrium oxide-containing coating 510 deposited thereon.

[0051]

[0056] Furthermore, as noted above, it will be apparent that when one or more chamber components include one or more apertures, the exposed aperture surface area is included in the exposed surface area of ​​the one or more chamber components. In any event, in embodiments, at least about 50% (e.g., about 60% or more, e.g., about 70% or more, e.g., about 80% or more, e.g., about 85% or more, e.g., about 90% or more, e.g., about 95% or more, e.g., about 97.5% or more, about 99% or more, etc., or any range or value therebetween, as shown in FIG. 5B ) of the exposed aperture surface area, which may include the surface area of ​​the apertures of a faceplate, showerhead, combinations thereof, etc., may have a yttrium oxide-containing coating 510 deposited thereon.

[0052]

[0057] In embodiments, yttrium oxide may form all or a portion (e.g., substantially all) of the yttrium oxide-containing coating 510. In such embodiments, yttrium oxide may comprise at least about 70% by weight of the yttrium oxide-containing coating 510 (e.g., about 75% by weight or more, e.g., about 80% by weight or more, e.g., about 85% by weight or more, e.g., about 90% by weight or more, e.g., about 92.5% by weight or more, e.g., about 95% by weight or more, e.g., about 97.5% by weight or more, e.g., about 99% by weight or more, or any range or value therebetween), based on the weight of the yttrium oxide-containing coating 510. However, in embodiments, the yttrium oxide-containing coating 510 may include additional components, such as trace amounts of fluorine (which may be present as fluorinated yttrium oxide (YOFx)), carbon, or chamber contaminants (such as aluminum, zirconium, or other similar materials), or other oxides. The content of these non-yttrium oxide components can be less than 50% by weight of the yttrium oxide-containing coating 510 (e.g., about 40% by weight or less, about 30% by weight or less, about 20% by weight or less, about 10% by weight or less, about 5% by weight or less, about 2.5% by weight or less, about 1% by weight or less, etc.).

[0053]

[0058] After the yttrium oxide-containing coating 510 is formed, a plasma may be formed to generate plasma effluents in step 420. In some embodiments, the plasma may be formed in a remote plasma region within the chamber or in fluid communication with the chamber, and plasma effluents generated from the remote plasma may be flowed into the processing region according to the discussion above with reference to FIGS. 1-3 above. In some embodiments, the plasma may be formed locally within the processing region, and plasma effluents may be generated from the plasma within the processing region. Once the plasma effluents are generated, the surface of the yttrium oxide-containing coating 510 may be contacted with the plasma effluents in step 430.

[0054]

[0059] The plasma generated in step 420 may, in some embodiments, be a hydrogen-containing plasma, a helium-containing plasma, an ammonia-containing plasma, an argon-containing plasma, combinations thereof, etc. Thus, in embodiments, the secondary ions or radicals in the plasma are hydrogen-, ammonia-, helium-, or argon-containing plasma. Other types of secondary ions or radicals may also be used in method 400.

[0055]

[0060] Regardless of the secondary ions and radicals present in the plasma, the present technique includes one or more halogen ions or radicals in the plasma. Thus, in an embodiment, the present method includes introducing a halogen-containing precursor in step 420. In an embodiment, the halogen-containing precursor is any precursor that generates fluorine radicals. In an embodiment, the halogen-containing precursor is a fluorine-containing precursor. Further, in an embodiment, the fluorine-containing precursor is nitrogen trifluoride (NF3).

[0056]

[0061] Specifically, the present technique surprisingly discovered that, when subjected to carefully controlled pressure and power, a fluorine-containing plasma interacts with the oxygen-rich yttrium oxide-containing coating in step 430, as shown in FIG. 5B. While not intending to be bound by theory, it is believed that the oxygen-rich yttrium oxide-containing coating 510 functions as a radical scavenger, interacting with fluorine radicals present in the plasma. Through continued exposure to the plasma under high pressure and power, the yttrium oxide-containing coating 510 is converted to an yttrium fluoride coating (YF3) in step 440, as shown in FIG. 5C. This conversion has several advantages. For example, the conversion from yttrium oxide to yttrium fluoride increases the thickness and / or density of the coating, as needed, resulting in a more robust coating that can withstand harsher chamber environments or result in components with a longer lifespan. Additionally, the conversion to yttrium fluoride imparts fluorine to the coating itself. This makes the yttrium oxide coating less susceptible or less susceptible to interaction with the plasma process gases, thereby minimizing or eliminating the first wafer effect.

[0057]

[0062] The present technique offers significant improvements over conventional chemical yttrium fluoride processes and deposition methods because the coatings of the present technique can be formed in situ within a semiconductor processing chamber, allowing any exposed surface to be coated while still in place within the chamber. Furthermore, for in situ or ex situ processes, the present technique not only allows for the formation of thicker and / or denser coatings than conventional methods, but also provides robust coatings even in small features or apertures.

[0058]

[0063] Thus, in embodiments, steps 420, 430, and / or 440 may be considered high-power plasma processes. Thus, they may be performed under power conditions of about 2 watts or greater (e.g., about 5 watts or greater, e.g., about 10 watts or greater, e.g., about 25 watts or greater, e.g., about 50 watts or greater, e.g., about 75 watts or greater, e.g., about watts or greater, e.g., about 250 watts or greater, e.g., about 500 watts or greater, e.g., about 750 watts or greater, e.g., about 1000 watts or greater, e.g., about 1500 watts or greater, e.g., about 2000 watts or greater, e.g., about 2500 watts or greater, e.g., up to about 3000 watts, or any range or value therebetween). Power may be supplied as known in the art or as described above. Additionally, the high power plasma process is carried out at a pressure of about 500 mTorr or greater (e.g., about 750 mTorr or greater, such as about 1 Torr or greater, for example about 1.5 Torr or greater, for example about 2 Torr or greater, for example about 2.5 Torr or greater, for example about 3 Torr or greater, for example about 3.5 Torr or greater, for example about 4 Torr or greater, for example about 4.5 Torr or greater, for example about 5 Torr or greater, for example about 6 Torr or greater, for example about 7 Torr or greater, for example about 8 Torr or greater, for example about 9 Torr or greater, for example about 10 Torr or greater, for example about 11 Torr or greater, for example about 12 Torr or greater, for example about 13 Torr or greater, for example about 14 Torr or greater, for example up to about 15 Torr, or any range or value therebetween). Pressures can be provided as known in the art or as described above.

[0059]

[0064] Nevertheless, in embodiments, high power plasma processes may also include voltages of about 10V or more (e.g., about 25V or more, such as about 50V or more, for example about 75V or more, for example about 100V or more, such as about 125V or more, for example about 150V or more, such as about 200V or more, for example about 250V or more, such as about 300V or more, for example about 350V or more, such as about 400V or more, for example about 450V or more, such as about 500V or more, for example about 600V or more, such as about 700V or more, for example about 800V or more, such as about 900V or more, for example up to about 1000V, or any range or value therebetween).

[0060]

[0065] Further, in embodiments, the high power plasma process may be carried out at high temperatures (e.g., about 30°C or higher, about 50°C or higher, about 75°C or higher, about 100°C or higher, about 125°C or higher, about 150°C or higher, about 175°C or higher, about 200°C or higher, about 250°C or higher, about 300°C or higher, about 350°C or higher, about 400°C or higher, about 450°C or higher, about 500°C or higher, about 550°C or higher, about 600°C or higher, about 650°C or higher, about 700°C or higher, about 750°C or higher, about 800°C or higher, about 850°C or higher, about 900°C or higher, about 950°C or higher, about 1000°C or higher, or any range or value therebetween).

[0061]

[0066] In an embodiment, the high power plasma process may be performed to increase the thickness of the nanoparticles to about 10 nm or more (e.g., about 25 nm or more, for example, about 50 nm or more, such as about 75 nm or more, for example, about 100 nm or more, such as about 250 nm or more, for example, 500 nm or more, for example, 750 nm or more, such as about 1 μm or more, for example, about 5 μm or more, such as about 10 μm or more, for example, about 15 μm or more, such as about 20 μm or more, for example, about 25 μm or more, such as about 50 μm or more, for example, about 100 μm or more, such as about 150 μm or more, for example, about 200 μm or more, for example, about 250 μm or more, for example, about 300 μm or more). The process may be carried out for a sufficient time to provide a yttrium fluoride-containing coating thickness of about 1000 nm or less, such as about 350 μm or more, for example about 400 μm or more, for example about 450 μm or more, for example about 500 μm or more, or for example about 1000 nm or less, for example about 900 nm or less, for example about 800 nm or less, for example about 700 nm or less, for example about 600 nm or less, for example about 500 nm or less, for example about 400 nm or less, for example about 300 nm or less, for example about 200 nm or less, for example about 100 nm or less, or any range or value therebetween. As noted above, in embodiments, the thickness of the yttrium fluoride-containing coating may be increased compared to the thickness of the yttrium oxide coating, either overall, or in one or more locations, or on one or more components. Nevertheless, in embodiments, if desired, the thickness of the yttrium fluoride-containing coating may be approximately equal to the thickness of the yttrium oxide coating, either overall, or in one or more locations, or on one or more components.

[0062]

[0067] For example, in embodiments, the coating may be relatively thin in thickness, yet have an improved density. Thus, in embodiments, the coating has a density of about 2 g / cm 3 or more (for example, about 2.25 g / cm 3 or more, for example, about 2.5 g / cm 3 or more, for example, about 2.75 g / cm 3 More than, for example, about 3 g / cm 3 or more, for example, about 3.5 g / cm 3 For example, about 4 g / cm 3 or more, for example, about 4.5 g / cm3 More than, for example, about 5 g / cm 3 For example, about 5.5 g / cm 3 For example, about 6 g / cm 3 For example, about 6.5 g / cm 3 or greater, or any range or value therebetween).

[0063]

[0068] Additionally or alternatively, in embodiments, the high-power plasma process may be carried out for about 30 minutes or more (e.g., about 45 minutes or more, e.g., about 1 hour or more, e.g., about 1.5 hours or more, e.g., about 2 hours or more, e.g., about 2.5 hours or more, e.g., about 3 hours or more, e.g., about 3.5 hours or more, e.g., about 4 hours or more, e.g., about 4.5 hours or more, e.g., about 5 hours or more, or any range or value therebetween). However, as discussed above and below, in embodiments, the time for which the high-power plasma process is carried out is determined based on one or more factors (e.g., the thickness of the coating or the percentage of the coating converted to yttrium fluoride), which may depend on the desired processing chamber, chamber components, etc.

[0064]

[0069] For example, in an embodiment, a possible reaction scheme for a process according to the present technology is assumed as follows: 4Y2O3+8F→8YOF+2O2 2YOF+4F→2YF3+O2 Thus, in embodiments, depending on the processing conditions and / or the time the conversion step 440 is allowed to proceed, a portion of the chamber component 500 may include a layer 512 including a fluorinated yttrium oxide, such as YOFx, as illustrated by FIG. 5C . While layer 512 is shown below the yttrium fluoride-containing coating 514, it should be understood that, in embodiments, layer 512 may be included in spots or locations scattered throughout the thickness of the yttrium fluoride-containing coating 514, or may be present only within features such as apertures 520. Furthermore, in embodiments, layer 512 may also include unreacted yttrium oxide, either alone or in combination with the fluorinated yttrium oxide. Thus, in embodiments, one or more apertures 520 may be only partially converted or may include uncoated or yttrium oxide-coated portions.

[0065]

[0070] Nevertheless, it should be understood that in embodiments, the high-power plasma process is carried out for a time sufficient to convert about 50% by weight or more (e.g., about 60% by weight or more, such as about 70% by weight or more, for example about 75% by weight or more, for example about 80% by weight or more, for example about 85% by weight or more, for example about 90% by weight or more, for example about 95% by weight or more, for example about 97.5% by weight or more, for example about 99% by weight or more, or any range or value therebetween) of the yttrium oxide in the coating 510 to yttrium fluoride.

[0066]

[0071] Further, in embodiments, yttrium fluoride may form all or a portion (e.g., substantially all) of the yttrium fluoride-containing coating 514. In such embodiments, yttrium fluoride may comprise at least about 50% by weight of the yttrium fluoride-containing coating 514 (e.g., about 60% by weight or more, e.g., about 70% by weight or more, e.g., about 75% by weight or more, e.g., about 80% by weight or more, e.g., about 85% by weight or more, e.g., about 90% by weight or more, e.g., about 92.5% by weight or more, e.g., about 95% by weight or more, e.g., about 97.5% by weight or more, e.g., about 99% by weight or more, or any range or value therebetween), based on the weight of the coating 514. However, in embodiments, the yttrium fluoride-containing coating 514 may include additional components, such as trace amounts of YOFx, yttrium oxide, carbon, or other impurities (e.g., aluminum, zirconium, or other similar materials). The content of these non-yttrium fluoride components can be less than 50% by weight (e.g., about 40% by weight or less, for example, about 30% by weight or less, for example, about 20% by weight or less, for example, about 10% by weight or less, for example, about 5% by weight or less, for example, about 2.5% by weight or less, for example, about 1% by weight or less, or any range or value therebetween).

[0067]

[0072] As described above, one or more exposed surfaces of one or more chamber components 500 can define an exposed surface area (e.g., the surface area of ​​all exposed surfaces to be coated), where, as shown in FIG. 5C , at least about 50% of the exposed surface area (e.g., about 60% or more, e.g., about 70% or more, e.g., about 80% or more, e.g., about 85% or more, e.g., about 90% or more, e.g., about 95% or more, e.g., about 97.5% or more, e.g., about 99% or more, or any range or value therebetween) has the yttrium fluoride-containing coating 514 deposited thereon. That is, it should be understood that the terms “formed thereon” or “deposited thereon” as used herein can include the yttrium fluoride coating being formed directly on the chamber component 500, or can include one or more intermediate layers, such as residual yttrium oxide or fluorinated yttrium oxide, between the yttrium fluoride coating and the chamber component.

[0068]

[0073] Furthermore, as noted above, it will be apparent that if the chamber component and a plurality of other components include one or more apertures, the exposed aperture surface area is included in the exposed surface area of ​​the one or more chamber components. In any event, in embodiments, at least about 50% (e.g., about 60% or more, e.g., about 70% or more, e.g., about 80% or more, e.g., about 85% or more, e.g., about 90% or more, e.g., about 95% or more, e.g., about 97.5% or more, about 99% or more, etc., or any range or value therebetween, as shown in FIG. 5C ) of the exposed aperture surface area, which may include the surface area of ​​the apertures of the faceplate, showerhead, combinations thereof, etc., may have the yttrium fluoride-containing coating 514 deposited thereon.

[0069]

[0074] Regardless of the process conditions selected, and as described above, it will be apparent that in embodiments, the present technique may be an “in situ process.” Such a process involves a processing chamber that can be assembled with the necessary or desired chamber components for processing substrates. These chamber components are then coated according to the present technique within the chamber that will ultimately be used for substrate processing. Such a process provides the benefits described above, as well as the additional benefit of ensuring that exposed surfaces are coated without unnecessarily coating covered or protected surfaces. However, it will be apparent that the technique may also be used as an “ex situ process” and still provide the benefits described above. In such a process, one or more components are loaded into a processing chamber, coated according to the present technique, and removed from the chamber before the chamber components are ultimately assembled into the final processing chamber that will be used for substrate processing. In embodiments, the chamber for coating chamber components according to the present technique may be any processing chamber in processing system 100 or chamber system 200 described above. Nevertheless, in embodiments, the processing chamber may be a CCP processing chamber, a bias plasma chamber, or a combination thereof.

[0070]

[0075] The corrosion- and erosion-resistant coatings formed according to the present technology can protect chamber components from chemical and plasma attack during processes such as etching, deposition, and cleaning. The corrosion- and erosion-resistant coatings provided herein can reduce or eliminate the first-wafer effect as well as contamination of the substrate by chamber component materials. As a result, the present technology can improve device productivity and further extend the life of components within the processing chamber.

[0071]

[0076] Although the above description, for purposes of explanation, sets forth numerous details in order to provide a thorough understanding of various implementations of the present technology, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details or with additional implementation details.

[0072]

[0077] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents may be used without departing from the spirit of the embodiments. Additionally, in order to avoid unnecessarily obscuring the technology, some well-known processes and elements have not been described. Therefore, the above description should not be construed as limiting the scope of the technology.

[0073]

[0078] Where a range of values ​​is given, unless the context clearly dictates otherwise, each intervening value between the upper and lower limit of that range is specifically disclosed, to the smallest unit of the lower limit. Any narrower range between any stated or unstated intervening value in a stated range, and any other stated or intervening value in that stated range, is also encompassed. The upper and lower limits of such narrower ranges may individually be included or excluded from that range. Each range where either, neither, or both limits are included in this narrower range is also encompassed within the technology, provided that any specifically excluded limit is within the stated range. Where a stated range includes one or both limits, ranges excluding either or both of those included limits are also included.

[0074]

[0079] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, a reference to "a layer" includes a plurality of such layers, a reference to "the precursor" includes a reference to one or more precursors and equivalents thereof known to those skilled in the art, and so forth.

[0075]

[0080] Additionally, the terms "comprise(s)," "comprising," "contain(s)," "containing," "include(s)," and "including," when used in this specification and claims, are intended to specify the presence of stated features, integers, components, or operations, but do not exclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

Claims

1. 1. A semiconductor processing system comprising: Chamber containing multiple chamber components The chamber component comprises: a pedestal configured to support a semiconductor substrate; Lid stack and a face plate supported by the lid stack, the face plate defining a plurality of first apertures; a showerhead positioned between the faceplate and the pedestal, the showerhead defining a plurality of second apertures; Including, 10. The semiconductor processing system of claim 1, wherein the faceplate, the showerhead, the lid stack, the pedestal, or a combination thereof, comprises a coating containing yttrium fluoride, yttrium oxyfluoride, or both yttrium fluoride and yttrium oxyfluoride, the coating having a thickness greater than 10 μm or less than about 100 nm on at least a portion of each of the chamber components or a combination thereof.

2. 10. The semiconductor processing system of claim 1, wherein the faceplate, the showerhead, or both the faceplate and the showerhead define an exposed surface having an exposed surface area, and wherein about 80% or more of the exposed surface area comprises a coating containing the yttrium fluoride, yttrium oxyfluoride, or both yttrium fluoride and yttrium oxyfluoride.

3. 3. The semiconductor processing system of claim 2, wherein about 90% or more of the exposed surface area of ​​the faceplate, the showerhead, or both the faceplate and the showerhead comprises a coating containing the yttrium fluoride, yttrium oxyfluoride, or both yttrium fluoride and yttrium oxyfluoride.

4. 10. The semiconductor processing system of claim 1, wherein the coating containing yttrium fluoride, yttrium oxyfluoride, or both yttrium fluoride and yttrium oxyfluoride has a thickness of about 50 μm or greater on at least a portion of each chamber component or combination thereof.

5. 2. The semiconductor processing system of claim 1, wherein the plurality of first apertures, the plurality of second apertures, or a combination thereof, define an open surface having an open surface area, and about 70% or more of the open surface area comprises a coating containing the yttrium fluoride, yttrium oxyfluoride, or both yttrium fluoride and yttrium oxyfluoride.

6. 6. The semiconductor processing system of claim 5, wherein the yttrium fluoride, yttrium oxyfluoride, or both yttrium fluoride and yttrium oxyfluoride containing coating on the open pore surface further comprises yttrium oxide, YOFx, or a combination thereof.

7. 1. A method for coating a component of a semiconductor processing chamber, the method comprising: Positioning a component having an exposed surface within a chamber; depositing a coating comprising yttrium oxide on at least a portion of said exposed surface; exposing the coating to a high power plasma process at a power of about 2 Watts or greater and a pressure of 500 millitorr, the high power plasma process comprising: flowing a fluorine-containing precursor into the chamber; forming a plasma from the fluorine-containing precursor to produce plasma effluents; and contacting the surface of the coating with the plasma effluents; exposing the coating, converting at least a portion of the yttrium oxide to yttrium fluoride, yttrium oxyfluoride, or both yttrium fluoride and yttrium oxyfluoride; A method comprising:

8. The method of claim 7 , wherein the plasma further comprises hydrogen, ammonia, helium, argon, or a combination thereof.

9. The method of claim 8 , wherein the fluorine-containing precursor comprises nitrogen trifluoride.

10. 8. The method of claim 7, wherein the yttrium oxide is deposited by atomic layer deposition, plasma spray, electron beam, chemical vapor deposition, physical vapor deposition, plasma enhanced chemical vapor deposition, or a combination thereof.

11. 11. The method of claim 10, wherein the yttrium oxide is deposited by a combination of atomic layer deposition and plasma spray or electron beam.

12. The method of claim 7 , wherein the component defines a plurality of apertures, each aperture having an exposed aperture surface, and the coating is deposited on at least a portion of the exposed aperture surface.

13. 8. The method of claim 7, wherein the high power plasma process comprises a power of about 10 watts to about 3000 watts, a pressure of about 1 Torr to about 15 Torr, and a voltage of about 10 volts to about 1000 volts.

14. 8. The method of claim 7, wherein the high power plasma process is carried out for a time sufficient to convert at least about 50% by weight of the yttrium oxide to yttrium fluoride.

15. 15. The method of claim 14, wherein the high power plasma process is carried out for at least about 1 hour.

16. 8. The method of claim 7, wherein the high power plasma process is carried out for a period of time sufficient to achieve a coating thickness of about 1 μm or greater.

17. 1. A method for coating one or more components of a semiconductor processing chamber, the method comprising: positioning a plurality of chamber components having exposed surfaces within the semiconductor processing chamber, the plurality of chamber components comprising: a face plate defining a plurality of first apertures; and A showerhead defining a plurality of second apertures positioning a plurality of chamber components, including: depositing a coating comprising yttrium oxide on at least a portion of the exposed surfaces of the plurality of chamber components; converting at least a portion of the yttrium oxide to yttrium fluoride, yttrium oxyfluoride, or both yttrium fluoride and yttrium oxyfluoride in the semiconductor processing chamber; A method comprising:

18. 20. The method of claim 17, wherein the plurality of chamber parts further comprises a lid stack supporting the faceplate and a pedestal configured to support a semiconductor substrate.

19. 18. The method of claim 17, wherein the method is carried out under pressure.

20. 20. The method of claim 17, wherein the semiconductor processing chamber further comprises a first electrode and a second electrode, the first electrode and the second electrode configured to provide at least about 2 watts of power during the conversion.

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