Array substrate and display device

Abstract

The array substrate includes a display area and a notch area. The display area includes a first display sub-area and a second display sub-area separated from each other by the notch area. The notch area includes an electrostatic discharge area. The array substrate includes a plurality of data lines and a plurality of scan signal lines. The plurality of data lines extend at least partially into the electrostatic discharge area. The plurality of scan signal lines straddle the electrostatic discharge area. At least a portion of the electrostatic discharge area includes a plurality of alternating first sub-areas and a plurality of second sub-areas. The plurality of scan signal lines are present in the plurality of first sub-areas and are absent in the plurality of second sub-areas. The plurality of data lines are present in the plurality of second sub-areas and are absent in the plurality of first sub-areas.

Description

[Technical Field]

[0001] The present invention relates to display technology, and more particularly to an array substrate and a display device. [Background technology]

[0002] Organic light-emitting diode (OLED) displays have attracted particular attention in today's research field of flat panel displays. Unlike thin-film transistor liquid crystal displays (TFT-LCDs), which control brightness with a stable voltage, OLEDs are driven by a drive current that must be kept constant to control brightness. An OLED display panel includes a plurality of pixel units arranged in a plurality of rows and columns and pixel drive circuits. Each pixel drive circuit includes a drive transistor having a gate terminal connected to one gate line per row and a drain terminal connected to one data line per column. When a row gated by a pixel unit is turned on, a switching transistor connected to the drive transistor is turned on, and a data voltage is applied from the data line to the drive transistor through the switching transistor, causing a current corresponding to the data voltage to be output by the drive transistor to the OLED device. The OLED device is driven to emit light at a corresponding brightness. Summary of the Invention [Means for solving the problem]

[0003] In one aspect, an embodiment of the present disclosure provides an array substrate including a display area and a notch area, wherein the display area includes a first display sub-area and a second display sub-area separated from each other by the notch area, and the notch area includes an electrostatic discharge area, the array substrate including a plurality of data lines and a plurality of scan signal lines, the plurality of data lines at least partially extending into the electrostatic discharge area and the plurality of scan signal lines straddling the electrostatic discharge area, at least a portion of the electrostatic discharge area including a plurality of alternating first sub-areas and a plurality of second sub-areas, the plurality of scan signal lines being present in the plurality of first sub-areas but not in the plurality of second sub-areas, and the plurality of data lines being present in the plurality of second sub-areas but not in the plurality of first sub-areas.

[0004] In some embodiments of the present disclosure, a scanning signal line extending from the first display sub-region and spanning a portion of the electrostatic discharge region adjacent to the first display sub-region and a scanning signal line extending from the second display sub-region and spanning a portion of the electrostatic discharge region adjacent to the second display sub-region are connected to each other.

[0005] In some embodiments of the present disclosure, each of the first sub-regions among the plurality of first sub-regions includes some of the plurality of scanning signal lines, and each of the second sub-regions among the plurality of second sub-regions includes at least one data line.

[0006] In some embodiments of the present disclosure, the electrostatic discharge area includes a plurality of electrostatic discharge units for protecting a plurality of data lines.

[0007] In some embodiments of the present disclosure, the electrostatic discharge region further includes a plurality of dummy electrostatic discharge units, the plurality of electrostatic discharge units being present in the plurality of second sub-regions and not present in the plurality of first sub-regions, and the plurality of dummy electrostatic discharge units being present in the plurality of first sub-regions and not present in the plurality of second sub-regions.

[0008] In some embodiments of the present disclosure, orthogonal projections onto the base substrate of individual scanning signal lines among the plurality of scanning signal lines that are located in individual first sub-regions among the plurality of first sub-regions partially overlap with orthogonal projections onto the base substrate of some dummy electrostatic discharge units among the plurality of dummy electrostatic discharge units.

[0009] In some embodiments of the present disclosure, the notch area further includes a transition area between the electrostatic discharge area and the first display sub-area or between the electrostatic discharge area and the second display sub-area, where no electrostatic discharge unit is present in the transition area, where the plurality of data lines and the plurality of scanning signal lines intersect with each other in the transition area, where portions of the plurality of scanning signal lines that intersect with the plurality of data lines respectively extend along a first direction, and portions of the plurality of data lines that intersect with the plurality of scanning signal lines respectively extend along a second direction, where the first direction and the second direction are substantially perpendicular to each other.

[0010] In some embodiments of the present disclosure, multiple scan signal lines from sub-pixels in the same row cross the same number of data lines.

[0011] In some embodiments of the present disclosure, the portions of the plurality of data lines that intersect with the plurality of scanning signal lines are located in a first signal line layer, and the portions of the plurality of scanning signal lines that intersect with the plurality of data lines are located in a second signal line layer that is located on the side of the first signal line layer that is away from the base substrate.

[0012] In some embodiments of the present disclosure, each of the plurality of scanning signal lines that crosses the transition region and the electrostatic discharge region includes a first portion, a second portion, and a third portion, wherein the first portion intersects with one or more data lines located in the transition region, the second portion crosses the electrostatic discharge region, the third portion is at least partially located in a part of the notch region that is located on a side of the electrostatic discharge region away from the transition region, and the second portion connects the first portion and the third portion.

[0013] In some embodiments of the present disclosure, the first portion is in a different layer than the second portion.

[0014] In some embodiments of the present disclosure, the first portion is in a first conductive layer, and the second portion is in a first signal line layer located on a side of the first conductive layer away from the base substrate.

[0015] In some embodiments of the present disclosure, each of the plurality of scanning signal lines that spans the transition region and the electrostatic discharge region further includes a fourth portion located at least partially in the display region, the first portion connects the fourth portion to the second portion, the first portion is in a first conductive layer, and the fourth portion is in a first signal line layer located on a side of the first conductive layer away from the base substrate.

[0016] In some embodiments of the present disclosure, the second portion and the fourth portion are located in the same layer as the plurality of data lines.

[0017] In some embodiments of the present disclosure, the second portion and the third portion of each of the plurality of scanning signal lines that cross the transition region and the electrostatic discharge region are in different layers.

[0018] In some embodiments of the present disclosure, second portions of some of the scanning signal lines located in the same first sub-region among the plurality of first sub-regions are connected to third portions of the some of the scanning signal lines, the second portions of the some of the scanning signal lines are located on a first conductive layer, and the third portions of the some of the scanning signal lines are alternately located on the first conductive layer and a second conductive layer located on a side of the first conductive layer away from the base substrate.

[0019] In some embodiments of the present disclosure, second portions of some of the scanning signal lines located in the same first sub-region among the plurality of first sub-regions are connected to first portions of the some of the scanning signal lines, and the first portions of the some of the scanning signal lines are alternately located on the first conductive layer and a second signal line layer located on a side of the first conductive layer away from the base substrate.

[0020] In some embodiments of the present disclosure, the individual second portions of the second signal line layer are connected to the individual first portions of the second signal line layer, and the individual second portions of the first signal line layer are connected to the individual first portions of the first conductive layer.

[0021] In some embodiments of the present disclosure, second portions of some of the scanning signal lines located in the same first sub-region among the plurality of first sub-regions are connected to third portions of some of the scanning signal lines, the third portions of some of the scanning signal lines are alternately located on the first conductive layer and a second conductive layer located on a side of the first conductive layer away from the base substrate, individual second portions in the second signal line layer are connected to individual third portions in the first conductive layer, and individual second portions in the first signal line layer are connected to individual third portions in the second conductive layer.

[0022] In one aspect, an embodiment of the present disclosure provides a display device including the array substrate and one or more integrated circuits connected to the array substrate. [Brief explanation of the drawings]

[0023] The following drawings are merely examples for illustrative purposes of various disclosed embodiments and are not intended to limit the scope of the invention. [Figure 1] FIG. 2 is a schematic diagram illustrating a configuration of a scanning circuit in some embodiments of the present disclosure. [Figure 2A] 1 illustrates the operation of a scanning circuit in some embodiments according to the present disclosure. [Figure 2B] 1 illustrates the operation of a scanning circuit in some embodiments according to the present disclosure. [Figure 3] FIG. 2 is a plan view of an array substrate in some embodiments according to the present disclosure. [Figure 4] FIG. 1 is a circuit diagram illustrating a configuration of a pixel driving circuit in some embodiments according to the present disclosure. [Figure 5] 4 is a timing chart illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure. [Figure 6A] 1 illustrates the layout of scanning circuits on an array substrate in some embodiments according to the present disclosure. [Figure 6B] 1 illustrates the layout of scanning circuits on an array substrate in some embodiments according to the present disclosure. [Figure 7] 10A and 10B are schematic diagrams illustrating corresponding scanning units of a scanning circuit in some embodiments of the present disclosure. [Figure 8] 10A and 10B are schematic diagrams illustrating corresponding scanning units of a scanning circuit in some embodiments of the present disclosure. [Figure 9] FIG. 2 is a plan view of an array substrate in some embodiments according to the present disclosure. [Figure 10] FIG. 2 is a plan view illustrating a portion of an array substrate in some embodiments according to the present disclosure. [Figure 11A]FIG. 11 is an enlarged view of the enlarged area in FIG. [Figure 11B] FIG. 11B is a schematic diagram of a first enlarged area of ​​FIG. 11A. [Figure 11C] FIG. 11B is an enlarged view of a portion of the first enlarged area in FIG. 11A. [Figure 11D] FIG. 11D is an enlarged view of a second enlarged region ZR2 in FIG. 11C. [Figure 11E] FIG. 11E is an enlarged view of the third enlarged region ZR3 in FIG. 11D. [Figure 12A] FIG. 11B is a cross-sectional view taken along line AA' in FIG. 11E. [Figure 12B] FIG. 11B is a cross-sectional view taken along line BB' in FIG. 11E. [Figure 13] FIG. 2 is a plan view illustrating a portion of an array substrate in some embodiments according to the present disclosure. [Figure 14A] FIG. 14 is a diagram showing the layout of signal lines in FIG. 13. [Figure 14B] FIG. 2 is a schematic diagram showing the layout of signal lines in a portion of an array substrate according to some embodiments of the present disclosure. [Figure 15] FIG. 2 is a schematic diagram illustrating the layout of signal lines and electrostatic discharge units in a portion of an array substrate in some embodiments according to the present disclosure. [Figure 16] FIG. 16 is a cross-sectional view taken along the line CC' in FIG. [Figure 17] FIG. 2 is a schematic diagram showing the layout of signal lines in a portion of an array substrate according to some embodiments of the present disclosure. [Figure 18] FIG. 18 is a cross-sectional view taken along the line DD' in FIG. [Figure 19] FIG. 2 is a schematic diagram showing the layout of signal lines in a portion of an array substrate according to some embodiments of the present disclosure. [Figure 20] FIG. 20 is an enlarged view of a fourth enlarged region ZR4 in FIG. [Figure 21] FIG. 21 is a cross-sectional view taken along line EE' in FIG. 20. [Figure 22] FIG. 21 is a cross-sectional view taken along the line FF' in FIG. 20. [Figure 23]FIG. 2 is a schematic diagram showing the layout of signal lines in a portion of an array substrate according to some embodiments of the present disclosure. [Figure 24] FIG. 24 is a cross-sectional view taken along line GG' in FIG. 23. [Figure 25] FIG. 24 is a cross-sectional view taken along line HH' in FIG. 23. [Figure 26] 1 illustrates the configuration of a display area on an array substrate according to some embodiments of the present disclosure. [Figure 27] FIG. 2 is a schematic diagram showing the layout of signal lines in a portion of an array substrate according to some embodiments of the present disclosure. [Figure 28] FIG. 2 is a schematic diagram showing the layout of signal lines in a portion of an array substrate according to some embodiments of the present disclosure. [Figure 29] FIG. 2 is a schematic diagram showing the layout of signal lines in a portion of an array substrate according to some embodiments of the present disclosure. [Figure 30] FIG. 2 is a schematic diagram showing the layout of signal lines in a portion of an array substrate according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0024] The present disclosure will be described in more detail below with reference to examples. It should be noted that the following description of some examples is merely exemplary and explanatory and is not intended to be exhaustive or limited to the precise forms disclosed.

[0025] The present disclosure provides, in particular, an array substrate and a display device that substantially overcome one or more problems resulting from limitations and drawbacks in the related art. In one aspect, the present disclosure provides an array substrate. In some embodiments, the array substrate includes a display area and a notch area. Optionally, the display area may include a first display sub-area and a second display sub-area spaced apart by the notch area. Optionally, the notch area may include an electrostatic discharge area. Optionally, the array substrate may include a plurality of data lines and a plurality of scan signal lines. Optionally, the plurality of data lines may extend at least partially into the electrostatic discharge area. Optionally, the plurality of scan signal lines may straddle the electrostatic discharge area. Optionally, at least a portion of the electrostatic discharge area may include a plurality of alternating first sub-areas and a plurality of second sub-areas. Optionally, the plurality of scan signal lines may be present in the plurality of first sub-areas and absent in the plurality of second sub-areas. Optionally, the plurality of data lines may be present in the plurality of second sub-regions and absent from the plurality of first sub-regions.

[0026] FIG. 1 is a schematic diagram illustrating a configuration of a scanning circuit in some embodiments of the present disclosure. Referring to FIG. 1, in some embodiments, the scanning circuit includes N stages. Each of the N stages includes a corresponding scanning unit. As shown in FIG. 1A, the scanning circuit includes a first scanning unit, a second scanning unit, a third scanning unit, a fourth scanning unit, ..., and an nth scanning unit. The N scanning units are configured to provide N control signals (e.g., gate signals, reset control signals, or light-emitting control signals) to N rows of subpixels. In FIG. 1A, the N control signals are represented as Output1, Output2, Output3, Output4, ..., OutputN. The nth scanning unit is configured to receive a start signal SS or an output signal from an output terminal of a previous scanning unit (e.g., the (n-1)th scanning unit, the (n-2)th scanning unit, or the (n-3)th scanning unit). In this specification, the term "previous scanning unit" is not limited to the immediately preceding scanning unit (e.g., the (n-1)th scanning unit), but includes any appropriate previous scanning unit (e.g., the (n-2)th scanning unit or the (n-3)th scanning unit). In Fig. 1A, the first scanning unit is configured to receive a start signal SS as an input signal, the second scanning unit is configured to receive an output signal from the first scanning unit as an input signal Input2, the third scanning unit is configured to receive an output signal from the second scanning unit as an input signal Input3, the fourth scanning unit is configured to receive an output signal from the third scanning unit as an input signal Input4, and the Nth scanning unit is configured to receive an output signal from the (N-1)th scanning unit as an input signal InputN.

[0027] 1A, the nth scanning unit is configured to receive an output signal from a subsequent scanning unit (e.g., the (n+1)th scanning unit, the (n+2)th scanning unit, or the (n+3)th scanning unit) as a reset signal. In this specification, the term "subsequent scanning unit" is not limited to the immediately subsequent scanning unit (e.g., the (n+1)th scanning unit), but includes any appropriate subsequent scanning unit (e.g., the (n+2)th scanning unit or the (n+3)th scanning unit). In FIG. 1A, the first scanning unit is configured to receive an output signal from the second scanning unit as a reset signal Reset1, the second scanning unit is configured to receive an output signal from the third scanning unit as a reset signal Reset2, the third scanning unit is configured to receive an output signal from the fourth scanning unit as a reset signal Reset3, and the fourth scanning unit is configured to receive an output signal from the fifth scanning unit as a reset signal Reset4.

[0028] FIG. 2A illustrates the operation of a scanning circuit in some embodiments according to the present disclosure. Referring to FIG. 2A, the scanning circuit is configured to drive the array substrate using a single-sided driving method. The scanning circuit includes a plurality of scanning units SU. The plurality of scanning units SU are provided on one side of the array substrate. Each scanning unit among the plurality of scanning units SU is configured to provide scanning signals to one or more rows of sub-pixels sp. The scanning signals are transmitted from one side of the array substrate to the other side of the array substrate. Therefore, scanning signal lines transmitting the scanning signals span the array substrate so that the scanning signals are provided to the entire row of sub-pixels sp.

[0029] FIG. 2B illustrates the operation of a scanning circuit in some embodiments according to the present disclosure. Referring to FIG. 2B, the scanning circuit is configured to drive the array substrate using a double-sided driving method. The scanning circuit includes a plurality of first scanning units SU1 located on a first side of the array substrate and a plurality of second scanning units SU2 located on a second side of the array substrate. Each first scanning unit among the plurality of first scanning units SU1 and a corresponding second scanning unit among the plurality of second scanning units SU2 are configured to provide scan signals to a row of subpixels. For example, each first scanning unit is configured to provide scan signals to a plurality of first subpixels sp1 in the same row, and the corresponding second scanning unit is configured to provide scan signals to a plurality of second subpixels sp2 in the same row. In the double-sided driving method, the first scanning signal line from each first scanning unit does not need to cross the array substrate, and the second scanning signal line from each second scanning unit does not need to cross the array substrate.

[0030] FIG. 3 is a plan view of an array substrate in some embodiments according to the present disclosure. Referring to FIG. 3, the array substrate includes an array of subpixels Sp. Each subpixel includes an electronic component, such as a light-emitting element. As an example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes a plurality of first gate lines GL1, a plurality of second gate lines GL2, a plurality of data lines DL, a plurality of voltage supply lines Vdd, and second voltage supply lines (e.g., low-voltage supply lines Vss). Each subpixel Sp is driven to emit light by a corresponding pixel driving circuit PDC. As an example, a high-voltage signal (e.g., a VDD signal) is input to a corresponding pixel driving circuit PDC connected to an anode of the light-emitting element via each high-voltage supply line among the plurality of voltage supply lines Vdd, and a low-voltage signal (e.g., a VSS signal) is input to a cathode of the light-emitting element via each low-voltage supply line. The voltage difference between a high voltage signal (for example, a VDD signal) and a low voltage signal (for example, a VSS signal) is a drive voltage ΔV that drives a light emitting element to emit light.

[0031] 4 is a circuit diagram showing the configuration of a pixel driving circuit in some embodiments according to the present disclosure. Referring to FIG. 4, in some embodiments, the pixel driving circuit includes a driving transistor Td, a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2, a gate electrode connected to a corresponding second reset control signal line rst2 of the plurality of second reset control signal lines, a second reset transistor Tr2 having a first electrode connected to a corresponding second reset signal line Vint2 of the plurality of second reset signal lines and a second electrode connected to the second electrode of the driving transistor Td, a gate electrode connected to a corresponding first gate line GL1 of the plurality of first gate lines, a first electrode connected to a corresponding data line DL of the plurality of data lines and a second electrode connected to the first electrode of the driving transistor Td, a gate electrode connected to a corresponding second gate line GL2 of the plurality of second gate lines, a first electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate electrode of the driving transistor Td, and a second electrode connected to the second electrode of the driving transistor Td. a third transistor T3 having a gate electrode connected to a corresponding light emission control signal line em of the plurality of light emission control lines, a first electrode connected to a corresponding voltage supply line Vdd of the plurality of voltage supply lines, and a second electrode connected to a first electrode of the drive transistor Td and a second electrode of the first transistor T1; a fourth transistor T4 having a gate electrode connected to a corresponding light emission control signal line em of the plurality of light emission control lines, a first electrode connected to the drive transistor Td and the second electrode of the second transistor T2, and a second electrode connected to an anode of the light emitting element LE; and a first reset transistor Tr1 having a gate electrode connected to a corresponding first reset control signal line rst1 of the plurality of first reset control signal lines, a first electrode connected to a corresponding first reset signal line Vint1 of the plurality of first reset signal lines, and a second electrode connected to the second electrode of the fourth transistor T4 and the anode of the light emitting element LE.The second capacitor electrode Ce2 is connected to a corresponding voltage supply line and to a first electrode of a third transistor T3.

[0032] As used herein, a first electrode or a second electrode refers to either a first terminal or a second terminal of a transistor connected to an active layer of the transistor. The direction of current flowing through the transistor may be configured to be from the first electrode to the second electrode or from the second electrode to the first electrode. Thus, depending on the direction of current flowing through the transistor, as an example, the first electrode may be configured to receive an input signal and the second electrode may be configured to output an output signal. As another example, the second electrode may be configured to receive an input signal and the first electrode may be configured to output an output signal.

[0033] The pixel driving circuit further includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the gate electrode of the driving transistor Td, the first capacitor electrode Ce1, and the first electrode of the second transistor T2. The second node N2 is connected to the second electrode of the third transistor T3, the second electrode of the first transistor T1, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the second transistor T2, the first electrode of the fourth transistor T4, and the second electrode of the second reset transistor Tr2. The fourth node N4 is connected to the second electrode of the fourth transistor T4, the second electrode of the first reset transistor Tr1, and the anode of the light-emitting element LE.

[0034] The present disclosure may be implemented in pixel drive circuits having various types of transistors, including pixel drive circuits having p-type transistors, pixel drive circuits having n-type transistors, and pixel drive circuits having one or more p-type transistors and one or more n-type transistors. Referring to Figure 4, the second transistor T2 is an n-type transistor, such as a metal oxide transistor, and the remaining transistors are p-type transistors, such as polysilicon transistors. For p-type transistors, the enable control signal (e.g., an on control signal) is a low-voltage signal, and the inactive control signal (e.g., an off control signal) is a high-voltage signal. For n-type transistors, the enable control signal (e.g., an on control signal) is a high-voltage signal, and the inactive control signal (e.g., an off control signal) is a low-voltage signal.

[0035] 5 is a timing chart showing the operation of a pixel driving circuit in some embodiments according to the present disclosure. Referring to FIGS. 4 and 5, during one frame image, the operation of the pixel driving circuit includes a reset subphase t1, a data writing subphase t2, and an emission subphase t3. During the initial subphase t0, an off reset control signal is provided to the gate electrode of the second reset transistor Tr2 via the corresponding second reset control signal line rst2, turning off the second reset transistor Tr2. During the initial subphase t0, an off signal is provided to the corresponding first gate line GL1 and the corresponding second gate line GL2, turning off the first transistor T1 and the second transistor T2.

[0036] During the reset subphase t1, an ON reset control signal is provided to the gate electrode of the second reset transistor Tr2 via the second reset control signal line rst2, turning on the second reset transistor Tr2. This causes an initialization voltage signal from the corresponding second reset signal line Vint2 to be transmitted from the first electrode of the second reset transistor Tr2 to the second electrode of the second reset transistor Tr2, and then to the first capacitor electrode Ce1 and the gate electrode of the drive transistor Td. The gate electrode of the drive transistor Td is initialized. The second capacitor electrode Ce2 receives a high-voltage signal from the corresponding voltage supply line Vdd. The voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 increases, charging the first capacitor electrode Ce1 during the reset subphase t1. During the reset subphase t1, an OFF signal is provided to the corresponding first gate line GL1 and the corresponding second gate line GL2, turning off the first transistor T1 and the second transistor T2. A high voltage signal is provided to the corresponding light emission control signal line em to turn off the third transistor T3 and the fourth transistor T4.

[0037] During the data write subphase t2, an OFF reset control signal is again provided to the gate electrode of the second reset transistor Tr2 via the corresponding second reset control signal line rst2, turning off the second reset transistor Tr2. An ON signal is provided to the corresponding first gate line GL1 and the corresponding second gate line GL2, turning on the first transistor T1 and the second transistor T2. The second electrode of the drive transistor Td is connected to the second electrode of the second transistor T2. The gate electrode of the drive transistor Td is connected to the first electrode of the second transistor T2. Since the second transistor T2 is turned on during the data write subphase t2, the gate electrode and second electrode of the drive transistor Td are connected and short-circuited, and only the PN junction between the gate electrode and first electrode of the drive transistor Td is active, thus putting the drive transistor Td into a diode-connected mode. The first transistor T1 is turned on during the data write subphase t2. The data voltage signal transmitted through the corresponding data line DL is received by the first electrode of the first transistor T1 and then transmitted to the first electrode of the drive transistor Td, which is connected to the second electrode of the first transistor T1. A node N2 connected to the first electrode of the drive transistor Td has the voltage level of the data voltage signal. Since only the PN junction between the gate electrode and the first electrode of the drive transistor Td is active, the voltage level of the node N1 gradually increases to (Vdata+Vth) during the data write subphase t2. Here, Vdata is the voltage level of the data voltage signal, and Vth is the voltage level of the threshold voltage Th of the PN junction. Since the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst is discharged. A high-voltage signal is provided to the corresponding light-emitting control signal line em, turning off the third transistor T3 and the fourth transistor T4.

[0038] In the data write subphase t2, an ON reset control signal is provided to the gate electrode of the first reset transistor Tr1 via the corresponding first reset control signal line rst1, turning on the first reset transistor Tr1, and the initialization voltage signal from the corresponding first reset signal line Vint1 is transmitted from the first electrode of the first reset transistor Tr1 to the second electrode of the first reset transistor Tr1 and further to the node N4, thereby initializing the anode of the light-emitting element LE.

[0039] In the light-emission subphase t3, an off-reset control signal is again provided to the gate electrode of the second reset transistor Tr2 via the corresponding second reset control signal line rst2, turning off the second reset transistor Tr2. An off signal is provided to the corresponding first gate line GL1 and the corresponding second gate line GL2, turning off the first transistor T1 and the second transistor T2. A low-voltage signal is provided to the corresponding light-emission control signal line em, turning on the third transistor T3 and the fourth transistor T4. In the light-emission subphase t3, the voltage level of the node N1 is maintained at (Vdata+Vth), and the drive transistor Td is turned on by this voltage level and operates in the saturation region. A path is formed that passes through the third transistor T3, the drive transistor Td, and the fourth transistor T4 to reach the light-emitting element LE. The drive transistor Td generates a drive current to drive the light-emitting element LE to emit light. The voltage level of the node N3 connected to the second electrode of the drive transistor Td is equal to the light-emission voltage of the light-emitting element LE.

[0040] 4 and 5, several types of scan signals are required for the operation of the pixel drive circuit. Examples of the scan signals required for the operation of the pixel drive circuit include first gate scan signals on a plurality of first gate lines GL1 for controlling p-type transistors (e.g., the first transistor T1), second gate scan signals on a plurality of second gate lines GL2 for controlling n-type transistors (e.g., the second transistor T2), light emission control signals on a plurality of light emission control signal lines em for controlling light emission control transistors (e.g., the third transistor T3 and the fourth transistor T4), first reset control signals on a plurality of first reset control signal lines rst1 for controlling first reset transistors (e.g., the first reset transistor Tr1), and second reset control signals on a plurality of second reset control signal lines rst2 for controlling second reset transistors (e.g., the second reset transistor Tr2).

[0041] In some embodiments, a plurality of scanning circuits are used to generate scanning signals required for operation of the pixel driving circuit, examples of the scanning circuits for generating the scanning signals required for operation of the pixel driving circuit include a first gate scanning circuit configured to generate a first gate scanning signal, a second gate scanning circuit configured to generate a second gate scanning signal, an emission control scanning circuit configured to generate an emission control signal, a first reset scanning circuit configured to generate a first reset control signal, and a second reset scanning circuit configured to generate a second reset control signal.

[0042] 6A shows a layout of scanning circuits on an array substrate in some embodiments according to the present disclosure. Referring to FIG. 6A, the array substrate includes a plurality of scanning circuits. In some embodiments, the plurality of scanning circuits includes a first gate scanning circuit P gate GOA configured to generate a first gate scanning signal, a second gate scanning circuit N gate GOA configured to generate a second gate scanning signal, a light-emitting control scanning circuit em GOA configured to generate a light-emitting control signal, a first reset scanning circuit P rst1 GOA configured to generate a first reset control signal, and a second reset scanning circuit P rst2 GOA configured to generate a second reset control signal.

[0043] The inventors of the present disclosure have found that the RC load on the scanning signal lines may be relatively large, particularly in medium- to large-sized display panels (e.g., laptop computers). The inventors of the present disclosure have found that a double-sided driving method can contribute to overcoming the RC load problem. As shown in FIG. 6A, the first gate scanning circuit P gate GOA, the second gate scanning circuit N gate GOA, the light-emission control scanning circuit em GOA, the first reset scanning circuit P rst1 GOA, and the second reset scanning circuit P rst2 GOA each include scanning units located on both sides of the display area DA of the array substrate. The operation methods of the first gate scanning circuit P gate GOA, the second gate scanning circuit N gate GOA, the light-emission control scanning circuit em GOA, the first reset scanning circuit P rst1 GOA, and the second reset scanning circuit P rst2 GOA are the same as those of FIG. 2B.

[0044] However, the inventors of the present disclosure have found that an array substrate with a double-sided driving and scanning circuit generally sacrifices frame area to accommodate additional scanning units on both sides of the display area, and an array substrate with a single-sided driving and scanning circuit may be used to achieve an increased display area.

[0045] 6B illustrates the layout of scanning circuits on an array substrate according to some embodiments of the present disclosure. Referring to FIG. 6B, the array substrate includes multiple scanning circuits. In some embodiments, the multiple scanning circuits include a first gate scanning circuit P gate GOA configured to generate a first gate scanning signal, a second gate scanning circuit N gate GOA configured to generate a second gate scanning signal, an emission control scanning circuit em GOA configured to generate an emission control signal, a first reset scanning circuit P rst1 GOA configured to generate a first reset control signal, and a second reset scanning circuit P rst2 GOA configured to generate a second reset control signal. As shown in FIG. 6B, each of the second gate scanning circuit N gate GOA, the emission control scanning circuit em GOA, the first reset scanning circuit P rst1 GOA, and the second reset scanning circuit P rst2 GOA includes a scanning unit located on only one side of the display area DA of the array substrate. For example, the second gate scanning circuit Ngate GOA and the light emission control scanning circuit emGOA are arranged on the left side of the display area DA, and the first reset scanning circuit Prst1 GOA and the second reset scanning circuit Prst2 GOA are arranged on the right side of the display area DA. The operation methods of the second gate scanning circuit Ngate GOA, the light emission control scanning circuit emGOA, the first reset scanning circuit Prst1 GOA and the second reset scanning circuit Prst2 GOA are the same as those in Fig. 2A.

[0046] Various suitable scanning circuits may be used in the present disclosure. FIG. 7 is a schematic diagram illustrating corresponding scanning units of a scanning circuit in some embodiments of the present disclosure. Referring to FIG. 7, in some embodiments, each scanning unit includes an input subcircuit ISC, an output subcircuit OSC, a first processing subcircuit PSC1, a second processing subcircuit PSC2, a third processing subcircuit PSC3, a first stabilization subcircuit SSC1, and a second stabilization subcircuit SSC2. Each scanning unit may be configured to transmit control signals to one or more rows of subpixels. As an example, each scanning unit is configured to transmit control signals to one row of subpixels. As another example, each scanning unit is configured to transmit control signals to two or more rows of subpixels.

[0047] In some embodiments, the output sub-circuit OSC is configured to supply the voltage of the first power supply VGH or the second power supply VGL to the output terminal TM4 in response to the voltages of the fourth node N4 and the first node N1. Optionally, the output sub-circuit OSC may include a ninth transistor T9 and a tenth transistor T10.

[0048] The ninth transistor T9 is coupled between the first power supply VGH and the output terminal TM4. The gate electrode of the ninth transistor T9 is coupled to the fourth node N4. The ninth transistor T9 may be turned on or off according to the voltage of the fourth node N4. Optionally, when the ninth transistor T9 is turned on, the voltage of the first power supply VGH (denoted as Outc in FIG. 7 ) may be provided to the output terminal TM4, which is transmittable to the n-th gate line and used as a gate-on level gate driving signal.

[0049] The tenth transistor T10 is coupled between the output terminal TM4 and the second power supply VGL. The gate electrode of the tenth transistor T10 is coupled to the first node N1. The tenth transistor T10 may be turned on or off depending on the voltage of the first node N1. Optionally, when the tenth transistor T10 is turned on, the voltage of the second power supply VGL (denoted as Outc in FIG. 7 ) that can be provided to the n-th gate line and used as a gate-off level gate drive signal is provided to the output terminal TM4. As an example, it can be understood that when the gate drive signal is at the gate-off level, no gate drive signal is provided.

[0050] In some embodiments, the input sub-circuit ISC is configured to control the voltages of the first node N1 and the fifth node N5 in response to signals provided to the first input terminal TM1 and the second input terminal TM2, respectively. Optionally, the input sub-circuit ISC may include a first transistor T1.

[0051] The first transistor T1 is connected between the first input terminal TM1 and the fifth node N5. The gate electrode of the first transistor T1 is connected to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the first transistor T1 is turned on, electrically connecting the first input terminal TM1 to the fifth node N5.

[0052] In some embodiments, the first processing sub-circuit PSC1 is configured to control the voltage of the fourth node N4 in response to the voltages of the first node N1 and the fifth node N5. Optionally, the first processing sub-circuit PSC1 may include an eighth transistor T8 and a second capacitor C2.

[0053] The eighth transistor T8 is coupled between the first power supply VGH and the fourth node N4. The gate electrode of the eighth transistor T8 is coupled to the fifth node N5. The eighth transistor T8 may be turned on or off depending on the voltage of the fifth node N5. Optionally, when the eighth transistor T8 is turned on, the voltage of the first power supply VGH may be provided to the fourth node N4.

[0054] The second capacitor C2 is coupled between the first power supply VGH and the fourth node N4. Optionally, the second capacitor C2 may be configured to charge a voltage applied to the fourth node N4. Optionally, the second capacitor C2 may be configured to maintain the voltage of the fourth node N4 stable.

[0055] In some embodiments, the second processing sub-circuit PSC2 is coupled to the sixth node N6 and configured to control the voltage of the fourth node N4 in response to a signal input to the third input terminal TM3. Optionally, the second processing sub-circuit PSC2 may include a sixth transistor T6, a seventh transistor T7, and a first capacitor C1.

[0056] A first terminal of the first capacitor C1 is coupled to the sixth node N6, and a second terminal of the first capacitor C1 is coupled to a third node N3, which is a common node between the sixth transistor T6 and the seventh transistor T7.

[0057] The sixth transistor T6 is connected between the third node N3 and a sixth node N6. The gate electrode of the sixth transistor T6 is connected to the sixth node N6. The sixth transistor T6 may be turned on in response to the voltage at the sixth node N6, so that a voltage corresponding to the second clock signal CB provided to the third input terminal TM3 may be applied to the third node N3.

[0058] The seventh transistor T7 is coupled between the fourth node N4 and the third node N3. The gate electrode of the seventh transistor T7 is coupled to the third input terminal TM3. The seventh transistor T7 may be turned on in response to the second clock signal CB provided to the third input terminal TM3, so that the voltage of the first power supply VGH is applied to the third node N3.

[0059] In some embodiments, the third processing subcircuit PSC3 is configured to control the voltage of the second node N2. Optionally, the third processing subcircuit PSC3 may include a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5.

[0060] The fifth transistor T5 is coupled between the first power supply VGH and the fourth transistor T4. The gate electrode of the fifth transistor T5 is coupled to the second node N2. The fifth transistor T5 may be turned on or off depending on the voltage of the second node N2.

[0061] The fourth transistor T4 is coupled between the fifth transistor T5 and the third input terminal TM3, and the gate electrode of the fourth transistor T4 is configured to receive the second clock signal CB provided to the third input terminal TM3.

[0062] The second transistor T2 is coupled between the second node N2 and the second input terminal TM2, and the gate electrode of the second transistor T2 is coupled to the fifth node N5.

[0063] The third transistor T3 is coupled between the second node N2 and the second power supply VGL. The gate electrode of the third transistor T3 is coupled to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the third transistor T3 may be turned on, thereby providing the voltage of the second power supply VGL to the second node N2.

[0064] In some embodiments, the first stabilization subcircuit SSCl is coupled between the second processing subcircuit PSC2 and the third processing subcircuit PSC3. Optionally, the first stabilization subcircuit SSCl may be configured to limit the voltage drop at the second node N2. Optionally, the first stabilization subcircuit SSCl may include an eleventh transistor T11.

[0065] The eleventh transistor T11 is connected between the second node N2 and the sixth node N6. The gate electrode of the eleventh transistor T11 is connected to the second power supply VGL. Since the second power supply VGL is a gate on-level voltage, the eleventh transistor T11 may always be kept on. Therefore, the second node N2 and the sixth node N6 may maintain the same voltage and operate as substantially the same node.

[0066] In some embodiments, the second stabilization subcircuit SSC2 is coupled between the first node N1 and the output subcircuit OSC. Optionally, the second stabilization subcircuit SSC2 may be configured to limit a voltage drop at the first node N1. Optionally, the second stabilization subcircuit SSC2 may include a twelfth transistor T12 and a third capacitor C3.

[0067] The twelfth transistor T12 is connected between the first node N1 and the gate electrode of the tenth transistor T10. The gate electrode of the twelfth transistor T12 is connected to the second power supply VGL. Since the second power supply VGL is a gate on-level voltage, the twelfth transistor T12 may always be kept on. Therefore, the first node N1 and the gate electrode of the tenth transistor T10 may be kept at the same voltage.

[0068] A first electrode of the third capacitor C3 is coupled to the gate electrode of the tenth transistor T10, and a second electrode of the third capacitor C3 is configured to receive the second clock signal CB provided to the third input terminal TM3.

[0069] In some embodiments, the first transistor T1 to the twelfth transistor T12 may each be a p-type transistor, and the gate-on voltages of the first transistor T1 to the twelfth transistor T12 may be set to a low level, and the gate-off voltages thereof may be set to a high level.

[0070] 8 is a schematic diagram illustrating corresponding scanning units of a scanning circuit according to some embodiments of the present disclosure. Referring to FIG. 8, each scanning unit includes a first control transistor GT1 to an eighth control transistor GT8, a first control capacitor GC1, and a second control capacitor GC2. In some embodiments, a gate electrode of the first control transistor GT1 is electrically connected to a first clock signal terminal GCK1, a first electrode of the first control transistor GT1 is electrically connected to an input terminal GIN, a second electrode of the first control transistor GT1 is electrically connected to a first node G1, a gate electrode of the second control transistor GT2 is electrically connected to the first node G1, a first electrode of the second control transistor GT2 is electrically connected to the first clock signal terminal GCK1, a second electrode of the second control transistor GT2 is electrically connected to a second node G2, a gate electrode of the third control transistor GT3 is electrically connected to the first clock signal terminal GCK1, a first electrode of the third control transistor GT3 is electrically connected to a second power supply VGL, a second electrode of the third control transistor GT3 is electrically connected to a second node G2, and a gate electrode of the fourth control transistor GT4 is electrically connected to the second node G1. a first electrode of the fourth control transistor GT4 electrically connected to the first power supply VGH and a second electrode of the fourth control transistor GT4 electrically connected to the output terminal GOUT; a gate electrode of the fifth control transistor GT5 electrically connected to the third node G3; a first electrode of the fifth control transistor GT5 electrically connected to the second clock signal terminal GCK2 and a second electrode of the fifth control transistor GT5 electrically connected to the output terminal GOUT; a gate electrode of the sixth control transistor GT6 electrically connected to the second node G2; a first electrode of the sixth control transistor GT6 electrically connected to the first power supply VGH; a second electrode of the sixth control transistor GT6 electrically connected to the first electrode of the seventh control transistor GT7; a gate electrode of the seventh control transistor GT7 electrically connected to the second clock signal terminal GCK2 and a second electrode of the seventh control transistor GT7The eighth control transistor GT8 is electrically connected to the first node G1, the gate electrode of the eighth control transistor GT8 is electrically connected to the second power supply VGL, the first electrode of the eighth control transistor GT8 is electrically connected to the first node G1, the second electrode of the eighth control transistor GT8 is electrically connected to the third node G3, the first plate GC11 of the first control capacitor GC1 is electrically connected to the second node G2, the second plate GC12 of the first control capacitor GC1 is electrically connected to the first power supply VGH, the first plate GC21 of the second control capacitor GC2 is electrically connected to the third node G3, and the second plate GC22 of the second control capacitor GC2 is electrically connected to the output terminal GOUT. As an example, the first control transistor GT1 to the eighth control transistor GT8 may be p-type transistors or n-type transistors. As another example, the first power supply VGH provides a continuous high-level signal, and the second power supply VGL provides a continuous low-level signal.

[0071] FIG. 9 is a plan view of an array substrate in some embodiments according to the present disclosure. Referring to FIG. 9 , in some embodiments, the array substrate includes a display area DA and a notch area NA. As used herein, the term "display area" refers to the area of ​​the array substrate where an image is actually displayed. Optionally, the display area may include both subpixel areas and inter-subpixel areas. A subpixel area refers to the emissive area of ​​a subpixel, such as an area corresponding to a pixel electrode in a liquid crystal display or an area corresponding to an emissive layer in an organic light-emitting display. An inter-subpixel area refers to the area between adjacent subpixel areas, such as an area corresponding to a black matrix in a liquid crystal display or an area corresponding to a pixel definition layer in an organic light-emitting display. Optionally, the inter-subpixel area may be the area between adjacent subpixel areas within the same pixel. Optionally, the inter-subpixel area may be the area between two adjacent subpixel areas from two adjacent pixels. As used herein, a "notch area" refers to an area of ​​the array substrate where a sensor, such as a camera, a light sensor, or a touch sensor, is located. Optionally, the notch area may not be capable of displaying an image. As an example, there are no light emitting elements in the notch region.

[0072] FIG. 10 is a plan view illustrating a portion of an array substrate in some embodiments according to the present disclosure. Referring to FIG. 10 , in some embodiments, the notch region NA includes an electrostatic discharge region EPA. The electrostatic discharge region EPA includes a plurality of electrostatic discharge units for protecting a plurality of data lines. The display region DA includes a first display subregion DA1 and a second display subregion DA2. The first display subregion DA1 and the second display subregion DA2 are separated from each other by the notch region NA. The array substrate includes one or more rows of subpixels located in the first display subregion DA1 and the second display subregion DA2. The subpixels in the same row located in the first display subregion DA1 and the second display subregion DA2 are divided into two parts in the first display subregion DA1 and the second display subregion DA2, respectively.

[0073] Referring to FIG. 9 , in some embodiments, the array substrate further includes a scanning circuit GOA located on one side of the display area DA. The scanning circuit GOA operates using a single-sided driving method. The array substrate further includes a plurality of scanning signal lines SSL penetrating the first display sub-area DA1 and the second display sub-area DA2. Due to the presence of the notch region NA, each of the scanning signal lines SSL does not extend in a straight line from the first display sub-area DA1 to the second display sub-area DA2. The portion of each scanning signal line located in the first display sub-area DA1 and the portion of each scanning signal line located in the second display sub-area DA2 are connected via the portion located in the notch region NA. Because the scanning circuit GOA operates using a single-sided driving method, the portion of each scanning signal line located in the first display sub-area DA1 must be connected to the portion of each scanning signal line located in the second display sub-area DA2 to drive the sub-pixels located in the second display sub-area DA2.

[0074] FIG. 11A is an enlarged view of the enlarged region in FIG. 10. FIG. 10 shows a first enlarged region ZR1. FIG. 11A is an enlarged view of the first enlarged region ZR1 in FIG. 10. FIG. 11B is a schematic diagram of the first enlarged region in FIG. 11A. Referring to FIGS. 11A and 11B, in some embodiments, the notch region includes an electrostatic discharge region EPA and a transition region TA. The transition region TA is located between the electrostatic discharge region EPA and the first display sub-region DA1 (the other portion of the transition region TA is located between the electrostatic discharge region EPA and the second display sub-region). As described above, the electrostatic discharge region EPA includes multiple electrostatic discharge units for protecting multiple data lines. The transition region TA is not present in the multiple electrostatic discharge units.

[0075] 11C is an enlarged view of a portion of the first enlarged region in FIG. 11A. FIG. 11C is an enlarged view of a region including a portion of the transition region, a portion of the first display sub-region, and a portion of the electrostatic discharge region. In FIG. 11C, the plurality of data lines are represented as "DL," the plurality of scan signal lines are represented as "SSL," and the plurality of electrostatic discharge units are represented as "ESD."

[0076] 11D is an enlarged view of a second enlarged region ZR2 in FIG. 11C. FIG. 11E is an enlarged view of a third enlarged region ZR3 in FIG. 11D. Referring to FIGS. 11C to 11E, in the transition region TA, the plurality of data lines DL and the plurality of scanning signal lines SSL intersect with each other. Optionally, the portions of the plurality of scanning signal lines SSL that intersect with the plurality of data lines DL may extend along a first direction DR1. Optionally, the portions of the plurality of data lines DL that intersect with the plurality of scanning signal lines SSL may extend along a second direction DR2. Optionally, the first direction DR1 and the second direction DR2 may be substantially perpendicular to each other. As used herein, "substantially perpendicular" means that the angle is in the range of about 75 degrees to about 105 degrees, for example, about 75 degrees to about 80 degrees, about 80 degrees to about 85 degrees, about 85 degrees to about 90 degrees, about 90 degrees to about 95 degrees, about 95 degrees to about 100 degrees, or about 100 degrees to about 105 degrees.

[0077] In some embodiments, each of the scanning signal lines SSL includes one or more portions other than the portions intersecting with one or more data lines, and the one or more portions other than the portions intersecting with the one or more data lines may extend along a direction different from the first direction DR1.

[0078] In some embodiments, each of the plurality of data lines DL includes one or more portions other than the portions intersecting with one or more scanning signal lines, and the one or more portions other than the portions intersecting with the one or more scanning signal lines may extend along a direction different from the second direction DR2.

[0079] In some embodiments, multiple scan signal lines from subpixels in the same row cross the same number of data lines. Optionally, multiple scan signal lines from at least one row of subpixels may cross two data lines.

[0080] The inventors of the present disclosure have found that by making the first direction DR1 and the second direction DR2 substantially perpendicular to each other and having multiple scanning signal lines from subpixels in the same row cross the same number of data lines, the parasitic capacitance between each of the multiple scanning signal lines SSL and the multiple data lines can be made substantially uniform, for example, the difference therebetween can be made less than 15%, less than 10%, less than 5%, less than 1% or less than 0.5%.

[0081] 12A is a cross-sectional view taken along line A-A' in FIG. 11E. Referring to FIG. 12A, portions of the scanning signal lines SSL that intersect with the data lines DL each extend along a first direction DR1. FIG. 12B is a cross-sectional view taken along line B-B' in FIG. 11E. Referring to FIG. 12B, portions of the data lines DL that intersect with the scanning signal lines SSL each extend along a second direction DR2. Referring to FIGS. 12A and 12B, in some embodiments, the data lines DL are in a first signal line layer SD1, and the scanning signal lines SSL are in a second signal line layer SD2 that is located on the side of the first signal line layer SD1 that is away from the base substrate BS.

[0082] FIG. 13 is a plan view showing a portion of an array substrate in some embodiments according to the present disclosure. FIG. 14A is a diagram showing the layout of signal lines in FIG. 13 . FIG. 14B is a schematic diagram showing the layout of signal lines in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 14A shows the layout of signal lines in a portion of the array substrate adjacent to the first display sub-region DA1. FIG. 14B shows the layout of signal lines in a portion of the array substrate adjacent to the second display sub-region DA2. The pixel driving circuits located in the first display sub-region DA1 and the second display sub-region DA2 are omitted in FIGS. 14A and 14B but are shown in FIG. 13 . The electrostatic discharge unit located in the electrostatic discharge region EPA is omitted in FIGS. 14A and 14B but is shown in FIG. 13 . FIGS. 14A and 14B show the layout of signal lines located in the electrostatic discharge region EPA.

[0083] 13, 14A, and 14B, in some embodiments, the notch area includes an electrostatic discharge area EPA and a transition area TA. The transition area TA is located between the electrostatic discharge area EPA and the first display sub-area DA1 or between the electrostatic discharge area EPA and the second display sub-area DA2. As described above, the electrostatic discharge area EPA includes multiple electrostatic discharge units for protecting multiple data lines. The transition area TA does not include multiple electrostatic discharge units.

[0084] 13, 14A, and 14B, in some embodiments, the plurality of data lines DL extends at least partially into the electrostatic discharge area EPA, and the plurality of scan signal lines SSL extends at least partially into the electrostatic discharge area EPA. Optionally, the plurality of scan signal lines SSL may cross the electrostatic discharge area EPA.

[0085] In some embodiments, at least a portion of the electrostatic discharge region EPA includes a plurality of alternating first sub-regions SR1 and a plurality of second sub-regions SR2. A plurality of scanning signal lines SSL are present in the plurality of first sub-regions SR1 but are not present in the plurality of second sub-regions SR2. A plurality of data lines DL are present in the plurality of second sub-regions SR2 but are not present in the plurality of first sub-regions SR1.

[0086] In some embodiments, at least one first sub-region of the plurality of first sub-regions SR1 includes a plurality of scanning signal lines. Optionally, each first sub-region of the plurality of first sub-regions SR1 may include a plurality of scanning signal lines. In some embodiments, at least one second sub-region of the plurality of second sub-regions SR2 includes at least one data line, such as a plurality of data lines. Optionally, each second sub-region of the plurality of second sub-regions SR2 may include at least one data line, such as a plurality of data lines.

[0087] In some embodiments, a scanning signal line extending from the first display sub-region DA1 across a portion of the electrostatic discharge region EPA adjacent to the first display sub-region DA1 and a scanning signal line extending from the second display sub-region DA2 across a portion of the electrostatic discharge region EPA adjacent to the second display sub-region DA2 are connected to each other. This connection ensures that, when a single-sided driving scanning circuit is used in the array substrate, scanning signals can be transmitted from the first display sub-region DA1 to the second display sub-region DA2, or from the second display sub-region DA2 to the first display sub-region DA1. This connection ensures that, when a single-sided driving scanning circuit is provided on the side of the first display sub-region DA1 away from the second display sub-region DA2, scanning signals can be transmitted from the first display sub-region DA1 to the second display sub-region DA2 to drive sub-pixels located in the second display sub-region DA2. This connection ensures that when the one-sided driving scanning circuit is provided on the side of the second display sub-area DA2 away from the first display sub-area DA1, a scanning signal is transmitted from the second display sub-area DA2 to the first display sub-area DA1 to drive the sub-pixels located in the first display sub-area DA1.

[0088] The inventors of the present disclosure have discovered that by providing alternating first and second sub-regions in at least a portion of the electrostatic discharge region EPA, with each first sub-region (e.g., sub-regions 1, 3, 5, 7, and 9 shown in FIG. 13) exclusively housing a scanning signal line and each second sub-region (e.g., sub-regions 2, 4, 6, and 8 shown in FIG. 13) exclusively housing a data line, each scanning signal line across the electrostatic discharge region EPA may have substantially the same parasitic capacitance as components in the electrostatic discharge unit. The parasitic capacitance between the scanning signal lines in the electrostatic discharge unit is distributed in a highly ordered pattern. The parasitic capacitance between each scanning signal line and the electrostatic discharge unit is substantially the same. This sophisticated configuration ensures that low-level mura in the notch region is distributed in a highly ordered pattern, which contributes to efficient and effective mura compensation using an appropriate mura correction algorithm.

[0089] In some embodiments, the electrostatic discharge area EPA includes a plurality of electrostatic discharge units ESD for protecting a plurality of data lines, for example, for discharging electrostatic charges in the electrostatic discharge area EPA, and in some embodiments, the electrostatic discharge area EPA further includes a plurality of dummy electrostatic discharge units DESD.

[0090] FIG. 15 is a schematic diagram showing the layout of signal lines and electrostatic discharge units in a portion of an array substrate according to some embodiments of the present disclosure. FIG. 16 is a cross-sectional view taken along line C-C' in FIG. 15. Referring to FIGS. 15 and 16, the electrostatic discharge region EPA further includes a plurality of dummy electrostatic discharge units DESD in addition to a plurality of electrostatic discharge units ESD for protecting a plurality of data lines. The orthogonal projection onto the base substrate of each of the plurality of scanning signal lines SSL located in each of the plurality of first sub-regions SR1 partially overlaps the orthogonal projection onto the base substrate of some of the plurality of dummy electrostatic discharge units DES. The inventors of the present disclosure have discovered that providing a plurality of dummy electrostatic discharge units DESD can achieve etching uniformity in the manufacturing process of the array substrate, particularly in the process of forming transistors of the electrostatic discharge units.

[0091] As used herein, the term "dummy" refers to an electrostatic discharge unit that has the same or similar structure as an active electrostatic discharge unit, but this structure is used only in a configuration that exists as a pattern and does not actually perform a function on the array substrate. Therefore, an electrical signal may not be applied to the "dummy" electrostatic discharge unit, and even if an electrical signal is applied to the "dummy" electrostatic discharge unit, the "dummy" electrostatic discharge unit does not perform an electrically equivalent function.

[0092] In some embodiments, at least a portion of the electrostatic discharge area EPA includes a plurality of alternating first sub-areas SR1 and a plurality of second sub-areas SR2, a plurality of dummy electrostatic discharge units DESD are present in the plurality of first sub-areas SR1 but are absent in the plurality of second sub-areas SR2, and a plurality of electrostatic discharge units ESD are present in the plurality of second sub-areas SR2 but are absent in the plurality of first sub-areas SR1.

[0093] In some embodiments, the plurality of scan signal lines SSL and the plurality of dummy electrostatic discharge units DESD are present in the plurality of first sub-regions SR1 but not in the plurality of second sub-regions SR2, and the plurality of data lines DL and the plurality of electrostatic discharge units ESD are present in the plurality of second sub-regions SR2 but not in the plurality of first sub-regions SR1.

[0094] The inventors of the present disclosure have further found that by providing alternating first sub-regions and second sub-regions in at least a portion of the electrostatic discharge area EPA, and by providing corresponding first sub-regions that exclusively accommodate scanning signal lines and dummy electrostatic discharge units, and by providing corresponding second sub-regions that exclusively accommodate data lines and electrostatic discharge units, the load between the scanning signal lines can be substantially uniform, and the risk of scanning signals interfering with the data lines or electrostatic discharge units can be reduced.

[0095] Figure 17 is a schematic diagram showing the layout of signal lines in a portion of an array substrate in some embodiments according to the present disclosure. Figure 18 is a cross-sectional view taken along line D-D' in Figure 17. Referring to Figures 17 and 18, in some embodiments, the electrostatic discharge area does not include multiple dummy electrostatic discharge units. By not providing dummy electrostatic discharge units below the scanning signal lines, any potential damage caused by electrostatic discharge between the scanning signal lines and the dummy electrostatic discharge units can be avoided.

[0096] FIG. 19 is a schematic diagram showing a layout of signal lines in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 20 is an enlarged view of a fourth enlarged region ZR4 in FIG. 19. FIG. 21 is a cross-sectional view taken along line E-E' in FIG. 20. FIG. 22 is a cross-sectional view taken along line F-F' in FIG. 20. Referring to FIGS. 19 to 22, in some embodiments, a corresponding scanning signal line among the plurality of scanning signal lines SSL that crosses the transition region TA and the electrostatic discharge region EPA includes a first portion P1, a second portion P2, and a third portion P3. The first portion P1 is a portion where one or more data lines located in the transition region TA cross. Optionally, the first portion P1 may extend in a first direction DR1. The second portion P2 straddles the electrostatic discharge region EPA. The third portion P3 is at least partially located in a portion of the notch region NA located on the side of the electrostatic discharge region EPA away from the transition region TA. Optionally, the second portion P2 may connect the first portion P1 to the third portion P3.

[0097] In some embodiments, the first portion P1 is located on a different layer from the second portion P2. Referring to FIGS. 20 to 22, in some embodiments, the first portion P1 is located on the first conductive layer CT1, and the second portion P2 is located on the first signal line layer SD1, which is located on the side of the first conductive layer CT1 that is farther from the base substrate BS. The inventors of the present disclosure have found that providing such an elaborately configured scanning signal line can further simplify the manufacturing process, for example, reducing the number of mask plates used in the manufacturing process by two.

[0098] In some embodiments, a corresponding scanning signal line among the plurality of scanning signal lines SSL that spans the transition region TA and the electrostatic discharge region EPA further includes a fourth portion P4 that is at least partially located in the display region (e.g., located in the first display sub-region DA1 or the second display sub-region DA2). Optionally, the first portion P1 may connect the fourth portion P4 to the second portion P2. Optionally, the fourth portion P4 may be in the first signal line layer SD1. Optionally, the fourth portion P4 may be connected to the first portion P1 through a via that penetrates the interlayer dielectric layer ILD and the insulating layer IN. Optionally, the second portion P2 may be connected to the first portion P1 through a via that penetrates the interlayer dielectric layer ILD and the insulating layer IN.

[0099] In some embodiments, the second portion P2 is located in the same layer as the plurality of data lines DL. In some embodiments, the fourth portion P4 is located in the same layer as the plurality of data lines DL. Optionally, the plurality of data lines DL may be located in the first signal line layer SD1.

[0100] FIG. 23 is a schematic diagram showing the layout of signal lines in a portion of an array substrate in some embodiments according to the present disclosure. FIG. 24 is a cross-sectional view taken along line G-G' in FIG. 23. FIG. 25 is a cross-sectional view taken along line H-H' in FIG. 23. Referring to FIGS. 23 to 25, in some embodiments, the second portion P2 and the third portion P3 of the corresponding scanning signal lines SSL that straddle the transition region TA and the electrostatic discharge region EPA are located in different layers. Optionally, the second portion P2 of the corresponding scanning signal line SSL that straddles the transition region TA and the electrostatic discharge region EPA may be located in the first signal line layer. As an example, the third portion P3 of the corresponding scanning signal line SSL that straddles the transition region TA and the electrostatic discharge region EPA is located in the first conductive layer CT1. As another example, among the multiple scanning signal lines SSL, the third portion P3 of the corresponding scanning signal line that straddles the transition area TA and the electrostatic discharge area EPA is located on the second conductive layer CT2 that is located on the side of the first conductive layer CT1 that is away from the base substrate BS and on the side of the first signal line layer SD1 that is closer to the base substrate BS.

[0101] In some embodiments, the second portions of some of the scanning signal lines SSL that are located in the same first sub-region of the plurality of first sub-regions SR1 are connected to the third portions of some of the scanning signal lines, and the third portions of some of the scanning signal lines are alternately located on the first conductive layer CT1 and the second conductive layer CT2.

[0102] 26 shows a configuration of a display area in an array substrate of some embodiments according to the present disclosure. Referring to FIG. 26, in some embodiments, the array substrate in the display area includes a base substrate BS (e.g., a flexible base substrate), one active layer ACT of each of a plurality of thin film transistors TFT located on the base substrate BS, a gate insulating layer GI located on the side of the active layer ACT away from the base substrate BS, a gate electrode G and a first capacitor electrode Ce1 (all of which are part of a first gate metal layer) located on the side of the gate insulating layer GI away from the base substrate BS, an insulating layer IN located on the side of the gate electrode G and the first capacitor electrode Ce1 away from the gate insulating layer GI, a second capacitor electrode Ce2 (part of a second gate metal layer) located on the side of the insulating layer IN away from the gate insulating layer GI, and a second capacitor electrode Ce2 (part of a second gate metal layer) located on the side of the second capacitor electrode Ce2 away from the gate insulating layer GI. the first planarization layer PLN1 is located on the side of the passivation layer PVX that is away from the interlayer dielectric layer ILD; a source electrode S and a drain electrode D (which are part of the first SD metal layer) that are located on the side of the interlayer dielectric layer ILD that is away from the gate insulating layer GI; a passivation layer PVX that is located on the side of the source electrode S and the drain electrode D that is away from the interlayer dielectric layer ILD; a first planarization layer PLN1 that is located on the side of the passivation layer PVX that is away from the interlayer dielectric layer ILD; a relay electrode RE (which is part of the second SD metal layer) that is located on the side of the first planarization layer PLN1 that is away from the passivation layer PVX; a second planarization layer PLN2 that is located on the side of the relay electrode RE that is away from the first planarization layer PLN1; a pixel definition layer PDL that defines a subpixel opening and that is located on the side of the second planarization layer PLN2 that is away from the base substrate BS; and a light-emitting element LE that is located in the subpixel opening. The light-emitting element LE includes an anode AD located on a side of the second planarization layer PLN2 away from the first planarization layer PLN1, an emitting layer EL located on a side of the anode AD away from the second planarization layer PLN2, and a cathode layer CD located on a side of the emitting layer EL away from the anode AD. The array substrate further includes a sealing layer EN in the display region that seals the light-emitting element LE and is located on a side of the cathode layer CD away from the base substrate BS.

[0103] In some embodiments, the encapsulation layer EN includes a first inorganic encapsulation sub-layer CVD1 located on a side of the cathode layer CD away from the base substrate BS, a first organic encapsulation sub-layer IJP1 located on a side of the first inorganic encapsulation sub-layer CVD1 away from the base substrate BS, a second inorganic encapsulation sub-layer CVD2 located on a side of the first organic encapsulation sub-layer IJP1 away from the base substrate BS, a second organic encapsulation sub-layer IJP2 located on a side of the second inorganic encapsulation sub-layer CVD2 away from the base substrate BS, and a third inorganic encapsulation sub-layer CVD3 located on a side of the second organic encapsulation sub-layer IJP2 away from the base substrate BS.

[0104] In the display area, the array substrate further includes: a buffer layer BUF located on a side of the sealing layer EN away from the base substrate BS; a first touch electrode layer TE1 located on a side of the buffer layer BUF away from the sealing layer EN; a touch insulating layer TI located on a side of the first touch electrode layer TE1 away from the buffer layer BUF; a second touch electrode layer TE2 located on a side of the touch insulating layer TI away from the buffer layer BUF; and an overcoat layer OC located on a side of the second touch electrode layer TE2 away from the touch insulating layer TI.

[0105] 26, the array substrate includes a semiconductor material layer SML, a first gate metal layer Gate1, a second gate metal layer Gate2, a first signal line layer SLL1, and a second signal line layer SLL2. The array substrate further includes an insulating layer IN located between the first gate metal layer Gate1 and the second gate metal layer Gate2, an interlayer dielectric layer ILD located between the second gate metal layer Gate2 and the first signal line layer SLL1, and at least a passivation layer PVX or a planarization layer PLN located between the first signal line layer SLL1 and the second signal line layer SLL2.

[0106] 27 is a schematic diagram showing a layout of signal lines in a portion of an array substrate according to some embodiments of the present disclosure. FIG. 28 is a schematic diagram showing a layout of signal lines in a portion of an array substrate according to some embodiments of the present disclosure. Referring to FIG. 27 and FIG. 28, in some embodiments, the second portions of some of the scanning signal lines SSL that are located in the same first sub-region SR1 among the plurality of first sub-regions SR1 are alternately located on the first signal line layer SD1 and the second signal line layer SD2.

[0107] In some embodiments, the second portions of some of the scanning signal lines SSL located in the same first sub-region of the plurality of first sub-regions SR1 are connected to the first portions of some of the scanning signal lines, and the first portions of some of the scanning signal lines are alternately located in the first conductive layer CT1 and the second signal line layer SD2. Optionally, individual second portions in the second signal line layer SD2 may be connected to individual first portions in the second signal line layer SD2. Optionally, individual second portions in the first signal line layer SD1 may be connected to individual first portions in the first conductive layer CT1.

[0108] In some embodiments, the second portions of some of the scanning signal lines SSL located in the same first sub-region SR1 among the plurality of first sub-regions SR1 are connected to the third portions of some of the scanning signal lines, and the third portions of some of the scanning signal lines are alternately located on the first conductive layer CT1 and the second conductive layer CT2. Optionally, individual second portions in the second signal line layer SD2 may be connected to individual third portions in the first conductive layer CT1. Optionally, individual second portions in the first signal line layer SD1 may be connected to individual third portions in the second conductive layer CT2.

[0109] The present disclosure is applicable to array substrates having single-sided driving and scanning circuits as well as array substrates having double-sided driving and scanning circuits. Figure 29 is a schematic diagram showing the layout of signal lines in a portion of an array substrate according to some embodiments of the present disclosure. Figure 30 is a schematic diagram showing the layout of signal lines in a portion of an array substrate according to some embodiments of the present disclosure.

[0110] 11B, 29, and 30, at least one data line among the plurality of data lines DL and at least one scan signal line among the plurality of scan signal lines SSL intersect with each other in the transition region TA. In some embodiments, individual scan signal lines extend from an individual row of subpixels to the transition region TA, straddle the electrostatic discharge region EPA, and extend to a portion of the notch region NA located on the side of the electrostatic discharge region EPA away from the transition region TA. Optionally, individual scan signal lines from an individual row of subpixels may intersect with individual data lines located in the transition region TA. Portions of the individual scan signal lines that intersect with the individual data lines extend along a first direction DR1. Portions of the individual data lines that intersect with the individual scan signal lines extend along a second direction DR2. Optionally, the first direction DR1 and the second direction DR2 may be substantially perpendicular to each other.

[0111] In some embodiments, as shown in FIG. 29, the portion of each scan signal line that straddles the electrostatic discharge area EPA is located between two adjacent rows of electrostatic discharge units in the electrostatic discharge area EPA.

[0112] In some embodiments, the portions of the individual scan signal lines that intersect with the individual data lines are in the first signal line layer, and in some embodiments, the portions of the individual data lines that intersect with the individual scan signal lines are in the second signal line layer.

[0113] In another aspect, the present invention provides a display device including an array substrate described herein or fabricated by the method described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital albums, GPS, etc. Optionally, the display device may be an organic light-emitting diode display device. Optionally, the display device may be a micro light-emitting diode display device. Optionally, the display device may be a mini light-emitting diode display device.

[0114] The foregoing description of embodiments of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the above description should be considered illustrative and not limiting, and many modifications and variations will be apparent to those skilled in the art. Many modifications and variations will be apparent to those skilled in the art. These embodiments have been chosen and described in order to explain the principles of the present invention and its practical application of its best mode, thereby enabling those skilled in the art to appreciate that the present invention is adaptable to various embodiments and variations of the particular applications or embodiments contemplated. The scope of the present invention is intended to be defined by the claims appended to this disclosure and their equivalents, and all terms are to be interpreted in the broadest reasonable manner unless otherwise indicated. Accordingly, the use of terms such as "the present invention," "the disclosure," or similar terms does not necessarily limit the claims to any particular embodiment, and reference to exemplary embodiments of the present invention does not suggest, and no limitation to, the present invention should be inferred. The present invention is limited only by the spirit and scope of the appended claims. Furthermore, these claims may use terms such as "first," "second," etc., followed by a noun or element. Unless a specific quantity is indicated, such terms should be understood as specialized terms, and the quantity of the modified element should not be construed as being limited by the specialized terms. Not all of the effects and advantages described apply to all embodiments of the present invention. Those skilled in the art will understand that modifications can be made to the described embodiments without departing from the scope of the present invention, as defined by the following claims. Furthermore, none of the elements and components of the present disclosure, whether or not explicitly recited in the following claims, are intended to be dedicated to the public.

Claims

1. An array substrate including a display area and a notch area, The display area includes a first display sub-area and a second display sub-area separated from each other by the notch area. The aforementioned notch region includes an electrostatic discharge region, The array substrate includes a plurality of data lines and a plurality of scan signal lines, The plurality of data lines extend at least partially into the electrostatic discharge region, The aforementioned multiple scanning signal lines span across the electrostatic discharge region. At least a portion of the electrostatic discharge region includes a plurality of alternately arranged first sub-regions and a plurality of second sub-regions, The plurality of scan signal lines are present in the plurality of first sub-regions and are not present in the plurality of second sub-regions. The aforementioned plurality of data lines are present in the plurality of second sub-regions and are not present in the plurality of first sub-regions. Array substrate.

2. A scanning signal line extending from the first display sub-region and spanning a portion adjacent to the first display sub-region of the electrostatic discharge region, and a scanning signal line extending from the second display sub-region and spanning a portion adjacent to the second display sub-region of the electrostatic discharge region, are connected to each other. The array substrate according to claim 1.

3. Each of the plurality of first sub-regions includes some of the plurality of scan signal lines, Each of the plurality of second sub-regions includes at least one data line. The array substrate according to claim 1.

4. The electrostatic discharge region includes multiple electrostatic discharge units for protecting multiple data lines. The array substrate according to claim 1.

5. The electrostatic discharge region further includes a plurality of dummy electrostatic discharge units, The plurality of electrostatic discharge units are located in the plurality of second sub-regions and are not located in the plurality of first sub-regions. The plurality of dummy electrostatic discharge units are located in the plurality of first sub-regions and are not located in the plurality of second sub-regions. The array substrate according to claim 4.

6. The orthographic projection onto the base substrate of individual scan signal lines located in individual first sub-regions of the plurality of first sub-regions of the plurality of scan signal lines partially overlaps with the orthographic projection onto the base substrate of some of the dummy electrostatic discharge units of the plurality of dummy electrostatic discharge units. The array substrate according to claim 5.

7. The notch region further includes a transition region between the electrostatic discharge region and the first display sub-region, or between the electrostatic discharge region and the second display sub-region. In the aforementioned transition region, there is no electrostatic discharge unit. In the transition region, the plurality of data lines and the plurality of scan signal lines intersect each other. The portions of the plurality of scan signal lines that intersect with the plurality of data lines each extend along the first direction, The portions of the aforementioned plurality of data lines that intersect with the aforementioned plurality of scan signal lines each extend along a second direction. The first direction and the second direction are substantially perpendicular to each other. The array substrate according to claim 1.

8. Multiple scan signal lines from subpixels in the same row intersect with the same number of data lines. The array substrate according to claim 7.

9. The portion of the plurality of data lines that intersects with the plurality of scan signal lines is located in the first signal line layer. The portion of the plurality of scan signal lines that intersects with the plurality of data lines is located in the second signal line layer, which is located on the side of the first signal line layer away from the base substrate. The array substrate according to claim 7.

10. Each of the plurality of scan signal lines that spans the transition region and the electrostatic discharge region includes a first portion, a second portion, and a third portion. The first portion intersects with one or more data lines located in the transition region, The second portion spans the electrostatic discharge region, The third portion is at least partially located in a part of the notch region that is located away from the transition region of the electrostatic discharge region, The second part connects the first part and the third part. The array substrate according to any one of claims 1 to 9.

11. The first part is located in a different layer from the second part. The array substrate according to claim 10.

12. The first portion is located in the first conductive layer, The second portion is located in the first signal line layer, which is situated on the side of the first conductive layer away from the base substrate. The array substrate according to claim 10.

13. Of the plurality of scan signal lines, each scan signal line that spans the transition region and the electrostatic discharge region further includes a fourth portion that is at least partially located in the display region. The first part connects the fourth part to the second part, The first portion is located in the first conductive layer, The fourth portion is located in the first signal line layer, which is situated on the side of the first conductive layer away from the base substrate. The array substrate according to claim 10.

14. The second and fourth portions are located on the same layer as the plurality of data lines. The array substrate according to claim 13.

15. Of the plurality of scanning signal lines, the second and third portions of each scanning signal line that spans the transition region and the electrostatic discharge region are located in different layers. The array substrate according to claim 10.

16. Of the plurality of scan signal lines, the second portion of several scan signal lines located in the same first sub-region of the plurality of first sub-regions is connected to the third portion of the several scan signal lines. The second portion of the aforementioned scan signal lines is located in the first conductive layer, The third portion of the aforementioned scan signal lines is alternately located on the first conductive layer and on the second conductive layer located away from the base substrate of the first conductive layer. The array substrate according to claim 10.

17. Of the plurality of scan signal lines, the second portion of several scan signal lines located in the same first sub-region of the plurality of first sub-regions is connected to the first portion of the several scan signal lines. The first portion of the aforementioned scan signal lines is alternately located on the first conductive layer and on the second signal line layer located away from the base substrate of the first conductive layer. The array substrate according to claim 10.

18. Each individual second portion in the second signal line layer is connected to each individual first portion in the second signal line layer. Each individual second portion in the first signal line layer is connected to each individual first portion in the first conductive layer. The array substrate according to claim 17.

19. Of the plurality of scan signal lines, the second portion of several scan signal lines located in the same first sub-region of the plurality of first sub-regions is connected to the third portion of the several scan signal lines. The third portion of some of the scan signal lines is alternately located on the first conductive layer and on the second conductive layer located away from the base substrate of the first conductive layer. Each individual second portion in the second signal line layer is connected to each individual third portion in the first conductive layer. Each individual second portion in the first signal line layer is connected to each individual third portion in the second conductive layer. The array substrate according to claim 18.

20. The array substrate is as described in any one of claims 1 to 9, and includes one or more integrated circuits connected to the array substrate. Display device.

Images