Backside power island for backside power applications

Abstract

A semiconductor structure is provided that includes a plurality of backside power islands, the backside power islands being present in a first device track and a second device track, the backside power islands located in the first device track and the second device track being separated by a first cutout region, and the backside power island located in the first device track being separated from the backside power island located in the second device track by a second cutout region, the second cutout region being oriented perpendicular to the first cutout region.

Description

[Background technology]

[0001] The present invention relates to semiconductor technology, and more particularly to semiconductor structures that include multiple backside power islands.

[0002] When forming a structure including multiple complementary metal-oxide semiconductor (CMOS) devices, such as an integrated circuit, standard cells can be used as a base unit for designing and manufacturing the integrated circuit. Standard cells can be used to form one or more functional circuits, and each standard cell can have the same footprint. Using standard cells when designing complex circuits and components reduces design and manufacturing costs.

[0003] In use, each standard cell of a semiconductor structure requires a power input (Vdd) and a ground (Vss) connection. To power its various components, each standard cell is generally coupled to a backside power rail that is electrically connected to the active layer of the standard cell and provides the power supply (Vdd). In some cases, multiple backside power rails may be provided for each standard cell to provide the power supply (Vdd) and ground (Vss), respectively.

[0004] In cells that include a backside contact structure that provides a direct connection of the backside power rail to one of the transistor's source / drain regions, the backside first metal level (M1) neighboring spacing is very small. Even with this very small neighboring spacing, the backside overlay requirement is very high (i.e., standard deviation is less than 10 nm). This problem becomes even more pronounced for mixed cell heights (i.e., 6T and 9T cells). Summary of the Invention

[0005] A semiconductor structure is provided that includes multiple backside power islands rather than a backside power rail. In one embodiment, the semiconductor structure includes backside power islands located in both a first device track and a second device track, wherein the backside power islands located in the first device track and the second device track are separated by a first cutout region, the backside power island located in the first device track is separated from the backside power island located in the second device track by a second cutout region, and further, the second cutout region is oriented perpendicular to the first cutout region. The inclusion of backside power islands rather than a backside power rail enables a structure with mixed cell height and a backside first metal level with small side-by-side space.

[0006] In some embodiments of the present invention, each of the first device track and the second device track comprises a p-type field effect transistor and an n-type field effect transistor arranged in rows and columns.

[0007] In some embodiments of the present invention, the first cut-out region is located between each pair of n-type and p-type field effect transistors present in the first device track and the second device track.

[0008] In some embodiments of the present invention, the backside power island of the first device track has a first width and the backside power island of the second device track has a second width, the first width being smaller than the second width.

[0009] In some embodiments of the present invention, the first device tracks each have a first active area having a first width, and the second device tracks each have a second active area having a second width greater than the first width.

[0010] In some embodiments of the present invention, both the first cut-out region and the second cut-out region are filled with a layer of backside interconnect dielectric material.

[0011] In some embodiments of the present invention, the backside interconnect dielectric material layer in both the first cut-out region and the second cut-out region is in direct physical contact with a sidewall of at least one of the backside power islands.

[0012] In some embodiments of the present invention, the backside interconnect dielectric material layer contacts the surface of the backside power distribution network.

[0013] In some embodiments of the present invention, the backside power distribution network is connected to at least one of the backside power islands located on both the first device track and the second device track by a metal via contact structure.

[0014] In some embodiments of the present invention, the metal via contact structure includes a diffusion barrier liner located along the sidewalls and bottom wall of the conductive metal or conductive metal alloy.

[0015] In some embodiments of the present invention, a first surface of each of the backside power islands contacts a diffusion barrier layer, a second surface of each of the backside power islands opposite to the first surface contacts a hard mask layer, and the first surface of each of the backside power islands is located farther from the backside power distribution grid than the second surface of each of the backside power islands.

[0016] In some embodiments of the present invention, at least one of the backside power islands is electrically connected to a source / drain region of a p-type field effect transistor or an n-type field effect transistor in at least one of the first device track or the second device track by a backside source / drain contact structure.

[0017] In some embodiments of the present invention, at least one source / drain region of either a p-type field effect transistor or an n-type field effect transistor in at least one of the first device track or the second device track is electrically connected to a front back-end (BEOL) structure by a front source / drain contact structure.

[0018] In some embodiments of the present invention, the structure further comprises a carrier wafer positioned on a surface of said front side BEOL structure.

[0019] In some embodiments of the present invention, the source / drain regions electrically connected to the frontside BEOL structure are located on a surface of a lower dielectric isolation layer.

[0020] In some embodiments of the present invention, the p-type field effect transistor and the n-type field effect transistor are nanosheet comprising transistors comprising a gate structure wrapped around at least one nanosheet of semiconducting channel material.

[0021] In some embodiments of the invention, a diffusion breakpoint structure separates the first device track from the second device track, and in such embodiments, the second cut region is located below the diffusion breakpoint structure.

[0022] In some embodiments of the present invention, the diffusion break structure is comprised of a dielectric material, and the diffusion break structure extends into a backside interlayer dielectric material layer.

[0023] In some embodiments of the present invention, the backside interlayer dielectric material layer overlies each of the backside power islands.

[0024] In another embodiment of the present invention, a semiconductor structure comprises a first device track located laterally adjacent to a second device track, wherein each of the first device track and the second device track has p-type field effect transistors and n-type field effect transistors arranged in rows and columns; a diffusion breakpoint structure separating the first device track from the second device track; and backside power islands located in both the first device track and the second device track, wherein the backside power islands located in the first device track and the backside power islands located in the second device track are separated by a first cutout region, and the backside power islands located in the first device track are separated from the backside power islands located in the second device track by a second cutout region, and further wherein the second cutout region is located below the diffusion breakpoint structure and oriented perpendicular to the first cutout region.

[0025] In this alternative embodiment of the present invention, the first cut-out region may be located between each pair of n-type and p-type field effect transistors present in the first device track and the second device track.

[0026] In this alternative embodiment of the present invention, the backside power island of the first device track has a first width and the backside power island of the second device track has a second width, the first width being smaller than the second width.

[0027] In this alternative embodiment of the present invention, the first device tracks each have a first active area having a first width, and the second device tracks each have a second active area having a second width greater than the first width.

[0028] In this alternative embodiment of the present invention, both the first cut-out region and the second cut-out region are filled with a layer of backside interconnect dielectric material.

[0029] In this alternative embodiment of the present invention, the backside interconnect dielectric material layer in both the first cut-out region and the second cut-out region is in direct physical contact with a sidewall of at least one of the backside power islands. [Brief explanation of the drawings]

[0030] [Figure 1] FIG. 1 is a top view showing a device layout that can be used in the present invention, the device layout including multiple gate structures located on different device tracks, the device layout shown including cuts Y1-Y1, Y2-Y2, and XX.

[0031] [Figure 2] FIG. 2A is a cross-sectional view through cut Y1-Y1, FIG. 2B is a cross-sectional view through cut Y2-Y2, and FIG. 2C is a cross-sectional view through cut XX of an exemplary semiconductor structure that can be used in the present invention, the exemplary structure including a substrate, a placeholder material layer overlying the substrate, and a material stack of alternating layers of sacrificial semiconductor material and semiconductor channel material overlying the placeholder material layer.

[0032] [Figure 3-1] 3A and 3B are cross-sectional views of the exemplary semiconductor structure shown in FIGS. 2A and 2B, respectively, after the material stack and placeholder material layer have been patterned into individual patterned material stacks, each of which includes remaining portions of the material stack and remaining portions of the placeholder material layer. [Figure 3-2] FIG. 3C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 2C after the material stack and placeholder material layer have been patterned into individual patterned material stacks, each of which includes remaining portions of the material stack and remaining portions of the placeholder material layer.

[0033] [Figure 4] 2 is a top view of the device layout shown in FIG. 1, illustrating the area where the backside contact (BC) will later be formed.

[0034] [Figure 5-1] 5A and 5B are cross-sectional views of the exemplary semiconductor structures shown in FIGS. 3A and 3B, respectively, after nanosheet device processing including the formation of a sacrificial gate structure, a gate spacer, a lower dielectric isolation layer, a nanosheet stack, a back contact placeholder material, and source / drain regions, each nanosheet stack comprising alternating sacrificial semiconductor material nanosheets and semiconductor channel material nanosheets. [Figure 5-2] Figure 5C is a cross-sectional view of the exemplary semiconductor structure shown in Figure 3C after nanosheet device processing including the formation of a sacrificial gate structure, a gate spacer, a lower dielectric isolation layer, a nanosheet stack, a back contact placeholder material, and source / drain regions, each nanosheet stack comprising alternating sacrificial semiconductor material nanosheets and semiconductor channel material nanosheets.

[0035] [Figure 6-1] 6A and 6B are cross-sectional views of the exemplary semiconductor structure shown in FIGS. 5A and 5B, respectively, after forming and planarizing a frontside interlayer dielectric (ILD) material layer. [Figure 6-2] FIG. 6C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 5C after forming a frontside inter-layer dielectric (ILD) material layer and planarizing.

[0036] [Figure 7-1] 7A and 7B are cross-sectional views of the exemplary semiconductor structures shown in FIGS. 6A and 6B, respectively, after forming self-aligned diffusion break areas. [Figure 7-2] FIG. 7C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 6C after forming a self-aligned diffusion break area.

[0037] [Figure 8-1] 8A and 8B are cross-sectional views of the exemplary semiconductor structure shown in FIGS. 7A and 7B, respectively, after forming a dielectric material in the self-aligned diffusion break area to provide a diffusion break structure. [Figure 8-2] FIG. 8C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 7C after forming a dielectric material in the self-aligned diffusion break area to provide a diffusion break structure.

[0038] [Figure 9-1] Figures 9A and 9B are cross-sectional views of the exemplary semiconductor structures shown in Figures 8A and 8B, respectively, after further nanosheet device processing including removing the sacrificial gate structure, suspending the semiconductor channel material nanosheets of each nanosheet stack, forming gate structures that wrap around the suspended semiconductor channel material nanosheets of each nanosheet stack, forming additional front-side ILD material, front-side source / drain contact structures, front-side back-end (BEOL) structures, and a carrier wafer. [Figure 9-2] Figure 9C is a cross-sectional view of the exemplary semiconductor structure shown in Figure 8C after further nanosheet device processing, including removing the sacrificial gate structure, suspending the semiconductor channel material nanosheets of each nanosheet stack, forming a gate structure that wraps around the suspended semiconductor channel material nanosheets of each nanosheet stack, forming additional front-side ILD material, front-side source / drain contact structures, front-side back-end (BEOL) structures, and a carrier wafer.

[0039] [Figure 10-1] 10A and 10B are cross-sectional views of the exemplary semiconductor structures shown in FIGS. 9A and 9B, respectively, after removing the first semiconductor material layer of the substrate. [Figure 10-2] FIG. 10C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 9C after removing the first semiconductor material layer of the substrate.

[0040] [Figure 11-1] 11A and 11B are cross-sectional views of the exemplary semiconductor structure shown in FIGS. 10A and 10B, respectively, after removing the substrate etch stop layer and the second semiconductor layer. [Figure 11-2] FIG. 11C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 10C after removing the substrate etch stop layer and the second semiconductor layer.

[0041] [Figure 12-1] 12A and 12B are cross-sectional views of the exemplary semiconductor structures shown in FIGS. 11A and 11B, respectively, after forming a first backside ILD material layer. [Figure 12-2] FIG. 12C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 11C after forming a first backside ILD material layer.

[0042] [Figure 13-1] 13A and 13B are cross-sectional views of the exemplary semiconductor structure shown in FIGS. 12A and 12B, respectively, after the back contact placeholder material has been removed to physically expose portions of the surface of the source / drain regions and a back source / drain contact structure has been formed that contacts the physically exposed surfaces of the source / drain regions. [Figure 13-2] Figure 13C is a cross-sectional view of the exemplary semiconductor structure shown in Figure 12C after removing the back contact placeholder material to physically expose the surfaces of portions of the source / drain regions and forming back source / drain contact structures that contact the physically exposed surfaces of the source / drain regions.

[0043] [Figure 14-1] 14A and 14B are cross-sectional views of the exemplary semiconductor structure shown in FIGS. 13A and 13B, respectively, after forming a diffusion barrier layer and a backside power rail conductive material layer. [Figure 14-2] FIG. 14C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 13C after forming a diffusion barrier layer and a backside power rail conductive material layer.

[0044] [Figure 15-1] 15A and 15B are cross-sectional views of the exemplary semiconductor structure shown in FIGS. 14A and 14B, respectively, after forming a hard mask layer over the backside power rail conductive material layer and performing a first backside metal cut (i.e., X-direction cut) into the hard mask layer. [Figure 15-2] FIG. 15C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 14C after forming a hard mask layer over the backside power rail conductive material layer and performing a first backside metal cut (i.e., X-direction cut) into the hard mask layer.

[0045] [Figure 16-1] 16A and 16B are cross-sectional views of the exemplary semiconductor structure shown in FIGS. 15A and 15B, respectively, after forming an organic planarization layer and performing a second backside metal cut (i.e., a cut in the Y direction) into the organic planarization layer and hard mask layer. [Figure 16-2] FIG. 16C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 15C after forming an organic planarization layer and performing a second backside metal cut (i.e., a cut in the Y direction) into the organic planarization layer and the hard mask layer.

[0046] [Figure 17-1] 17A and 17B are cross-sectional views of the exemplary semiconductor structure shown in FIGS. 16A and 16B, respectively, after removing the organic planarization layer and patterning the conductive material layer of the backside power rail using the patterned hard mask layer as an etch mask. [Figure 17-2] FIG. 17C illustrates a cross-sectional view of the exemplary semiconductor structure shown in FIG. 16C after removing the organic planarization layer and patterning the conductive material layer of the backside power rail using the patterned hard mask layer as an etch mask.

[0047] [Figure 18-1]18A and 18B are cross-sectional views of the exemplary semiconductor structures shown in FIGS. 17A and 17B, respectively, after forming a second backside ILD material layer. [Figure 18-2] FIG. 18C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 17C after forming a second backside ILD material layer.

[0048] [Figure 19-1] 19A and 19B are cross-sectional views of the exemplary semiconductor structure shown in FIGS. 18A and 18B, respectively, after forming metal via contact structures and backside power distribution networks. [Figure 19-2] FIG. 19C is a cross-sectional view of the exemplary semiconductor structure shown in FIG. 18C after forming metal via contact structures and backside power distribution networks.

[0049] [Figure 20] FIG. 1 is a schematic diagram showing a prior art backside power rail.

[0050] [Figure 21] FIG. 1 is a schematic diagram illustrating a backside power island according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0051] The present invention will now be described in more detail by reference to the following discussion and the drawings that accompany the present invention. It should be noted that the drawings of the present invention are provided for illustrative purposes only and therefore the drawings are not drawn to scale. It should also be noted that like and corresponding elements are referred to by like reference numerals.

[0052] In the following description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, to provide an understanding of various embodiments of the present invention. However, those skilled in the art will understand that various embodiments of the present invention may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail to avoid obscuring the present invention.

[0053] When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it will be understood that the element can be directly on the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "beneath" or "under" another element, it will be understood that the element can be directly below or directly underneath the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly beneath" or "directly under" another element, there are no intervening elements present.

[0054] As mentioned above, a semiconductor structure is provided that includes a plurality of backside power islands rather than a backside power rail. In an embodiment of the present invention, the backside power islands are cut-out sections of the conductive material layer of the backside power rail. The backside power islands are present in a first device track (i.e., a first device region) and a second device track (i.e., a second device region). The backside power islands located in the first device track and the backside power islands located in the second device track are separated by a first cut-out region; the first cut-out region is typically located between each pair of n-type field effect transistors and p-type field effect transistors present in the first device track and the second device track. The backside power islands located in the first device track are separated from the backside power islands located in the second device track by a second cut-out region. In an embodiment of the present invention, the second cut-out region is oriented perpendicular to the first cut-out region. The second cut-out region is located below a diffusion breakpoint structure (i.e., a dielectric material pillar) that separates the first device track from the second device track. The second cut region runs along the entire length of the diffusion breakpoint structure. The inclusion of a backside power island rather than a backside power rail allows for a structure with mixed cell height and a backside first metal level with small adjacent spacing.

[0055] Referring first to FIG. 1, a device layout that can be used in the present invention is shown. The device layout shown in FIG. 1 includes multiple gate structures GS located in different device tracks (i.e., a first device track DT1 and a second device track DT2). In an embodiment of the present invention, DT1 has a first active area (AA1), and DT2 has a second active area (AA2), where AA2 has a larger (i.e., wider) width than AA1. The different device tracks, i.e., DT1 and DT2, are located laterally adjacent to each other and each include a p-type field effect transistor (i.e., PFET) and an n-type field effect transistor (NFET) arranged in rows and columns. The NFETs and PFETs are typically, but not always, nanosheet transistors that include a gate structure wrapped around at least one nanosheet of semiconductor channel material (preferably, the gate structure wraps around multiple vertical stacks, spacing the nanosheets of semiconductor channel material apart). In some embodiments, and as shown in FIG. 1 , DT1 is a 6T design including a column of PFET, NFET, NFET, PFET, PFET, and NFET written from the bottom of the page to the top, while DT2 is a 9T design including a column of NFET, PFET, PFET, and NFET written from the bottom of the page to the top. In embodiments of the invention, the XX cut is along the row including the bottom PFET of DT1 and the bottom NFET of DT2, the Y1-Y1 cut is located between the gate structures GS located in DT1 along the length of the gate structures GS, and the Y2-Y2 cut is located between the gate structures GS located in DT2 along the length of the gate structures GS. Note that the device layout is not limited to device layouts including 6T and 9T devices.

[0056] 2A, 2B, and 2C, there are shown exemplary structures that may be used in the present invention, taken through cuts Y1-Y1, Y2-Y2, and XX, respectively, of Figure 1. The exemplary structures include substrates 10, 12, and 14, placeholder material layers 16L located on substrates 10, 12, and 14, and a material stack of alternating layers of sacrificial semiconductor material (i.e., sacrificial semiconductor material layer 18L) and semiconductor channel material (i.e., semiconductor material layer 20L) located on placeholder material layer 16L.

[0057] 2A, 2B, and 2C, the substrate can include a first semiconductor material layer 10, an etch stop layer 12, and a second semiconductor material layer 14. In other embodiments, the etch stop layer 12 and the second semiconductor material layer 14 can be omitted, and in such embodiments, the substrate is comprised of the first semiconductor material layer 10. In still other embodiments, the etch stop layer 12 can be omitted, and in such embodiments, the substrate is comprised of the first semiconductor material layer 10 and the second semiconductor material layer 14 (in such embodiments, the semiconductor materials providing the first and second semiconductor material layers 10, 14 are compositionally different from one another).

[0058] The first semiconductor material layer 10 is composed of a first semiconductor material. The second semiconductor material layer 14 is composed of a second semiconductor material. The term "semiconductor material" is used throughout this application to refer to a material having semiconducting properties. Examples of semiconductor materials that can be used in the present invention to provide the first and second semiconductor materials include, but are not limited to, silicon (Si), silicon germanium (SiGe) alloys, silicon germanium carbide (SiGeC) alloys, germanium (Ge), III-V compound semiconductors, or II-VI compound semiconductors. The second semiconductor material providing the second semiconductor material layer 14 can be compositionally the same as or different from the first semiconductor material providing the first semiconductor material layer 10. In some embodiments of the present invention, the etch stop layer 12 can be composed of a dielectric material such as, for example, silicon dioxide and / or boron nitride. In other embodiments of the present invention, etch stop layer 12 is composed of a third semiconductor material that is compositionally different from the first semiconductor material that provides first semiconductor material layer 10 and the second semiconductor material that provides second semiconductor material layer 14. In one example, first semiconductor material layer 10 is composed of silicon, etch stop layer 12 is composed of silicon dioxide, and second semiconductor material layer 14 is composed of silicon. In another example, first semiconductor material layer 10 is composed of silicon, etch stop layer 12 is composed of silicon germanium, and second semiconductor material layer 14 is composed of silicon.

[0059] The substrate including the first semiconductor material layer 10, the etch stop layer 12, and the second semiconductor material layer 14 can be formed using techniques well known to those skilled in the art. For example, the substrate including the first semiconductor material layer 10, the etch stop layer 12, and the second semiconductor material layer 14 can be formed by an oxygen ion implantation separation process or by wafer bonding.

[0060] Placeholder material layer 16L is composed of a fourth semiconductor material that is compositionally different from the semiconductor materials that provide the top semiconductor material portion of the substrate, sacrificial semiconductor material layer 18L, and semiconductor channel material layer 20L. In one example, placeholder material layer 16L is composed of a silicon germanium alloy having a germanium content of 40 atomic percent to 75 atomic percent. Typically, placeholder material layer 16L has a thickness of 5 nm to 20 nm, although other thicknesses are contemplated and can be used for placeholder material layer 16L.

[0061] As mentioned above, the material stack includes alternating sacrificial semiconductor material layers 18L and semiconductor channel material layers 20L. In some embodiments, and as shown in FIGS. 2A, 2B, and 2C, there are an equal number of sacrificial semiconductor material layers 18L and semiconductor channel material layers 20L. That is, the material stack can include “n” semiconductor channel material layers 20L and “n” sacrificial semiconductor material layers 18L, where n is an integer starting from 1. As an example, the material stack includes three sacrificial semiconductor material layers 18L and three semiconductor channel material layers 20L. Each sacrificial semiconductor material layer 18L is composed of a fifth semiconductor material, while each semiconductor channel material layer 20L is composed of a sixth semiconductor material that is compositionally different from the fifth semiconductor material; note that both the fifth and sixth semiconductor materials are compositionally different from the fourth semiconductor material.

[0062] In some embodiments, the sixth semiconductor material providing each semiconductor channel material layer 20L can provide high channel mobility for an n-type field effect transistor (FET) device. In other embodiments, the sixth semiconductor material providing each semiconductor channel material layer 20L can provide high channel mobility for a p-type FET device. The fifth semiconductor material providing each sacrificial semiconductor material layer 18L and the sixth semiconductor material providing each semiconductor channel material layer 20L can include one of the semiconductor materials mentioned above. In one example, each sacrificial semiconductor material layer 18L is composed of a silicon-germanium alloy having a germanium content of 20 atomic percent to 40 atomic percent (note that each sacrificial semiconductor material layer 18L is compositionally different from the sacrificial placeholder material layer 16L mentioned above), and the sixth semiconductor material providing each semiconductor channel material layer 20L is composed of silicon. Other combinations of semiconductor materials are possible, so long as the fifth semiconductor material providing each sacrificial semiconductor material layer 18L is compositionally different from the sixth semiconductor material providing each semiconductor channel material layer 20L, and the semiconductor materials providing the sacrificial semiconductor material layer 18L and the semiconductor channel material layer 20L are compositionally different from the semiconductor material providing the sacrificial placeholder material layer 16L.

[0063] Each sacrificial semiconductor material layer 18L can have a first thickness, and each semiconductor channel material layer 20L can have a second thickness. In embodiments of the present invention, the first thickness can be equal to, greater than, or less than the second thickness.

[0064] The exemplary structures shown in FIGS. 2A, 2B, and 2C can be formed by first depositing a sacrificial placeholder material layer 16L on a substrate (in the illustrated embodiment, the sacrificial placeholder material layer 16L is formed on the second semiconductor material layer 14 of the substrate), and then secondly depositing a material stack on the sacrificial placeholder material layer 16L. The second deposition includes forming alternating blanket layers of the fifth and sixth semiconductor materials mentioned above. The first and second depositions can include one of chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or epitaxial growth. The terms “epitaxial growth” or “epitaxially grown” refer to the growth of a semiconductor material on the growth surface of another semiconductor material, where the grown semiconductor material has the same crystalline properties as the growth surface of the other semiconductor material. In epitaxial deposition processes, chemical reactants provided by source gases are controlled and system parameters are set so that the depositing atoms arrive at the growth surface of another semiconductor material with enough energy to move about the growth surface and orient themselves in the crystalline arrangement of the atoms of the growth surface. Examples of various epitaxial growth process equipment that can be used in the present invention include, for example, rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). Epitaxial deposition temperatures typically range from 550°C to 900°C.Typically, higher temperatures result in faster deposition, but faster deposition can result in crystalline defects and film cracking.

[0065] 3A, 3B, and 3C, there are shown views of the exemplary semiconductor structure shown in FIGS. 2A, 2B, and 2C, respectively, after the material stack and placeholder material layer 16L have been patterned into individual patterned material stacks PS, with each individual patterned material stack PS including a remaining portion of the material stack and a remaining portion of the placeholder material layer 16L. That is, each individual patterned material stack PS includes a remaining portion of the placeholder material layer 16L (hereinafter, patterned placeholder material layer 16), a remaining portion of a respective sacrificial semiconductor material layer 18L (hereinafter, patterned sacrificial semiconductor material layer 18), and a remaining portion of a respective semiconductor channel material layer (hereinafter, patterned semiconductor channel material layer 20). As shown, each patterned material stack PS formed in FIG. 3A has a first width, while each patterned material stack PS formed in FIG. 3B has a second width, where the second width is greater than the first width.

[0066] Patterning the material stack includes lithography and etching. In some embodiments, a hard mask may be formed on top of the material stack, and the hard mask may be patterned by lithography and etching to form a patterned hard mask on the material stack. The patterned hard mask may be designed to have different widths depending on the area where the patterned hard mask is formed. The pattern provided by the patterned hard mask may be transferred into the material stack by etching, and the patterned hard mask may then be removed from each individual patterned material stack PS.

[0067] As further shown in FIGS. 3A-3B, shallow trench isolation structures 22 can be formed in the substrate; in the illustrated embodiment, shallow trench isolation structures 22 are formed in second semiconductor material layer 14. Shallow trench isolation structures 22 can be composed of any trench dielectric material, such as, for example, silicon oxide. In some embodiments, a trench dielectric liner, composed of, for example, SiN, can be present along the sidewalls and bottom wall of the trench dielectric material. Shallow trench isolation structures 22 can have a top surface that is coplanar with the top surface of the unetched portion of the substrate; in the illustrated embodiment, shallow trench isolation structures 22 can have a top surface that is coplanar with the top surface of the unetched portion of second semiconductor material layer 14. The shallow trench isolation structure 22 can be formed by first forming (by lithography and etching) a trench in the upper portion of the substrate (in the embodiment shown, the trench is formed in the upper portion of the second semiconductor material layer 14), depositing an optional trench dielectric liner material and trench dielectric material in the trench, and then performing an etch-back process.

[0068] 4, there is shown the device layout of FIG. 1 showing the areas where the back contacts (BC) will later be formed. The BCs are formed in areas that will contain the back contact placeholder material 34 shown in FIGS. 5A, 5B, and 5C below.

[0069] 5A, 5B, and 5C, there are shown views of the exemplary semiconductor structure shown in FIGS. 3A, 3B, and 3C, respectively, after nanosheet device processing, including the formation of a sacrificial gate structure 24, gate spacers 28, a lower dielectric isolation layer 30, a nanosheet stack, a backside contact placeholder material 34, and source / drain regions 36. Each nanosheet stack includes alternating sacrificial semiconductor material nanosheets 18NS and semiconductor channel material nanosheets 20NS. Also shown in FIGS. 5A, 5B, and 5C are a sacrificial gate cap 26 and an inner spacer 32, both of which are formed during nanosheet device processing.

[0070] Nanosheet device processing first includes forming a sacrificial gate material layer (not specifically shown) and a sacrificial gate cap material layer (not specifically shown). In some embodiments, the sacrificial gate dielectric material layer (also not specifically shown) may be formed before forming the sacrificial gate dielectric material. The optional sacrificial gate dielectric material layer can be composed of a dielectric material such as silicon dioxide. The sacrificial gate material layer includes a sacrificial gate material such as, but not limited to, polysilicon, amorphous silicon, amorphous silicon germanium, or amorphous germanium. The sacrificial gate cap is composed of a hard mask material such as silicon nitride. The optional sacrificial gate dielectric material layer, sacrificial gate material layer, and sacrificial gate cap material layer can be formed using a deposition process such as CVD, PECVD, physical vapor deposition (PVD), or atomic layer deposition (ALD). In embodiments of the present invention, the optional sacrificial gate dielectric material and sacrificial gate material layer are deposited before depositing the sacrificial gate cap material layer. In some embodiments, the formation of the sacrificial gate cap material layer may be omitted.

[0071] The optional sacrificial gate dielectric material layer, sacrificial gate material layer, and sacrificial gate cap material layer are then patterned by lithography and etching to provide sacrificial gate structures 24 capped by sacrificial gate caps 26. Each sacrificial gate structure 24 includes at least an unetched portion of the sacrificial gate material layer. Each sacrificial gate structure 24 may also include an unetched portion of the sacrificial gate dielectric material layer. Each sacrificial gate cap 26 includes an unetched portion of the sacrificial gate cap material layer.

[0072] After forming the sacrificial gate structures 24 capped with the sacrificial gate caps 26, the patterned placeholder material layers 16 are removed to form gaps beneath each of the patterned material stacks PS. The patterned material stacks PS are non-floating structures fixed in place by at least the sacrificial gate structures 24. Removal of the patterned placeholder material layers 16 includes an etching process that is selective in removing the fourth semiconductor material that provided the placeholder material layers 16L.

[0073] After removing the patterned placeholder material layer 16 from each patterned material stack, nanosheet device processing continues by forming gate spacers 28 along the sidewalls of each sacrificial gate-capped sacrificial gate structure (this structure is a combination of the sacrificial gate structure 24 and the sacrificial gate cap 26). During the formation of the gate spacers 28, gaps formed under each patterned material stack PS are filled to form a lower dielectric isolation layer 30. As such, the gate spacers 28 and the lower dielectric isolation layer 30 are composed of the same dielectric spacer material and have a monolithic structure. Exemplary dielectric spacer materials that can be used in providing the gate spacers 28 and the lower dielectric isolation layer 30 include, but are not limited to, silicon dioxide, SiN, SiBCN, SiOCN, or SiOC. The gate spacers 28 and the lower dielectric isolation layer 30 can be formed by a deposition process, such as CVD, PECVD, or ALD.

[0074] After forming the gate spacers 28 and the lower dielectric isolation layer 30, each of the patterned material stacks PS is converted into a nanosheet stack. This conversion involves etching using the respective gate spacers 28 and the sacrificial gate-capped sacrificial gate structure as an etching mask. The etching can include reactive ion etching. The term "nanosheet stack" refers to the various material layers present in the stack being nanosheets. In the nanosheet stack, each remaining patterned sacrificial semiconductor material layer 18 may be referred to as a sacrificial semiconductor material nanosheet 18NS, and each remaining patterned semiconductor channel material layer 20 may be referred to as a semiconductor channel material nanosheet 20NS.

[0075] Next, each sacrificial semiconductor material nanosheet 18NS present in the nanosheet stack is recessed using a recess etching process, which is a lateral etching process that is selective to remove a portion of each sacrificial semiconductor material nanosheet 18NS. Note that the recessed sacrificial semiconductor material nanosheet 18NS has a width that is smaller than the width of each of the semiconductor channel material nanosheets 20NS present in the nanosheet stack.

[0076] Next, an inner spacer 32 is formed laterally adjacent to each recessed semiconductor material nanosheet 18NS present in each of the nanosheet stacks. Each inner spacer 32 is composed of one of the dielectric spacer materials mentioned above for forming the gate spacers 28 and the lower dielectric isolation layers 30. The dielectric spacer material providing each inner spacer 32 may be compositionally the same as or different from the dielectric material providing the gate spacer 28 and each lower dielectric isolation layer 30. The inner spacers 32 are formed by deposition and etching.

[0077] After forming the inner spacers 32, backside contact placeholder material 34 is formed in selective locations of the structure by etching the lower dielectric isolation layer 30 and upper portions of the substrate that do not include the shallow trench isolation structures 22 (in the embodiment shown, this etch is through the upper portion of the second semiconductor material layer 14). The openings created by this etch may then be filled with a sacrificial material, such as SiGe, TiOx, or AlOx (e.g., by a deposition process such as epitaxy, CVD, or PECVD), and a recess etch may be performed to provide the backside contact placeholder material 34 shown in Figures 5A, 5B, and 5C.

[0078] Next, source / drain regions 36 are formed. The source / drain regions 36 are typically formed by the epitaxial growth process defined above. The source / drain regions 36 extend laterally outward from the sidewalls of each semiconductor channel material nanosheet 20NS. Some of the source / drain regions 36 are formed in direct physical contact with the lower dielectric isolation layer 30, while other source / drain regions 36 are formed in direct physical contact with the back contact placeholder material 34. Each of the source / drain regions 36 is composed of a semiconductor material and a dopant. As used herein, a "source / drain" region can be either a source region or a drain region, depending on the subsequent wiring and the application of voltages during transistor operation. The semiconductor material providing each of the source / drain regions 36 is composed of one of the semiconductor materials mentioned above. The semiconductor material providing the source / drain regions 36 can be compositionally the same as or different from the respective semiconductor channel material nanosheet 20NS. However, the semiconductor material providing each source / drain region 36 is compositionally different from each recessed sacrificial semiconductor material nanosheet 18NS. The dopants present in the source / drain regions 36 can be either p-type or n-type dopants. The term "p-type" refers to the addition of impurities to an intrinsic semiconductor that create a deficiency of valence electrons. In silicon-containing semiconductor materials, examples of p-type dopants, or impurities, include, but are not limited to, boron, aluminum, gallium, phosphorus, and indium. "N-type" refers to the addition of impurities that contribute free electrons to an intrinsic semiconductor. In silicon-containing semiconductor materials, examples of n-type dopants, or impurities, include, but are not limited to, antimony, arsenic, and phosphorus. In one example, each of the source / drain regions has a 4×10 20 atoms / cm 3 ~3×10 21 atoms / cm 3 The dopant concentration may be

[0079] 6A, 6B, and 6C, there are shown views of the exemplary semiconductor structure shown in FIGS. 5A, 5B, and 5C, respectively, after forming and planarizing a front interlayer dielectric (ILD) material layer 38. The front ILD material layer 38 is composed of a dielectric material including, for example, silicon oxide, silicon nitride, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. As used throughout this application, the term "low-k" refers to a dielectric material having a dielectric constant of less than 4.0 (all dielectric constants referred to herein are relative to a vacuum unless otherwise specified). The front ILD material layer 38 can be formed by a deposition process, including, but not limited to, CVD, PECVD, or spin-on coating. Planarization processes include chemical mechanical polishing (CMP). As shown in FIG. 6C, the planarization process removes the upper portion of each sacrificial gate cap 26 and the upper portion of each gate spacer 28.

[0080] 7A, 7B, and 7C, which illustrate views of the exemplary semiconductor structure shown in FIGS. 6A, 6B, and 6C, respectively, after forming self-aligned diffusion break areas 42. The self-aligned diffusion break areas 42 are formed in regions of the structure between each of the transistors in the first device track and each of the transistors in the second device track. The self-aligned diffusion break areas 42 can be formed by first forming an organic planarizing layer (OPL) 40 on the structure provided in FIGS. 6A, 6B, and 6C. The OPL 40 can be formed by a deposition process, including, for example, CVD, PECVD, or spin-on coating. The OPL 40 is then patterned by lithography and etching to include openings therein. Etching is then used to transfer the openings in the OPL 40 into the upper portion of the substrate (in the illustrated embodiment, the etching transfers the openings in the OPL 40 into the upper portion of the second semiconductor material layer 14). The etch completely removes any front-side ILD material layer 38, source / drain regions 36, and lower dielectric isolation layer 30 located directly below the opening in OPL 40, and the etch partially removes the upper portion of the substrate, as shown in FIG. 7C.

[0081] 8A, 8B, and 8C, there are shown views of the exemplary semiconductor structure shown in Figures 7A, 7B, and 7C, respectively, after forming a dielectric material in self-aligned diffusion break area 42 to provide diffusion break structure 44. The dielectric material providing diffusion break structure 44 may include, for example, silicon dioxide, silicon nitride, or silicon oxynitride, and the dielectric material providing diffusion break structure 44 is compositionally different from the dielectric material providing sacrificial gate cap 26. Prior to forming this dielectric material, OPL 40 is removed using a material removal process that is selective in removing OPL 40.

[0082] A dielectric material providing the diffusion break structure 44 is then deposited (CVD, PECVD, etc.) within the remaining portions of the self-aligned diffusion break area 42 and on top of the structure, and then a planarization process such as CMP is used to provide the final diffusion break structure 44. This planarization process removes the dielectric material formed outside the self-aligned diffusion break area 42, the upper portions of the front side ILD material layer 38, the remaining portions of the respective sacrificial gate caps 26, and the upper portions of the remaining gate spacers 28.

[0083] Referring now to Figures 9A, 9B, and 9C, there are shown views of the exemplary semiconductor structures shown in Figures 8A, 8B, and 8C, respectively, after further nanosheet device processing including removing the sacrificial gate structure 24, suspending the semiconductor channel material nanosheets 20NS of each nanosheet stack, forming a gate structure 45 that wraps around the suspended semiconductor channel material nanosheets 20NS of each nanosheet stack, forming additional front ILD material, front source / drain contact structures 46, front BEOL structures 48, and a carrier wafer 50.

[0084] Removal of the sacrificial gate structure 24 to expose the nanosheet stack includes any material removal process, such as, for example, etching, that is selective in removing the sacrificial gate structure 24. Removal of the sacrificial semiconductor material nanosheets 18NS to free the respective semiconductor channel material nanosheets 20NS includes any material removal process, such as, for example, etching, that is selective in removing the sacrificial semiconductor material nanosheets 18NS.

[0085] Next, a gate structure 45 is formed. The gate structure 45 includes a gate dielectric material and a gate electrode, both of which are not separately shown but are intended to be within the region defined by the gate structure 45. As known to those skilled in the art, the gate dielectric material directly contacts the physically exposed surface of each semiconductor channel material nanosheet 20NS, and the gate electrode is formed on the gate dielectric material. The gate dielectric material has a dielectric constant of 4.0 or greater. Illustrative examples of gate dielectric materials include, for example, silicon dioxide, hafnium dioxide (HfO), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiO), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium dioxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium silicon oxynitride (ZrSiO). x N y ), tantalum oxide (TaO x Examples of suitable gate dielectric materials include, but are not limited to, titanium oxide (TiO), barium strontium titanium oxide (BaOSrTi), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YbO), aluminum oxide (AlO), lead tantalum scandium oxide (Pb(Sc,Ta)O), and / or lead zinc niobate (Pb(Zn,Nb)O). The gate dielectric material may further include dopants such as lanthanum (La), aluminum (Al), and / or magnesium (Mg).

[0086] The gate electrode can include a work function metal (WFM) and, optionally, a conductive metal. The WFM can be used to set the threshold voltage of the transistor to a desired value. In some embodiments, the WFM can be selected to achieve an n-type threshold voltage shift. "N-type threshold voltage shift," as used herein, refers to a shift in the effective work function of a work function metal-containing material toward the conduction band of silicon in the silicon-containing material. In one embodiment, the work function of the n-type work function metal ranges from 4.1 eV to 4.3 eV. Examples of such materials that can achieve an n-type threshold voltage shift include, but are not limited to, titanium aluminum, titanium aluminum carbide, tantalum nitride, titanium nitride, hafnium nitride, hafnium silicon, or combinations thereof. In other embodiments, the WFM can be selected to achieve a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal ranges from 4.9 eV to 5.2 eV. As used herein, "threshold voltage" refers to the lowest achievable gate voltage that turns on a semiconductor device, e.g., a transistor, by making the device's channel conductive. The term "p-type threshold voltage shift," as used herein, refers to a shift in the effective work function of a metal-containing material toward the valence band of silicon in the silicon-containing material. Examples of such materials that can achieve a p-type threshold voltage shift include, but are not limited to, titanium nitride, tantalum carbide, hafnium carbide, and combinations thereof. Optional conductive metals may include, but are not limited to, aluminum (Al), tungsten (W), or cobalt (Co). The gate structure 45 can be formed by deposition of a gate dielectric material and a gate electrode material, followed by a planarization process.

[0087] After forming the gate structure 45, an additional front ILD material is formed. The additional front ILD material typically comprises the same dielectric material as the previously formed front ILD material layer 38. Collectively, the additional front ILD material and the previously formed front ILD material layer 38 provide a front middle-of-the-line (MOL) dielectric layer 39 that will accommodate the front source / drain contact structures 46. The additional front ILD material can be formed utilizing the deposition process that was used to provide the previous front ILD material layer 38.

[0088] The front source / drain contact structures 46 are then formed using a metallization process that includes forming front contact openings in the MOL dielectric material layer 39 and then filling (including deposition and planarization) each front contact opening with at least a contact conductor material. The contact conductor material may include, for example, a silicide liner such as Ni, Pt, or NiPt, an adhesion metal liner such as TiN, and a conductive metal such as W, Cu, Al, Co, Ru, Mo, Os, Ir, Rh, or alloys thereof. The front source / drain contact structures 46 may also include one or more contact liners (not shown). In one or more embodiments, the contact liners (not shown) may include a diffusion barrier material. Exemplary diffusion barrier materials include, but are not limited to, Ti, Ta, Ni, Co, Pt, W, Ru, TiN, TaN, WN, WC, and alloys thereof, or stacks thereof, such as Ti / TiN and Ti / WC. In one or more embodiments in which a contact liner is present, the contact liner (not shown) may include a silicide liner, such as Ti, Ni, NiPt, or the like, and a diffusion barrier material as defined above. Each front side source / drain contact structure 46 contacts a source / drain region 36 located directly on the lower dielectric isolation layer 30, and the front side source / drain contact structure 46 does not physically contact a source / drain region 36 located on the back side contact placeholder material 34. Each front side source / drain contact structure 46 has a top surface that is coplanar with the top surface of the MOL dielectric material layer 39. The front side source / drain contact structure 46 and the front side MOL dielectric material layer 39 represent a MOL structure.

[0089] The front side BEOL structure 48 may include one or more interconnect dielectric material layers (including one of the dielectric materials mentioned above with respect to the front side ILD material layer 38) with one or more wiring regions embedded therein (the wiring regions may include any conductive metal or conductive metal alloy). The front side BEOL structure 48 may be formed utilizing any interconnect device processing technique. In some embodiments, the wiring regions are Cu wiring regions. The carrier 50 may include one of the semiconductor materials mentioned above with respect to the first semiconductor material layer 10. The carrier wafer 50 is bonded to the front side BEOL structure 48 after forming the front side BEOL structure 48.

[0090] 10A, 10B, and 10C, which illustrate the exemplary semiconductor structure shown in FIGS. 9A, 9B, and 9C, respectively, after removal of the first semiconductor material layer 10 of the substrate. Removal of the first semiconductor material layer 10 typically involves flipping the wafer 180° to physically expose the backside of the substrate. This flipping step is not shown in the drawings herein for clarity. In the illustrated embodiment, the substrate includes the first semiconductor material layer 10, the etch stop layer 12, and the second semiconductor material layer 14. Thus, flipping can physically expose the first semiconductor material layer 10 of the substrate. This flipping step enables backside processing of the exemplary structure. Backside processing is performed on the side of the wafer opposite the side on which the transistor, i.e., gate structure 45, is formed. Flipping the structure can be performed manually or by utilizing mechanical means, such as a robotic arm.

[0091] Removing the physically exposed first semiconductor material layer 10 of the substrate physically exposes the substrate's etch stop layer 12. Removal of the first semiconductor material layer 10 of the substrate can be performed using a material removal process that is selective in removing the first semiconductor material that provides the first semiconductor material layer 10.

[0092] 11A, 11B, and 11C, there are shown views of the exemplary semiconductor structure shown in FIGS. 10A, 10B, and 10C, respectively, after removal of the etch stop layer 12 and the second semiconductor layer 14 of the substrate. Removal of the etch stop layer 12 includes a material removal process that is selective in removing the etch stop layer 12. Removal of the etch stop layer 12 physically exposes the second semiconductor layer 14 of the substrate. The physically exposed second semiconductor material layer 14 of the substrate can be removed utilizing a material removal process that is selective in removing that layer from the structure. Depending on the type of substrate used, other material removal processes may be used. For example, in some embodiments where the substrate is composed entirely of a single semiconductor material, a single material removal process may be used rather than the multiple material removal processing steps described herein.

[0093] 12A, 12B, and 12C, there are shown views of the exemplary semiconductor structure shown in FIGS. 11A, 11B, and 11C, respectively, after forming a first backside ILD material layer 52. The first backside ILD material layer 52 may include one of the dielectric materials mentioned above with respect to the frontside ILD material layer 38. The first backside ILD material layer 52 may be formed utilizing one of the deposition processes mentioned above with respect to forming the frontside ILD material layer 38. The deposition process used in forming the first backside ILD material layer 52 may be followed by a planarization process. In an embodiment of the present invention, the first backside ILD material layer 52 has a surface that is coplanar with the surface of the backside contact placeholder material 34. Note that the backside contact placeholder material 34 embeds a lower portion of the diffusion breakpoint structure 44.

[0094] 13A, 13B, and 13C, there are shown views of the exemplary semiconductor structure shown in FIGS. 12A, 12B, and 12C, respectively, after removing the backside contact placeholder material 34 to physically expose the surfaces of portions of the source / drain regions 36 and forming backside source / drain contact structures 54 that contact the physically exposed surfaces of the portions of the source / drain regions 36. Removal of the backside contact placeholder material 34 includes a material removal process, such as etching, that is selective in removing the backside contact placeholder material 34. The physically exposed source / drain regions 36 are source / drain contacts that do not include the frontside source / drain contact structures 46. The backside source / drain contact structures 54 include the materials mentioned above with respect to the frontside source / drain contact structures 46. The backside source / drain contact structures 54 can be formed by the metallization process defined above with respect to the frontside source / drain contact structures 46. The backside source / drain contact structures 54 have surfaces that are coplanar with the surface of the first backside ILD material layer 52 .

[0095] 14A, 14B, and 14C, there is shown a view of the exemplary semiconductor structure shown in FIGS. 13A, 13B, and 13C, respectively, after forming a diffusion barrier layer 56 and a backside power rail conductive material layer 58.

[0096] The diffusion barrier layer 56 comprises a diffusion barrier material that prevents metal ions from the backside power rail conductive material layer 58 from diffusing into the backside source / drain contact structure 54. Illustrative examples of diffusion barrier materials that can be used as the diffusion barrier layer 56 include TiN, TaN, or a multilayer structure of TaN and TaN. The diffusion barrier layer 56 can be formed using a deposition process such as CVD, PECVD, atomic layer deposition (ALD), sputtering, or plating. The diffusion barrier layer 56 typically has a thickness of 1 nm to 20 nm, although other thicknesses are contemplated and can be used as the thickness of the diffusion barrier layer 56.

[0097] The backside power rail conductive material layer 58 is composed of any conductive power rail material, including, but not limited to, tungsten (W), cobalt (Co), ruthenium (Ru), aluminum (Al), copper (Cu), platinum (Pt), rhodium (Rh), or palladium (Pd). The backside power rail conductive material layer 58 can be formed using a deposition process, such as CVD, PECVD, ALD, sputtering, or plating. The backside power rail conductive material layer 58 typically has a thickness of 10 nm to 100 nm, although other thicknesses are contemplated and can be used as the backside power rail conductive material layer 58 thickness.

[0098] 15A, 15B, and 15C, there are shown views of the exemplary semiconductor structure shown in Figures 14A, 14B, and 14C, respectively, after forming a hard mask layer 60 over the backside power rail conductive material layer 58 and performing a first backside metal cut (i.e., cut in the X direction) into the hard mask layer 60. An opening 62 is formed by this metal cut in the X direction. The hard mask layer 60 comprises a dielectric material such as, for example, silicon dioxide or silicon nitride. The metal cut in the X direction comprises lithography and metal etching.

[0099] 16A, 16B, and 16C, there are shown views of the exemplary semiconductor structure shown in FIGS. 15A, 15B, and 15C, respectively, after forming an organic planarization layer 64 and performing a second backside metal cut (i.e., cut in the Y direction) into the organic planarization layer 64 and hard mask layer 60. An opening 66 is formed by this metal cut in the Y direction. The organic planarization layer 64 fills the opening 62 and is formed using a deposition process such as CVD, PECVD, or spin-on coating. The opening 66 is located in the area below the diffusion breakpoint structure 44. The metal cut in the Y direction includes lithography and metal etching.

[0100] 17A, 17B, and 17C, which illustrate the exemplary semiconductor structure shown in FIGS. 16A, 16B, and 16C, respectively, after removing the organic planarization layer 64 and patterning using the patterned hard mask layer 58 as an etch mask. The backside power rail conductive material layer 58 is patterned into individual backside power islands 58P by this process. Removal of the organic planarization layer 64 is performed using any material removal process that is selective in removing the organic planarization layer 64 from the structure. Patterning includes a metal etch that is selective in etching the backside power rail conductive material layer 58. Openings 68A and 68B are formed. Opening 68A is in the X direction, while opening 68B is in the Y direction. This patterning step cuts the backside power rail conductive material layer 58 in both the X and Y directions. As such, individual backside power islands 58P are formed in the first backside metal level BM1 and can be used as Vss or Vdd components, as shown in Figures 19A, 19B, and 19C. In an embodiment of the present invention, a first surface of each of the backside power islands 58P contacts the diffusion barrier layer 56, and a second surface of each of the backside power islands 58P, opposite the first surface, contacts the hard mask layer 60, where the first surface of each of the backside power islands 58P is located farther from the backside power distribution net 76 than the second surface of each of the backside power islands 58P.

[0101] 18A, 18B, and 18C, there are shown views of the exemplary semiconductor structure shown in FIGS. 17A, 17B, and 17C, respectively, after forming a second backside ILD material layer 70. The second backside ILD material layer 70 includes one of the dielectric materials mentioned above with respect to the first frontside ILD material layer 38. The dielectric material providing the second backside ILD material layer 70 may be compositionally the same as or compositionally different from the dielectric material providing the first backside ILD material layer 52. The second backside ILD material layer 70 may be formed by a deposition process such as, for example, CVD, PECVD, or spin-coating. As shown in FIGS. 18A, 18B, and 18C, the openings 68A and 68B are filled with the second backside ILD material layer 70.

[0102] 18A and 18B show first cut regions CT1. Each CT1 is located between each pair of n-type and p-type field effect transistors in the first and second device tracks. FIG. 18C shows second cut regions CT2. CT2 is located in the area between the first and second device tracks, and CT2 is located below the diffusion breakpoint structure 44. Note that each CT1 runs perpendicular to CT2, and both CT1 and CT2 are filled with the second backside interlayer dielectric material layer 70. Furthermore, note that the second backside interlayer dielectric material layer 70 at CT1 and CT2 directly contacts the sidewalls of the backside power island 58P.

[0103] 19A, 19B, and 19C, there are shown views of the exemplary semiconductor structure shown in FIGS. 18A, 18B, and 18C, respectively, after forming metal via contact structures and a backside power distribution network 76. Each metal via contact structure includes a conductive material 74 and a diffusion barrier liner 72. The diffusion barrier liner 72 can include one of the diffusion barrier materials mentioned above with respect to the diffusion barrier layer 56, and the conductive material 74 includes one of the conductive power rail materials mentioned above with respect to the backside power rail conductive material layer 58. The metal via contact structures (including the conductive material 74 and the diffusion barrier liner 72) can be formed using a metallization process. This metallization process includes forming openings in the second backside ILD material layer 70 and the patterned hard mask layer 60, thereby physically exposing one of the backside power islands 58P. These openings are filled to include the conductive material 74 and the diffusion barrier liner 72. The backside power distribution net 76 is formed to contact the second backside ILD material layer 70 and respective metal via contact structures, as shown in Figures 19A, 19B, and 19C. As such, the backside power distribution net 76 is in electrical contact with at least one of the backside power islands 59P (here labeled BM1 Vdd) by the metal via contact structures; a portion of the backside power island 59P is configured to be a BM1 Vss element. The backside power distribution net 76 includes elements / components configured to provide power to the transistors.

[0104] Referring now to FIG. 20, a schematic diagram illustrating a prior art backside power rail is shown, while FIG. 21 shows a schematic diagram illustrating a backside power island in accordance with the present invention. As shown in FIG. 20, the prior art backside power rail (labeled Vss and Vdd) is a metal line that extends continuously across different device tracks. In contrast, FIG. 21 shows backside power islands (labeled Vss and Vdd) located in both DT1 and DT2, where the backside power islands located in DT1 and the backside power islands located in DT2 are separated by a first cutout region, i.e., CT1, and the backside power island located in the first device track DT1 is separated from the backside power island located in the second device track DT2 by a second cutout region, CT2. As shown, CT2 is oriented perpendicular to CT1, and each CT1 is oriented parallel to one another. In an embodiment of the present invention, CT1 is located between each pair of n-type and p-type field effect transistors present in the first and second device tracks. In an embodiment of the present invention, and as shown in Figure 21, the back power island of DT1 has a first width w1 and the back power island of DT2 has a second width w2, where w1 is less than w2. This aspect provides the back power islands of DT1 staggered relative to the back power islands of DT2.

[0105] While the present invention has been particularly shown and described with respect to preferred embodiments thereof, workers skilled in the art will recognize that these and other changes in form and detail may be made therein without departing from the scope of the invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.

[0106] In a preferred embodiment of the present invention described herein, there is provided a semiconductor structure comprising: a first device track laterally adjacent to a second device track, wherein each of the first and second device tracks has p-type and n-type field effect transistors arranged in rows and columns; a diffusion breakpoint structure separating the first device track from the second device track; and backside power islands located in both the first and second device tracks, wherein the backside power islands located in the first device track and the backside power islands located in the second device track are separated by a first cutout region, and the backside power islands located in the first device track are separated from the backside power islands located in the second device track by a second cutout region, and further, the second cutout region is located below the diffusion breakpoint structure and oriented perpendicular to the first cutout region. The first cutout region may be located between each pair of n-type and p-type field effect transistors present in the first and second device tracks. The backside power island of the first device track may have a first width, and the backside power island of the second device track may have a second width, where the first width is smaller than the second width. The first device tracks may each comprise a first active area having the first width, and the second device tracks may each comprise a second active area having a second width larger than the first width. Both the first cut-out region and the second cut-out region may be filled with a backside interconnect dielectric material layer. The backside interconnect dielectric material layer in both the first cut-out region and the second cut-out region may be in direct physical contact with a sidewall of at least one of the backside power islands.

Claims

1. 1. A semiconductor structure comprising: a backside power island located in both a first device track and a second device track, wherein each backside power island located in the first device track and the second device track is separated by a first cutout region, the backside power island located in the first device track is separated from the backside power island located in the second device track by a second cutout region, and further wherein the second cutout region is oriented perpendicular to the first cutout region.

2. 2. The semiconductor structure of claim 1, wherein each of the first and second device tracks comprises a p-type field effect transistor and an n-type field effect transistor arranged in rows and columns.

3. 3. The semiconductor structure of claim 2, wherein the first cut-out region is located between each pair of n-type and p-type field effect transistors present in the first device track and the second device track.

4. 2. The semiconductor structure of claim 1, wherein the backside power island of the first device track has a first width and the backside power island of the second device track has a second width, the first width being less than the second width.

5. 2. The semiconductor structure of claim 1, wherein the first device tracks each have a first active area having a first width, and the second device tracks each have a second active area having a second width greater than the first width.

6. 2. The semiconductor structure of claim 1, wherein both the first cut-out region and the second cut-out region are filled with a layer of backside interconnect dielectric material.

7. 7. The semiconductor structure of claim 6, wherein the backside interconnect dielectric material layer in both the first cut-out region and the second cut-out region is in direct physical contact with a sidewall of at least one of the backside power islands.

8. 7. The semiconductor structure of claim 6, wherein the backside interconnect dielectric material layer contacts a surface of a backside power distribution network.

9. 9. The semiconductor structure of claim 8, wherein the backside power distribution net is connected to at least one of the backside power islands located in both the first device track and the second device track by a metal via contact structure.

10. 10. The semiconductor structure of claim 9, wherein the metal via contact structure includes a diffusion barrier liner located along sidewalls and bottom walls of the conductive metal or conductive metal alloy.

11. 9. The semiconductor structure of claim 8, wherein a first surface of each of the backside power islands contacts a diffusion barrier layer, a second surface of each of the backside power islands opposite the first surface contacts a hard mask layer, and the first surface of each of the backside power islands is located farther from the backside power distribution grid than the second surface of each of the backside power islands.

12. 2. The semiconductor structure of claim 1, wherein at least one of the backside power islands is electrically connected to a source / drain region of a p-type field effect transistor or an n-type field effect transistor in at least one of the first device track or the second device track by a backside source / drain contact structure.

13. 2. The semiconductor structure of claim 1, wherein at least one source / drain region of either a p-type field effect transistor or an n-type field effect transistor in at least one of the first device track or the second device track is electrically connected to a front end of line (BEOL) structure by a front source / drain contact structure.

14. The semiconductor structure of claim 13 further comprising a carrier wafer located on a surface of the front side BEOL structure.

15. 14. The semiconductor structure of claim 13, wherein the source / drain regions electrically connected to the front side BEOL structure are located on a surface of a lower dielectric isolation layer.

16. 3. The semiconductor structure of claim 2, wherein the p-type field effect transistor and the n-type field effect transistor are nanosheets comprising transistors including a gate structure wrapped around at least one nanosheet of semiconducting channel material.

17. 2. The semiconductor structure of claim 1, further comprising a diffusion break structure separating the first device track from the second device track, the second undercut region being located below the diffusion break structure.

18. 20. The semiconductor structure of claim 17, wherein the diffusion break structure is comprised of a dielectric material, and wherein the diffusion break structure extends into a backside interlayer dielectric material layer.

19. 20. The semiconductor structure of claim 18, wherein said backside interlevel dielectric material layer overlies each of said backside power islands.

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