Configurable photon sensing device

Abstract

A photon sensing device for photon sensing, comprising a plurality of photon detectors connected to a plurality of shift registers, wherein the plurality of photon detectors and shift registers are provided as part of a configurable processing circuit that can be configured to combine two or more of the plurality of shift registers and combine two or more photon detectors to form one or more coupled shift registers and one or more coupled photon detectors, respectively.

Description

Technical Field

[0001] Field The present invention relates to a photon sensing device for photon sensing, particularly a configurable photon sensing device.

Background Art

[0002] Background Single photon sensing devices, particularly single photon avalanche detector (SPAD)-based sensors, can typically be implemented in various applications, including, for example, LiDAR, time-of-flight (ToF), and 3D imaging applications.

[0003] The characteristics and operation of a SPAD can be affected by several factors, such as the underlying semiconductor technology used to implement the SPAD, as well as the associated processing circuitry that controls and senses the SPAD operation and records SPAD events, such as photon collisions. In some examples, the processing circuitry required to read out and / or store the state of the SPAD can substantially affect the size, cost, power consumption, and general performance of a SPAD-based device. Due to such characteristics and operation of SPAD-based pixels, the utilization of SPAD-based pixels in applications such as image sensing has been somewhat limited.

Summary of the Invention

Means for Solving the Problems

[0004] Summary According to a first aspect, there is provided a photon sensing device for photon sensing, comprising a plurality of photon detectors connected to a plurality of shift registers, wherein the plurality of photon detectors and shift registers are provided as part of a configurable processing circuit configurable to combine two or more of the plurality of shift registers and combine two or more photon detectors to form one or more combined shift registers and one or more combined photon detectors.

[0005] At least two or more shift registers coupled with two or more photon detectors may provide an exchange between time range and / or depth range and spatial resolution. At least two or more shift registers coupled with two or more photon detectors may provide an exchange between time range and / or depth resolution and spatial resolution. At least two or more shift registers coupled with two or more photon detectors may provide one or more choices of time range, depth range, time resolution, depth resolution, and spatial resolution.

[0006] The time range and / or depth range and / or time resolution and / or depth resolution may be adjustable by selecting the characteristics of one or more clock signals provided to multiple shift registers, such as speed and / or frequency and / or period.

[0007] The time range or depth range may include the maximum available time range or depth range. The time range or depth range may depend on the number of shift register elements in the combined shift register. The time range may include the period during which the histogram bin is defined and / or a photon detection event is recorded within a laser cycle. The depth range may include the depth to which the histogram bin is defined and / or a photon detection event is recorded within a laser cycle.

[0008] Multiple shift registers may be supplied with one or more clock signals. Time resolution or depth resolution can be adjusted by selecting the characteristics of the clock signals supplied to the multiple shift registers. The characteristics of the clock signals may include speed and / or frequency and / or period.

[0009] The time range of each combined shift register may include the number of shift register elements of the combined shift register multiplied by the clock period. The depth range of each combined shift register may depend on the number of shift register elements of the combined shift register multiplied by the clock period.

[0010] Combining two or more shift registers while maintaining the clock period can increase the time range and / or depth range. Combining two or more shift registers while shortening the clock period can at least maintain the time resolution and / or depth resolution, and optionally increase the time resolution and / or depth resolution.

[0011] At a minimum, combining two or more shift registers and two or more photon detectors may provide an exchange between temporal and / or depth resolution and spatial resolution.

[0012] A configurable processing circuit may be controllable by one or more configuration signals to couple multiple photon detectors and / or multiple shift registers. Coupled two or more photon detectors may include providing one or more configuration signals to the multiple photon detectors. Coupled two or more shift registers may include providing one or more configuration signals to the multiple shift registers.

[0013] Multiple photon detectors may include multiple single-photon detectors. Multiple photon detectors may include multiple single-photon avalanche diodes (SPADs).

[0014] A coupled photon detector may include a group of photon detectors operating together as single-photon detectors. The group of photon detectors, operating together as single-photon detectors, can detect photons over a wider spatial region than each individual photon detector in the group. A coupled photon detector may include a common electrode, such as an anode, formed in response to one or more constituent signals. Coupling two or more photon detectors may include short-circuiting the connections between the two or more photon detectors to form a common anode, such that a photon detection event from any of the photon detectors is detected at the common anode.

[0015] A combined shift register may include a group of shift registers that operate together as a single shift register. A single shift register may offer longer acquisition times compared to each individual shift register in a group of shift registers. Combining two or more shift registers while maintaining a clock period may increase the time range and / or depth range. Combining two or more shift registers while shortening the clock period may at least maintain or increase the time resolution and / or depth resolution.

[0016] The configurable processing circuit may include a signal routing processing circuit for multiple shift registers, which is selectively operable to route signals for the shift registers and thereby combine output signals from one or more of the multiple shift registers. The signal routing processing circuit may include one or more multiplexers. Combining two or more shift registers may involve selectively operating the signal routing processing circuit to combine output signals from one or more of the multiple shift registers.

[0017] The shift registers may be provided in a linear or series configuration. The output of a first shift register may be selectively provided as an input to a further shift register. The first shift register may be connected to a further shift register and configured to selectively provide an input to the further shift register.

[0018] Multiple shift registers may be arranged in a chain configuration that allows for the selective chaining of two or more shift registers together, thereby forming one or more combined shift registers. Combining two or more shift registers may involve chaining two or more shift registers together.

[0019] Multiple shift registers may include other shift registers. Multiple shift registers may include dynamic shift registers.

[0020] The photon sensing device may include a shared photon detection processing circuit configurable to perform a shared recharge and / or quench operation for each coupled photon detector. Coupled two or more photon detectors may involve operating the shared photon detection processing circuit to perform a shared recharge and / or quench operation.

[0021] The photon detection processing circuit may include at least one shared electrode. The photon detection processing circuit may include at least one shared anode. The photon detection processing circuit may include at least one recharge transistor between photon detectors.

[0022] The photon detection processing circuit may include, or form part of, the front end of the photon detector. The shift register is connected to the photon detection processing circuit and / or the front end.

[0023] The sensing device may further include a shared memory module. The shared memory module may be shared among at least some of the configurable circuits. The shared memory module may be configured to store data representing spatial information and / or timing information and / or count information from at least some of the configurable circuits. The shared memory module may include an SRAM or DRAM memory module.

[0024] At least two of the plurality of shift registers, preferably at least three of the plurality of shift registers, can be connected to a shared memory module.

[0025] The shared memory module can be configured to select a data structure for storing spatial information and / or timing information and / or count information from at least a part of the reconfigurable circuit, and the data structure is selected to correspond to the time resolution and / or depth resolution and / or spatial resolution of at least a part of the reconfigurable circuit.

[0026] The plurality of shift registers may include dynamic memory, and the shared memory module includes static memory.

[0027] The plurality of photon detectors, the plurality of shift registers and / or the shared memory blocks can be provided in a layered structure.

[0028] At least one of the plurality of photon detection devices and at least one of the plurality of shift registers can be provided together as part of an array-like pixel element. The array-like pixel element can include one photon detector and a corresponding shift register.

[0029] The device may further include a plurality of additional array-like macro pixel elements, and each macro pixel element includes a plurality of array-like pixel elements together with a shared memory module.

[0030] The sensing device may further include a further shared resource shared between two or more of the macro pixels, such as a gate ring oscillator.

[0031] Multiple photon detectors and shift registers may be in a spatial distribution, and the sensing device includes a signal transfer processing circuit configured to provide one or more signals to the multiple shift registers and / or multiple photon detectors across the spatial distribution, the signal transfer processing circuit being in an H-tree configuration. The signal transfer processing circuit may include a timing signal transfer processing circuit. The signal transfer processing circuit may be configured to provide one or more constituent signals.

[0032] The configurable processing circuit may be configurable to at least a first configuration and a second configuration. In the first configuration, each coupled photon detector may be coupled to a corresponding coupled shift register, and the coupled photon detector is configured to modify the coupled coupled shift register in response to a photon detection event so that the coupled coupled shift register stores photon detection event information. In the second configuration, each photon detector may be coupled to a corresponding shift register, and the photon detector is configured to modify the coupled shift register in response to a photon detection event so that the coupled coupled shift register stores photon detection event information.

[0033] The first configuration may include a first temporal resolution and a first spatial resolution. The second configuration may include a configuration having a second temporal resolution and a second spatial resolution, where the first spatial resolution is lower than the second spatial resolution and the first temporal resolution is higher than the second temporal resolution.

[0034] In the first configuration, two or more SPADs and / or shift registers may be coupled together. In the first and second configurations, the device may be configured to acquire a time-of-flight signal. The first configuration may be a first long-range LiDAR configuration compared to the short-range LiDAR configuration of the second configuration.

[0035] The first configuration may be a time-resolved Raman configuration. In the first configuration, the state of each shift register may represent timing information and / or count information of the corresponding photon detector. The second configuration may be a fluorescence lifetime configuration. In the second configuration, the state of each coupled shift register may represent timing information and / or count information of the corresponding coupled photon detector.

[0036] The configurable processing circuit may be operable to be reconfigured within a single clock laser cycle to enable data acquisition with predetermined depth-related spatial and temporal resolutions.

[0037] The sensing device may include an image sensor. The sensing device may include a time-of-flight sensor. The sensing device may include a proximity sensor. The sensing device may include a sensor.

[0038] According to a second embodiment that may be provided independently, a method is provided for operating a photon sensing device, comprising configuring the photon sensing device, which comprises coupling two or more of a plurality of shift registers and coupling two or more of a plurality of photon detectors to form one or more coupled shift registers and one or more coupled photon detectors, respectively. The method may further comprise operating the photon sensing device to perform a photon sensing process. The sensing device may be provided according to the first embodiment.

[0039] According to a third aspect, a photon sensing device for photon sensing is provided, comprising a plurality of photon detectors coupled to a plurality of data shift circuits, wherein the plurality of photon detectors and data shift circuits are provided as part of a configurable processing circuit that can be configured to combine two or more of the plurality of data shift circuits and combine two or more photon detectors to form one or more coupled data shift circuits and one or more coupled photon detectors, respectively.

[0040] A data shift circuit is configured to update and / or shift data in response to a clock signal. The data shift circuit is configured to represent count information and / or timing information for one or more photon detection events. Each data shift circuit may include a shift register. The data shift circuit may be configured to adopt states representing count information and / or timing information. The data shift circuit may be configured to adopt states representing temporary or transient data. The data shift circuits may be configured to be coupled together by a chain.

[0041] Multiple shift registers may be connected to the front end of a photon sensing device. Multiple shift registers may be configured to function in chains and / or together, for example, as one or more larger shift registers. Multiple shift registers are capable of operating together. Multiple shift registers and optionally associated signal routing processing circuits may be capable of operating together in parallel-in-serial-out (PISO), serial-in-parallel-out (SIPO), or parallel-in-parallel-out (PIPO) mode. Multiple shift registers may be configured to be chained together and used in a loadable manner in parallel or series.

[0042] Multiple shift registers may be connected to the corresponding front ends of multiple photon detectors. The device may further include a shared memory, such as an SRAM device. The shared memory may be coupled to one or more shift registers.

[0043] The device may be capable of operating in several imaging modes, including high dynamic range (HDR), direct time of flight (dToF), and gated imaging.

[0044] In a further embodiment, a device is provided comprising a plurality of photon detectors, a shared memory module, such as an SRAM device, and one or more clock-controlled shift registers configured to be used in a chain that can be loaded in parallel or in series.

[0045] In a further embodiment, a photon sensing device is provided comprising a plurality of shift registers connected to a photon sensing device front end, such as a SPAD front end, wherein the plurality of shift registers are operable to function together in parallel input series output (PISO) mode, series input parallel output (SIPO) mode, or parallel input parallel output (PIPO) mode. The device may further comprise a shared memory, which may be coupled to one or more shift registers.

[0046] The device may be capable of operating in several imaging modes, including HDR, dToF, and gated imaging.

[0047] In a further embodiment, a device is provided comprising a plurality of photon detectors, a shared memory module, such as an SRAM device, and one or more clock-controlled shift registers configured to be used in a chain that can be loaded in parallel or in series.

[0048] Features in one embodiment may be provided as features in any other embodiment as needed. For example, features of an apparatus may be provided as features of a method, and vice versa. Any one or more features in one embodiment may be provided in combination with any one or more suitable features in any other embodiment.

[0049] Brief explanation of the drawing Herein, various embodiments of the present invention will be described only as examples, with reference to the attached drawings. [Brief explanation of the drawing]

[0050] [Figure 1] This is a schematic diagram of a sensing device according to one embodiment. [Figure 2]Figure 1 is a schematic diagram of a part of the sensing device. [Figure 3] This is a circuit diagram of a part of the sensing device according to an embodiment. [Figure 4] This is a circuit diagram of a part of the sensing device according to an embodiment. [Figure 5] This is a circuit diagram of a part of the sensing device according to an embodiment. [Figure 6] This is a circuit diagram of a part of the sensing device according to an embodiment. [Figure 7] This is a schematic diagram of a coupling circuit for multiple photon detectors according to one embodiment. [Figure 8a] This is a schematic diagram of a 4x4 photon detector array with a first configuration according to one embodiment. [Figure 8b] This is a schematic diagram of a 4x4 photon detector array with a second configuration according to one embodiment. [Figure 9] This is a schematic diagram of the pixel architecture of a sensing device according to a further embodiment. [Figure 10] This is a schematic diagram of a photon sensing device according to a further embodiment. [Figure 11] This is a diagram of a circuit layout for a signal transmission processing circuit according to one embodiment. [Figure 12] This is a timing signal diagram for the operation of a sensing device according to an embodiment. [Figure 13] This is a timing signal diagram for the operation of a sensing device according to an embodiment. [Figure 14] This is a timing signal diagram for the operation of a sensing device according to an embodiment. [Figure 15] This is a timing signal diagram for the operation of a sensing device according to an embodiment. [Figure 16] This is a timing signal diagram for the operation of a sensing device according to an embodiment. [Figure 17] This is a circuit diagram of a part of the sensing device according to an embodiment. [Figure 18] This is a circuit diagram of a part of the sensing device according to an embodiment. [Figure 19] This is a circuit diagram of a part of the sensing device according to an embodiment. [Figure 20] This is a circuit diagram of a part of the sensing device according to an embodiment. [Modes for carrying out the invention]

[0051] Detailed explanation Figure 1 is a schematic diagram of a photon sensing device 10 according to one embodiment. Sensing device 10 is a configurable sensing device. Sensing devices are sometimes called sensors. Sensing device 10 can be thought of as being formed by a hierarchically arranged array of elements. In this embodiment, the sensing device can be thought of as being formed by a first type of array of elements called macropixels, and the macropixels themselves can be thought of as being formed from a second, smaller type of array of elements called single-photon avalanche diode (SPAD) pixels or simply pixels. Thus, as will be described below, sensing device 10 can be thought of as a hierarchy of modules / arrays from the pixel / SPAD level to the macropixel level, and shared processing circuits can be provided at different levels of the hierarchy (for example, shared processing circuits can be provided per pixel, per macropixel, or shared between groups of macropixels).

[0052] Figure 1 depicts a sensing device 10 having multiple macro pixels 11 arranged in an array. Figure 2 is a schematic diagram of a typical macro pixel 12 of the sensing device 10. In Figure 1, only two of the multiple macro pixels 11, 12a and 12p, are labeled, but it will be understood that each macro pixel of the device substantially corresponds to a macro pixel 12. The macro pixel 12 has several SPADs provided together with processing circuits for each SPAD (the SPADs and the processing circuits for each SPAD are collectively called SPAD pixels, or simply pixels). Since each SPAD pixel 14a, ..., 14n has the same components and processing circuits, for the sake of brevity, only the first pixel 14a will be described below.

[0053] In detail, pixel 14a has a single-photon avalanche diode (SPAD) 16a and associated processing circuitry 18a. The associated processing circuitry 18a may include processing circuits for sampling and holding voltage levels, processing circuits for resetting the SPAD, processing circuits for quenching the SPAD, and so on. Furthermore, pixel 14a has a state memory processing circuitry 20a for each SPAD. In the embodiments described, the state memory processing circuitry 20a for each SPAD includes a dynamic shift register. The state memory processing circuitry may also be referred to as a state memory element. A collection of dynamic shift registers for the device may be thought to form a dynamic memory.

[0054] Multiple SPADs, at least some of their associated processing circuits, and the device's state memory processing circuit are provided as part of a configurable processing circuit, which is a processing circuit that can be controlled using one or more control signals to place the SPADs and state memory processing circuits into one of several configurations. The configurable processing circuit is controllable to combine the multiple SPADs and state memory processing circuits to enable the exchange of time and / or depth range and / or resolution with spatial resolution.

[0055] More specifically, the configurable processing circuit has a SPAD coupling processing circuit 22 that can operate to combine one or more SPADs and optionally some of their associated processing circuits to form one or more coupled SPADs. The configurable processing circuit also has a state memory processing circuit 24 that can operate to combine one or more memory processing circuits to form one or a coupled memory processing circuit. The coupling processing circuit extends between different pixels of the macro pixels to enable the reconstruction of the SPADs and memory processing circuits across the macro pixels. In this embodiment, it will be understood that the pixel configuration is performed before sensing (i.e., before data acquisition / detection). The coupling processing circuits 22 and 24 will be described in more detail with reference to the remaining figures. The macro pixels also have a control processing circuit for receiving a configuration signal and thereby controlling the coupling processing circuit 20 to reconstruct the SPAD / memory elements. The configuration signal may also be called a control signal.

[0056] Other examples of temporary or transient memory circuits may be used in further embodiments. For example, a data shift circuit configured to shift data in response to a clock signal or the like, and configured to be coupled in a chain, may be suitable. Such a data shift circuit may be configured to represent count information and / or timing information for one or more photon detection events, for example, the data shift circuit may be configured to take up states representing count information and / or timing information. The data shift circuit may be configured to take up states representing temporary or transient data. The data shift circuits may be configured to be coupled together in a chain.

[0057] In this embodiment, the coupling circuit extends between different pixels of a macropixel to enable the reconfiguration of the SPAD and memory processing circuit across the macropixel. In an alternative embodiment, the coupling between the SPAD and the memory processing circuit is not limited to macropixels, and the coupling circuit may be provided throughout the entire device.

[0058] For the purposes of the following explanation, a coupled SPAD can be considered as a group of SPADs that operate collectively such that any one of the SPADs in the group can detect a photon during the detection period. Coupled a group of SPADs to a larger coupled SPAD increases the detection area of ​​the coupled SPAD (the coupled SPAD can operate to detect photons over a larger spatial region than the individual SPADs), and therefore reduces the spatial resolution of the macropixel / device. Along with the coupling of SPADs, their corresponding state memories can also be coupled to a coupled state memory. When SPADs are coupled, the common anode fires when the first photon strikes any one of the coupled detectors. Regardless of which of the coupled SPADs receives the photon, all VSPAD voltages respond with a simultaneous pulse. When SPADs are used individually, each SPAD responds uncorrelatedly to photons that collide with its own active region.

[0059] In embodiments where the state memory is a shift register, in a configuration where each individual shift register is paired with its associated pixel SPAD, each individual dynamic shift register is configured such that, during operation, the associated SPAD coupled to the shift register or another SPAD provides a signal to the shift register in response to a photon detection event, and the shift register captures event count or event timing information of the photon detection event. The count or timing information of the photon detection event is represented by the final state of the shift register after a certain period of time. By coupling two or more shift registers together, a combined or extended shift register is formed, thus enabling the collection of photon detection event information over a higher temporal resolution and / or longer range.

[0060] For example, a shift register may contain or represent a binary string pattern (e.g., a pattern like "111000"), where the transition position from 1 (the SPAD has fired in response to a photon) to 0 (the SPAD has not yet detected a photon and is still in a reset state) represents the time from the start of the clock that operates the shift register synchronized with the laser pulse. The time offset of the photon event from the start of the clock can be calculated by multiplying the number of 1s in the binary string pattern by the time, where the clock period is the time offset of the photon event from the start of the clock.

[0061] For example, a group of SPADs are combined to form a combined SPAD, and their corresponding shift registers are combined to form a corresponding combined shift register. During operation, signals from the combined SPAD are directed to the combined shift register such that the state of the combined shift register at the end of a certain period (also called the acquisition period) represents timing information / event information of the photon detection event detected by the combined SPAD.

[0062] The macro pixel 12 also has a shared memory 26 and associated processing circuits including a memory addressing and reading processing circuit 28 and a memory increment processing circuit 30. The memory addressing and reading processing circuit includes an overflow processing circuit and a precharge reading and writing processing circuit, which are described in detail with reference to Figure 9. The shared memory may be referred to as a shared memory module.

[0063] The shared memory 26 is static memory, and in this embodiment, it is SRAM. The shared memory 26 may comprise an array of SRAM elements. The shared memory 26 is configured to store photon detection event information or other photon timing information transferred from the pixel's memory processing circuit after the initial event acquisition process. Alternative memory implementations may be used. Although the above embodiment uses SRAM, 1T1C or gain cell DRAM requiring refresh cycles is also possible, and the refresh cycles can be easily implemented by forcing the updating of all processing circuits at a selected repetition rate. Memories using Phase Change, STT-RAM, MRAM, and FeRAM are also possible.

[0064] In some embodiments, the shared memory module can be configured to select a data structure for storing spatial information and / or timing information and / or count information from at least a portion of the reconfigurable circuitry. The data structure may be selected to correspond to the operating mode of the sensing device, for example, having a data structure corresponding to the time and / or depth resolution or range and / or spatial resolution of at least a portion of the reconfigurable circuitry.

[0065] Returning to Figure 1, the sensing device 10 has an array of such macro pixels. The macro pixels are arranged in a subarray. Figure 1 depicts four subarrays (40a, 40b, 40c, 40d). Each subarray has associated processing circuits shared among its macro pixels. For clarity, Figure 1 depicts the shared processing circuits of the first subarray 40a, and it will be understood that each subarray has associated processing circuits. Subarray 40a has 16 macro pixels (12a, ..., 12p), each macro pixel substantially corresponding to the macro pixel 12 described with reference to Figure 1. Subarray 40a also has associated processing circuits, such as a memory addressing processing circuit 41 and a clock management processing circuit 42.

[0066] The sensing device 10 also has a device processing circuit that includes a serial control interface 44, a stop clock and gate generation processing circuit 46, an addressing control processing circuit 48, a readout control processing circuit 50, and a processing and readout processing circuit 52. The device processing circuit can be considered to be shared among the subarrays of macro pixels.

[0067] Figure 1 depicts 16 macro pixels in each subarray, for a total of 64 macro pixels; however, such an arrangement is a non-limiting example, and it will be understood that different numbers and configurations of macro pixels may be used in alternative embodiments. Furthermore, it will be understood that each macro pixel may have a different total number of SPADs and pixels, and such pixels may be arranged in alternative configurations.

[0068] Figure 3 depicts a SPAD pixel 200 according to one embodiment. It will be understood that the SPAD pixel 200 forms part of a sensing device, such as the sensing device 10 described with reference to Figures 1 and 2. As described with reference to Figures 1 and 2, a pixel is an array element that forms part of a sensing device and may form part of a larger array element, such as a macropixel. In the embodiment of Figure 3, the pixel 200 is one of N pixels that form a macropixel.

[0069] An exemplary pixel 200 comprises a SPAD202. As is known in the art, the operation of the SPAD202 is based on the pn junction of the SPAD202 being biased beyond its breakdown region, known as operation within the “Geiger” region. The high reverse bias voltage generates an electric field large enough to induce the generation of a self-sustaining avalanche current by a single charge carrier introduced into the depletion layer of the SPAD202, due to shock ionization caused by one or more incident photons. When in use, the SPAD202 may be reset by “quenching” the avalanche with a quench circuit, thereby enabling further detection of photons.

[0070] In the exemplary pixel 200, the cathode of SPAD202 is connected to a high-voltage supply line denoted as VHV. The anode of SPAD202 is connected to a recharge transistor 204, which can be configured by a signal Vcas connected to the gate of the recharge transistor 204 to recharge SPAD202. A clamp diode 206 is provided to limit the excessive bias voltage generated across SPAD202 and prevent damage to SPAD202 during use. A voltage signal Vclamp is provided to the clamp diode 206.

[0071] The recharge transistor 204 is gate-controlled by a first quench transistor 208 and a second quench transistor 210 arranged in series. A common anode connection 212 is provided between the first and second transistors. The gate of the first quench transistor 208 is controlled by a quench signal called the “recharge” signal. The gate of the second quench transistor 210 is controlled by a “common recharge” signal. The quench resistor is sometimes called the recharge transistor. By controlling the common signal, quenching of the SPAD can be performed using either the first or second quench transistor. In the first mode, the first quench transistor is used to enable individual quenching of each SPAD. In the second mode, the second quench transistor is used to enable simultaneous quenching of two or more SPADs (thus forming a coupled SPAD). In some embodiments, a common electrode is provided.

[0072] The recharge transistor 204 is a cascode transistor intended to extend the overbias over which the SPAD can operate by shielding the source transistor from the high voltage deviation (equal to the overbias voltage) caused by SPAD ignition. Higher overbias voltages may be desirable as they allow for an extension of the SPAD's photon detection efficiency.

[0073] Pixel 200 also has a dynamic shift register 214 containing a cascade of M D-type flip-flops (216a, ..., 216m). A flip-flop can be thought of as either a state memory element or a shift register element. The output of each flip-flop is connected to the input of the next flip-flop. Each flip-flop is configured to receive a clock signal (Clk). The last flip-flop in the shift register is configured to receive a reset signal (RstN) to reset the shift register. The dynamic shift register shares a single clock signal that shifts the stored data along the dynamic shift register. The RstN signal is generated globally for the entire array and synchronized with the laser pulses. This allows the shift register chain to be flushed or reset before each laser pulse is ready to acquire a new laser return from the target. After each laser cycle, as described below, the contents of the shift register are transferred to and stored in a shared SRAM memory. In this embodiment, the maximum time range available for binning or recording photon detection events provided by the shift register is the number of shift register elements multiplied by the clock period. In the case of a coupled shift register, the maximum time range is the number of coupled shift register elements multiplied by the clock period.

[0074] The shift register 214 is connected to a 2:1 (two inputs, two outputs) multiplexer 218. The shift register provides one of its inputs to the multiplexer 218. The signal read from each shift register (the i-th shift register) is Q.<M,i> This is denoted as an M-sized word. Each SPAD pixel has an M-bit shift register. When coupled and chained with N-pixel macro pixels, the total length of the combined shift register is N × M. The SRAM memory word is provided bit by bit in the combined shift register in shared memory, and therefore shared memory provides N × M for each macro pixel.

[0075] The other input to the multiplexer 218 is provided from an additional SPAD pixel located on the macro pixel. The additional SPAD pixel (not shown) is provided in a chain configuration with the SPAD pixel 200 (an exemplary chain configuration is depicted in Figures 8a and 8b). The input signal from the preceding SPAD pixel (the i-1 pixel) to the multiplexer is C <i-1>This is denoted as follows. The output signal from the multiplexer for this SPAD pixel (the i-th pixel) is C This is how it is written. Chain signal 220 is provided to the multiplexer.

[0076] Once configured and / or reconfigured, the sensing device is operable to perform the photon sensing process. The operation of the sensing device from a pixel such as pixel 200 can be described with respect to a first configuration phase and a second data acquisition phase. The data acquisition phase can be described in three phases: itself, an event detection phase, an event transfer phase, and a data readout phase.

[0077] In the configuration phase, each macropixel is provided with a control (or configuration) signal to place it into one of several configurations. The configuration or control signal includes the recharge signal and common signal described above. As an example, the operation of the sensing device in two non-limiting configurations is described below. The configuration of the SPAD and shift register is predetermined by an external control signal depending on the type of photon event desired. For example, sensing of high time frequencies, high spatial frequencies or low time frequencies, low spatial frequencies may be possible.

[0078] Other combinations are possible, such as high temporal and low spatial frequency (HL) and low temporal and high spatial frequency (LH). As mentioned above, the spatial frequency portion is controlled simply by operating with a common SPAD anode / chained shift register or individual SPAD anode / unchained shift register, thereby selecting the spatial resolution. The temporal resolution is controlled by the frequency of the clock applied to the shift registers. As a non-limiting example, a clock in the 10 GHz range (with a time bin step of 100 ps) may be suitable for short flight times where the total return time from a few meters is in the range of a few nanoseconds. As a further non-limiting example, in LIDAR applications, the clock may be in the hundreds of MHz range with nanosecond bin steps for return times of hundreds of nanoseconds for distances of tens to hundreds of meters. It will be understood that combination cases can be created by coupling SPADS and shift registers (by commonizing or shorting electrodes and chaining the shift registers) and by applying high or low frequencies to the clocks of the shift registers.

[0079] It will be understood that there is a difference between operation and configuration control that implements reconstruction. For example, a photon detection event triggers a sequence of bits moving during data acquisition. Furthermore, some bits move as control signals change to reconstruct the hierarchy of pixels and shift registers when adjusting the temporal resolution versus spatial resolution. Thus, data acquisition can be understood as dependent on the configuration of the apparatus. Moreover, each configuration can therefore be thought of as a separate state machine in which the configuration is static during any particular operation.

[0080] The first configuration described is one in which each individual SPAD is paired with its corresponding shift register, thereby providing the maximum spatial resolution and, correspondingly, the minimum temporal resolution of the device.

[0081] By controlling the voltage level (common signal) at the common anode, each SPAD of a pixel can be recharged individually (using the coupling of the recharge transistor 204 and the first quench transistor 208) or collectively as part of a group of SPADs that form a coupled SPAD (using the coupling of the recharge transistor 204 and the second quench transistor 210).

[0082] More specifically, in the first configuration, the common anode connecting the SPAD processing circuits is at a voltage such that a first quench transistor is grounded for each pixel. In this configuration, a second quench transistor is not used, and therefore, recharging and the first quench transistor can operate to recharge each SPAD individually.

[0083] In this mode, if SPAD202 ignites in one configuration during the event detection period, the SPAD voltage VSPAD Generates the signal VSPAD. This is supplied to the input of the shift register and is therefore recorded as a digital bit in the first flip-flop. As the detection period continues, the digital bit is continuously moved along the shift register with a successive clock signal. Thus, the state of the shift register at the end of the detection period represents the timing information of the photon detection event. Since the SPAD must be recharged by the recharge transistor, it will be understood that each SPAD can fire only once during the event detection period.

[0084] As explained with reference to Figures 12-16, a clock is generated at a high acquisition rate (10 MHz) to capture the moment the SPAD fires. Since it is not possible to write information from the SPAD at this rate, timing information is instead collected in a shift register and written to SRAM. Therefore, at the end of the event detection period, a chain signal is provided to each multiplexer, and the individual information stored in each shift register is read out. During the subsequent data writing period, the timing information and count information stored in each shift register are written to SRAM.

[0085] In the first configuration, the SRAM is configured to store N words (one word for each SPAD), each word having M bits. In some embodiments, the shared memory is configured to receive counts from each individual SPAD and store the counts in memory as words. In such an example, the memory is configured to store a first count associated with a first pixel, a second count associated with a second pixel, and so on, up to the Nth count associated with the Nth pixel. As an example, since there are an equal number of spaces in the SRAM memory for each SPAD / shift register, each SPAD writes one word within a specific time window. In this operation, for each memory location, the state of each shift register corresponds to the SPAD event for each SPAD. Next, the state of each shift register is read in series, and the state of each shift register is stored in the SRAM. Then the adder is incremented and moves to the next memory location.

[0086] In the third phase, the data stored in the SRAM is then transferred from the sensing device to an external device by the operation of the address controller.

[0087] The above description concerns a configuration in which each individual SPAD and associated processing circuit is coupled to a corresponding shift register. As illustrated with reference to Figures 1 and 2, SPADs can be combined into two or more groups to form a combined SPAD and its respective combined shift register. Below, the operation of a non-limiting, exemplary configuration (second configuration) in which all SPADs of a macropixel are combined is described. In this second exemplary configuration, the spatial resolution is reduced, but the maximum time (or depth) range of the device is extended.

[0088] In the second configuration, the common anode is held at a voltage level such that the first quench transistor is effectively bypassed. In this configuration, the first quench transistor is not used, and therefore, recharging and the second quench transistor can operate to recharge the SPADs collectively. In this configuration, the shift registers of the macro pixels are coupled to a single combined shift register. When one SPAD in the group of SPADs fires, the fired SPAD is voltage VSPAD This generates the signal VSPAD. This is provided as input to the coupled shift register and is therefore recorded as a digital bit in the first flip-flop of the coupled shift register. As the detection period continues, the digital bit is continuously moved along the shift register with a successive clock signal. Thus, the state of the coupled shift register at the end of the detection period represents the timing information of the photon detection event of the coupled SPAD. Therefore, the coupled shift register stores the timing information and / or count information and / or event information of the coupled SPAD.

[0089] It will be understood that only one SPAD in a group of SPADs can fire in response to a photon detection event during the event detection period, and that all SPADs forming a coupled SPAD are recharged using a second quench transistor by providing a common signal to a second quench resistor.

[0090] At the end of the event detection period, a chain signal is provided to the multiplexer to obtain timing information and / or count information and / or event information for the coupled SPAD. During the data write period, the information stored in the coupled shift register is written to the SRAM. Since the coupled data is obtained from the coupled SPAD / shift register, the memory allocation in the SRAM is different from the first configuration.

[0091] In the third phase, the data stored in the SRAM is transferred from the device to an external device via the operation of the address controller.

[0092] Figures 4 to 6 show non-limiting examples of SPAD pixels according to further embodiments. Each of the SPAD pixel circuits depicted in Figures 4 to 6 operates substantially the same as the SPAD pixel circuit in Figure 3. In more detail, Figure 4 is an example of a 4-bin indirect time of flight (iToF). Figure 5 is an example of a 2-bin iToF. Figure 6 is a pixel suitable for a photon count image sensor.

[0093] Each of Figures 4 through 6 has several features common to Figure 3, in particular, SPAD coupling processing circuits (including, for example, common anode and shared quench processing circuits) and signal routing processing circuits for shift registers. Thus, it will be understood that each of the exemplary pixels in Figures 4 through 6 can be arranged in a larger macropixel array, substantially as described with reference to Figure 2.

[0094] More specifically, Figure 4 depicts a 4-bin indirect time-of-flight (iToF) embodiment. Figure 4 shows a SPAD pixel 300 having SPAD 302, a recharge transistor 304, a clamp diode 306, a first quench transistor 308, a second quench transistor 310, a common anode junction 312, a dynamic shift register 314 including a cascade of four D-type flip-flops (316a, ..., 316m), and a multiplexer 318. A chain signal 320 is provided to the multiplexer 318.

[0095] Figure 5 shows an example of a two-bin iToF. Figure 5 depicts a SPAD pixel 400 having a SPAD 402, a recharge transistor 404, a clamp diode 406, a first quench transistor 408, a second quench transistor 410, a common anode connection 412, a dynamic shift register 414 including a cascade of two D-type flip-flops (416a, ..., 416m), and a multiplexer 418. A chain signal 420 is supplied to the multiplexer 418.

[0096] Figure 6 shows a pixel suitable for a photon count image sensor. Figure 6 depicts a SPAD pixel 500 having a SPAD 502, a recharge transistor 504, a clamp diode 506, a first quench transistor 508, a second quench transistor 510, a common anode connection 512, a dynamic shift register 514 including a D-type flip-flop 516a, and a multiplexer 518. A chain signal 520 is supplied to the multiplexer 518.

[0097] Figure 6 depicts a pixel suitable for a photon counting image sensor. In this example, only one D-type and multiplexer is required per SPAD. This allows for a very small pixel pitch of approximately 3 μm, matching modern SPAD technology without requiring further logical scaling. This pixel can achieve the performance of a simple gated time binning or quantum image sensor.

[0098] It should also be noted that implementations of direct flight time with large M values ​​are possible. In some embodiments, the implementation of direct flight time requires M = 1, 2, 4, or 8.

[0099] Figure 7 illustrates a sensing device having four SPAD pixels 700a, 700b, 700c, and 700d according to one embodiment. For clarity, it will be understood that Figure 7 does not depict the corresponding memory state elements of each pixel. As observed in Figure 7, each SPAD 702a, 702b, 702c, and 702d has a corresponding recharge transistor 704a, 704b, 704c, and 704d, a corresponding clamp diode 706a, 706b, 706c, and 706d, and a corresponding first quench transistor 708a, 708b, 708c, and 708d, and a second quench transistor 710a, 710b, 710c, and 710d. Each SPAD circuit is connected to a common anode 712 at the point between its respective first and second quench transistors.

[0100] Referring to Figure 7, in this embodiment, to combine SPADs, the anodes of multiple SPADs are short-circuited to form a substantially larger SPAD. In this embodiment, this is achieved by setting the recharge signal to a logic high voltage, and the common signal is either briefly pulsed at the start of the laser period to recharge (in high-Z recharge mode) or set to a DC voltage slightly above the threshold voltage of the NMOS to place the device in the high-impedance linear region for passive quenching. In the former case, the SPADs function as a single larger device and are fired by a first photon incident on any of the anodes. The voltage from the substantially larger device is then applied to all VSPADs. <0> VSPAD from the node <3> They appear identically at the node because they are short-circuited together here by a constant high state of the recharge signal.

[0101] Figure 7 shows the case of four SPADs in a macropixel. In the operating mode where the SPADs are not coupled and operate individually, the common signal is set to a logic high voltage that shorts all common signals to ground, and the recharge signal is either pulsed (high-Z recharge) or set to a DC voltage slightly above a threshold to bias the device to act as a passive quench transistor for each SPAD. In the latter case, all SPADs are isolated from each other and can be pulsed individually from different photon arrivals.

[0102] Figures 8a and 8b depict sensing devices according to further embodiments of the first and second configurations. The sensing devices of Figures 8a and 8b have 4x4 SPAD pixels. Each pixel has an SPAD and associated SPAD processing circuitry, as described above. Each pixel also has a memory state circuitry in the form of a shift register (in this embodiment, the shift register is a single D-type flip-flop).

[0103] With respect to the shift register, each pixel is provided with a single routing processing circuit, namely a multiplexer. Each multiplexer can be operated by one or more control signals. In total, the multiplexer for each SPAD forms a signal routing processing circuit for the SPAD. As described below, the signal routing processing circuit is configured to route signals for the shift register and thereby combine the output signals. With respect to the SPAD, each SPAD is provided together with first and second quench transistors connected via a common anode, which provide part of the SPAD coupling processing circuit as described above.

[0104] Figures 8a and 8b also show the SPAD coupling processing circuits. In Figure 8a, the common anode connecting the SPAD processing circuits is at a voltage such that the first quench transistor is grounded for each pixel, and each SPAD can operate to be triggered independently of the others. In Figure 8b, the common anode connecting the SPAD processing circuits is at a voltage such that the first quench transistor is substantially bypassed for each pixel, and the SPADs can operate to be triggered as a group.

[0105] As depicted in Figures 8a and 8b, each shift register and its respective multiplexer are arranged in a chained configuration to form a chained or combined shift register. Thus, a combined shift register can operate to combine shift registers into separate groups. Shift registers can be thought of in a series configuration where each shift register is connected to its successor and successor. Such a configuration is sometimes called a linear configuration because the shift registers can define a signal path through the array. In Figure 8a, all 16 shift registers are chained to form an extended or combined shift register. The output of the combined shift register is delivered to shared memory. In this configuration, the shared memory is configured to have one bin per pixel. In the first configuration, the SPADs operate independently, and as a result, the output is attributable to the fired SPAD.

[0106] More specifically, each SPAD is provided with its own shift register and multiplexer. Figures 8a and 8b depict a shift register with a single flip-flop, but it will be understood that other sizes of shift registers may be provided for each SPAD. Each multiplexer is a 2-to-1 (two inputs, one output) multiplexer controllable using a single selection line. The output of the shift register for each SPAD is connected to the input of the corresponding multiplexer for the SPAD. The output of the multiplexer is connected to the subsequent multiplexer in series (the multiplexer for the subsequent SPAD in the array). Thus, the subsequent multiplexer in series receives inputs from the preceding multiplexer and the shift register of the subsequent multiplexer.

[0107] Figures 8a and 8b depict signal routing and SPAD coupling circuits connecting pixels in the row direction, but in other embodiments, it will be understood that the signal routing circuit may connect shift registers in the column direction. In further embodiments, the signal routing and SPAD coupling circuits may be capable of coupling any group of SPADs.

[0108] Figure 9 illustrates the pixel architecture of a sensing device according to a further embodiment. Figure 9 illustrates a sensing device relating to three modules. The first module 102 relates to a per-pixel processing circuit. The second module 104 relates to a processing circuit provided for each macropixel. The third module 106 relates to a processing circuit shared among several macropixels. It will be understood that some elements of the sensing device 100 in Figure 9 correspond to elements described with reference to Figures 1 and 2.

[0109] The first module 102 has N SPADs (in this embodiment, each SPAD is provided as part of a separate pixel). As described with reference to Figure 10, the SPADs are provided in the top stage or layer of the sensing device.

[0110] The first module 102 also has associated processing circuits, in particular front-ends, for each SPAD. Thus, the first module has N SPAD front-ends. The term “SPAD front-end” is understood to refer to the processing circuits associated with the SPAD. For example, such associated processing circuits may include, as will be described in more detail below, processing circuits for sampling and holding voltage levels, processing circuits for resetting the SPAD, processing circuits for quenching the SPAD, and so on. In this embodiment, each front-end may be considered to operate as a high-Z front-end.

[0111] High Z refers to the operation of the gate voltage of the quench or recharge transistor (which can be either 208 or 210 here, depending on the mode). When the SPAD operates in high Z mode, a logic pulse is applied to the gate, putting the SPAD into a recharge state (high signal state) or high impedance state "high Z," thereby storing the SPAD's prepared "low" state in its own capacitance. When the SPAD fires, it fires into the "high" state, thereby storing the fire state in the SPAD's own capacitance, and the SPAD cannot refire until it is recharged by a pulse applied to the gate of the recharge transistor 208 or 210. This is in contrast to "passive" quenching or recharging, where a DC level is placed over the quench or recharge transistor, allowing the SPAD to fire and quench independently and asynchronously, independently of any clock, and multiple times upon receiving multiple photon arrivals at different times.

[0112] For individual SPADs to generate useful outputs, components are needed for quenching or recharging, as illustrated with reference to Figure 3, for example. Further components can be added to gate-control SPAD events and to store the state of the SPADs. For the highest spatial resolution, it will be understood that such components are not shared in order to have separate outputs from each SPAD. However, they are combined when a group of SPADs is configured to operate together as a combined SPAD (e.g., all SPADs in a macropixel).

[0113] The first module also has N dynamic shift registers 112, such that each SPAD is provided with a corresponding dynamic shift register. The shift registers are M-stage shift registers (i.e., have M shift register elements). The first module also has a signal routing processing circuit that includes N multiplexers provided in a chain arrangement 114. The signal routing processing circuit can be considered to form part of the state memory coupling processing circuit described with reference to Figures 1 and 2.

[0114] The embodiments described describe a shift register element in the form of a Type D flip-flop. It will be understood that both dynamic and static flip-flops may be used. In some embodiments, an alternative shift register element configured to store a single bit may be used.

[0115] Turning to the second module 104, the second module 104 includes a shared memory 118 (corresponding to the shared memory 26 in Figure 2), an overflow processing circuit 116, a precharge read and write processing circuit 120 and a read tristate processing circuit 126 (collectively corresponding to the memory addressing and read processing circuit 28), and an increment processing circuit 122 (corresponding to the memory increment processing circuit 32).

[0116] The most significant bit of each SRAM word is considered an overflow bit. If any one of these bits is set, the SRAM integration scheme building the time-of-flight histogram overflows and is set to begin wrapping around in binary count space. This can lead to histogram corruption and additional power consumption of the SPADs in the pixel array, as these continue firing and proceed with pixel arithmetic and clock operations. The D-type flip-flop in the overflow handling circuit 116 detects any single most significant SRAM word and stores the memory overflow state, which prohibits pixel recharge pulses until a global ExtRecharge signal is asserted at the beginning of the frame. This can provide power savings because the SPADs are not constantly resetting and do not draw charge to each photon from the high-voltage bias.

[0117] More specifically, the shared memory 118 is described as an "N × M × k bit memory". When transferring data from the temporary storage in the shift register to the shared memory, the shift register is operated with different clock signals (different frequencies) corresponding to the memory read-write-modify timing. In some embodiments, the output of the shift register may also optionally feed into a circuit that detects the toggle state of the SPAD and increments the state of a memory word. Each memory word corresponds to an element of the SPAD (or group thereof) and the shift register (or time bin). K is the bit depth of each SRAM word. This allows for counting 2 to the power of k-1 photons at each time offset within the histogram range.

[0118] The memory increment processing circuit has an LFSR shifter and XOR feedback. The LFSR solution requires an external decoder but is more compact because it is provided by macro pixels, thereby reducing the need for sharing and enabling smaller N. In an alternative embodiment, the memory increment processing circuit may include a binary chain of half adders.

[0119] Turning to the third module 106, the third module has an address controller 128 (corresponding to the memory addressing processing circuit 41 in Figure 1) and a gate ring oscillator 130.

[0120] The address controller 128 sends an access signal to the SRAM 118.<N*M-1:0> The shared gate ring oscillator 130 is configured to transmit a clock signal for the pixels and forms part of the clock management processing circuit (corresponding to the clock management processing circuit 42 in Figure 2).

[0121] Referring to Figure 2, Figure 9 does not depict the device processing circuit including the serial control interface 44, the stop clock and gate generation processing circuit 46, the addressing control processing circuit 48, and the read control processing circuit 50, nor does it show the processing and read processing circuit 52.

[0122] As shown in Figure 9, the first module is configured to receive several control signals. In particular, the front-end 110 receives a common signal, sometimes called a common recharge signal. The dynamic shift register is also configured to receive a clock signal from the clock management processing circuit. The multiplexer arrangement is also configured to receive a chain signal ("chain"). The second module is further configured to receive several control signals. In particular, the memory is configured to receive an access signal. The increment processing circuit 122 is configured to receive a clock signal from the clock management processing circuit. The chain is a global signal of the pixel array that is asserted when a lower spatial resolution and / or higher bin depth mode is desired. The pixel array also has a state controller that needs to control the use of the common signal and the recharge signal (in some embodiments, the signals can also come from off-chip). In some embodiments, the chain and common are applied simultaneously.

[0123] The common recharge signal is, for example, in SPAD in direct time-of-flight mode. A wired OR gate for signals can be provided. However, in some embodiments, a similar function can be provided by connecting an N-input OR gate to the output of the SPAD (i.e., the signal SPAD<0:N-1>).

[0124] Figure 9 does not show the timing signal processing circuit in the form of an H-tree configuration. The timing signal processing circuit will be described in more detail with reference to Figure 11. The timing signal processing circuit provides the external clock signal (ExtClk) and Win signals to the clock management processing circuit. The clock management processing circuit is configured to receive the ClkSel signal to select either the ExtClk signal from the H-tree configuration or the ClkInt signal from the gate ring oscillator.

[0125] The clock management processing circuit can be controlled to operate in different modes, as will be described in more detail below. For Raman applications, a shared gated ring oscillator is configured to generate a clock signal of a higher frequency than required. For example, a shared gated ring oscillator provides the 10 GHz clock required for a 100 ps bin resolution for Raman. Distributing such high-frequency clock signals is difficult and can be power-intensive via an H-tree arrangement. The gated ring oscillator is shared among P macro pixels to reduce power consumption per SPAD. For Raman applications, the gated ring oscillator is enabled only for very short time intervals (e.g., a few nanoseconds) around the Raman signature, allowing on-chip decoupling to absorb much of the inrush current and prevent IR drop. In such embodiments, lower frequency START, chain, and MemClk signals are distributed by a timing-balanced H-tree arrangement.

[0126] For indirect time-of-flight applications, the H-tree provides uniform sampling of laser pulse information across the entire pixel array. An imager with several shift register bits forms compact indirect time-of-flight pixels for high-resolution imagers without requiring extreme logical scaling at advanced nodes. The pixels are laser-power efficient because the shift registers only operate to capture photons immediately after the laser pulse. For the remaining time until the next laser pulse, data is transferred from dynamic memory to static memory, and the 1 / r^2 characteristic means that return photons from the laser are unavailable.

[0127] Figure 10 depicts a sensing device 1000 according to a further embodiment. Figure 10 shows the hierarchical structure of the device. It will be understood that Figure 10 depicts the stages of the hierarchy, not levels in the sense of layers of a stacked sensor. The bottom stage is the SPAD pixel, the next stage is the macro pixel, the next is a group of P macro pixels sharing a common timing generator, and the next stage is the pixel array and the entire image sensor with readout.

[0128] At the first upper level 1004 of the hierarchy (also called the highest level), the sensing device has multiple SPADs. The upper levels may be located on an outward or outward-facing surface to enable the detection of photons. In this embodiment, the SPADS are provided as part of a macropixel.

[0129] The lowest level, 1002 (also called the bottom level), is provided with processing circuits for the SPAD. In particular, the lowest level contains the SPAD pre-pixel processing circuit (corresponding to the related processing circuit 18a and state memory processing circuit 20a in Figure 2). The pixel processing circuit is understood to include individual recharge processing circuits (including recharge transistors) and D-type shift registers. The lowest layer also contains a shared macropixel processing circuit (a processing circuit shared among N×N SPADs located in corresponding positions in the upper layers) which includes a shared memory (corresponding to shared memory 26), a memory read / write controller (corresponding to memory addressing processing circuit 28), and an increment processing circuit (called an arithmetic logic unit, or ALU, and also corresponding to the memory increment processing circuit 30).

[0130] An intermediate level 1006 (between the upper and lower levels) is provided with an H-tree configuration, substantially as described with reference to Figure 11. The intermediate level also includes a processing circuit shared among arrays of P macro pixels. This shared processing circuit includes a memory addressing processing circuit (corresponding to the address controller 41 in Figure 2) and a clock management processing circuit (corresponding to the clock management processing circuit 44, which includes a shared gate ring oscillator). The clock management processing circuit provides a memclock signal to the macro pixels.

[0131] The device also includes a serial control interface, a stop clock and gate generation processing circuit, an addressing control processing circuit, a read control processing circuit, and processing and read processing circuits, as substantially illustrated with reference to Figure 2. These further components contribute to the operation of the sensing device. In this embodiment, the array of SPADs is addressed in the row direction and read in the column direction. Stop clock and gate generation processing circuit and row addressing processing circuit. The sensing device further includes a column read control unit, and further processing circuits and data pads. A device-wide serial control interface is provided for receiving and sensing external control signals.

[0132] It will be understood that each macropixel (having N×N SPADs) can be represented as having a width of X microns. Therefore, the pitch of the N×N SPADs is X / N microns. A typical non-restrictive value for X is 10 microns, but it will be understood that smaller pitches, such as 3-5 microns, can be achieved.

[0133] As described above, referring to Figure 10, for example, the SPAD and associated shift registers are provided in a spatial distribution, e.g., an array. The operation of the sensing device depends on the delivery and sampling of signals across the sensing device. In some embodiments, the sensing device has signal processing circuits, e.g., timing signal processing circuits, configured to deliver signals across their spatial distribution to the shift registers and SPADs. Figure 11 depicts the arrangement of such a signal delivery processing circuit according to one embodiment, where the signal processing circuit is in an H-tree arrangement.

[0134] The H-tree configuration enables uniform sampling of laser pulse information across the pixel array. The H-tree signaling configuration also enables uniform delivery of timing signals across the pixel array. In particular, the timing signals include clock signals to the shift registers and gate signals to the SPAD processing circuitry. Other timing signals that can be delivered by the H-tree configuration include START, chain, and MemClk signals. Specifically, the clock signals to each shift register, the gate signals (including the common signals mentioned above), and the chain signals are provided by the H-tree configuration. The recharge signal may also be distributed by the H-tree, depending on the operating mode. The chain signal does not need to be distributed by the H-tree, as it is only asserted at a low rate at the start of frame capture or a series of frame captures. In the embodiments described above, the signals using the H-tree configuration are the shift register clock (Clk), recharge, and common signals (one of which has a clock pulse, depending on the high or low spatial resolution mode).

[0135] The H-tree configuration allows two D-type SPAD image arrays to replace the EMCCD, thus facilitating alignment with diffraction grating spectral lines that can be post-processed in software. Furthermore, if time-resolved Raman is to be captured, the laser pulse may be shifted toward the active time bin by an on-chip DLL, and the sensor operates with full spatial / spectral resolution but shorter temporal resolution. If fluorescence lifetime is to be captured, as described above, SPAD / shift registers within macro pixels are chained, reducing spatial / spectral resolution but increasing the number of time bins to capture full exponential decay. In such embodiments, lower frequency START, chain, and MemClk signals are distributed by a timing-balanced H-tree configuration.

[0136] It will be understood that the H-tree provides uniform sampling of laser pulse information across the entire pixel array. An imager with several shift register bits forms compact indirect time-of-flight pixels for high-resolution imagers without requiring extreme logical scaling at advanced nodes. The pixels are laser power efficient because the shift registers only operate to capture photons immediately after the laser pulse. For the remaining time until the next laser pulse, data is transferred from dynamic memory to static memory, and the 1 / r^2 characteristic means that return photons from the laser are unavailable.

[0137] Figures 12 to 16 are timing diagrams of the operation of the sensing device. Figure 12 is a timing diagram of the first operating mode. The timing diagram has two phases: a first data acquisition phase and a second data writing phase. A further phase in which data is transferred from the device follows the data writing phase.

[0138] In Figure 12, the laser fires while multiple SPADs are being recharged. The recharged SPADs are then primed to detect photon detection events. During the data acquisition phase, a clock signal is generated at the first acquisition rate. One of the multiple SPADs (SPAD) during the acquisition phase... <n-1>(A signal is recorded). This triggers a change in the state within the corresponding shift register, as explained with reference to Figure 2.

[0139] At the end of the data acquisition phase, the data writing phase begins. The clock signal changes from a higher rate to a slower rate for the data writing phase. The state of the shift registers represents the timing information and / or event information acquired during the data acquisition phase. Next, the signal Dout from the shift registers is received by the signal routing circuit. Depending on the configuration, this may include multiplexed signals from each individual shift register (per pixel) or from one or more chained groups of shift registers. The signals from the shift registers are then written to shared memory. The address controller and / or increment circuit access the SRAM memory and function to write the collected timing information to memory according to a predetermined write order.

[0140] In Figure 12, the signal access<N*M-1:0> This indicates the addressed SRAM word. This signal can be thought of as a one-shot code from a shift register clocked by MemClk, which has the same period as Clk during memory transfer. The photon is captured in the M preceding Clk cycles before the rising edge of the chain. The position of the laser edge can be adjusted to place the relevant photon within this time interval.

[0141] Figures 13, 14, and 15 are timing diagrams for further non-restrictive modes of operation of the sensing device. In Figure 13, the summation of SPAD counts is performed by correcting the clock rate of Memclk relative to the clock. In this example (for a 4-bin iToF), we provide a photon count per SPAD, and all four time bins are summed together.

[0142] Figure 14 is an exemplary timing diagram of a macropixel with N SPADs when all N SPADs are combined. The summation of SPAD counts is performed by modifying the Memclk clock rate relative to Clk. In this example, all photon counts are summed up over all N SPADs to a single bin (N). This timing allows for photon counting across the entire macropixel.

[0143] Figure 15 illustrates an example of a 4-bin (M=4) iToF where all N SPAD bins are summed into a 4-bin histogram. In this example, the N SPADs are combined into a single SPAD. The timing diagram in Figure 15 allows all N 4-bin shift registers to be aggregated into a single (4-bin) histogram. Thus, the SRAM has a size of N × 4, and therefore each histogram has a size of N.

[0144] Figure 16 illustrates an example where M=1 for photon counting (i.e., each SPAD has a corresponding shift register of size 1). In this example, a recharge signal is placed after the rising edge of the chain to allow each SPAD to sense photons over the entire cycle time (without using laser pulses). In this example, N clock cycles are used to update N memory bins.

[0145] Further comments on the potential non-limited applications of the sensing device are provided below. Firstly, the sensing device may be configured to operate as a time-of-flight sensor. The ability to simultaneously change the time range and time resolution to reconstruct pixels from high spatial resolution to low spatial resolution is a trade-off in indirect time-of-flight imaging, for example. At long distances, high spatial / angular resolution is required, but a larger bin time is acceptable for lower depth accuracy. At short distances, lower spatial / angular resolution is required, and a shorter bin width is needed for better accuracy.

[0146] In a further example, the configurable processing circuit may be pre-configured depending on whether it is capturing Raman photons or fluorescent photons. In the former case, the shift registers are unchained with high temporal resolution (fast clock) to capture fast Raman transient information (typically hundreds of ps). Spatial (equivalent to spectral) resolution is high. In the latter case, the shift registers are chained, and lower temporal resolution (slower clock) is applied. This results in low spectral and temporal resolution with lifetime decay typically exceeding tens of nanoseconds.

[0147] In the embodiments described above, the configuration / reconstruction phase was explained. In some embodiments, reconstruction may be performed on the fly, and it will be understood that reconstruction may be performed within a single clock laser cycle to enable data acquisition at a given depth-related spatial and temporal resolution.

[0148] In a further embodiment, a minimally feasible SPAD macropixel is described. The minimally feasible macropixel has N SPADs, each having an individual recharge transistor and a plurality of state memory elements (shift register type D) per SPAD. A shared clock generator is also provided for the shift registers. Coupling functions (coupling processing circuits) between the SPADs and memory cells are also provided, which may include, for example, a multiplexing arrangement, an OR tree combiner, and a memory address controller. An intrapixel memory bank (shared memory) is also provided, configured to store N words for every M bits. A shared addressing and read mechanism for the memory is also provided (one is shared per macropixel). A memory increment function (ALU, shared per macropixel) is also provided. Such a macropixel may reduce the read rate from E to log2(E) frames / second, where E is the maximum rate of events per second from each SPAD. Furthermore, a TDC is not required, rather two-phase burst storage is performed, followed by transfer to memory (time-divided multi-event TDC).

[0149] It will be understood that the above configuration can be implemented in a variety of applications, including LiDAR, time-of-flight (ToF), and 3D imaging applications.

[0150] It will be understood that the apparatus in the embodiments described above illustrates the exchange between time range and / or depth range and spatial resolution. The choice of spatial resolution arises from coupling photon detectors such that a sensing apparatus having a group of coupled photon detectors acting as a coupled photon detector has a lower spatial resolution than a sensing apparatus having individually operating photon detectors. Similarly, the maximum time (or depth) range depends on the coupling of the corresponding shift registers.

[0151] As a non-limiting example, if the clock speed is kept the same, two or more coupled shift registers may detect photon detection events over longer acquisition periods than each shift register would if it operated individually. In other applications, temporal and / or depth resolution may be exchanged for spatial resolution by coupling shift registers along with modifications to the clock speed / frequency. For example, if the coupling of shift registers involves a corresponding change in the clock frequency (and thus resulting in an increase in temporal and / or depth resolution), the coupled shift register may provide the same maximum range as each individual shift register. For example, doubling the size of a shift register doubles the temporal (or depth) range at the same clock frequency. However, if the clock frequency is also doubled, and therefore the possible depth and / or temporal resolution is doubled, doubling the size of the shift register provides the same maximum temporal (or depth) range. Depending on the application, it will be understood that the depth resolution of a sensing device is related to the temporal resolution.

[0152] In some embodiments, the time range and depth range correspond to the maximum time range or maximum depth range available using the coupled shift register (time corresponds to depth in time-of-flight applications). The time range can be thought of as the total time range available for histogram bins to bin / record photon detection events within a laser cycle. In some embodiments, the time range is equal to the number of coupled shift register elements (flip-flops in each shift register in the embodiments above) multiplied by the clock period. In time-of-flight applications, for example, the depth range is equivalent to the time range and therefore depends on the number of coupled shift register elements (flip-flops in each shift register in the embodiments above) multiplied by the clock period.

[0153] In the embodiments described above, the terms static and dynamic are used. With respect to flip-flops, in embodiments, the term dynamic may refer to the ability to hold and store its state over parasitic capacitance, which will leak if not refreshed. In contrast, in embodiments, static may mean the ability to hold and store its state by feedback without the need for refreshing. These terms are the same as those for dynamic or static memory (DRAM / SRAM). In embodiments, a shift register may consist of dynamic or static flip-flops. In some embodiments, static flip-flops may offer better performance due to the absence of leakage, but they tend to have a larger circuit area.

[0154] In the above embodiment, the multiplexer is located after the D-type flip-flop. In an alternative embodiment, the multiplexer takes the first input from the SPAD (i.e., the signal VSPAD) ) and C <i-1>A second input is provided before the dynamic shift register to obtain from the previous input. The output of the multiplexer is then provided to the dynamic shift register. In such embodiments, a global chain signal is still provided to obtain information from the shift register. In particular, for each pixel, a chain signal is provided to the multiplexer to obtain information from the preceding shift register.

[0155] Figure 17 depicts a SPAD pixel 1200 according to such an embodiment. It will be understood that the SPAD pixel 1200 corresponds to the SPAD pixel 200. In particular, the pixel 1200 comprises a SPAD 1202, a recharge transistor 1204, a clamp diode 1206, a first quench transistor 1208, a second quench transistor 1210, a common anode connection 212, and a dynamic shift register 1214 including a cascade of M D-type flip-flops (1216a, ..., 1216m).

[0156] The SPAD and shift register are connected to the inputs of the 2:1 (two inputs, two outputs) multiplexer 1218. In contrast to Figure 3, in the embodiments of Figures 17-20, the first input to the multiplexer 1218 is the generated voltage VSAP. As mentioned above, when one SPAD in a group of SPADs ignites, the ignited SPAD will have a voltage VSPAD. This generates the signal VSPAD. This is provided as an input to multiplexer 218. The other input to multiplexer 1218 is provided from further SPAD pixels provided on the macro pixels. Further SPAD pixels (not shown) are provided in a chained arrangement with SPAD pixels 1200 (exemplary chained arrangements are depicted in Figures 8a and 8b).

[0157] The input signal from the preceding SPAD pixel (the i-1 pixel) to the multiplexer is C <i-1>This is denoted as follows. The output signal from the multiplexer provided to this SPAD pixel (the i-th pixel) is C This is denoted as follows. The output of the multiplexer is provided to the shift register 1214. The signal read from each shift register (the i-th shift register) is Q.<M,i> This is denoted as an M-sized word. Each SPAD pixel has an M-bit shift register. When coupled and chained with N-pixel macro pixels, the total length of the combined shift register is N × M. The SRAM memory word is provided bit by bit in the combined shift register in shared memory, and therefore shared memory provides N × M for each macro pixel.

[0158] Figures 18 to 20 correspond to embodiments. In particular, Figures 18 to 20 correspond to Figures 4 to 6, in which a 2:1 (two inputs, two outputs) multiplexer 218 is placed between the SPAD and the shift register, as described substantially with reference to Figure 17.

[0159] More specifically, Figure 18 depicts a 4-bin indirect time-of-flight (iToF) embodiment. Figure 4 shows a SPAD pixel 1300 having SPAD 302, a recharge transistor 1304, a clamp diode 1306, a first quench transistor 1308, a second quench transistor 1310, a common anode connection 1312, a dynamic shift register 1314 including a cascade of four D-type flip-flops (1316a, ..., 1316m), and a multiplexer 1318. A chain signal 1320 is provided to the multiplexer 1318.

[0160] Figure 19 shows an example of a 2-bin iToF. Figure 175 depicts a SPAD pixel 1400 having SPAD 1402, a recharge transistor 1404, a clamp diode 1406, a first quench transistor 1408, a second quench transistor 1410, a common anode junction 1412, a dynamic shift register 1414 including a cascade of two D-type flip-flops (1416a, ..., 1416m), and a multiplexer 1418. A chain signal 1420 is supplied to the multiplexer 1418.

[0161] Figure 20 shows a pixel suitable for a photon count image sensor. Figure 20 depicts a SPAD pixel 1500 having a SPAD 1502, a recharge transistor 1504, a clamp diode 1506, a first quench transistor 1508, a second quench transistor 1510, a common anode connection 1512, a dynamic shift register 1514 including a D-type flip-flop 1516a, and a multiplexer 1518. A chain signal 1520 is supplied to the multiplexer 1518.

[0162] In the embodiments described above, a shift register was discussed. It will be understood that shift registers can be coupled to form one or more larger shift registers. Shift registers may be operable to be loaded in parallel or in series. For example, a shift register may be loaded in parallel in response to a photon detection event. In some embodiments, a shift register may be loaded in series in response to a photon detection event. A shift register and its corresponding multiplexer may be operable to operate in either a series-input parallel-output (SIPO) mode or a parallel-input series-output (PISO) mode. In some embodiments, such a device may be provided with shared memory, such as SRAM or shared DRAM, and configured to efficiently map or transfer data from the shift register to the SRAM or DRAM. Such a device of shift registers, photon detectors, and shared memory may offer advantages in terms of density when forming an array, and may provide a higher density arrangement.

[0163] In some embodiments, the shift register and the corresponding multiplexer may be operable to operate in either series-input parallel-output (SIPO) mode or parallel-input series-output (PISO) mode. In further embodiments, the device is configured to operate in parallel-input / parallel-output (PIPO) mode, having logic suitable for addressing shared module memory (for addressing SRAM words).

[0164] In the embodiments described above, photons are sampled by a shift register and subsequently transferred to shared memory. Sharing memory between shift registers can reduce the pixel area. Furthermore, sampling using a shift register can enable both high dynamic range and direct time-of-flight modes in a single sensing device.

[0165] Those skilled in the art will understand that variations of the disclosed configurations are possible without departing from the scope of the present invention. Therefore, the above description of specific embodiments is provided only as examples and is not intended to limit them. Those skilled in the art will see that minor modifications can be made without substantially altering the described operations.

Claims

1. A photon sensing device for photon sensing, Multiple photon detectors connected to multiple shift registers, provided as part of a configurable processing circuit that can be configured to combine two or more of the multiple shift registers and combine two or more photon detectors to form one or more coupled shift registers and one or more coupled photon detectors, respectively. A device equipped with the following features.

2. The apparatus according to claim 1, wherein at least two or more of the plurality of shift registers and the two or more photon detectors provide an exchange between time or depth range and / or resolution and spatial resolution.

3. The apparatus according to any of the preceding claims, further comprising a shared memory module, for example, an SRAM or DRAM memory module, which is shared among at least a portion of the configurable circuits and is configured to store data representing spatial information and / or timing information and / or count information from at least a portion of the configurable circuits.

4. The apparatus according to any of the preceding claims, wherein at least two of the plurality of shift registers, preferably at least three of the plurality of shift registers, are connected to the shared memory module.

5. The apparatus according to claim 3 or 4, wherein the shared memory module can be configured to select a data structure for storing spatial information and / or timing information and / or count information from at least a portion of the reconfigurable circuit, and the data structure is selected to correspond to the temporal resolution and / or depth resolution and / or acquisition period and / or spatial resolution of at least a portion of the reconfigurable circuit.

6. The apparatus according to any one of claims 3 to 5, wherein the plurality of shift registers are provided with dynamic memory and the shared memory module is provided with static memory.

7. The apparatus according to any of the preceding claims, wherein the plurality of photon detectors, the plurality of shift registers and / or the shared memory block are provided in a layered structure.

8. The apparatus according to any one of the preceding claims, wherein the configurable processing circuit is controllable by one or more configuration signals to couple the plurality of photon detectors and / or the plurality of shift registers.

9. The apparatus according to any of the preceding claims, wherein the time or depth range or resolution is adjustable by selecting the characteristics of one or more clock signals provided to the plurality of shift registers, e.g., speed and / or frequency.

10. The apparatus according to any of the preceding claims, wherein the plurality of photon detectors include a plurality of single-photon detectors, for example, a plurality of SPADs.

11. The apparatus according to any of the preceding claims, wherein the coupled photon detector includes a group of photon detectors that operate together as single photon detectors and detect photons over a larger spatial region than each individual photon detector in the group of photon detectors, and / or the coupled shift register includes a group of shift registers that operate together as a single shift register and provide a longer acquisition period than each individual shift register in the group of shift registers.

12. The apparatus according to any of the preceding claims, wherein the configurable processing circuit comprises a signal routing processing circuit for the plurality of shift registers, the signal routing processing circuit is selectively operable to route signals for the shift registers, thereby combining output signals from one or more of the plurality of shift registers.

13. The apparatus according to any of the preceding claims, wherein the shift registers are provided in a linear or series arrangement, and optionally the output of the first shift register is selectively provided as an input to a further shift register.

14. The apparatus according to any of the preceding claims, wherein the plurality of shift registers are arranged in a chain configuration that allows two or more of the shift registers to be selectively chained together to form one or more combined shift registers.

15. The apparatus includes the plurality of shift registers, such as dynamic shift registers.

16. The apparatus according to any one of the preceding claims, wherein the photon sensing device comprises a shared photon detection processing circuit that can be configured to perform a shared recharge operation and / or quench operation for each coupled photon detector.

17. The apparatus according to claim 16, wherein the photon detection processing circuit comprises at least one shared anode and / or at least one recharge transistor between photon detectors.

18. The apparatus according to any of the preceding claims, wherein at least one of the plurality of photon detection devices and at least one of the plurality of shift registers are provided together as part of an array of pixel elements, and optionally each array of pixel elements includes one photon detector and a corresponding shift register.

19. The apparatus according to any of the preceding claims, further comprising a plurality of further array-like macropixel elements, wherein each macropixel element includes a plurality of array-like pixel elements together with a shared memory module.

20. The apparatus according to claim 19, further comprising a further shared resource shared among two or more of the macro pixels, for example, a gate ring oscillator.

21. The apparatus according to any of the preceding claims, wherein the plurality of photon detectors and shift registers are in a spatial distribution, and the sensing device comprises a signal transmission processing circuit, such as a timing signal transmission processing circuit, configured to provide one or more signals to the plurality of shift registers and / or the plurality of photon detectors across the spatial distribution, and the signal transmission processing circuit is in an H-tree arrangement.

22. The configurable processing circuit is configurable in at least a first configuration and a second configuration, In the first configuration described above, each coupled photon detector is connected to a corresponding coupled shift register, and the coupled photon detector is configured to modify the connected coupled shift register in response to a photon detection event so that the connected coupled shift register stores photon detection event information. The apparatus according to any of the preceding claims, wherein each photon detector is coupled to a corresponding shift register, and the photon detector is configured to modify the coupled shift register in response to a photon detection event so that the coupled shift register stores information about the photon detection event.

23. The apparatus according to any of the preceding claims, wherein the first configuration includes a first temporal resolution and a first spatial resolution, and the second configuration has a second temporal resolution and a second spatial resolution, wherein the first spatial resolution is lower than the second spatial resolution and the first temporal resolution is higher than the second temporal resolution.

24. The apparatus according to any of the preceding claims, wherein the configurable processing circuit is operable to be reconfigured within a single clock laser cycle to enable data acquisition with a predetermined depth-related spatial resolution and / or temporal resolution.

25. The configuration of a photon sensing device includes combining two or more of a plurality of shift registers and combining two or more of a plurality of photon detectors to form one or more combined shift registers and one or more combined photon detectors, respectively. Operate the aforementioned photon sensing device to perform the photon sensing process. Methods that include...

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