Semiconductor devices and methods for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same. The method includes the steps of: preparing a substrate and forming a drift region on the substrate; forming a plurality of channel spacing regions in the drift region such that channel regions are formed with spacing between each of the two channel spacing regions; forming a source contact region, a drain contact region and a gate contact region in the drift region, and forming a substrate contact region on the substrate with spacing between it and the drift region, wherein the gate contact region is located between the source contact region and the drain contact region, and the source contact region and the drain contact region are in communication via a channel region. In the solution of the present invention, a plurality of channel spacing regions are formed such that channel regions are formed with spacing between each of the two channel spacing regions, thereby adjusting the width of the channel regions to adjust the pinch-off voltage of the device, ensuring that the device has a sufficiently high on-current when it is turned on, further reducing the on-resistance of the device, reducing the power consumption of the device, and improving the performance of the device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductors, and specifically, to semiconductor devices and manufacturing methods thereof.

Background Art

[0002] With the continuous development of integrated circuits, in order to save area, it has become common to simultaneously manufacture multiple devices on the same substrate. For example, in a BCD (Bipolar-CMOS-DMOS) process, high-voltage power devices such as bipolar transistors (Bipolar), complementary metal-oxide semiconductors (CMOS), and diffused metal-oxide semiconductors (DMOS) can be manufactured on the same substrate. The BCD process has already been widely applied in fields such as mobile devices, household appliances, displays, automobiles, and data centers.

[0003] The junction field-effect transistor (JFET) is a device commonly used in the BCD process. It has a very high input impedance, enables a high degree of separation between the input circuit and the output circuit, and there is no inherent noise of electron tubes and transistors. Furthermore, since it has a negative temperature coefficient, the risk of thermal runaway can be avoided. In addition, it has a very high power gain.

[0004] In a JFET, the pinch-off voltage is a very important parameter and plays an important role in adjusting the current from the source to the drain and controlling the operating state of the JFET. However, in the related art, the pinch-off voltage of the JFET generally cannot be controlled, or if it can be controlled, when the pinch-off voltage is small, the on-current of the JFET becomes low, resulting in an increase in the on-resistance of the JFET, further increasing the power consumption in the practical use of the JFET and degrading the device performance.

Summary of the Invention

[0005] The summary section of the invention introduces a set of simplified concepts, which will be described in more detail in the section on embodiments for carrying out the invention. The summary section of the invention is not intended to identify any important or necessary features of the technical solution for which protection is claimed, nor is it intended to determine the scope of the technical solution for which protection is claimed.

[0006] In contrast to the conventional problems, in one aspect of the present invention, A substrate having a first conductivity type, A drift region extending from the first surface of the substrate to the interior of the substrate and having a second conductivity type, A plurality of channel spacing regions located in the drift region and exposed to the first surface, having a first conductivity type, wherein a channel region is formed between two adjacent channel spacing regions, with a gap between each of them. A source contact region, a drain contact region, and a gate contact region located in the drift region, wherein the gate contact region is located between the source contact region and the drain contact region, the source contact region and the drain contact region are in communication with each other by the channel region, the source contact region and the drain contact region have the second conductivity type, and the gate contact region has the first conductivity type. The present invention provides a semiconductor device comprising a substrate contact region having the first conductivity type, which is located within the substrate and spaced apart from the drift region.

[0007] In one embodiment, the drain contact region and the gate contact region are annular, the gate contact region surrounds the outside of the source contact region, the drain contact region surrounds the outside of the gate contact region, or The source contact region and the gate contact region are annular, the gate contact region surrounds the outside of the drain contact region, and the source contact region surrounds the outside of the gate contact region.

[0008] In one embodiment, the semiconductor device is A first field oxide layer and a second field oxide layer located in the drift region, wherein the first field oxide layer is located between the gate contact region and the drain contact region, and the second field oxide layer is located between the gate contact region and the source contact region, A first gate structure and a second gate structure, further comprising: the first gate structure located on the first field oxide layer and partially extending over the drift region; and the second gate structure located on the first field oxide layer and on the side of the first gate structure closer to the drain contact region.

[0009] In one embodiment, the second gate structure is a floating gate structure.

[0010] In one embodiment, the semiconductor device further includes a source change region and a drain change region located in the drift region, the source contact region is located in the source change region, the drain contact region is located in the drain change region, and the source contact region and the drain contact region have the second conductivity type.

[0011] In another embodiment of the present invention, The steps include: preparing a substrate having a first conductivity type, The steps include forming a drift region having a second conductivity type that extends from the first surface of the substrate to the interior of the substrate, The steps include forming a plurality of channel spacing regions having the first conductivity type in the drift region such that channel regions are formed with spacing between each of the two channel spacing regions, A method for manufacturing a semiconductor device is provided, comprising the steps of forming a source contact region having a second conductivity type, a drain contact region and a gate contact region having a first conductivity type in the drift region, and forming a substrate contact region having a first conductivity type on the substrate at a distance from the drift region, wherein the gate contact region is located between the source contact region and the drain contact region, and the source contact region and the drain contact region are in communication through the channel region.

[0012] In one embodiment, the drain contact region and the gate contact region are annular, the gate contact region surrounds the outside of the source contact region, the drain contact region surrounds the outside of the gate contact region, or The source contact region and the gate contact region are annular, the gate contact region surrounds the outside of the drain contact region, and the source contact region surrounds the outside of the gate contact region.

[0013] In one embodiment, the method is A step of forming a first field oxide layer and a second field oxide layer within the drift region, wherein the first field oxide layer is located between the gate contact region and the drain contact region, and the second field oxide layer is located between the gate contact region and the source contact region, A step of forming a first gate structure and a second gate structure, further comprising the steps of: the first gate structure being located on the first field oxide layer and partially extending over the drift region; and the second gate structure being located on the first field oxide layer and on the side of the first gate structure closer to the drain contact region.

[0014] In one embodiment, the second gate structure is a floating gate structure.

[0015] In one embodiment, before forming the source contact region and the drain contact region, the method is The method further includes forming a source change region and a drain change region having a second conductivity type in the drift region, wherein the source contact region is located in the source change region and the drain contact region is located in the drain change region.

[0016] According to an embodiment of the present invention, a semiconductor device and a method for manufacturing the same are formed such that a plurality of channel spacing regions are formed with spacing between each of two adjacent channel spacing regions, and each channel region can be pinched off in two directions. By adjusting the width of the channel region, the pinch-off voltage of the device can be adjusted, and a sufficiently high on-current can be ensured when the device is turned on. Furthermore, the on-resistance of the device is reduced, the power consumption of the device is reduced, and the performance of the device is improved. [Brief explanation of the drawing]

[0017] The following drawings of the present invention are used to help understand the present invention as part of the present invention. Embodiments and descriptions thereof are shown in the drawings to illustrate the principles of the present invention. [Figure 1] A flowchart of a method for manufacturing a semiconductor device according to one specific embodiment of the present invention is shown. [Figure 2A] This diagram shows a schematic cross-sectional view of a semiconductor device obtained by sequentially carrying out a method for manufacturing a semiconductor device according to one specific embodiment of the present invention. [Figure 2B] This diagram shows a schematic cross-sectional view of a semiconductor device obtained by sequentially carrying out a method for manufacturing a semiconductor device according to one specific embodiment of the present invention. [Figure 2C] This diagram shows a schematic cross-sectional view of a semiconductor device obtained by sequentially carrying out a method for manufacturing a semiconductor device according to one specific embodiment of the present invention. [Figure 2D] This diagram shows a schematic cross-sectional view of a semiconductor device obtained by sequentially carrying out a method for manufacturing a semiconductor device according to one specific embodiment of the present invention. [Figure 2E]A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to one specific embodiment of the present invention is shown. [Figure 2F] A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to one specific embodiment of the present invention is shown. [Figure 2G] A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to one specific embodiment of the present invention is shown. [Figure 2H] A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to one specific embodiment of the present invention is shown. [Figure 2I] A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to one specific embodiment of the present invention is shown. [Figure 2J] A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to one specific embodiment of the present invention is shown. [Figure 3] A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to another specific embodiment of the present invention is shown. [Figure 4] A layout schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to one specific embodiment of the present invention is shown. [Figure 5] A plan view of a semiconductor device according to one specific embodiment of the present invention at pinch-off is shown. [Figure 6] A plan view of a semiconductor device according to another specific embodiment of the present invention at pinch-off is shown. [Figure 7] A cross-sectional schematic diagram of a semiconductor device according to one specific embodiment of the present invention at pinch-off is shown. [Figure 8] A cross-sectional schematic diagram of a semiconductor device according to another specific embodiment of the present invention is shown. [Figure 9] A cross-sectional schematic diagram of a semiconductor device according to another specific embodiment of the present invention at pinch-off is shown. [Modes for carrying out the invention]

[0018] The present invention will be described in more detail below with reference to the drawings, which illustrate embodiments of the invention. However, the present invention can be carried out in different forms and should not be construed as being limited to the embodiments described herein. On the contrary, providing these embodiments makes the disclosure thorough and comprehensive and fully communicates the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions of layers and areas and relative dimensions may be exaggerated. The same reference numerals in the drawings represent the same elements from beginning to end.

[0019] It should be understood that when an element or layer is said to be "on top of," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be an intermediate element or layer. Conversely, when an element is said to be "directly on top of," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there is no intermediate element or layer. It should be understood that various elements, components, regions, layers, and / or parts can be described using terms such as first, second, third, etc., but these elements, components, regions, layers, and / or parts should not be limited to these terms. These terms are merely for distinguishing one element, component, region, layer, or part from another element, component, region, layer, or part. Accordingly, without departing from the implications of the present invention, the first element, component, region, layer, or part considered below may be represented as the second element, component, region, layer, or part.

[0020] Spatial relation terms such as "...below," "...located below," "below," "below," "...on top," and "above" can be used here, for the sake of explanation, to describe the relationship between one element or feature shown in the diagram and another element or feature. It should be understood that, in addition to the directions shown in the diagram, spatial relation terms are intended to further encompass different directions of the device during use and operation. For example, if the device in the drawing is turned upside down, the direction of an element or feature described as "below another element," "below it," or "below" changes to "above" the other element or feature. Thus, exemplary terms such as "...below" and "...below" may include two directions, up and down. The device may adopt other directions (90-degree rotation or other directions), and the spatial descriptive terms used here are interpreted correspondingly.

[0021] The purpose of the terms used herein is not to limit the invention, but to describe specific embodiments. When used herein, the singular forms “one,” “one,” and “the said / the said” are also intended to include the plural form unless the context clearly indicates otherwise. Furthermore, it should be understood that when used in this specification, the terms “consist of” and / or “include” clarify the existence of the described features, integers, steps, operations, elements, and / or components, but do not preclude the existence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the relevant items listed.

[0022] This specification describes embodiments of the present invention with reference to cross-sectional views serving as schematic diagrams of ideal embodiments (and intermediate structures) of the present invention. Thus, variations in the shown shape are expected, for example, due to manufacturing techniques and / or tolerances. Therefore, embodiments of the present invention should not be limited to specific shapes of the regions shown herein, and may include, for example, manufacturing deviations. For example, an injection region shown as a rectangle typically has circular or curved features and / or a gradient of injection concentration at its edges, rather than a binary change from the injection region to the non-injected region. Similarly, an embedded region formed by injection may result in some injection in the region between the embedded region and the injected surface. Therefore, the regions shown in the drawings are substantially schematic, and their shapes are not intended to represent the actual shapes of the regions of the device, nor are they intended to limit the scope of the present invention.

[0023] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as those generally understood by those skilled in the art. Furthermore, terms such as those defined in commonly used dictionaries should be understood to have the meaning consistent with their meaning in the relevant field and / or in the context of this specification, and not to be interpreted as ideal or overly formal unless explicitly defined herein.

[0024] To fully understand the present invention, the following description will provide detailed steps and structures to illustrate the technical solutions provided by the present invention. Preferred embodiments of the present invention will be described in detail below, but the present invention may have other embodiments besides those described in detail.

[0025] In view of the above technical challenges, embodiments of the present invention are as follows: A substrate having a first conductivity type, A drift region extending from the first surface of the substrate to the interior of the substrate and having a second conductivity type, A plurality of channel spacing regions located in the drift region and exposed to the first surface, having a first conductivity type, wherein a channel region is formed between two adjacent channel spacing regions, with a gap between each of them. A source contact region, a drain contact region, and a gate contact region located in the drift region, wherein the gate contact region is located between the source contact region and the drain contact region, the source contact region and the drain contact region are in communication with each other by the channel region, the source contact region and the drain contact region have the second conductivity type, and the gate contact region has the first conductivity type. The present invention provides a semiconductor device comprising a substrate contact region having the first conductivity type, which is located within the substrate and spaced apart from the drift region.

[0026] The present invention The steps include: preparing a substrate having a first conductivity type, and forming a drift region having a second conductivity type that extends from the first surface of the substrate to the interior of the substrate; The steps include forming a plurality of channel spacing regions having a first conductivity type in the drift region such that channel regions are formed with spacing between each of two adjacent channel spacing regions, Further, we propose a method for manufacturing a semiconductor device, which mainly includes the steps of forming a source contact region having a second conductivity type, a drain contact region and a gate contact region having a first conductivity type in the drift region, and forming a substrate contact region having a first conductivity type that extends from the first surface of the substrate to the inside of the substrate, spaced apart from the drift region, wherein the gate contact region is located between the source contact region and the drain contact region, and the source contact region and the drain contact region are in communication through the channel region.

[0027] According to an embodiment of the present invention, a semiconductor device and a method for manufacturing the same are formed such that a plurality of channel spacing regions are formed with a gap between each of two adjacent channel spacing regions, and each channel region has a current path formed by connecting the source contact region and the drain contact region, thereby adjusting the width of the channel region to adjust the pinch-off voltage of the device and ensuring that the device has a sufficiently high on-current when it is turned on, further reducing the on-resistance of the device, reducing the power consumption of the device, and improving the performance of the device.

[0028] Example 1 The method for manufacturing a semiconductor device according to the present invention will be described in detail below with reference to Figures 1 to 9. Here, Figure 1 shows a flowchart of the method for manufacturing a semiconductor device according to one specific embodiment of the present invention, Figures 2A to 2J show schematic cross-sectional diagrams of a semiconductor device obtained by sequentially carrying out the method for manufacturing a semiconductor device according to one specific embodiment of the present invention, Figure 3 shows a schematic cross-sectional diagram of a semiconductor device obtained by sequentially carrying out the method for manufacturing a semiconductor device according to another specific embodiment of the present invention, Figure 4 shows a schematic layout diagram of a semiconductor device obtained by sequentially carrying out the method for manufacturing a semiconductor device according to one specific embodiment of the present invention, Figure 5 shows a schematic plan view of a semiconductor device in pinch-off mode according to one specific embodiment of the present invention, Figure 6 shows a schematic plan view of a semiconductor device in pinch-off mode according to another specific embodiment of the present invention, Figure 7 shows a schematic cross-sectional diagram of a semiconductor device in pinch-off mode according to one specific embodiment of the present invention, Figure 8 shows a schematic cross-sectional diagram of a semiconductor device according to another specific embodiment of the present invention, and Figure 9 shows a schematic cross-sectional diagram of a semiconductor device in pinch-off mode according to another specific embodiment of the present invention.

[0029] Exemplary, a method for manufacturing a semiconductor device according to an embodiment of the present invention includes the following steps.

[0030] First, a substrate having a first conductivity type is prepared, and step S1 is performed to form a drift region having a second conductivity type that extends from the first surface of the substrate into the substrate.

[0031] Exemplary, the semiconductor device of this application includes a JFET device, and the semiconductor device may be any suitable device well known to those skilled in the art. In this embodiment, the technical solution of this application will be interpreted and explained primarily using the example that the semiconductor device is a JFET device.

[0032] In one example, as shown in Figure 2A, the substrate 200 may comprise at least one of Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors, or the substrate 200 may comprise silicon on an insulator (SOI), multilayer silicon on an insulator (SSOI), multilayer silicon germanize on an insulator (S-SiGeOI), silicon germanize on an insulator (SiGeOI), or germanium on an insulator (GeOI). While several examples of materials that can form the substrate 200 are described herein, any material usable as the substrate 200 is included in the spirit and scope of this application.

[0033] Exemplary, the substrate 200 includes a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate. Selectively, the semiconductor substrate and the epitaxial layer may have the same conductivity type. Exemplary, the semiconductor substrate and the epitaxial layer may have different doping concentrations; for example, the doping concentration of the epitaxial layer may be lower than that of the semiconductor substrate. Exemplary, the substrate 200 has a first conductivity type, which may be N-type or P-type.

[0034] In one example, as shown in Figure 2A, the process further includes forming a shallow trench isolation structure 201 before forming the drift region 202. Exemplarily, the step of forming the shallow trench isolation structure 201 may include etching the substrate 200 from a first surface of the substrate 200 to a predetermined depth to form shallow trenches, and forming a silicon oxide layer within the shallow trenches to form the shallow trench isolation structure 201. Exemplarily, the shallow trench isolation structure 201 is located between the active regions of the device.

[0035] In one example, as shown in Figure 2B, a drift region 202 having a second conductivity type is formed extending from a first surface of the substrate 200 into the substrate 200. Specifically, the drift region 202 may be formed by the steps of: forming a patterned mask layer on the first surface of the substrate 200; performing an ion implantation process using the mask layer as a mask to form the drift region 202; and finally removing the mask layer. Exemplarily, the mask layer includes a photoresist layer. Exemplarily, when the first conductivity type is a P-type conductivity type, the second conductivity type is an N-type conductivity type, and when the first conductivity type is an N-type conductivity type, the second conductivity type is a P-type conductivity type. Exemplarily, the drift region 202 has a lower resistivity because it has a higher doping concentration than the substrate 200. Exemplarily, the drift region 202 is located within the active region of the device.

[0036] As shown in Figure 2D, after forming the drift region 202 and before performing step S2, the method of the present application further includes the step of forming a first implanted region 204 having a second conductivity type in the drift region 202. Specifically, the first implanted region 204 may be formed by the steps of forming a patterned mask layer, performing an ion implantation process using the mask layer as a mask to form the first implanted region 204, and finally removing the mask layer. Exemplarily, the mask layer includes a photoresist layer. Exemplarily, the first implanted region 204 can have a higher doping concentration than the drift region 202, thereby further reducing its resistivity.

[0037] Next, step S2 is performed to form a plurality of channel spacing regions having a first conductivity type in the drift region, such that channel regions are formed with a gap between each of two adjacent channel spacing regions.

[0038] Specifically, as shown in Figures 2E, 4, 5, and 6, a plurality of channel spacing regions 205 having a first conductivity type are formed in the drift region 202, the plurality of channel spacing regions 205 are exposed on the first surface of the substrate and are spaced apart along the first surface of the substrate, a channel region is formed between two adjacent channel spacing regions 205 with a gap between them, and a first injection region 204 is formed in the drift region 202, in which case the gap between the two channel spacing regions 205 is the first injection region 204, or the first injection region 204 between the two channel spacing regions 205 is a channel region.

[0039] In one example, as shown in Figure 2E, the channel spacing region 205 may be formed by the steps of forming a patterned mask layer, performing an ion implantation process using the mask layer as a mask to form the channel spacing region 205, and finally removing the mask layer. Exemplarily, the mask layer includes a photoresist layer.

[0040] In one example, as shown in Figures 2E, 5, and 6, the depth of the channel spacing region 205 is smaller than the depth of the drift region 202, and furthermore, the depth of the channel spacing region 205 is even smaller than the first injection region 204. In this case, the first injection region 204 and the drift region 202 between the channel spacing region 205 and the substrate 200 are also channel regions. In another example, the depth of the channel spacing region 205 may be greater than or equal to the depth of the drift region 202. In this case, the channel region is located between two adjacent channel spacing regions 205.

[0041] Next, as shown in Figure 2H, step S3 is performed to form a source contact region 211 and a drain contact region 210 having a second conductivity type in the drift region, and to connect the source contact region 211 and the drain contact region 210 by a channel region. Specifically, the source contact region 211 and the drain contact region 210 may be formed by the steps of forming a patterned mask layer, performing an ion implantation process using the mask layer as a mask to form the source contact region 211 and the drain contact region 210, and finally removing the mask layer. Exemplarily, the mask layer includes a photoresist layer.

[0042] As shown in Figure 2I, a gate contact region 212 having a first conductivity type is formed in the drift region, and a substrate contact region 213 having a first conductivity type is formed on the substrate 200, extending from the first surface of the substrate 200 into the substrate 200. The gate contact region 212 is located between the source contact region 211 and the drain contact region 210, and the substrate contact region 213 and the drift region 202 are spaced apart from each other. Specifically, the gate contact region 212 and the substrate contact region 213 can be formed by the steps of forming a patterned mask layer, performing an ion implantation process using the mask layer as a mask to form the gate contact region 212 and the substrate contact region 213, and finally removing the mask layer. Exemplarily, the mask layer includes a photoresist layer. Exemplarily, the source contact region 211, the drain contact region 210, the gate contact region 212, and the substrate contact region 213 are all highly doped regions, thereby effectively reducing the contact resistance when subsequently electrically connected to the contact plug 214. For example, the substrate contact area 213 is located between shallow trench separation structures 201.

[0043] In one example, as shown in Figures 2C and 2G, the method of the present application further includes the steps of forming a first field oxide layer 2031 and a second field oxide layer 2032 in a drift region 202, wherein the first field oxide layer 2031 is located between the gate contact region 212 and the drain contact region 210, and the second field oxide layer 2032 is located between the gate contact region 212 and the source contact region 211; and forming a first gate structure 2091 and a second gate structure 2092, wherein the first gate structure 2091 is located on the first field oxide layer 2031 and partially extends over the drift region 202, and the second gate structure 2092 is located on the first field oxide layer 2031 and is located on the side of the first gate structure 2091 closer to the drain contact region 210.

[0044] Exemplary, the first field oxide layer 2031 and the second field oxide layer 2032 may be formed by any suitable method well known to those skilled in the art, for example, by thermal oxidation.

[0045] Exemplary, both the first gate structure 2091 and the second gate structure 2092 include a gate layer and sidewalls located on both sides of the gate layer. Exemplary, the gate layer is composed of a polycrystalline silicon material, and generally, metals, metal nitrides, metal silicides, or similar compounds may be used as the gate layer material. Exemplary, the material of the sidewalls includes insulating materials such as silicon nitride, silicon oxide, or silicon oxynitride, and the sidewalls may be in a single-layer or multi-layer structure.

[0046] In one example, as shown in Figure 2J, the gate contact region 212 and the first gate structure 2091 are electrically connected to the same external metal layer via contact plugs to form a gate. That is, the gate contact region 212 and the first gate structure 2091 are electrically connected via contact plugs. When a bias voltage is applied to the gate, the first gate structure 2091 and the first field oxide layer 2031 can form a bias field plate structure, thereby increasing the average electric field of the drift region 202, decreasing the electric field peak value, suppressing the hot carrier effect, and achieving objectives such as increasing the breakdown voltage. Exemplarily, the second gate structure 2092 is a floating gate structure. That is, the second gate structure 2092 does not need to be connected to an external electrode. The second gate structure 2092 can form a floating field plate structure together with the first field oxide layer 2031, making the electric field distribution in the drift region 202 more uniform and ensuring that corners where the electric field is concentrated are less likely to break down, thereby further increasing the breakdown voltage.

[0047] In one example, as shown in Figure 2J, the contact plug 214 further electrically connects the source contact region 211 to the outer metal layer to form a source, the contact plug 214 further electrically connects the drain contact region 210 to the outer metal layer to form a drain, and at the same time, the contact plug 214 further electrically connects the substrate contact region 213 to the outer metal layer so that the substrate 200 is pulled out and a substrate edge is formed. Exemplary materials for the contact plug 214 include, but are not limited to, copper, tungsten, gold, silver, and aluminum.

[0048] In one example, as shown in Figure 2F, before forming the source contact region 211 and the drain contact region 210, the method of the present application further includes the step of forming a source de-converting region 208 and a drain de-converting region 207 having a second conductivity type in the drift region 202, the source contact region 211 being located in the source de-converting region 208 and the drain contact region 210 being located in the drain de-converting region 207. Specifically, the source de-converting region 208 and the drain de-converting region 207 may be formed by the steps of forming a patterned mask layer, performing an ion implantation process using the mask layer as a mask to form the source de-converting region 208 and the drain de-converting region 207, and finally removing the mask layer. Exemplarily, the mask layer includes a photoresist layer. For example, the doping concentration of the source slow-change region 208 is smaller than that of the source contact region 211, and the doping concentration of the drain slow-change region 207 is smaller than that of the drain contact region 210. By forming the source slow-change region 208 and the drain slow-change region 207, the antistatic performance of the device can be improved, the phenomenon of excessive carrier concentration can be effectively altered, and the thermoelectric effect can be effectively mitigated. For example, first, the first field oxide layer 2031 and the second field oxide layer 2032 may be formed, then the source slow-change region 208 and the drain slow-change region 207 may be formed, and then the first gate structure 2091 and the second gate structure 2092 may be formed.

[0049] In one example, as shown in Figure 2E, the method of the present application further includes the step of forming a second implantation region 206 on a substrate 200, wherein the substrate contact region 213 is located in the second implantation region 206. Specifically, the second implantation region 206 may be formed by the steps of forming a patterned mask layer, performing an ion implantation process using the mask layer as a mask to form the second implantation region 206, and finally removing the mask layer. Exemplarily, the mask layer includes a photoresist layer. Exemplarily, the second implantation region 206 has a first conductivity type.

[0050] In one example, referring together to Figures 2J and 4, the drain contact region 210 and the gate contact region 212 are annular, the gate contact region 212 surrounds the outside of the source contact region 211, and the drain contact region 210 surrounds the outside of the gate contact region 212. Alternatively, as shown in Figure 3, the source contact region 211 and the gate contact region 212 are annular, the gate contact region 212 surrounds the outside of the drain contact region 210, and the source contact region 211 surrounds the outside of the gate contact region 212. Here, Figure 3 shows a cross-sectional view of a semiconductor device according to another embodiment of the present application, which can achieve the same functionality as the semiconductor device obtained in Figures 2A to 2J. Such an annular surrounding structure can effectively save device area. Exemplarily, in this case, the first gate structure 2091 and the second gate structure 2092 are also annular structures. For example, as shown in Figure 5, the gate contact region 212 may not be located in the first injection region 204, but rather in the channel spacing region 205, in which case the entire gate contact region 212 is an annular shape with spacing between them.

[0051] In one example, each of the regions formed by the ion implantation process is subjected to a rapid temperature-up annealing process immediately after the ion implantation process, thereby activating the dopants in the ion-implanted regions and simultaneously repairing the lattice structure damaged during the ion implantation process.

[0052] In one example, to meet actual demands, the pinch-off voltage of the device can be adjusted by adjusting the width of the channel region between the channel spacing regions 205.

[0053] In one example, as shown in Figure 5, the gate contact region 212 may not be located in the first injection region 204, but rather in the channel spacing region 205. Alternatively, as shown in Figure 6, the gate contact region 212 may be located in both the channel spacing region 205 and the first injection region 204.

[0054] In one example, as shown in Figures 4, 5, and 6, taking the case where the first conductivity type is P-type and the second conductivity type is N-type, when no reverse bias voltage is applied to the gate and substrate edge, current can flow from the source through the channel region between the channel spacing regions 205 to the drain. In this application, since channel regions are formed between the channel spacing regions 205, multiple current paths can be formed, thereby ensuring that the device still has a high on-current when it has a small pinch-off voltage, further reducing the on-resistance of the device, reducing the power consumption of the device, and improving the performance of the device. When a reverse bias voltage is applied to the gate and substrate edge, the depletion layer between the channel spacing region 205 and the channel region gradually expands until it completely occupies the channel region. At this time, the channel region is pinched off, and the device is also in a pinch-off state. The arrows shown in Figures 5 and 6 indicate the direction in which the depletion layer pinches off the channel region.

[0055] Exemplary, as shown in Figure 7, when the depth of the channel spacing region 205 is less than the depth of the drift region 202, a channel region can be formed between the channel spacing region 205 and the substrate 200, and this channel region can also form a current path, thereby further increasing the on-current of the device. The arrow in Figure 7 indicates the direction in which the depletion layer pinches off the channel region between the channel spacing region 205 and the substrate 200. Exemplary, as shown in Figure 8, when the depth of the channel spacing region 205 is greater than or equal to the depth of the drift region 202, a channel region cannot be formed between the channel spacing region 205 and the substrate 200.

[0056] Furthermore, as shown in Figure 9, when the gate contact region 212 is located in the channel spacing region 205 and the first injection region 204, the conductivity types of the gate contact region 212 and the substrate 200 are both P-type between adjacent channel spacing regions 205, and the conductivity type of the first injection region 204 between them is N-type. Therefore, a channel region can also be formed between the gate contact region 212 and the substrate 200. Specifically, the first injection region 204 between the gate contact region 212 and the substrate 200 can form a channel region, and the channel spacing regions 205 on both sides of the gate contact region 212, the substrate 200, and the first injection region 204 simultaneously pinch off the channel region between the gate contact region 212 and the substrate 200. The arrow in Figure 9 indicates the direction in which the depletion layer pinches off the channel region between the gate contact region 212 and the substrate 200.

[0057] This concludes the explanation of the important steps of the semiconductor device manufacturing method of the present invention. The manufacturing of a complete semiconductor device may include other steps, which are omitted here in detail, and it should be noted that the order of the above steps can be adjusted on the premise that they do not conflict.

[0058] As described above, according to the semiconductor device manufacturing method of the embodiment of the present invention, multiple channel spacing regions are formed such that channel regions are spaced apart between two channel spacing regions, and each channel region connects a source contact region and a drain contact region to form a current path, that is, multiple current paths can be formed, thereby adjusting the pinch-off voltage of the device by adjusting the width of the channel regions, ensuring that the device has a sufficiently high on-current when it is turned on, further reducing the on-resistance of the device, reducing the power consumption of the device, and improving the performance of the device. Exemplarily, when the depth of the channel spacing region is smaller than the depth of the drift region, a channel region can also be formed between the channel spacing region and the substrate to form a current path, further increasing the on-current of the device. Exemplarily, the drain contact region and the gate contact region are annular, the gate contact region surrounds the outside of the source contact region, and the drain contact region surrounds the outside of the gate contact region, or the source contact region and the gate contact region are annular, the gate contact region surrounds the outside of the drain contact region, and the source contact region surrounds the outside of the gate contact region. Such annular surrounding structures can effectively save the area of ​​the device. For example, the second gate structure can form a bias field plate structure together with the first field oxide layer, thereby increasing the average electric field in the drift region, decreasing the electric field peak value, suppressing the hot carrier effect, and increasing the breakdown voltage. The second gate structure can also form a floating field plate structure together with the first field oxide layer, making the electric field distribution in the drift region more uniform and ensuring that corners where the electric field is concentrated are less likely to break, thereby further increasing the breakdown voltage.

[0059] Example 2 The present invention further provides a conductive device that can be manufactured by the method of Example 1. Specifically, as shown in Figure 2J, the semiconductor device is A substrate 200 having a first conductivity type, A drift region 202 having a second conductivity type extends from the first surface of the substrate 200 into the substrate 200, A plurality of channel spacing regions 205 located in the drift region 202 and exposed on the first surface of the substrate, having a first conductivity type, wherein a plurality of channel spacing regions are formed between two channel spacing regions 205, A source contact region 211, a drain contact region 210, and a gate contact region 212 located in the drift region 202, wherein the gate contact region 212 is located between the source contact region 211 and the drain contact region 210, the source contact region 211 and the drain contact region 210 are connected by a channel region, the source contact region 211 and the drain contact region 210 have a second conductivity type, and the gate contact region 212 has a first conductivity type. It includes a substrate contact region 213 having a first conductivity type, which extends from the first surface of the substrate 200 into the substrate 200 and is provided at a distance from the drift region 202.

[0060] Exemplary, the substrate 200 may comprise at least one of Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors, or the substrate 200 may further comprise silicon on an insulator (SOI), multilayer silicon on an insulator (SSOI), multilayer silicon germanize on an insulator (S-SiGeOI), silicon germanize on an insulator (SiGeOI), or germanium on an insulator (GeOI), etc. Although several examples of materials that can form the substrate 200 are described herein, any material that can form the substrate 200 is included in the spirit and scope of this application.

[0061] For example, the first conductivity type may be N-type and the second conductivity type may be P-type, or the first conductivity type may also be P-type, in which case the second conductivity type is N-type.

[0062] In one example, as shown in Figure 2J, the semiconductor device of the present application further includes a first injection region 204 having a second conductivity type located in a drift region 202. Exemplarily, when the first injection region 204 is formed in the drift region 202, the space between two channel spacing regions 205 is the first injection region 204, or the first injection region 204 between two channel spacing regions 205 is a channel region.

[0063] In one example, the depth of the channel spacing region 205 is less than the depth of the drift region 202, and furthermore, the depth of the channel spacing region 205 is also less than the depth of the first injection region 204. In this case, the first injection region 204 and the drift region 202 between the channel spacing region 205 and the substrate 200 are also channel regions. In another example, the depth of the channel spacing region 205 may be greater than or equal to the depth of the drift region 202.

[0064] In one example, the semiconductor device of this application further includes shallow trench isolation structures 201 located between the active regions of the device. Exemplarily, the substrate contact region 213 is located between the shallow trench isolation structures 201. Exemplarily, the drift region 202 is located within the active region of the device.

[0065] In one example, the semiconductor device of the present application further includes a first field oxide layer 2031 and a second field oxide layer 2032 located within a drift region 202, wherein the first field oxide layer 2031 is located between the gate contact region 212 and the drain contact region 210, and the second field oxide layer 2032 is located between the gate contact region 212 and the source contact region 211. The semiconductor device of the present application further includes a first gate structure 2091 and a second gate structure 2092, wherein the first gate structure 2091 is located on the first field oxide layer 2031 and partially extends over the drift region 202, and the second gate structure 2092 is located on the first field oxide layer 2031 and is located on the side of the first gate structure 2091 closer to the drain contact region 210.

[0066] In one example, both the first gate structure 2091 and the second gate structure 2092 include a gate layer and side walls located on both sides of the gate layer.

[0067] In one example, the gate contact region 212 and the first gate structure 2091 are electrically connected to the same external metal layer via contact plugs to form a gate, that is, the gate contact region 212 and the first gate structure 2091 are electrically connected via contact plugs, and when a bias voltage is applied to the gate, the first gate structure 2091 and the first field oxide layer 2031 can form a bias field plate structure, thereby increasing the average electric field of the drift region 202, decreasing the electric field peak value, suppressing the hot carrier effect, and achieving objectives such as increasing the breakdown voltage. Exemplarily, the second gate structure 2092 is a floating gate structure, that is, the second gate structure 2092 does not need to be connected to an external electrode, and the second gate structure 2092 can form a floating field plate structure together with the first field oxide layer 2031, making the electric field distribution in the drift region 202 more uniform and ensuring that corners where the electric field is concentrated are less likely to break, thereby further increasing the breakdown voltage.

[0068] In one example, as shown in Figure 2J, the contact plug 214 further electrically connects the source contact region 211 to the outer metal layer to form a source, the contact plug 214 further electrically connects the drain contact region 210 to the outer metal layer to form a drain, and at the same time, the contact plug 214 further electrically connects the substrate contact region 213 to the outer metal layer so that the substrate 200 is pulled out and a substrate edge is formed. Exemplary materials for the contact plug 214 include, but are not limited to, copper, tungsten, gold, silver, and aluminum.

[0069] In one example, as shown in Figure 2F, the semiconductor device of this application further includes a source change region 208 and a drain change region 207 located in the drift region 202, the source contact region 211 is located in the source change region 208, the drain contact region 210 is located in the drain change region 207, and the source change region 208 and the drain change region 207 have a second conductivity type. Exemplarily, the doping concentration of the source change region 208 is smaller than that of the source contact region 211, and the doping concentration of the drain change region 207 is smaller than that of the drain contact region 210. By forming the source change region 208 and the drain change region 207, the antistatic performance of the device can be improved, the phenomenon of excessive carrier concentration can be effectively altered, and the thermoelectric effect can be effectively mitigated.

[0070] In one example, as shown in Figure 2E, the semiconductor device of this application further includes a second injection region 206, the substrate contact region 213 is located in the second injection region 206, and the second injection region 206 has a first conductivity type.

[0071] In one example, referring together to Figures 2J and 4, the drain contact region 210 and the gate contact region 212 are annular, the gate contact region 212 surrounds the outside of the source contact region 211, and the drain contact region 210 surrounds the outside of the gate contact region 212. Alternatively, as shown in Figure 3, the source contact region 211 and the gate contact region 212 are annular, the gate contact region 212 surrounds the outside of the drain contact region 210, and the source contact region 211 surrounds the outside of the gate contact region 212. Here, Figure 3 shows a cross-sectional view of a semiconductor device according to another embodiment of the present application, which can achieve the same functionality as the semiconductor device obtained in Figures 2A to 2J. Such an annular surrounding structure can effectively save device area. Exemplarily, in this case, the first gate structure 2091 and the second gate structure 2092 are also annular structures. For example, as shown in Figure 5, the gate contact region 212 may not be located in the first injection region 204, but rather in the channel spacing region 205, in which case the entire gate contact region 212 is an annular shape with spacing between them.

[0072] In one example, to meet actual demands, the pinch-off voltage of the device can be adjusted by adjusting the width of the channel region between the channel spacing regions 205.

[0073] In one example, as shown in Figure 5, the gate contact region 212 may not be located in the first injection region 204, but rather in the channel spacing region 205. Alternatively, as shown in Figure 6, the gate contact region 212 may be located in both the channel spacing region 205 and the first injection region 204.

[0074] In one example, as shown in Figures 4, 5, and 6, taking the case where the first conductivity type is P-type and the second conductivity type is N-type, when no reverse bias voltage is applied to the gate and substrate edge, current can flow from the source through the channel region between the channel spacing regions 205 to the drain. In this application, since channel regions are formed between the channel spacing regions 205, multiple current paths can be formed, thereby ensuring that the device still has a high on-current when it has a small pinch-off voltage, further reducing the on-resistance of the device, reducing the power consumption of the device, and improving the performance of the device. When a reverse bias voltage is applied to the gate and substrate edge, the depletion layer between the channel spacing region 205 and the channel region gradually expands until it completely occupies the channel region. At this time, the channel region is pinched off, and the device is also in a pinch-off state. The arrows shown in Figures 5 and 6 indicate the direction in which the depletion layer pinches off the channel region.

[0075] Exemplary, as shown in Figure 7, when the depth of the channel spacing region 205 is less than the depth of the drift region 202, a channel region can be formed between the channel spacing region 205 and the substrate 200, and this channel region can also form a current path, thereby further increasing the on-current of the device. The arrow in Figure 7 indicates the direction in which the depletion layer pinches off the channel region between the channel spacing region 205 and the substrate 200. Exemplary, as shown in Figure 8, when the depth of the channel spacing region 205 is greater than or equal to the depth of the drift region 202, a channel region cannot be formed between the channel spacing region 205 and the substrate 200.

[0076] Furthermore, as shown in Figure 9, when the gate contact region 212 is located in the channel spacing region 205 and the first injection region 204, the conductivity types of the gate contact region 212 and the substrate 200 are both P-type between adjacent channel spacing regions 205, and the conductivity type of the first injection region 204 between them is N-type. Therefore, a channel region can also be formed between the gate contact region 212 and the substrate 200. Specifically, the first injection region 204 between the gate contact region 212 and the substrate 200 can form a channel region, and the channel spacing regions 205 on both sides of the gate contact region 212, the substrate 200, and the first injection region 204 simultaneously pinch off the channel region between the gate contact region 212 and the substrate 200. The arrow in Figure 9 indicates the direction in which the depletion layer pinches off the channel region between the gate contact region 212 and the substrate 200.

[0077] Exemplary, the semiconductor device of this application includes a JFET device, and the semiconductor device may be any suitable device well known to those skilled in the art. In this embodiment, the technical solution of this application will be interpreted and explained primarily using the example that the semiconductor device is a JFET device.

[0078] This concludes the explanation of the structure of the semiconductor device of the present invention. The complete device may include other constituent structures, but a detailed explanation is omitted here.

[0079] Example 3 Another embodiment of the present invention further provides an electronic device including the semiconductor device described above.

[0080] The electronic device according to this embodiment may be any electronic product or device such as a mobile phone, tablet computer, notebook computer, netbook, game console, television, VCD, DVD, navigator, camera, video camera, pen-type micro recorder, MP3, MP4, PSP, etc., or any intermediate product including the semiconductor device. Because the electronic device according to the embodiment of the present invention uses the above semiconductor device, it has superior performance.

[0081] While several embodiments are described herein, those skilled in the art should understand that various other modifications and embodiments can be conceived, all of which fall within the spirit and scope of the concept disclosed herein. More particularly, various modifications and changes are possible with respect to the arrangement scheme and / or components of the subject matter combination arrangement within the disclosure, drawings, and appended claims of the present invention. In addition to modifications and changes to the components and / or arrangement scheme, the use of substitution means is also an obvious choice for those skilled in the art.

Claims

1. A substrate having a first conductivity type, A drift region extending from the first surface of the substrate to the interior of the substrate and having a second conductivity type, A plurality of channel spacing regions located in the drift region and exposed to the first surface, having a first conductivity type, wherein a channel region is formed between two adjacent channel spacing regions, with a gap between each of them. A source contact region, a drain contact region, and a gate contact region located in the drift region, wherein the gate contact region is located between the source contact region and the drain contact region, the source contact region and the drain contact region are in communication with each other by the channel region, the source contact region and the drain contact region have the second conductivity type, and the gate contact region has the first conductivity type. A semiconductor device characterized by including a substrate contact region having the first conductivity type, which is located within the substrate and is spaced apart from the drift region.

2. The drain contact region and the gate contact region are annular, the gate contact region surrounds the outside of the source contact region, the drain contact region surrounds the outside of the gate contact region, or The semiconductor device according to claim 1, characterized in that the source contact region and the gate contact region are annular, the gate contact region surrounds the outside of the drain contact region, and the source contact region surrounds the outside of the gate contact region.

3. A first field oxide layer and a second field oxide layer located in the drift region, wherein the first field oxide layer is located between the gate contact region and the drain contact region, and the second field oxide layer is located between the gate contact region and the source contact region, The semiconductor device according to claim 1, further comprising a first gate structure and a second gate structure, wherein the first gate structure is located on the first field oxide layer and partially extends to the drift region, and the second gate structure is located on the first field oxide layer and is located on the side of the first gate structure closer to the drain contact region.

4. The semiconductor device according to claim 3, characterized in that the second gate structure is a floating gate structure.

5. The semiconductor device according to claim 1, further comprising a source change region and a drain change region located in the drift region, wherein the source contact region is located in the source change region, the drain contact region is located in the drain change region, and the source contact region and the drain contact region have the second conductivity type.

6. The steps include: preparing a substrate having a first conductivity type, The steps include forming a drift region having a second conductivity type that extends from the first surface of the substrate to the interior of the substrate, The steps include forming a plurality of channel spacing regions having the first conductivity type in the drift region such that channel regions are formed with spacing between each of the two channel spacing regions, A method for manufacturing a semiconductor device, comprising the steps of forming a source contact region having a second conductivity type, a drain contact region and a gate contact region having a first conductivity type in the drift region, and forming a substrate contact region having a first conductivity type on the substrate at a distance from the drift region, wherein the gate contact region is located between the source contact region and the drain contact region, and the source contact region and the drain contact region are in communication through the channel region.

7. The drain contact region and the gate contact region are annular, the gate contact region surrounds the outside of the source contact region, the drain contact region surrounds the outside of the gate contact region, or The manufacturing method according to claim 6, characterized in that the source contact region and the gate contact region are annular, the gate contact region surrounds the outside of the drain contact region, and the source contact region surrounds the outside of the gate contact region.

8. A step of forming a first field oxide layer and a second field oxide layer within the drift region, wherein the first field oxide layer is located between the gate contact region and the drain contact region, and the second field oxide layer is located between the gate contact region and the source contact region. The manufacturing method according to claim 6, further comprising the steps of forming a first gate structure and a second gate structure, wherein the first gate structure is located on the first field oxide layer and partially extends to the drift region, and the second gate structure is located on the first field oxide layer and is located on the side of the first gate structure closer to the drain contact region.

9. The manufacturing method according to claim 8, characterized in that the second gate structure is a floating gate structure.

10. Before forming the source contact region and the drain contact region, the method The manufacturing method according to claim 6, further comprising the step of forming a source change region and a drain change region having a second conductivity type in the drift region, characterized in that the source contact region is located in the source change region and the drain contact region is located in the drain change region.

Images