Physical layout synthesis of standard cells using slice layout

Abstract

A method for automatically generating a standard cell may include receiving a circuit definition for the standard cell. The definition may include one or more semiconductor devices. The method may further include identifying multiple slices that will implement the device within one or more semiconductor devices. Each of the multiple slices may include a partial layout for the device. When forming the standard cell, the method may further include combining one or more slices from the multiple slices to form a combined layout and implement the device.

Description

Technical Field

[0001] Cross - reference to Related Applications

[0001] This application claims the benefit and priority of U.S. Non - Provisional Application No. 18 / 170,335, filed on February 16, 2023, entitled "PHYSICAL LAYOUT SYNTHESIS FOR STANDARD CELLS USING SLICE LAYOUTS", the content of which is hereby incorporated by reference in its entirety for all purposes.

[0002]

[0002] This disclosure generally describes a synthesis process for generating standard cells used in a front - end - of - line (FEOL) process. More specifically, this disclosure describes automatically generating standard cells for a standard cell library using device slices combined to implement a circuit definition.

Background Art

[0003]

[0003] Over the past several decades, circuit architectures have utilized scaling techniques to meet the ever-increasing workload demands. Scaling traditionally involves reducing the size of integrated circuit element features (for example, from 10nm to 7nm, 5nm, etc.). However, in recent years, as we have reached the limits of physics, the benefits that could have been obtained from scaling techniques have been dramatically reduced by the physical limitations of silicon structures. Furthermore, with the recent emergence of artificial intelligence and machine learning (AI / ML) algorithms, the volume of data processed and the diversity of various workload types are beginning to overwhelm the benefits that could be obtained from scaling techniques. Hardware computational requirements are increasing exponentially, and keeping up with this pace may require advances in new circuit manufacturing. Therefore, in addition to the increasing processing demands from AI / ML techniques, the decrease in performance benefits achieved by conventional circuit scaling may necessitate alternative techniques to improve performance. Thus, improvements in design methods, including the generation of standard cell libraries, are needed. [Overview of the Initiative]

[0004]

[0004] In some embodiments, a method for automatically generating a standard cell may include receiving a definition of a circuit for the standard cell by a computer system. The circuit may include one or more semiconductor devices. The method may further include the computer system identifying a plurality of slices that will implement the device within one or more semiconductor devices. Each of the plurality of slices may include a partial layout for the device. When forming the standard cell, the method may further include the computer system combining one or more slices from the plurality of slices to form a combined layout and implement the device.

[0005]

[0005] In some embodiments, the system comprises one or more processors and one or more memory devices containing instructions, which, when executed by one or more processors, cause one or more processors to perform an operation that includes receiving a definition of a circuit for a standard cell. The circuit may include one or more semiconductor devices. The operation may further include identifying a plurality of slices that implement the device within one or more semiconductor devices. Each of the plurality of slices may include a partial layout for the device. The operation may further include combining one or more slices of the plurality of slices to form a combined layout and implement the device when forming a standard cell.

[0006]

[0006] In some embodiments, one or more non-temporary computer-readable media may store instructions. When executed by one or more processors, the instructions cause one or more processors to perform an operation which includes receiving a definition of a circuit for a standard cell. The circuit may include one or more semiconductor devices. The operation may further include identifying a plurality of slices that implement the device within one or more semiconductor devices. Each of the plurality of slices may include a partial layout for the device. When forming the standard cell, the operation may further include combining one or more slices of the plurality to form a combined layout which implements the device.

[0007]

[0007] In any embodiment, any and all of the following features may be implemented in any combination, without limitation: The device may include functional circuit elements. Partial layouts may not be functional circuit elements, while combined layouts may form functional circuit elements. A slice of a plurality of slices may include partial layouts for one or more semiconductor devices than one of a plurality of semiconductor devices. A combined layout may include additional slices, together with one or more slices of the plurality of slices, for implementing one or more semiconductor devices for standard cells. A first slice of a plurality of slices may include a first partial layout for a device. A second slice of a plurality of slices may include a second partial layout for a device. The device may be a transistor or a diode. A first partial layout may include a source region or drain region layout for a transistor. A second partial layout may include a gate region layout for a transistor. A plurality of slices may include a first set of slices. Each of the first set of slices includes a different implementation of the first partial layout for a device. The method / operation may further include selecting a first slice from a first set of slices for a device. The first slice may include connections to a first cross track in a metal layer. A second slice may include connections to a second cross track in a metal layer. The method / operation may further include determining one or more device chains for generating a cell layout for a standard cell. One or more device chains may represent connections between devices in one or more semiconductor devices and inputs / outputs in a standard cell. The method / operation may further include selecting a set of candidate slices from a slice library that can be used to implement each of the connections.The method / operation may further include assigning tracks in the metal layer to inputs and outputs in a standard cell, optimizing a set of candidate slices by eliminating slices that could be implemented by placing two slices adjacent to each other, and optimizing a set of candidate slices by eliminating slices whose connections to tracks in the metal layer are conflicting. The method / operation may further include generating one or more combinations of slices from a set of candidate slices, each of which implements a standard cell. The method / operation may further include optimizing one or more combinations of slices based on design rules for the metal layer. One or more combinations of slices may include multiple slices for the optimized device. The circuit definition may include a netlist having device characteristics and connections between one or more semiconductor devices. The method / operation may further include accessing a first slice library for the device and taking out multiple slices. The first slice library may include partial layouts for various implementations of a first device type for the device. A second slice library for the device may include partial layouts for various implementations of a second device type for the device. The device may include a transistor. The first device type may include a metal-oxide-semiconductor field-effect transistor (MOSFET), and the second device type may include a fin field-effect transistor (FinFET).

[0008]

[0008] A further understanding of the properties and advantages of various embodiments can be achieved by referring to the remainder of this specification and the drawings. In the drawings, similar reference numbers are used across several drawings to refer to similar components. In some cases, sublabels are associated with reference numbers to indicate one of several similar components. When a reference number is referred to without specifying an existing sublabel, it is intended to refer to all such several similar components. [Brief explanation of the drawing]

[0009] [Figure 1] A simplified integration flow or synthesis of standard cells according to several embodiments is shown. [Figure 2] Schematic diagrams of inverter designs for standard cells according to several embodiments are shown. [Figure 3] An example of a set of SD slices used to implement the source / drain regions of a transistor with corresponding connections, according to several embodiments, is shown. [Figure 4] An example of a set of gate slices used to implement the gate region of a transistor having corresponding connections, according to several embodiments, is shown. [Figure 5] The complete layout of a standard cell generated from a device slice according to several embodiments is shown. [Figure 6] A schematic diagram of a circuit used in a NAND2 standard cell according to several embodiments is shown. [Figure 7] The following shows possible device chains that can be derived from the circuit according to several embodiments. [Figure 8] The following are candidate gate slices that may be used to implement a selected transistor chain according to several embodiments. [Figure 9] The following are candidate SD slices that may be used to implement a selected transistor chain according to several embodiments. [Figure 10] A flowchart shows a method for automatically generating standard cells according to several embodiments. [Figure 11] A flowchart of operations that may be used to select and optimize a set of slices used to implement a standard cell, according to several embodiments, is shown. [Figure 12] This illustrates an exemplary computer system in which various embodiments can be implemented. [Modes for carrying out the invention]

[0010]

[0021] For decades, circuit architectures have utilized scaling techniques to meet the ever-increasing workload demands. Scaling traditionally involves reducing the size of integrated circuit element features (e.g., from 10nm to 7nm, 5nm, etc.). However, in recent years, the benefits that could be gained from scaling techniques have dramatically slowed due to the physical limitations of silicon structures. Furthermore, with the recent emergence of artificial intelligence and machine learning (AI / ML) algorithms, the volume of data processed and the diversity of workload types are beginning to overwhelm the benefits that could be gained from scaling techniques. Hardware computational requirements are increasing exponentially, and new advancements in circuit manufacturing may be necessary to keep pace. Therefore, the combination of increasing processing demands from AI / ML techniques and the diminishing performance benefits achieved by traditional circuit scaling may necessitate alternative techniques to improve performance. One such alternative technique for improving performance is material / process innovation by equipment manufacturers.

[0011]

[0022] Materials innovations include, for example, any changes to various physical aspects of semiconductor devices, such as the size of source / drain contacts, the type of insulation between transistors, gate oxide material, work function metal, doping in the source / drain region, contact material, liner in the contact material, and / or any other parameters of the semiconductor device. The impact of these types of changes on large processors and / or system-on-chip (SoCs) with different software algorithms may not be apparent in the early stages of the semiconductor design cycle. For example, improvements in power-performance-area-cost (PPAC) from materials engineering innovations may appear small, but can increase dramatically at the SoC level, and vice versa.

[0012]

[0023] Despite the promising future benefits of materials innovation, the difficulties and inherent limitations of existing tools, processes, and systems make it challenging to actually implement materials innovation without a multi-year, extensive design verification process. The inherent complexity of designing, testing, implementing, and manufacturing complex circuit-based systems has traditionally fragmented the design process among different entities within the semiconductor ecosystem. For example, material or process changes at the semiconductor level might be introduced by equipment manufacturers. Subsequently, material changes would be implemented in semiconductor manufacturing plants or foundries using compact models in simplified device structures. Process design kits (PDKs), standard cell libraries, and embedded memory for PDKs were developed by integrated circuit design entities providing electronic design automation (EDA) software. Standard cells / memory in PDKs were used by "fabless" device design entities or integrated device manufacturers (IDMs) to generate block-level designs, entire SoCs, and system-level devices. Finally, software designers would use the manufactured IC devices to execute complex software designs and algorithms. Each of these various stages in the IC design and manufacturing pipeline is performed by different entities, and each of these entities uses different software / hardware tools to perform its part of the process.

[0013]

[0024] For example, a simplified device and / or compact model designed by a semiconductor manufacturing plant is tested against its own internal benchmarks to determine that the corresponding simplified circuit device meets its own technical requirements. The simplified device and / or compact model is then passed to an integrated circuit (IC) design entity, which will use the compact model to design the entire PDK, standard cells, and memory cells for EDA software. The IC design entity will also test the standard cells against its own internal technical requirements. Finally, the entire IC system will be designed using the standard cells. The entire IC system will also be tested against its own software benchmarks. Therefore, it is often very difficult to verify the impact of changes to standard cells of basic functional devices such as transistors and diodes once these devices are incorporated into a complete processing system.

[0014]

[0025] One of the main bottlenecks when testing new designs is the generation of a library of standard cells, which are traditionally designed and propagated through a multi-step process. After compact models representing functional devices (e.g., transistors) are generated, these compact models can be used to construct circuits for the standard cells. This step may be performed by device manufacturers and / or integrated circuit design entities. For example, when compact models of individual transistors are combined, further aspects of circuit performance may be affected based on the connections between these transistors. Capacitance and dielectric can be formed between compact model transistors when they are combined into a larger multi-transistor circuit. Therefore, at this level, standard cells are typically designed in EDA software and tested at the circuit level rather than the transistor level. For example, standard circuits may be benchmarked against power consumption, frequency, and / or other simple electrical characteristics. As mentioned earlier, material / process changes can affect the operation of standard cells, but this effect may not be detected until the material / process change propagates down to the IC design entity, such as during EDA software simulations and use, or during SPICE simulations.

[0015]

[0026] One of the most time-consuming aspects of the process was generating a complete PDK library and standard cells. The PDK library can include symbols, device parameters, parametric cells, design rules, circuit diagram versus layout (LVS) rules, electrical rules, layers, and the like. When changes to the material / process are made by the device manufacturer, the PDK library containing standard circuit elements and cells is generally redesigned by the device manufacturer and / or an IC design entity. This is a time-consuming process that is mainly done manually. This is because the standard cell library contains up to thousands of cells that must be laid out and the electrical characteristics such as power and delay need to be simulated. Reducing the size of the library to save effort is not an effective option as it reduces the accuracy of subsequent PPA evaluations.

[0016]

[0027] Test experiments on standard cells have been carried out using simple and small electronic circuits such as ring oscillators. However, in this field, in recent years, there have been technical problems in that it has become impossible to quickly and accurately evaluate performance, power, and cost (PPA) even using these simple circuits. To perform appropriate evaluations, circuits more realistic than simple ring oscillators are required. Therefore, appropriate tests may require the complete creation of a standard cell library. The physical layout of the logic circuits within the standard cell library can be assembled by EDA tools (e.g., Place&Route tools) to create a complex design that provides a more realistic PPA characteristic evaluation. However, in advanced technologies, currently, the generation of the standard cell library is done manually by circuit designers and thus has become a major bottleneck in the DTCO cycle.

[0017]

[0028] The embodiments described herein solve these technical problems and other technical problems by automatically synthesizing a standard cell library in a fully automated manner. These embodiments maintain the flexibility necessary to address various technology changes while maintaining the layout quality required to generate realistic PPA evaluations. These improvements are realized by further decomposing the building block devices of the standard cell into partial layouts, herein referred to as slices. The tool can then be configured to optimize the selection of slices used to construct the devices combined within the standard cell.

[0018]

[0029] Prior to this disclosure, attempts to synthesize standard cells using automated methods had problems. Each of these earlier attempts at solutions utilized essentially two steps in the cell synthesis process: (1) arranging individual transistors (e.g., NMOS and PMOS transistors) in rows at the bottom and top of the cell region, and then (2) routing the transistor nodes to circuit terminals. Typically, in these earlier attempts, there was the fact that each design of transistors and / or other devices was a complete, distinct, and functional device. In other words, each basic device such as transistors and diodes used as building blocks for a standard cell was itself a complete, functional circuit element with a complete geometric layout. In the synthesis process, these complete functional blocks were used to assemble and form a standard cell. The problem with this approach is that the assembly of the complete cell layout depends heavily on how these building blocks need to interact and connect. This made it impossible to create software that was general enough to synthesize a wide variety of device layouts. For example, it would be impossible to perform synthesis for a technology where NMOS and PMOS devices are represented by separate building blocks (e.g., in a FinFET process) and then implement a building block representing the combination of NMOS and PMOS devices (e.g., in a CFET process) using the same software program.

[0019]

[0030] However, as mentioned above, it is often desirable to modify the design of these functional building blocks in order to fully test how the changes will affect the subsequent system design as the changes propagate through the design process. Changing transistors to a different type or technology (e.g., from MOSFET to finFET) required redesigning the device model and subsequently manually redesigning the standard cell. Transistor types and technologies were not readily interchangeable within the standard cell without going through this time-consuming redesign process.

[0020]

[0031] To solve this problem, in the embodiments described herein, each device is further subdivided into “slices” to represent transistors and other devices in a fundamentally different way. In this different representation, the actual layout of the device is abstracted to the software within the slice. The software does not need to know its layout or technical details, only that it was to connect to the device terminals (e.g., transistor source, drain, or gate), starting from the initial BEOL interconnect layer. For example, a slice for a transistor may include a vertical cross-section of the layout representing the possible locations and connections of the main positions. Each slice can define layouts for one or more devices so that the slices can be easily used to form device chains or pairs of devices, as will be described in more detail below. For example, three slices (e.g., one for the source, one for the gate, and one for the drain) may be used to form a pair of transistors. The final standard cell layout is not made by arranging individual transistors and then routing them, as in the previous method, but instead is generated by arranging a series of slices and then routing them. The advantage of this technique is that many of the manufacturing and design details are hidden within the slice, and the standard cell generation or synthesis tool can generally function with the slice without requiring details or understanding of the underlying slice design. This abstraction of slice details allows the tool to generally function with various device technology options. For example, instead of redesigning the standard cell with transistor placement when moving from MOSFET to finFET, CFET, or multilayer 3D transistor configurations, these options can be provided to the tool. This allows for the automatic selection of the appropriate slice and creation of the standard cell layout using the techniques described below.This tool may include a computer program that reads the circuit definition for a standard cell, creates one or more device chains (e.g., a transistor chain of NMOS and / or PMOS transistors), selects a sequence of slices to implement the device chains, including alternating gate matches and source / drain matches, and routes the connections required by the slices to implement the final layout of the standard cell. Each of these steps may be performed automatically by the tool without requiring human intervention.

[0021]

[0032] Figure 1 shows a simplified integration flow 100 for the synthesis of a standard cell according to several embodiments. Tool 101 may be configured to perform many of these operations. Tool 101 may be implemented as a set of instructions stored in one or more non-temporary computer-readable media. This may include a single set of instructions stored in instruction memory, or it may include a distributed set of instructions that each perform a portion of this method on various processors and / or arithmetic systems. These instructions may be executed by one or more processors located in the same location or distributed in any manner to perform the operations described below.

[0022]

[0033] The tool may receive a circuit definition for standard cell 102. The circuit definition for standard cell 102 may be provided in any format, such as a device netlist. For example, in some embodiments, a .CDL file type may be used to define the circuit netlist in a Circuit Definition Language. The circuit for the standard cell may be designed using any computer-aided design (CAD) software tool.

[0023]

[0034] Figure 2 shows a schematic diagram of an inverter 200 design for a standard cell according to several embodiments. The inverter 200 may include I / O connections that form the interface of the standard cell. For example, the inverter 200 may include a VDD connection 206, an IN connection 208, an OUT connection 210, and a VSS connection 212. Furthermore, the inverter 200 may include several devices such as a PFET 202 and an NFET 204. CAD software tools may enable circuit designers to construct the inverter 200 or other standard cells from building block devices such as the PFET 202 and NFET 204. These building block devices are wired together within the CAD software. An example of the circuit definition for a standard cell 102 of the inverter may include the following netlist. .SUBCKT Invertor IN OUT VSS VDD M0 VDD IN OUT VDD pfet W=1.0 L=1.0 nfin=2 M1 VSS IN OUT VSS nfet W=1.0 L=1.0 nfin=2 .ENDS

[0024]

[0035] As used herein, there is a distinction between the term “standard cell” and “device” used as a building block for a standard cell. In this embodiment, the inverter 200 is considered a standard cell, and the PFET 202 and NFET 204 may be considered devices used as building blocks for a standard cell, respectively. A standard cell typically includes a number of individual devices used as building blocks wired together. A device may typically be a single functional circuit element placed using a CAD software tool. A device can be characterized as a functional circuit element, such as a transistor or diode. Here, by placing connections to available ports or I / O connections on the device, a functional circuit element is produced that performs an intended function (such as operation as a transistor switch, regulation of current flow, or voltage scaling), depending on the type of device. Typically, a device may be defined as a functional block within a CAD software tool. For example, the PFET 202 and NFET 204 devices in the inverter 200 are defined as M0 and M1 transistor devices in the netlist. The characteristics of these transistor devices (e.g., width, length, and / or other physical device characteristics) may also be included in the netlist.

[0025]

[0036] Returning to Figure 1, the circuit definition for the standard cell 102 can be passed to the tool 101, which can then automatically synthesize the circuit definition for the standard cell 102 to construct the resulting circuit layout 118 or complete circuit layout for the standard cell. First, the tool 101 may generate a device chain 104 that implements the circuit for the standard cell. The device chain may represent a sequence for connecting multiple devices represented within the standard cell. For example, a transistor chain may include a sequence of connections between transistors within the standard cell. This sequence of connections can be used to efficiently lay out transistors that are chained together via connections or adjacencies in the circuit definition. For example, PFET 202 and NFET 204 may be laid out such that the drain of PFET 202 is adjacent to the drain of NFET 204, thereby forming a unique connection. Furthermore, the device chain may be determined so that the source / drain of one device is shared with the source / drain of another device when the source / drain of that device is connected to the same electrical node. This approach saves the resulting area on the chip. As will be explained in more detail below, tool 101 can generate a list of possible device chains that may be used to implement a standard cell, and then select the optimal device chain from the list of possible device chains.

[0026]

[0037] Traditionally, a standard cell would be constructed directly from the device layout of each device in a device chain. However, the embodiments described herein include several additional processes or operations to optimize the synthesis of a standard cell by using partial layouts called “slices” instead of complete device models. After generating one or more device chains to implement a standard cell, tool 101 may identify several slices that implement combinations of devices in device chain 106. The slices selected by tool 101 can be retrieved from a library of slice definitions 108.

[0027]

[0038] As used herein, there is a distinction between the term “device” used as a building block for a standard cell and “slice” used as a building block for a device. Generally, a slice may contain a partial layout for a device, such as a transistor, rather than a functional circuit element. For example, a first slice may contain a partial layout for a device, including the source and drain regions for a transistor, but without including the layout for connections for the gate region. A second slice may contain a partial layout for the gate region. A gate slice can define the shape dimensions that define the gate layout and how the gate may be connected to the upper metal layer. Similarly, a source / drain (SD) slice can define the SD layout and how the source and / or drain are connected to power, ground, signal tracks, etc., within the metal layer. A first slice defining the partial layout of the source and drain regions can be combined with a second slice defining the gate region to form a complete transistor. An SD slice can also define how adjacent transistors or devices abut each other within the layout. It should be emphasized that a slice can often define partial layouts for multiple devices. For example, a single slice can define layouts for both the source and drain regions of NMOS and PMOS transistors, which may be parts of two different transistor devices. However, some partial layouts may be specific to only a single device. Therefore, a collection of partial layouts can be combined to form a combined layout for multiple devices or a single device within a standard cell.

[0028]

[0039] Furthermore, the library of slice definitions 108 may include multiple sets of slices for each region. For example, the library of slice definitions 108 may include a first set of slices that each include various implementation forms of partial layouts for the source region and the drain region. The library of slice definitions 108 may further include a second set of slices that each define various implementation forms of partial layouts for the gate region of the transistor. For example, slices from both of these sets may include connections to different signal tracks within the metal layer. Tool 101 may select slices from each of these sets of slices to provide a list of possible slices for implementing each device chain. Examples of slices and their corresponding partial layouts are described in detail below.

[0029]

[0040] Figure 3 shows an example of a set of SD slices 300 used to implement the source / drain regions of a transistor having corresponding connections, according to several embodiments. Each slice in the set of SD slices 300 may include a alignment shape 316. The alignment shape 316 may be implemented as a default layer in the layout. The alignment shape 316 may be used to align various slices for the device. For example, the alignment shape 316 can be used to align an SD slice with a corresponding gate slice. Thus, the alignment shape 316 may be present in each slice in a slice library for the device. The alignment shapes 316 may be further positioned so that these rectangles are vertically aligned and / or horizontally in contact within each slice, so that slices for a partial layout of the device can be combined using the alignment shapes 316 on the substrate. For example, the alignment shapes 316 can be used to horizontally align shapes so that one alignment shape is in contact with an adjacent horizontal alignment shape.

[0030]

[0041] Each slice in the set of SD slices 300 may further include the following features: VDD region 302, VSS region 304, P source / drain (PSD) region 310, N source / drain (NSD) region 312, N well 314, PSD metal connection 306, and NSD metal connection 308. Note that tool 101 does not need to know any of the layout details shown in Figure 3 to synthesize a standard cell. For example, NFET and PFET slices can be easily replaced with finFET or other transistor mounting configurations. As long as tool 101 knows the location of the alignment shape 316, the metal connections 306, 308 to the metal layers, and the basic purpose of the slice (e.g., partial layout of the SD), tool 101 can select a slice that includes the connections required for the device chain described above.

[0031]

[0042] A set of SD slices 300 may include different connections to the source and drain regions, respectively. For example, slice 322 has a PSD metal connection 306 connected to the VDD region 302, resulting in a source / drain connection to VDD (e.g., via a connection such as a via). Note that the power track including the VDD region 302 may extend above the device in the metal layer or below the device on the power plane in the substrate. Slice 322 further shows an NSD metal connection 308 connected to the VSS region 304 to form a source / drain connection to the VSS. In another embodiment, slice 324 shows an NSD metal connection 308 connected to a signal track in the upper M0 metal layer, instead of the VSS connection shown in slice 322. Slice 326 shows both the NSD metal connection 308 and the PSD metal connection 306 connected to different signal tracks in the upper M0 metal layer. Slice 328 shows both source and drain regions connected to the same signal track within the M0 metal layer, with a connection 320 (e.g., a trench contact) between the PSD region and the NSD region, and a single metal connection 318.

[0032]

[0043] This set of SD slices 300 is provided for illustrative purposes only and is not intended to be limiting. For example, other slices in the set may include connections to different signal tracks on various metal layers. Tool 101 can analyze the netlist circuit definition of a standard cell and select any of the set of SD slices 300 to create the necessary connections to the source / drain regions of a transistor. For example, for a transistor with a source connection to VDD and a drain connection to a signal, slice 324 may be selected to implement a partial layout of the transistor. This selection can be made based on the connections to the metal layers made by each of the slices in the set 300. Thus, Tool 101 does not need to know how these connections are made in the partial layout of the slice or in the type of source / drain region used. For example, when implementing a finFET, the PSD region 310 and NSD region 312 may be replaced with horizontal fins in the slice. Also, please understand that any of the partial layouts of slices described herein are greatly simplified, and additional layers, features, and geometry dimensions not explicitly shown in these figures may exist.

[0033]

[0044] The tool can also select other partial layouts necessary to create a complete layout for the device. For example, in addition to selecting one or more SD slices, tool 101 may proceed to select gate slices, but may also adapt the necessary connections in the netlist of the standard cell to implement the device chain. Thus, tool 101 can use the alignment shape 316 to align each of the selected slices with each other to construct a complete layout for the device. When constructing the standard cell, the slices representing the partial layouts of each device can be combined together to efficiently form a complete layout for the standard cell.

[0034]

[0045] Figure 4 shows an example of a set of gate slices 400 used to implement the gate region of a transistor having corresponding connections according to several embodiments. Each of the set of gate slices 400 can implement the gate region of a transistor having various connections. These slices may include the shape dimensions of the VDD region 402, VSS region 404, and N well 414, as described above for the set of SD slices 300. In addition, the set of gate slices 400 may include the gate region 410 (e.g., a polysilicon region or a metal gate region) together with the gate metal connection 412. As described above for the set of SD slices 300, the set of gate slices 400 may further include alignment shapes 416 that can be used to align the gate slices and SD slices when combining them for device layout.

[0035]

[0046] As described above for the set of SD slices 300, each of the set of gate slices 400 may contain different gate connections. For example, slice 422 may not contain a connection to the upper metal layer, thereby forming a dummy gate. The dummy gate is used to insulate or boundary a region of the standard cell by diffusion fracturing. Slice 424 may locate a gate metal connection 412 at the location of a first signal track in the metal layer. Slice 426 may locate a gate metal connection 412 at a second signal track in the metal layer. Slice 428 may locate a gate metal connection 412 at the first signal track, but includes a gate region 418 above the PMOS region of the transistor that is disabled. This gate region 418 may be disabled by diffusion fracturing or by using other materials.

[0036]

[0047] Tool 101 can select SD slices and gate slices that can be used to implement the device chain. The process of selecting the optimal SD slices and / or gate slices is described in more detail below. Returning to Figure 1, the selected slices can be optimized so that one or more combinations of slices are identified to implement the device chain. Each set of selected slices can be combined together to form a complete layout of standard cells. For example, multiple selected slices can be laid out adjacent to each other by aligning each slice horizontally and / or vertically using the alignment shape described above. Connections may be routed in the upper metal layer.

[0037]

[0048] Figure 5 shows a complete layout of a standard cell generated from device slices according to several embodiments. To implement the standard cell, several different slices that can be efficiently implemented in a horizontal sequence can be selected using a device chain for two transistors to form an inverter. For example, dummy gates of slice 422 may be placed on both sides of the standard cell. The output of the inverter may be connected to the metal track 510 using slice 328. The input of the inverter may be connected to the metal track 512 and implemented with gate slice 424. Finally, the VSS 506 and VDD connections 502 may be implemented using SD slice 322. These slices may be arranged horizontally adjacent to each other so that the alignment shapes 316, 416 are adjacent and in contact. By aligning these SD and gate slices, the connections specific to the PSD region 310 and / or NSD region 312 described above can be formed.

[0038]

[0049] Furthermore, the complete layout may include metal connections within the metal layers. Each metal track may be aligned horizontally with respect to the gate area within the slice. Each horizontal "track" may be used to connect I / O signals or internal nets of standard cells. The routing of these metal layers can be determined using design rules and other routing techniques. Returning to Figure 1, the back-of-line (BEOL) design rule 112 can be used to exclude a particular slice from a selected set of slices if that slice is incompatible with the routing rules. The BEOL design rule 112 can also be used to select metal tracks and / or connect the metal tracks to signals exposed in each slice.

[0039]

[0050] Tool 101 can identify several different slice combinations that can be used to implement a standard cell. In other words, various slice arrangements can be used to generate various implementations of the standard cell by separately arranging transistors on different metal tracks or signals. In some cases, one of the slice combinations can be selected and used to synthesize a standard cell. In other cases, each slice combination may be used to synthesize a standard cell, and the resulting cell can be tested at various levels in the design pipeline to identify the most efficient implementation in terms of PPA and / or other metrics. For example, the resulting standard cell can be tested independently against a specific standard cell benchmark or optimization parameter 116. Alternatively, the resulting standard cell may be incorporated into a larger design such as an AI or system-on-a-chip (SoC) processor, and these larger designs may be tested to evaluate the effectiveness of the standard cell. Based on these simulations or tests, Tool 101 can select the best layout 114 generated from one of the selected sets of slices to identify the resulting final layout 118 for the design.

[0040]

[0051] Figure 6 shows a schematic diagram of a circuit 600 used for a standard cell according to several embodiments. This circuit 600 is more complex than the circuit 200 described above for the inverter. The following sections specifically describe how a set of slices can be selected using this circuit 600 and how these selected sets of slices can be optimized when forming a candidate layout for a standard cell. Circuit 600 may include a first input 606, a second input 608, and an output 610. Circuit 600 may include a VDD input 602 and a VSS input 620. Devices used in circuit 600 may include transistors 612, 614, 616, and 618. Note that this circuit 600 is provided for illustrative purposes only and is not intended to be limiting. The corresponding definition of the circuit for a standard cell may be stored as a netlist as follows: .SUBCKT NAND2 AB OUT VSS VDD T0 VDD A OUT VDD pfet W=1.0 L=1.0 nfin=2 T1 VDD B OUT VDD pfet W=1.0 L=1.0 nfin=2 T2 VSS A n1 VSS nfet W=1.0 L=1.0 nfin=2 T3 n1 B OUT VSS nfet W=1.0 L=1.0 nfin=2 .ENDS

[0041]

[0052] Figure 7 shows possible device chains that can be derived from circuit 600 according to several embodiments. In this embodiment, the device chain includes transistor chains for each branch or type of transistor. For example, possible transistor chain 702 shows chains of four different connections that can be made through the P-type transistors 612, 614 of circuit 600. For example, each of the possible transistor chains 702 may use different start / end positions and may traverse around the P-type transistors 612, 614 in different directions (e.g., clockwise or counterclockwise). Similarly, possible transistor chain 704 shows chains of two different connections that can be made through the N-type transistors 616, 618 of circuit 600. Each of these possible transistor chains 704 may traverse the N-type transistors 616, 618 in different directions (e.g., up and down).

[0042]

[0053] Tool 101 can implement a standard cell by selecting from possible transistor chains 702 and 704 and identifying the optimal combination of transistor chains from each group. For example, the selected transistor chain 706 can be chosen from each group of possible P-type transistor chains 702 and possible N-type transistor chains 704. In some embodiments, tool 101 may be configured to select the transistor chain that results in the most suitable connection. For example, the selected transistor chain 706 in Figure 7 is suitable for the input signal on the gate and the SD output.

[0043]

[0054] Figure 8 shows candidate gate slices 800 that may be used to implement a selected transistor chain 706 according to several embodiments. As in the embodiments described above, the candidate gate slice 800 may represent a partial layout of a transistor. Specifically, the candidate gate slice 800 may include connections made to the gate region of a transistor. Note that a slice alone does not represent a functional circuit or functional device, but rather may be used as a building block with a partial layout of other slices to form a functional device, and ultimately the standard cell itself.

[0044]

[0055] Each of these candidate gate slices 800 may include the alignment shape 806 described above, the VDD region 802, the VSS region 804, the gate region 812 which can be formed as a trench contact connecting the transistor epi silicon to the metal layer contact, the metal layer contact 110 (e.g., via), and the corresponding metal contact 808 within the metal layer. Each candidate gate slice 800 may make connections to different signal tracks in the upper metal layer. For example, slice 850 may connect to a first signal track, slice 852 may connect to a second signal track, and slice 856 may connect to a third signal track. Some slices may further divide the trench gate region 812 into two halves. For example, a trench cut layer 814 may separate the trench contact of the gate region 812. Slice 858 may include a connection to a second signal track on one side of the gate region 812, while slice 860 may include a connection to a second signal track on the other side of the gate region 812. Slice 862 may include a dummy gate that is not connected to the upper metal layer.

[0045]

[0056] Figure 9 shows candidate gate slices 900 that may be used to implement a selected transistor chain 706 according to several embodiments. Each candidate SD slice 900 may include a VDD region 904, a VSS region 901, a PSD region 902, an NSD region 903, a alignment shape 906, an SD connection 910, an SD cut layer for (optionally) separating source and drain, a metal layer contact 912 (e.g., vias), and a corresponding metal contact 914 within the metal layer.

[0046]

[0057] Figure 9 shows the specific connections and configurations of each of these different slices. For example, slice 920 may represent a slice in which the source and drain regions are not connected to signal or VSS / VDD tracks in the metal layer. Instead, the source and drain regions may be connected by abutting with adjacent source or drain regions of adjacent devices. Slice 922 may include an NSD connection to a third signal track, slice 924 may include a PSD connection to a first signal track, and slice 926 may include connections to both of these signal tracks. Slices 928 and 930 may include PSD connections to VSS with optional connections to the first signal track. Slices 932 and 934 may include NSD connections to VDD with optional connections to a third signal track. Slice 936 may include connections to VDD and VSS. Slices 938, 940, and 942 may include combined PSD and NSD connections to each of the three signal tracks.

[0047]

[0058] For each of the selected transistor chains 706, the tool can identify possible SD slices and gate slices from the layouts shown in Figures 8 and 9. These slices can then be optimized and combined to form the final layout of the circuit 600.

[0048]

[0059] Figure 10 shows a flowchart 1000 of a method for automatically generating a standard cell according to several embodiments. The method may include receiving a definition of a circuit for the standard cell (1002). The circuit may include one or more semiconductor devices. As described above, these devices may include building blocks (e.g., transistors and diodes, etc.) that can be combined together to form the standard cell. The circuit may be defined or represented by a netlist or other representation.

[0049]

[0060] The method may further include identifying multiple slices for implementing devices within one or more semiconductor devices of a standard cell (1004). As described above, slices may represent partial layouts for each of the devices. These partial layouts may not function on their own but can be combined to form a functioning device. Partial layouts may include layouts for source / drain regions, layouts for gate regions, and / or other regions for various devices. For example, multiple slices may include a first set of slices each implementing a partial layout in a different way (e.g., using different source / drain connections). Various implementation configurations may be connected to different cross-signal tracks in the upper metal layer. In some embodiments, the circuit definition for the standard cell may also be used to identify a device chain, such as a transistor chain, and the optimal device chain may be selected for implementation as described above. A device chain represents the connections between devices within the standard cell and between inputs and outputs. Then, a set of possible slices can be identified to implement each of the nodes or connections in the device chain. Thus, each slice may include partial layouts that can implement parts of multiple devices. For example, a slice implementing source / drain connections can implement source / drain connections for multiple transistors. Conversely, a slice implementing gate connections can be used to implement a partial layout for a single transistor. This same procedure can be performed for each device within a standard cell.

[0050]

[0061] It is possible to optimize this set of possible slices, and then, when forming a standard cell, combine the remaining set of slices to construct a combined layout and implement the device (1006). The combination of slices in the combined layout may include slices having partial layouts used to implement the aforementioned device (and possibly other devices simultaneously). The combined slices may also include other slices having partial layouts to implement the remaining devices within the standard cell. Thus, a partial layout of a slice for a single device may be only a part of the combination of slices used to generate the combined layout.

[0051]

[0062] Figure 11 shows a flowchart of operations that may be used to select and optimize a set of slices used to implement a standard cell according to several embodiments. This method may include receiving a device chain (1102) that implements the standard cell. These operations may be performed after the selected device chain 706, as described above in relation to Figure 7, has been identified and selected. As shown in Figure 11, each connection of a device in a device chain (e.g., source, drain, gate, etc.) can be considered a node in the circuit. As described above, the device chains may be selected to maximize the number of nodes that have common connections across each device chain.

[0052]

[0063] This method may include selecting a set of candidate slices from a slice library that can be used for each connection (1104). As shown in Figure 11, possible slices for each node can be selected by identifying the nodes that may make the necessary connections. For example, slice 930 (SDVSSP3) in Figure 9 may be used to implement the connection at node 1 because it contains a connection to the VSS and a signal track on the metal layer that can be used as an output. In another embodiment, any of the gate slices 850, 852, and 856 may be used to implement nodes 2 and 4, since these nodes only require connections to output signals in the metal layer. The set of possible slices that can be used to implement each other connection can be identified in a similar manner.

[0053]

[0064] The method may further include optimizing the slice selection for each node (1106). For example, the total Cartesian product of the possible slices for each node identified in operation 1104 may include 54 possible slice sequences. To optimize these slice selections for each node, signals can be assigned to signal tracks in the metal layer, and the suitability of each possible slice can be determined. For example, since only track 3 is available for the SDVSSP3 slice 930, track 3 must be assigned to the output. This effectively eliminates slices GT3, SDPN1, and SDPN2, because these slices either connect their outputs to other tracks or connect other signals to the output track. Thus, optimization can be performed by limiting slices that conflict with connections to tracks in the metal layer.

[0054]

[0065] Another optimization method may involve identifying internal connections that do not require connections to the metal track. For example, node n1, which internally connects two PFETs, can eliminate slice SDVDDN1 because it does not need to connect to other nodes via the metal layer. Instead, this connection can be facilitated by connecting these slices together by the abutment of adjacent SDs as described above. This allows the tool to optimize the set of candidate slices for each node by limiting the slices that can be implemented by placing two slices adjacent to each other.

[0055]

[0066] The method may further include generating combinations of slices to implement a standard cell (1108). By combining the Cartesian products of the remaining possible slices of each node, one or more combination slices may be formed from the set of candidate slices. Each of these combinations can individually implement a standard cell. The method may then include optimizing the combinations of slices based on the design rules of the metal layer (1110). The first and fourth slice combinations in Figure 11 can be eliminated because using either GT1 or GT2 exclusively for both gates would lead to a collision in the metal layer between these two input signals. In the remaining two slice combinations, GT1 is used for one input and GT2 for the other.

[0056]

[0067] The method may further include completing BEOL routing for each of the remaining slice combinations (1112). As described above, several embodiments may fully implement multiple different layout options for the standard cell. These various options may be simulated and tested at various levels of the design pipeline to identify the standard cell that yields the best test results. For example, the standard cell with the best cost or the best PPA score may be selected as the final result for the standard cell.

[0057]

[0068] The operations described in Figures 10 and 11 may be performed for various implementations of various devices. One of the many technical advantages provided by these embodiments is that it allows standard cell designers to easily swap device technologies without relying on manual intervention and automatically synthesize the resulting standard cells. For example, returning to Figure 1, the library of slice definitions 108 may be replaced with another library of slices containing various implementations of slices for devices in a device chain. For example, the transistors defined by the first library may include MOSFETs with various source / drain and gate slices. The second library may include a different type of transistor (e.g., a finFET with corresponding source / drain and gate fin slices). Since the slice interface remains the same (e.g., gate, source, drain), details of the underlying implementation can be contained within the slice itself. Thus, tool 101 can perform the same process described above for both different device types in the various slice libraries in order to quickly generate various implementations of standard cells.

[0058]

[0069] It should be understood that the specific steps shown in Figures 10 and 11 provide a specific method for automatically generating standard cells according to various embodiments. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments may perform the steps described above in a different order. Furthermore, the individual steps shown in Figures 10 and 11 may include multiple substeps that can be performed in various sequences suitable for the individual steps. In addition, additional steps may be added or removed depending on the particular application. Many variations, modifications, and alternatives are also included in the scope of this disclosure.

[0059]

[0070] Each of the methods described herein may be implemented by a computer system. Each step of these methods may be performed automatically by the computer system and / or provided with user-involved inputs / outputs. For example, a user may provide inputs for each step in the method. Each of these inputs may be in response to a particular output requesting such input, where the output is generated by the computer system. Each input may be received in response to a corresponding requested output. Furthermore, inputs may be received from a user, received as a data stream from another computer system, retrieved from a memory location, retrieved over a network, requested from a web service, and so on. Similarly, outputs may be provided to a user, provided as a data stream to another computer system, stored in a memory location, sent over a network, provided to a web service, and so on. In short, each step of the methods described herein may be performed by a computer system and may involve any number of inputs, outputs, and / or requests to and from the computer system, which may or may not involve a user. Steps that do not involve the user are sometimes said to be performed automatically by a computer system without human intervention. Therefore, in light of this disclosure, it will be understood that each step of each method described herein may be modified to include input and output to and from a user, or may be performed automatically by a computer system without human intervention, where any decisions are made by a processor. Furthermore, several embodiments of each of the methods described herein may be implemented as a set of instructions stored in a tangible, non-temporary storage medium to form a tangible software product.

[0060]

[0071] Figure 12 shows an exemplary computer system 1200 in which various embodiments can be implemented. System 1200 can be used to implement any of the computer systems described above. For example, computer system 1200 can be used to perform the methods described above in relation to Figures 10 and 11. As shown in the figure, computer system 1200 includes a processing unit 1204 that communicates with several peripheral subsystems via a bus subsystem 1202. These peripheral subsystems may include a processing acceleration unit 1206, an I / O subsystem 1208, a storage subsystem 1218, and a communication subsystem 1224. The storage subsystem 1218 includes a tangible computer-readable storage medium 1222 and system memory 1210.

[0061]

[0072] The bus subsystem 1202 provides a mechanism for various components and subsystems of the computer system 1200 to communicate with each other as intended. Although the bus subsystem 1202 is schematically shown as a single bus, alternative embodiments of the bus subsystem may utilize multiple buses. The bus subsystem 1202 may be one of several types of bus structures, including a memory bus or memory controller, a peripheral bus, and a local bus using any of the various bus architectures. For example, such architectures may include industry standard architecture (ISA) buses, microchannel architecture (MCA) buses, extended ISA (EISA) buses, video electronics standards institute (VESA) local buses, and peripheral component interconnect (PCI) buses, which may be implemented as mezzanine buses manufactured to the IEEE P1386.1 standard.

[0062]

[0073] The processing unit 1204, which can be implemented as one or more integrated circuits (e.g., conventional microprocessors or microcontrollers), controls the operation of the computer system 1200. One or more processors may be included in the processing unit 1204. These processors may include single-core processors or multi-core processors. In certain embodiments, the processing unit 1204 is implemented as one or more independent processing units 1232 and / or 1234, each processing unit may include a single or multi-core processor. In other embodiments, the processing unit 1204 may also be implemented as a quad-core processing unit formed by integrating two dual-core processors onto a single chip.

[0063]

[0074] In various embodiments, the processing unit 1204 can execute various programs in response to program code and can maintain multiple programs or processes running simultaneously. At a given time, some or all of the program code to be executed may reside in one or more processors 1204 and / or in the storage subsystem 1218. Through suitable programming, one or more processors 1204 can provide the various functions described above. The computer system 1200 may further include a processing acceleration unit 1206 (which may include a digital signal processor (DSP) or a dedicated processor, etc.).

[0064]

[0075] The I / O subsystem 1208 may include user interface input devices and user interface output devices. User interface input devices may include pointing devices such as keyboards, mice or trackballs, touchpads or touchscreens integrated into displays, scroll wheels, click wheels, dials, buttons, switches, keypads, audio input devices with voice command recognition systems, microphones, and other types of input devices. User interface input devices may include, for example, motion detection and / or gesture recognition devices (e.g., Microsoft Kinect® motion sensor, which enables a user to control and interact with an input device such as a Microsoft Xbox® 360 game controller via a natural user interface using gestures or spoken commands). User interface input devices may further include eye gesture recognition devices (e.g., Google Glass® blink detector, which detects eye activity from a user (e.g., blinking while taking a picture and / or making a menu selection) and translates the eye gestures as input to an input device (e.g., Google Glass®). Furthermore, the user interface input device may include a voice recognition detection device that enables the user to interact with a voice recognition system (e.g., Siri® Navigator) via voice commands.

[0065]

[0076] User interface input devices may, but are not limited to, include, three-dimensional (3D) mice, joysticks or pointing sticks, gamepads and graphic tablets, audio / visual devices such as speakers, digital cameras, digital camcorders, portable media players, webcams, image scanners, fingerprint scanners, barcode readers, 3D scanners, 3D printers, laser rangefinders, and eye-tracking devices. Furthermore, user interface input devices may include, for example, medical imaging input devices such as computed tomography, magnetic resonance imaging, positional emission tomography, and medical ultrasound imaging devices. User interface input devices may further include, for example, audio input devices such as MIDI keyboards and digital musical instruments.

[0066]

[0077] User interface output devices may include non-visual displays such as display subsystems, indicator lights, or audio output devices. Display subsystems may include flat panel devices such as cathode ray tubes (CRTs), liquid crystal displays (LCDs), or plasma displays, projection devices, touchscreens, etc. In general, the use of the term “output device” shall include all possible types of devices and mechanisms for outputting information from the computer system 1200 to a user or another computer. For example, user interface output devices may include, but are not limited to, various display devices that visually convey text, graphics, and audio / video information (e.g., monitors, printers, speakers, headphones, car navigation systems, plotters, audio output devices, and modems).

[0067]

[0078] The computer system 1200 may include a storage subsystem 1218 containing software elements that are currently located in the system memory 1210. The system memory 1210 may store program instructions that can be loaded and executed on the processing unit 1204, as well as data generated during the execution of these programs.

[0068]

[0079] Depending on the configuration and type of the computer system 1200, the system memory 1210 may be volatile (e.g., random access memory (RAM)) and / or non-volatile (e.g., read-only memory (ROM) or flash memory). RAM typically contains data and / or program modules that are immediately accessible and / or currently being manipulated and executed by the processing unit 1204. In some implementations, the system memory 1210 may include several different types of memory, such as static random access memory (SRAM) or dynamic random access memory (DRAM). In some implementations, the basic input / output system (BIOS) (which includes basic routines that help transfer information between elements within the computer system 1200, such as during startup) may be stored in ROM. As an example, but not an limitation, the system memory 1210 may include application programs 1212 (which may include client applications, web browsers, intermediate-tier applications, relational database management systems (RDBMS), etc.), program data 1214, and the operating system 1216. For example, Operating System 1216 may include various versions of Microsoft Windows®, Apple Macintosh®, and / or Linux operating systems, various commercially available UNIX® or UNIX-like operating systems (including, but not limited to, various GNU / Linux operating systems, Google Chrome® OS, etc.), and / or mobile operating systems such as iOS, Windows® Phone, Android® OS, BlackBerry® 10 OS, and Palm® OS.

[0069]

[0080] The storage subsystem 1218 may further provide a tangible, computer-readable storage medium for storing basic programming and data structures that provide the functionality of several embodiments. Software (programs, code modules, instructions) that, when executed by the processor, provides the functionality described above, may be stored in the storage subsystem 1218. These software modules or instructions may be executed by the processing unit 1204. The storage subsystem 1218 may also provide a repository for storing data used according to several embodiments.

[0070]

[0081] The memory subsystem 1200 may further include a computer-readable storage medium reader 1220, which may be further connected to the computer-readable storage medium 1222. Together with the system memory 1210, and optionally in combination with the system memory 1210, the computer-readable storage medium 1222 may comprehensively represent remote, local, fixed, and / or removable storage devices and storage media for temporarily and / or more permanently containing, storing, transmitting, and retrieving computer-readable information.

[0071]

[0082] The computer-readable storage medium 1222 containing code or a portion of code may further include any suitable medium (including, but not limited to, storage and communication media such as volatile and non-volatile, removable and non-removable media, which are implemented in any method or technique for storing and / or transmitting information). This may include tangible computer-readable storage media (e.g., RAM, ROM, electronically erasable programmable ROM (EEPROM), flash memory or other memory technologies, CD-ROM, digital multipurpose disk (DVD), or other optical storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices), or other tangible computer-readable media. This may further include non-tangible computer-readable media (e.g., any other medium that can be used to transmit data signals, data transmission, or desired information and is accessible by the computing system 1200).

[0072]

[0083] For example, computer-readable storage media 1222 may include hard disk drives that read from or write to non-removable non-volatile magnetic media, magnetic disk drives that read from or write to removable non-volatile magnetic disks, and optical disk drives that read from or write to removable non-volatile optical disks, such as CD-ROMs, DVDs, and Blu-ray® discs, or other optical media. Computer-readable storage media 1222 may also include, but are not limited to, Zip® drives, flash memory cards, Universal Serial Bus (USB) flash drives, Secure Digital (SD) cards, DVD discs, digital videotapes, and the like. The computer-readable storage medium 1222 may further include flash memory-based solid-state drives (SSDs), enterprise flash drives, SSDs based on non-volatile memory such as solid-state ROM, SSDs based on volatile memory such as solid-state RAM, dynamic RAM, static RAM, DRAM-based SSDs, magnetoresistive RAM (MRAM) SSDs, and hybrid SSDs using a combination of DRAM and flash memory-based SSDs. The disk drives and their associated computer-readable media may provide non-volatile storage for computer-readable instructions, data structures, program modules, and other data for the computer system 1200.

[0073]

[0084] The communication subsystem 1224 provides interfaces to other computer systems and networks. The communication subsystem 1224 acts as an interface for receiving data from other systems and for transmitting data from computer system 1200 to other systems. For example, the communication subsystem 1224 may enable computer system 1200 to connect to one or more devices via the Internet. In some embodiments, the communication subsystem 1224 may include radio frequency (RF) transceiver components for accessing wireless voice and / or data networks (e.g., using cellular telephone technology, 3G, 4G, or advanced data network technologies such as EDGE (Global Evolutionary High Speed ​​Data Rate), WiFi (IEEE 802.11 family standards), or other mobile communication technologies, or any combination thereof), a Global Positioning System (GPS) receiver component, and / or other components. In some embodiments, the communication subsystem 1224 may provide wired network connectivity (e.g., Ethernet) in addition to or instead of the wireless interface.

[0074]

[0085] In some embodiments, the communication subsystem 1224 may receive input communications in the form of structured and / or unstructured data feeds 1226, event streams 1228, event updates 1230, etc., for one or more users who may use the computer system 1200.

[0075]

[0086] For example, the communication subsystem 1224 may be configured to receive data feeds 1226 in real time from users of social networks and / or other communication services, such as web feeds including Twitter® feeds, Facebook® updates, Rich Site Summary (RSS) feeds, and / or real-time updates from one or more third-party information sources.

[0076]

[0087] Furthermore, the communication subsystem 1224 may be further configured to receive data in the form of a continuous data stream. This data may include an event stream 1228 of real-time events and / or event updates 1230. These may have no explicit end and may be substantially continuous or infinite. Examples of applications that generate continuous data may include, for example, sensor data applications, financial tickers, network performance measurement tools (e.g., network monitoring and traffic management applications), clickstream analysis tools, and automotive traffic monitoring.

[0077]

[0088] The communication subsystem 1224 may be further configured to output structured and / or unstructured data feeds 1226, event streams 1228, event updates 1230, etc., to one or more databases that can communicate with one or more streaming data source computers coupled to the computer system 1200.

[0078]

[0089] The computer system 1200 may be one of various types, including handheld portable devices (e.g., iPhone® cellular phone, iPad® computing tablet, PDA), wearable devices (e.g., Google Glass® head-mounted display), PCs, workstations, mainframes, kiosks, server racks, or any other data processing systems.

[0079]

[0090] Due to the ever-changing nature of computers and networks, the description of the computer system 1200 shown in the figure is merely an example. Many other configurations are possible, having more or fewer components than the system shown in the figure. For example, customized hardware may be used, and / or certain elements may be implemented in hardware, firmware, software (including applets), or a combination thereof. Furthermore, connections to other computing devices, such as network input / output devices, may be employed. Based on the disclosures and teachings provided herein, other ways and / or methods for implementing various embodiments should be apparent.

[0080]

[0091] As used herein, the terms “about,” “approximately,” and “substantially” should be interpreted as being within the range expected by those skilled in the art in light of this specification.

[0081]

[0092] In the above description, for the sake of clarity and to provide a complete understanding of various embodiments, numerous specific details have been included. However, it will be apparent that some embodiments can be carried out without some of these specific details. In other examples, well-known structures and devices are shown in the form of block diagrams.

[0082]

[0093] The above description provides only illustrative embodiments and does not limit the scope, applicability, or configuration of this disclosure. Rather, the foregoing description of various embodiments provides a feasible disclosure for implementing at least one embodiment. It should be understood that various modifications may be made to the function and arrangement of the elements without departing from the spirit and scope of some embodiments, as described in the appended claims.

[0083]

[0094] Specific details are given in the above description to provide a complete understanding of the embodiments. However, it will be understood that embodiments can be carried out even without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in the form of block diagrams to avoid obscuring the embodiments with unnecessary details. In other examples, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary details to avoid obscuring the embodiments.

[0084]

[0095] Furthermore, note that individual embodiments have been described as processes, shown as flowcharts, flow diagrams, data flow diagrams, structural diagrams, or block diagrams. While flowcharts may describe operations as sequential processes, many operations can be performed in parallel or simultaneously. Moreover, the order of operations may be rearranged. A process terminates when an operation is completed, but there may be additional steps not shown in the diagram. A process can correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, its termination may correspond to the function's return to the calling function or main function.

[0085]

[0096] The term “computer-readable medium” includes, but is not limited to, portable or fixed-storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying one or more instructions and / or data. A code segment or machine-executable instruction may represent a procedure, function, subprogram, program, routine, subroutine, module, software package, class, or any combination of instructions, data structures, or program statements. A code segment may be connected to another code segment or hardware circuit by passing information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc., may be passed, transferred, or transmitted via any suitable means, including memory sharing, message passing, token passing, network transmission, etc.

[0086]

[0097] Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, a hardware description language, or any combination thereof. If implemented by software, firmware, middleware, or microcode, program code or code segments for performing the required tasks may be stored in a machine-readable medium. One or more processors may perform the required tasks.

[0087]

[0098] While the features are described in the above specification with reference to specific embodiments, it should be noted that not all embodiments are limited thereto. Various features and aspects of several embodiments may be used individually or collectively. Furthermore, embodiments may be used in any number of environments and applications other than those described herein without departing from the broader spirit and scope of this specification. Accordingly, this specification and the drawings should be considered illustrative, not limiting.

[0088]

[0099] Furthermore, for illustrative purposes, the method has been described in a specific order. It should be understood that in alternative embodiments, the method may be performed in an order different from that described. Furthermore, it should be understood that the method described above may be performed by hardware components or embodied by a sequence of machine-executable instructions, which can be used to cause a machine (e.g., a general-purpose or special-purpose processor, or a logic circuit programmed with instructions) to perform the method. These machine-executable instructions may be stored in one or more machine-readable media (e.g., CD-ROM or other types of optical disks, floppy diskettes, ROM, RAM, EPROM, EEPROM, magnetic or optical cards, flash memory, or other types of machine-readable media suitable for storing electronic instructions). Alternatively, the method may be implemented by a combination of hardware and software.

Claims

1. A method for automatically generating standard cells, Receiving a definition of a circuit for a standard cell by a computer system, wherein the circuit includes one or more semiconductor devices; The computer system identifies a plurality of slices for mounting a device within the one or more semiconductor devices, wherein each of the plurality of slices includes a partial layout for the device. When forming the standard cell, the computer system combines one or more slices from the plurality of slices to form a combined layout and implement the device. A method that includes this.

2. The method according to claim 1, wherein the device includes a functional circuit element.

3. The method according to claim 2, wherein the partial layout is not a functional circuit element, and the combined layout forms the functional circuit element.

4. The method according to claim 2, wherein one of the plurality of slices includes a partial layout for one or more semiconductor devices than the one or more of the plurality of semiconductor devices, and the combined layout includes additional slices, together with one or more of the plurality of slices, for mounting the one or more semiconductor devices for the standard cell.

5. The first slice among the plurality of slices includes a first partial layout for the device, The method according to claim 1, wherein a second slice among the plurality of slices includes a second partial layout for the device.

6. The method according to claim 5, wherein the first partial layout includes a layout of the source region or drain region of a transistor.

7. The method according to claim 5, wherein the second partial layout includes a layout of the gate region of a transistor.

8. It is a system, One or more processors, and One or more memory devices containing instructions The instruction, when executed by the one or more processors, is provided to the one or more processors, Receiving a definition of a circuit for a standard cell, wherein the circuit includes one or more semiconductor devices, Identifying a plurality of slices for mounting a device within the one or more semiconductor devices, wherein each of the plurality of slices includes a partial layout for the device. When forming the standard cell, one or more slices from the plurality of slices are combined to form a combined layout and implement the device. A system that allows you to perform operations that include [specific actions].

9. The plurality of slices include a first set of slices, each slice in the first set includes a different implementation of a first partial layout for the device. The system according to claim 8, wherein the operation further comprises selecting a first slice from the first set of slices for the device.

10. The first slice includes a connection to a first cross track in the metal layer, The system according to claim 9, wherein a second slice in a second set of slices for the device includes a connection to a second cross track in the metal layer.

11. The system according to claim 8, wherein the operation further comprises determining one or more device chains for generating a cell layout for the standard cell, the one or more device chains representing connections between devices in the one or more semiconductor devices and inputs and outputs in the standard cell.

12. The system according to claim 11, wherein the operation further comprises selecting a set of candidate slices from a slice library that can be used to implement each of the connections.

13. The aforementioned operation, Assigning tracks in the metal layer to the input / output within the standard cell, The set of candidate slices is optimized by eliminating slices that can be implemented by placing two slices adjacent to each other, By eliminating slices that have conflicting connections to the tracks within the metal layer, the set of candidate slices is optimized. The system according to claim 12, further comprising:

14. The system according to claim 13, further comprising generating one or more combinations of slices from the set of candidate slices, each of which implements the standard cell.

15. The aforementioned operation, The system according to claim 14, further comprising optimizing one or more combinations of the slices based on design rules for the metal layer, wherein one or more combinations of slices includes the plurality of slices for the optimized device.

16. One or more non-temporary computer-readable media containing instructions, wherein, when the instructions are executed by one or more processors, the one or more processors, Receiving a definition of a circuit for a standard cell, wherein the circuit includes one or more semiconductor devices, Identifying a plurality of slices for mounting a device within the one or more semiconductor devices, wherein each of the plurality of slices includes a partial layout for the device. When forming the standard cell, one or more slices from the plurality of slices are combined to form a combined layout and implement the device. A non-temporary computer-readable medium that allows operations including the following to be performed.

17. The definition of the circuit includes a netlist having device characteristics and connections between the one or more semiconductor devices, according to claim 16, one or more non-temporary computer-readable media.

18. The aforementioned operation, The method further includes accessing a first slice library for the device and retrieving the plurality of slices, The one or more non-temporary computer-readable media according to claim 16, wherein the first slice library includes partial layouts for various implementations of the first device type for the device.

19. The one or more non-temporary computer-readable media according to claim 18, further comprising a second slice library for the device, wherein the second slice library includes partial layouts for various implementations of a second device type for the device.

20. One or more non-temporary computer-readable media according to claim 19, wherein the device includes a transistor, the first device type includes a metal-oxide-semiconductor field-effect transistor (MOSFET), and the second device type includes a fin field-effect transistor (FinFET).

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