A method for inspecting via holes in wafers using deep learning.

The wafer inspection system uses deep learning to automate wafer handling and defect detection, addressing limitations of existing methods by ensuring accurate and efficient inspection of via holes in wafers.

JP2026510386APending Publication Date: 2026-04-02GOOIL SOLUTION CO LTD
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Applications
Current Assignee / Owner
Filing Date
2024-10-14
Publication Date
2026-04-02

AI Technical Summary

Technical Problem

Existing methods for inspecting via holes in wafers are limited by time delays, vibrations, and small inspection areas, making it difficult to accurately confirm the formation of via holes according to design intentions and detect shape and depth defects.

Method used

A wafer inspection system using deep learning to analyze 3D image information, combining a wafer transfer unit, inspection unit, and control unit to automate wafer handling, edge detection, and defect judgment, enabling continuous imaging and accurate defect determination through edge and volume analysis.

Benefits of technology

Enables rapid wafer transfer and accurate detection of shape and depth defects in via holes, improving inspection efficiency and reliability compared to existing methods.

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Abstract

The present invention relates to a method for inspecting via holes formed on a wafer, and more specifically, to an inspection method for inspecting the presence or absence of shape defects in via holes formed on a wafer using deep learning. The method for determining the presence or absence of shape defects in via holes formed on a wafer using a program built into a wafer inspection system includes the steps of: receiving 3D image information of the via holes formed on the wafer; detecting the edges of the via holes using the provided 3D image information and an edge detection algorithm; confirming whether the detected edges are within a predetermined range and determining whether the shape of the via holes is good or bad; generating defect judgment training data by learning the 3D image information of the via holes and the determined shape defect information using a deep learning algorithm; and determining the presence or absence of shape defects from the input 3D image of the via holes using the defect judgment training data.
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Description

Technical Field

[0001] The present invention relates to a method for inspecting via holes formed in a wafer, and more particularly, to an inspection method for inspecting whether there are shape defects in the via holes formed in the wafer by using deep learning.

Background Art

[0002] Recently, as miniaturization, multifunctionalization, and thin film type of electronic products are required, in order to improve the integration degree of devices in the semiconductor industry, 3D packaging processes such as TSV (Through Silicon Via) and POP (Package on Package), which are next-generation semiconductor technologies, have attracted attention.

[0003] Particularly, in order to confirm defects during the TSV process, after fabricating a stacked circuit, an actual operation test is performed or a sample is destroyed and confirmed using equipment such as a SEM (scanning electron microscope).

[0004] Although approaches have been made in a non-contact / non-destructive manner using a confocal microscope or WSI, etc., when acquiring three-dimensional image information by a method of scanning the cross-section as the Z-axis, there is a limit in mounting on an in-line equipment due to the influence of time delay and vibration.

[0005] In order to solve such problems, recently, inspections at the sample test level using a digital holographic microscope (Digital Holographic microscopy, DHM) have been carried out, but since the inspection area by the digital holographic microscope is very small compared to the wafer area to be inspected, it has not been substantially applied to semiconductor inspection lines. In addition, there is a need for a solution that can inspect whether the via holes formed in the wafer are accurately formed according to the designer's intention.

Summary of the Invention

Problems to be Solved by the Invention

[0006] The present invention aims to solve these problems by providing a wafer inspection system configured to allow operators to easily perform wafer supply, 3D image generation, and control processes when inspecting for abnormalities in wafers, and to confirm the presence or absence of abnormalities in wafers with high accuracy.

[0007] Furthermore, the present invention aims to solve these problems by providing a method for inspecting whether or not via holes formed on a wafer have defects in shape and depth.

[0008] Furthermore, the present invention aims to solve these problems by providing a method for inspecting for defects in the shape and depth of via holes formed on a wafer using deep learning. [Means for solving the problem]

[0009] To this end, the method for determining whether or not there are shape defects in via holes formed on a wafer using a program built into the wafer inspection system proposed in the present invention is characterized by comprising the steps of: receiving 3D image information of via holes formed on a wafer; detecting the edges of the via holes using the provided 3D image information and an edge detection algorithm; confirming whether the detected edges are within a predetermined range and determining whether or not the shape of the via holes is good or bad; generating defect judgment learning data by learning the 3D image information of the via holes and the determined shape defect information using a deep learning algorithm; and determining whether or not there are shape defects from the input 3D image of the via holes using the defect judgment learning data. [Effects of the Invention]

[0010] The wafer inspection system according to the present invention provides an automated method for pulling out wafers from a cassette placed on a load port or inserting wafers into the cassette, thereby enabling rapid wafer transfer.

[0011] Furthermore, the wafer inspection system according to the present invention provides a configuration that allows the wafer to be continuously moved left / right or forward / backward in accordance with the imaging and inspection area of ​​the digital holographic microscope, so that the presence or absence of abnormalities in the wafer can be accurately determined from the three-dimensional image information of the wafer using the holographic image.

[0012] Furthermore, the via hole inspection method for wafers using deep learning according to the present invention divides the via holes formed on the wafer into a number of regions and utilizes the volume of the divided regions to accurately determine whether or not there are defects in the shape and depth of the via holes compared to existing methods. [Brief explanation of the drawing]

[0013] [Figure 1] This is a perspective view of a wafer inspection system according to one embodiment of the present invention. [Figure 2] This is a rear-view perspective of the overall configuration of the wafer transfer unit according to one embodiment of the present invention. [Figure 3] Figure 2 is a plan view of the wafer transfer section. [Figure 4] This is a perspective view of a wafer inspection unit according to one embodiment of the present invention. [Figure 5] Figure 4 is a plan view of the wafer inspection section. [Figure 6] Figure 4 is a side view of the wafer inspection section. [Figure 7] This figure shows a wafer placed on a rotating stage according to one embodiment of the present invention. [Figure 8] This is a perspective view showing a rotating stage according to one embodiment of the present invention positioned below an optical module. [Figure 9] It is a diagram showing a procedure for determining the presence or absence of shape defects and depth defects of via holes formed in a wafer according to an embodiment of the present invention. [Figure 10] It is a diagram showing an example of extracting the edge of a via hole according to an embodiment of the present invention. [Figure 11] It is a diagram showing an example of determining the presence or absence of shape defects of a via hole according to an embodiment of the present invention. [Figure 12] It is a diagram showing an example of determining the presence or absence of depth defects of a via hole using volume according to an embodiment of the present invention. [Figure 13] It is a diagram showing a method for inspecting the presence or absence of shape defects of via holes in a wafer using deep learning according to an embodiment of the present invention. [Figure 14] It is a diagram showing an image of a wafer's via hole taken and an image restored in three dimensions. [Figure 15] It is an image obtained by a line scan camera. [Figure 16] It is a diagram in which the edge inclination of the acquired image is formed into a three-dimensional shape. [Figure 17] It is a diagram showing typical morphological structure elements. [Figure 18] It is a diagram schematically showing the process in which morphology is applied according to the values of each structure element. [Figure 19a] It is an image for measuring the diameter of a via hole and the pitch between patterns using an edge detection image processing technique. [Figure 19b] It is a diagram for extracting a blob using a morphological algorithm, calculating the number of pixels in the corresponding blob, and measuring the area of the via hole.

Embodiments for Carrying Out the Invention

[0014] The advantages, features, and methods for achieving these of the present invention will become clear by referring to the embodiments described in detail hereinafter together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be realized in a variety of different forms. These embodiments are provided to complete the disclosure of the present invention and to fully inform those who are ordinary skill in the art to which the invention pertains, and the present invention is defined only by the scope of the claims.

[0015] A wafer inspection system according to one embodiment of the present invention will be described in detail below with reference to Figures 1 to 8. In describing the present invention, specific descriptions of related known functions or configurations will be omitted in order to clarify the gist of the invention.

[0016] Figure 1 is a perspective view of a wafer inspection system according to one embodiment of the present invention, Figure 2 is a perspective view showing the overall configuration of the wafer transfer unit according to one embodiment of the present invention, Figure 3 is a plan view of the wafer transfer unit shown in Figure 2, Figure 4 is a perspective view of the wafer inspection unit according to one embodiment of the present invention, Figure 5 is a plan view of the wafer inspection unit shown in Figure 4, Figure 6 is a side view of the wafer inspection unit shown in Figure 4, Figure 7 shows a state in which a wafer is placed on the rotating stage according to one embodiment of the present invention, and Figure 8 is a perspective view showing a state in which the rotating stage according to one embodiment of the present invention is positioned below the optical module.

[0017] As shown in Figures 1 to 5, a wafer inspection system 100 according to one embodiment of the present invention may include: a wafer transfer unit 200 that loads and unloads a wafer W (see Figure 7) to be inspected; a wafer inspection unit 300 that receives the wafer W from the wafer transfer unit 200 and acquires three-dimensional image information of the wafer using a hologram image; and a control unit 400 that determines whether or not there is an abnormality in the wafer W from the three-dimensional image information measured by the wafer inspection unit 300 and controls the wafer transfer unit 200 and the wafer inspection unit 300.

[0018] First, the wafer transfer unit 200 is a device for loading or unloading wafers W into the wafer inspection unit 300, which will be described later, and is located inside the housing 10 shown in Figure 1.

[0019] As shown in Figures 2 and 3, the wafer transfer unit 200 may include a load port 210 on which a cassette (not shown) containing wafers W (see Figure 7) is placed, a robot arm 220 for picking up the wafers W from the cassette placed on the load port 210, and an alignment unit 230 for aligning the wafers W picked up by the robot arm 220.

[0020] The load port 210 is provided on one surface of the housing 10 and provides a predetermined space in which a wafer W can be placed. It also includes a gate 211 to transfer the wafer W placed in the space into the interior of the housing 10. In one embodiment of the present invention, the drawings show that a pair of load ports 210 are provided on one surface of the housing 10.

[0021] Of the pair of load ports 210, one load port 210 can hold a cassette containing wafers W to be inspected, and the other load port 210 can hold a cassette containing inspected wafers W. Therefore, it is preferable that at least one load port 210 be provided on one surface of the housing 10.

[0022] The robot arm 220 can be positioned on one side inside the housing 10 and plays a role in transferring the wafer W placed on the load port 210.

[0023] The robot arm 220 is configured to rotate in the direction in which the load port 210 or alignment unit 230 is located, and is also configured to rotate in the direction in which the wafer inspection unit 300, described later, is located.

[0024] As shown in Figure 2, the robot arm 220 may include a first arm 221 whose longitudinal end is rotatably connected to a drive shaft, a second arm 222 whose longitudinal end is rotatably connected to the other longitudinal end of the first arm 221, and a pickup arm 223 whose longitudinal end is rotatably connected to the other longitudinal end of the second arm 222, and which is provided with a pickup member 223a for gripping a wafer W at the other longitudinal end.

[0025] The first arm 221, the second arm 222, and the pickup arm 223 are configured to be rotatable in one direction or in other directions, and can be rotated individually or simultaneously in various directions. For example, one of the configurations of the first arm 221, the second arm 222, and the pickup arm 223 can be selectively driven or driven simultaneously to pick up a wafer W from a cassette placed on the load port 210, or to transfer the picked-up wafer W to the alignment unit 230 or the wafer inspection unit 300.

[0026] On the other hand, the pickup member 223a provided at the tip of the pickup arm 233 can be said to be a component that directly grips the wafer. The pickup member 223a can have an overall fork shape and can be positioned on the top and bottom of the wafer W, respectively. That is, the pickup members 223A can be configured in pairs, and when they move toward each other and narrow, they can grip the wafer W.

[0027] The alignment section 230 is a component for aligning the wafer W supported by the pickup arm 233, and can typically be implemented in a known wafer mounting aligner. A typical aligner can align wafers using a CCD camera, infrared, or ultrasonic sensor.

[0028] The wafer transfer unit 200 configured in this way can sequentially perform the following steps: picking up the wafer W placed on the load port 210, aligning the picked-up wafer W, and supplying the aligned wafer W to the wafer inspection unit 300. The wafer inspection unit 300 can be described as a device that receives the wafer W to be inspected from the wafer transfer unit 200 and inspects whether or not there are any abnormalities in the wafer W.

[0029] As shown in Figures 4 to 8, a wafer inspection unit 300 according to one embodiment of the present invention may include: a rotating stage 310 on which a wafer W to be inspected is placed and which aligns the wafer W; a first stage 320 to which the rotating stage 310 is attached and which moves the rotating stage 310 forward or backward; a second stage 330 to which the first stage 320 is attached and which moves the first stage 320 to the left or right; and an optical module 340 that photographs the wafer W placed on the rotating stage 310 and acquires three-dimensional hologram information. The rotary stage 310 rotates by receiving power from a drive unit (not shown) and may include a rotary plate 311 on which wafers to be inspected are placed. The rotating plate 311 provides a predetermined area on which the wafer W can be placed.

[0030] Furthermore, the rotating plate 311 can be made of a porous material in order to fix the wafer W using a vacuum suction method. That is, a channel through which air can flow can be formed in the lower part of the rotating plate 311, and when an air pump (not shown) is activated, the wafer W can be attracted to the rotating plate 311. Furthermore, the rotating plate 311 may be provided with mounting grooves 312.

[0031] The tip of the pickup arm 223, which grips the wafer W, can be inserted into the mounting groove 312 of the rotating plate 311. Therefore, the mounting groove 312 can have a shape that corresponds to the pickup member 223a provided at the tip of the pickup arm 223.

[0032] As shown in Figure 7, when the pickup member 223a, which is gripping the wafer W, is inserted into the mounting groove 312 provided on the rotating plate 311, the wafer W can be placed on the upper surface of the rotating plate 311.

[0033] When the pickup member 223a of the pickup arm 223 slides and detaches from the mounting groove 312 in the state described above, the wafer W can be vacuum-adsorbed onto the rotating plate 311.

[0034] The rotating plate 311 rotates while holding the wafer W in place, allowing the inspection area of ​​the wafer W to be aligned with the lens of the optical module 340, which will be described later.

[0035] The first stage 320 is equipped with a guide rail for moving the rotating stage 310 forward or backward, and this guide rail is connected to the rotating stage 310. The power source for moving the rotary stage 310 mounted on the first stage 320 can consist of a drive motor or a known actuator.

[0036] The second stage 330 is equipped with a guide rail for moving the first stage 320 to the left or to the right, and this guide rail is connected to the first stage 320. Similarly, the power source for transporting the first stage 320 mounted on the second stage 330 can consist of a drive motor or a known actuator. The aforementioned rotating stage 310, first stage 320, and second stage 330 may be provided on the surface plate 370. In this configuration, the second stage 330 may be positioned along the length of the surface plate 370, and the first stage 320 may be positioned along the width of the surface plate.

[0037] The first stage 320 and the second stage 330 are responsible for transporting the wafer W, which is placed on the rotating plate 311, along the length or width of the base plate 370.

[0038] In other words, as shown in Figure 8, the first stage 320 and the second stage 330 are also configured so that the inspection area of ​​the wafer W to be inspected corresponds to the lens of the optical module 340. The optical module 340 can be mounted on a support frame 380 provided on the surface plate 370 so as to be able to move up or down. The support frame 380 is mounted on the base plate 370 while maintaining its gantry shape, and a lifting stage 350 is provided in its central part.

[0039] The optical module 340 can be mounted on the lifting stage 350 and consist of a reflective digital holographic microscope (DHM) that generates holographic information using reflected light to measure the three-dimensional image information of the wafer W. Therefore, the optical module 340 can be lowered by the lifting stage 350 in the direction in which the wafer W is positioned, or raised back to its original position.

[0040] For reference, a reflective digital holographic microscope is configured to allow observation of the reflected image produced by shining light from in front of the hologram. Unlike existing holographic microscopes, it has the advantage of providing a clear three-dimensional effect, making it suitable for checking for abnormalities in wafer W.

[0041] On the other hand, the inspection area in which the optical module 340 can photograph the wafer W and acquire three-dimensional image information is only a portion of the total area formed by the wafer W.

[0042] In other words, the imaging area in which the optical module 340 can acquire three-dimensional holographic information is, for example, 1 / 30 to 1 / 40 of the total area formed by the wafer W.

[0043] Therefore, it is extremely important to continuously move the wafer W placed on the rotating plate 311 using the aforementioned rotating stage 310, first stage 320, and second stage 330. In other words, in order to inspect the entire area of ​​a wafer W with a diameter of 20 to 30 cm, a process is required in which a portion of the wafer W to be inspected is continuously and sequentially aligned with the lens of the optical module 340, and such a process can be performed by the rotating plate 311, first stage 320, and second stage 330.

[0044] Furthermore, preventing the wafer W from moving during the process is extremely important from the perspective of enabling the optical module 340 to acquire three-dimensional holographic information with high accuracy. Therefore, a vibration damping platform 360 is provided at the lower corner of the surface plate 370.

[0045] The vibration damping table 360 ​​plays a role in correcting the position of the surface plate 370 to a predetermined position when shocks or vibrations are generated on the surface plate 370 due to external forces. Specifically, it can correct the tilt of the surface plate 370 in the horizontal direction and correct the height or tilt of the surface plate 370 so that the wafer W maintains a predetermined position from frictional forces or minute vibrations generated during the transfer process of the rotating stage 310, the first stage 320, and the second stage 330.

[0046] As described above, the wafer inspection unit 300 according to the present invention provides a configuration that allows the wafer W to be continuously moved left / right or forward / backward in accordance with the imaging and inspection area of ​​the digital holographic microscope, so that the presence or absence of abnormalities in the wafer can be accurately determined from the three-dimensional image information of the wafer obtained from the holographic image.

[0047] The control unit 400 can receive 3D image information measured by the wafer inspection unit 300. It can then determine whether or not there is an abnormality in the wafer W from the measurement information and communicate whether or not there is an abnormality in the wafer W to the inspector.

[0048] For example, if an abnormality occurs in the wafer W, the control unit 400 can control the wafer transfer unit 200 to separate the abnormal wafer W from the wafer inspection unit 300.

[0049] As another example, if no abnormality occurs in the wafer W, the control unit 400 can control the wafer transfer unit 200 to transfer the wafer W, which has been determined to be good, to the load port 210.

[0050] The control unit 400 described above may be located on one side of the wafer transfer unit 200 and may be configured to include various control buttons and a display so that the inspector can control the drive commands of the wafer transfer unit 200 and the wafer inspection unit 300 and visually confirm the three-dimensional image information of the wafer W.

[0051] Figure 9 is a flowchart showing the process for determining whether via holes formed on a wafer according to one embodiment of the present invention are defective. The process for determining whether via holes formed on a wafer according to one embodiment of the present invention are defective in shape and depth will be described in detail below using Figure 9.

[0052] In step S900, the control unit receives a hologram image input. As described above, the hologram image information is three-dimensional image information of the wafer in which the via holes are formed.

[0053] In step S902, the control unit detects the edges of the via holes. To do this, the control unit uses an edge detection algorithm to extract the edges formed in the via holes. The edge detection algorithms include a first edge detection algorithm that detects edges using mask coefficients, a second edge detection algorithm that detects edges by noise reduction using filters, detection of tilt intensity and direction by applying horizontal / vertical tilt masks, non-maximum suppression by comparing the size of the current pixel and adjacent pixels, and hysteresis criticality processing, or a third edge detection algorithm that detects edges using linear equations and trigonometric functions. In addition, various other methods are used to detect edges formed on the wafer. Figure 10 shows an example of an edge detected using an edge detection algorithm. Figure 10 shows cross-sections of via holes of various sizes and shapes.

[0054] In step S904, the control unit determines whether there is a defect in the shape of the via hole from the detected edge. The control unit compares the edge detected by the edge detection algorithm with a set edge. In relation to the present invention, the control unit compares the radius (or diameter) of the edge detected by the edge detection algorithm with the radius (or diameter) of the set edge. If the radius (or diameter) of the edge detected by the edge detection algorithm falls outside the set edge radius (or diameter), it is determined to be defective. Of course, the set radius is not a specific value but has a range. Figure 11 shows an example of determining whether there is a defect in the shape of a via hole according to one embodiment of the present invention. As shown in Figure 11, if the diameter of the detected via hole falls outside a predetermined range, it is determined to be defective.

[0055] In step S906, the control unit divides the three-dimensional via hole image into multiple regions, calculates the volume of each region, and determines whether the via hole has a defective depth. As an example, the three-dimensional via hole is divided into three regions, and the volume of each region is calculated. The calculated volume of each region is compared with a predetermined volume range to determine whether the via hole has a defective depth. Of course, the control unit can divide the three-dimensional via hole into three or four or more regions and then calculate the volume of each region. Figure 12 shows an example of determining whether the via hole has a defective depth using volume according to one embodiment of the present invention. In relation to the present invention, the volume can be calculated using the diameter of the upper end face, the diameter of the lower end face, and the length between the upper and lower end faces of the divided region. For this purpose, the control unit calculates the diameter of the upper end face, the diameter of the lower end face, and the length between the upper and lower end faces of the divided region. In addition, the control unit can calculate the volume of the divided region in various other ways.

[0056] Thus, the present invention first determines whether there is a defect in the shape of a via hole using the cross-section (edge) of the formed via hole, then secondarily determines whether there is a defect in the depth of the via hole using the volume of the divided via hole, and can improve inspection reliability by increasing the number of divided via holes. To further explain, the present invention does not simply determine whether there is a defect using only the shape of the via hole, but determines whether there is a defect in the depth of the via hole using both the cross-section and the volume.

[0057] Furthermore, although the present invention describes determining the presence or absence of via hole defects in the control unit, it is not limited to this. The presence or absence of via hole defects can be determined using a program installed in a wafer inspection system or a device connected to a wafer inspection system.

[0058] Figure 13 shows a method for inspecting the shape of via holes in a wafer using deep learning according to one embodiment of the present invention. Below, the method for inspecting the shape of via holes in a wafer using deep learning according to one embodiment of the present invention will be described in detail using Figure 13. In step S1300, the system receives 3D data input. In step S1302, the algorithm shown in Figure 9 is used to determine whether or not there is a defect in the shape of the via hole. In step S1304, the 3D data entered in step S1300 and the result of the determination of whether or not there are shape defects in step S1302 are received. In step S1306, the via hole region is extracted from the input 3D data. In step S1308, deep learning is used to repeatedly train the system to determine whether the extracted via hole regions are good or bad, thereby generating training data. Using the training data acquired in step S1310, the system determines whether the via holes extracted from the input 3D data are good or bad, and sends the determination result to the control PC. Thus, the present invention proposes a method for inspecting the shape of a beer hall using beer hall shape data and a deep learning algorithm.

[0059] Figure 14 shows an image of a via hole in a wafer and a 3D reconstruction of that image. It can be seen that the via hole is not accurately represented in the image due to interference phenomena. The beer hall learns in the following way: it classifies the four input images into three categories, and then uses these three categories for learning.

[0060] The four input types are categorized into normal via holes, defective via holes, cut via holes, and patterns other than via holes. Cut via holes and patterns other than via holes are then classified into a single type for learning.

[0061] The parameters used for learning include the Optimize method, Activation function, Dropout, and Train / val data rate. The hyperparameters used are Epoch number (number of iterations), Batch Size (number of data points to create as a single set), and Learning Rate (0-1) (a parameter that determines the amount of change in weighted values ​​due to optimization). The optimal conditions are selected based on the learning rate, batch size, and epoch changes, and the learning accuracy under the selected conditions is calculated.

[0062] The following describes an algorithm for measuring via holes in a multi-layered substrate. When a substrate is made up of multiple layers, the positional accuracy of the via holes formed in each layer and the alignment of the via holes in each layer are of paramount importance.

[0063] By using a high-resolution line scan camera with consideration for measurement accuracy, and by synchronizing the line scan camera with motion, the user can acquire the desired image. The role of illumination in the process of transmitting image data to the camera's light sensor is extremely important. An appropriate type of light source is selected considering the characteristics of the subject to be photographed, the purpose of inspection, and the input equipment. When small via holes are processed in a large area, abundant illumination is required. Also, since the camera is a line scan camera, fiber optics illumination using halogen as the light source is used, and a light line method is used for the light guide.

[0064] Figure 15 shows an image acquired with a line scan camera. By synchronizing the motion and camera, a single substrate is divided into 32 equal sections to acquire images. Among the elements necessary for precise measurement using image processing techniques, high resolution must be fundamental in terms of hardware configuration. However, even with images acquired at the same resolution, if the boundaries of the pattern shape are unclear, measurement errors may occur. There are many methods for extracting boundaries using image processing techniques, but errors exist, and basically, if the boundaries of the image are clear, the accuracy of the measurement can be guaranteed. Therefore, verification of the acquired image must be performed in a step before applying the algorithm. The boundaries of the pattern can be confirmed by the slope of the edges.

[0065] Figure 16 shows the 3D shape representation of the edge slope of the acquired image. As mentioned above, when thousands of holes are machined over a large area, measuring each hole individually is extremely inefficient and leads to increased inspection time.

[0066] This invention processes images based on the morphology of the object in the image. In digital image processing, morphology is applied using m x n structure elements. Differences in the resulting image arise depending on the shape and size of the structure elements.

[0067] Figure 17 shows typical morphological structural elements, and Figure 18 schematically illustrates the process by which morphology is applied based on the values ​​of each structural element.

[0068] These morphological techniques are used to detect regions in an image that consist of bright or dark pixels. These regions are called blobs, and the detected blobs contain various information such as count or area. Based on morphology, edges forming holes are detected and measured, and since the change in intensity (litensity) is greatest near the edges, differential operators are used to detect the edges.

[0069] TIFF2026510386000002.tif72166

[0070] Figure 19a is an image showing the diameter of a via hole and the pitch between patterns measured using an edge detection image processing technique, and Figure 19b is a diagram showing the area of ​​a via hole measured by extracting blobs using a morphological algorithm and calculating the number of pixels within those blobs. After examining the images shown in Figure 19a and Figure 19b, it can be seen that the morphological algorithm proposed in this invention accurately reproduces the via hole. Although specific embodiments of the present invention have been described so far, it goes without saying that various modifications are possible without departing from the scope of the present invention.

[0071] Therefore, the scope of the present invention should not be limited to the embodiments described, but should be defined not only by the claims described below, but also by equivalent claims. [Industrial applicability]

[0072] The present invention relates to a method for inspecting via holes formed on a wafer, and more particularly to an inspection method for inspecting whether or not via holes formed on a wafer have shape defects using deep learning.

[0073] The wafer inspection system according to the present invention provides an automated method for pulling out wafers from a cassette placed on a load port or inserting wafers into the cassette, thereby enabling rapid wafer transfer.

Claims

1. A method for determining whether or not there are shape defects in via holes formed on a wafer, using a program built into a wafer inspection system, The steps include receiving 3D image information of via holes formed on a wafer, The steps include: detecting the edges of via holes using the provided 3D image information and edge detection algorithm; The steps include: checking whether the detected edge is within a predetermined range and determining whether the shape of the via hole is good or bad; The process involves generating defect detection training data by using a deep learning algorithm to learn 3D image information of a beer hall and information on whether or not it has shape defects, and This includes the step of determining whether or not there are shape defects from a 3D image of an input via hole using defective judgment training data. A method for determining whether or not there are defects in the shape of a via hole using deep learning, characterized by the features described above.

2. The input via holes include normal shape via holes, defective shape via holes, cut shape via holes, and patterns other than via holes. The system learns by classifying the four input images into three categories. A method for determining whether or not there is a defect in the shape of a via hole using deep learning, as described in claim 1.

3. The deep learning algorithm is characterized by including parameters consisting of Epoch number, which is the number of iterations for learning; Batch Size, which is the number of data points to create as a single set; and Learning Rate, which is a parameter that determines the amount of change in the weighted value due to optimization. A method for determining whether or not there is a defect in the shape of a via hole using deep learning, as described in claim 2.

4. The wafer inspection system is A wafer transfer unit that loads and unloads wafers to be inspected, A wafer inspection unit receives a wafer from the wafer transfer unit and acquires three-dimensional image information of the wafer using a hologram image. The wafer inspection unit determines whether or not there is an abnormality in the wafer from the three-dimensional image information measured by the wafer inspection unit, and includes a control unit that controls the wafer transfer unit and the wafer inspection unit. A method for determining whether or not there is a defect in the shape of a via hole using deep learning, as described in claim 3.

5. The aforementioned three-dimensional image information is holographic image information. A method for determining whether or not there is a defect in the shape of a via hole using deep learning, as described in claim 1.