Gate-all-around transistor selective oxidation process

Abstract

Semiconductor devices such as gate-all-around (GAA) devices and methods for forming semiconductor devices are described. Selective oxidation processes useful in front-end-of-line (FEOL) and back-end-of-line (BEOL) applications and processes are also described. For example, in a FEOL process, if a dielectric inner spacer is not present, the silicon-germanium (SiGe) layer is protected by selective oxidation while etching the silicon (Si) channel recesses. For example, in a BEOL process, the growth of the silicon-germanium (SiGe) layer on the sidewalls of the superlattice structure is protected by selective oxidation during bottom-up epitaxial growth.

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure relate to the field of electronic devices and methods and apparatuses for manufacturing semiconductor devices. More specifically, embodiments of the present disclosure provide a selective oxidation process for a method of forming gate-all-around (GAA) devices.

Background Art

[0002]

[0002] Integrated circuits have evolved into complex devices that can incorporate millions of transistors, capacitors, and resistors on a single chip. In the process of the evolution of integrated circuits, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the feature size (i.e., the smallest component (or line) that can be created using the manufacturing process) has decreased.

[0003]

[0003] A transistor is a circuit component or circuit element that is often formed on a semiconductor device. Depending on the circuit design, many transistors can be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements. An integrated circuit incorporates a planar field-effect transistor (FET) in which current flows through a semiconductor channel between a source and a drain depending on the voltage applied to a control gate.

[0004]

[0004] In order to achieve improvements in circuit density and high performance, the feature size of transistor devices has been continuously reduced. Therefore, it is necessary to improve the transistor device structure in order to improve electrostatic coupling and reduce adverse effects such as parasitic capacitance and off-state leakage. Examples of transistor device structures include planar structures, FinFET structures, and gate-all-around (GAA) structures.

[0005]

[0005] A GAA transistor includes several lattice-matched nanosheet channels suspended in a stacked configuration and connected by source / drain regions. In a GAA transistor with a dielectric inner spacer, the silicon (Si) channel can be etched with high selectivity relative to the dielectric inner spacer. In such cases, the dielectric inner spacer protects the silicon germanium (SiGe) in the superlattice structure. However, if a dielectric inner spacer is not present, a process is required to protect the silicon germanium (SiGe) recesses within the recesses of the silicon (Si) channel.

[0006]

[0006] Connecting semiconductors to power rails is usually done on the front of the cell, but this requires a considerable cell area. In back-side power rail formation, there is a need for improved methods to protect silicon germanium (SiGe) growth during bottom-up SiGe growth in order to obtain direct bottom contact to the source / drain region without an etching stop layer and to obtain a self-aligned bottom contact structure. [Overview of the project]

[0007]

[0007] One or more embodiments of the present disclosure relate to a method for forming a semiconductor device. In some embodiments, the method comprises selectively oxidizing a superlattice structure formed on the upper surface of a semiconductor substrate to form a plurality of silicon germanium oxide (SiGeO) layers, wherein the superlattice structure comprises a plurality of first layers of a first material and a plurality of corresponding second layers of a second material, arranged alternately to form a plurality of stacked pairs, and the plurality of silicon germanium oxide (SiGeO) layers are formed selectively on the plurality of first layers. The method further comprises laterally etching each of the plurality of second layers to form a plurality of recessed second layers and removing the silicon germanium oxide (SiGeO) layer from each of the plurality of first layers.

[0008]

[0008] Further embodiments of the present disclosure relate to methods for forming gate-all-around (GAA) devices. In some embodiments, the method involves selectively oxidizing a superlattice structure formed on the upper surface of a semiconductor substrate to form a plurality of silicon-germanium oxide (SiGeO) layers, wherein the superlattice structure comprises a plurality of silicon-germanium (SiGe) layers and a corresponding plurality of silicon (Si) layers, arranged alternately to form a plurality of stacked pairs, and the plurality of silicon-germanium oxide (SiGeO) layers are selectively formed on the plurality of silicon-germanium (SiGe) layers. The method further includes laterally etching each of the plurality of silicon (Si) layers to form a plurality of recessed silicon (Si) layers and removing the plurality of silicon-germanium oxide (SiGeO) layers from each of the plurality of silicon-germanium (SiGe) layers.

[0009]

[0009] Further embodiments of the present disclosure include a non-temporary computer-readable medium including instructions, which, when executed by a controller of a processing chamber, cause the processing chamber to selectively oxidize a superlattice structure formed on the upper surface of a semiconductor substrate to form a plurality of silicon germanium oxide (SiGeO) layers, wherein the superlattice structure comprises a plurality of first layers of a first material and a plurality of corresponding second layers of a second material, arranged alternately to form a plurality of stacked pairs, and the plurality of silicon germanium oxide (SiGeO) layers are selectively formed on the plurality of first layers. In some embodiments, the controller causes the processing chamber to laterally etch each of the plurality of second layers to form a plurality of recessed second layers and to remove a silicon germanium oxide (SiGeO) layer from each of the plurality of first layers.

[0010]

[0010] One or more embodiments of the present disclosure relate to a method for forming a semiconductor device. In some embodiments, the method comprises forming a recessed source / drain region in a semiconductor substrate, selectively oxidizing a superlattice structure formed on the upper surface of the semiconductor substrate above the recessed source / drain region to form a plurality of silicon germanium oxide (SiGeO) layers, wherein the superlattice structure comprises a plurality of first layers of a first material and a plurality of corresponding second layers of a second material, arranged alternately to form a plurality of stacked pairs, and the plurality of silicon germanium oxide (SiGeO) layers are selectively formed on the plurality of first layers, forming a plurality of silicon germanium oxide (SiGeO) layers, epitaxially growing a silicon germanium (SiGe) layer from the bottom of the recessed source / drain region to fill a portion of the recessed source / drain region, pre-cleaning the recessed source / drain region to remove the plurality of silicon germanium oxide (SiGeO) layers, and epitaxially growing a source / drain layer on the silicon germanium (SiGe) layer.

[0011]

[0011] Further embodiments of the present disclosure relate to methods for forming gate-all-around (GAA) devices. In some embodiments, the method comprises: creating a recess in a semiconductor substrate to form a recessed source / drain region; selectively oxidizing a superlattice structure formed on the upper surface of the semiconductor substrate above the recessed source / drain region to form a silicon germanium oxide (SiGeO) layer, wherein the superlattice structure includes a plurality of silicon germanium (SiGe) layers and a corresponding plurality of silicon (Si) layers arranged alternately to form a plurality of stacked pairs, and the silicon germanium oxide (SiGeO) layer is selectively formed on the plurality of silicon germanium (SiGe) layers; epitaxially growing a silicon germanium (SiGe) layer from the bottom of the recessed source / drain region to fill a portion of the recessed source / drain region; pre-cleaning the recessed source / drain region to remove the silicon germanium oxide (SiGeO) layer; and epitaxially growing a source / drain layer on the silicon germanium (SiGe) layer.

[0012]

[0012] Further embodiments of the present disclosure relate to a non-temporary computer-readable medium including instructions. The instructions, when executed by a controller of a processing chamber, cause the processing chamber to: recess source / drain regions in a semiconductor substrate to form recessed source / drain regions; and selectively oxidize a superlattice structure formed on the upper surface of the semiconductor substrate above the recessed source / drain regions to form a silicon germanium oxide (SiGeO) layer, wherein the superlattice structure comprises a plurality of first layers of a first material and a plurality of corresponding second layers of a second material, arranged alternately to form a plurality of stacking pairs. The process involves forming silicon germanium oxide (SiGeO) layers selectively on multiple first layers, epitaxially growing silicon germanium (SiGe) layers from the bottom of recessed source / drain regions to fill a portion of the recessed source / drain regions, pre-cleaning the recessed source / drain regions to remove the silicon germanium oxide (SiGeO) layers, and epitaxially growing source / drain layers on the silicon germanium (SiGe) layers.

[0013]

[0013] To enable a more detailed understanding of the above-described features of the Disclosure, a more detailed description of the Disclosure, which has been briefly summarized above, can be obtained by referring to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings only show typical embodiments of the Disclosure and should not be considered to limit the scope of the Disclosure, as the Disclosure may also permit other equally valid embodiments. [Brief explanation of the drawing]

[0014] [Figure 1A]

[0014] This is a process flow diagram of a method for forming a semiconductor device according to one or more embodiments. [Figure 1B]

[0015] This is a process flow diagram of a method for forming a semiconductor device according to one or more embodiments. [Figure 2A]

[0016] It is a cross-sectional view of a semiconductor device according to one or more embodiments. [Figure 2B]

[0017] It is a cross-sectional view of a semiconductor device according to one or more embodiments. [Figure 2C]

[0018] It is a cross-sectional view of a semiconductor device according to one or more embodiments. [Figure 3A]

[0019] It is a cross-sectional view of a semiconductor device according to one or more embodiments. [Figure 3B]

[0020] It is a cross-sectional view of a semiconductor device according to one or more embodiments. [Figure 3C]

[0021] [[ID=​​​​​​​​​​​​​​​​​​​​​​​​​​​​​Before describing some exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the configuration or process step details specified in the following description. Other embodiments of this disclosure are possible and can be implemented or performed in various ways.

[0017]

[0028] As used herein and in the appended claims, the term “substrate” refers to a surface or part of a surface on which a process is performed. Furthermore, unless otherwise clearly indicated in the context, a reference to a substrate may refer only to a part of a substrate. Moreover, when a reference is made to deposition on a substrate, it may mean both a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0018]

[0029] In this specification, “substrate” refers to any substrate on which a film treatment is performed during a manufacturing process, or any material surface formed on such a substrate. For example, substrate surfaces on which treatment may be performed include, depending on the application, materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. Substrates can be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to direct film treatment on the surface of the substrate itself, any of the disclosed film treatment steps may be performed on underlying layers formed on the substrate, as will be disclosed in more detail below. The term “substrate surface” is intended to include underlying layers as indicated in the context. Therefore, for example, if a film / layer or partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0019]

[0030] The term "on" indicates that there is contact between elements, and there may be intervening elements or layers. The term "directly on" indicates that there is direct contact between elements without any intervening elements.

[0020]

[0031] As used herein and in the appended claims, terms such as “precursor,” “reactant,” and “reactive gas” are interchangeable and refer to any gas species that can react with the substrate surface.

[0021]

[0032] Epitaxy is a process in which a deposited film is forced into a highly crystalline alignment with the substrate. In a broad sense, epitaxial growth is defined as the condensation of a gas precursor to form a film on a substrate. Liquid precursors can also be used. Vapor precursors can be obtained by chemical vapor deposition (CVD) or laser ablation. Currently, several epitaxy techniques are available, including molecular beam epitaxy (MBE), epitaxial CVD, or atomic layer epitaxy (ALE).

[0022]

[0033] In the following description, numerous specific details, such as particular materials, chemical properties, and element dimensions, are provided to give a comprehensive understanding of one or more embodiments of the disclosure. However, it will be apparent to those skilled in the art that one or more of these embodiments of the disclosure can be carried out without these specific details. In other examples, semiconductor manufacturing processes, techniques, materials, equipment, etc., are not described in great detail to avoid unnecessarily obscuring the description. Those skilled in the art will be able to implement appropriate functionality using the descriptions contained herein without conducting unnecessary experiments.

[0023]

[0034] While certain exemplary embodiments of this disclosure are described and shown in the accompanying drawings, such embodiments are merely illustrative and not limiting to this disclosure. Those skilled in the art can conceive of variations, so please understand that this disclosure is not limited to the specific configurations and arrangements shown and described.

[0024]

[0035] A transistor is a circuit component or element that is often formed on a semiconductor device. Depending on the circuit design, transistors are formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped substrate regions and exhibit a doping profile suitable for a particular application. The gate is located above the channel region and includes a gate dielectric interposed between the gate electrode of the substrate and the channel region. In one or more embodiments, the gate surrounds all of the nanosheets between the bottom substrate and the channel above.

[0025]

[0036] As used herein, the term “field-effect transistor” or “FET” refers to a transistor that uses an electric field to control the electrical behavior of a device. Enhancement-mode field-effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field within the device, which is generated by the voltage difference between the device body and the gate. The three terminals of an FET are the source (S) where carriers enter the channel, the drain (D) where carriers exit the channel, and the gate (G) which modulates the channel conductivity. Conventionally, the current entering the channel at the source (S) is designated IS, and the current entering the channel at the drain (D) is designated ID. The drain-source voltage is designated VDS. By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., ID) can be controlled.

[0026]

[0037] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate, and the voltage across the insulated gate determines the device's conductivity. This ability to change conductivity in response to the applied voltage is used to amplify or switch electronic signals. A MOSFET is based on the modulation of charge concentration by metal-oxide-semiconductor (MOS) capacitance between the body electrodes and the gate electrode, which is located above the body and insulated from all other device regions by the gate dielectric layer. Compared to MOS capacitors, MOSFETs include two additional terminals (source and drain), each connected to a separate, highly doped region separated by the body region. These regions can be p-type or n-type, but both are the same type, and are the opposite type to the body region. The source and drain are highly doped (unlike the body), and the doping type is indicated by a "+" sign.

[0027]

[0038] If a MOSFET is n-channel or nMOSFET, the source and drain are in the n+ region, and the body is in the p region. If a MOSFET is p-channel or pMOSFET, the source and drain are in the p+ region, and the body is in the n region. The source is so named because it is the source of charge carriers (electrons in the case of n-channels, and holes in the case of p-channels) flowing through the channel. Similarly, the drain is where charge carriers exit the channel.

[0028]

[0039] As used herein, the term “Fin-field-effect transistor (FinFET)” refers to a substrate-built MOSFET transistor in which the gate is located on two or three sides of the channel, forming a double or triple-gate structure. FinFET devices are given the common name FinFET because the channel region forms “fins” on the substrate. FinFET devices have fast switching times and high current density.

[0029]

[0040] As used herein, the term “gate all around (GAA)” is used to refer to an electronic device (e.g., a transistor) in which the gate material surrounds the channel region on all four sides. The channel region of a GAA transistor may include nanowires or nanoslabs, rod-shaped channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device has a plurality of horizontal nanowires or horizontal bars spaced vertically apart, making the GAA transistor a stacked horizontal gate all around (hGAA) transistor.

[0030]

[0041] As used herein, the term "nanowire" refers to a nanometer (10⁻¹⁰) -9 The term "nanowire" refers to a nanostructure having a diameter in units of meters. A nanowire can also be defined as having a length-to-width ratio greater than 1000. Alternatively, a nanowire can be defined as a structure whose thickness or diameter is limited to tens of nanometers or less, and whose length is not limited. Nanowires are used in transistors and certain laser applications, and in one or more embodiments, they are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in logic CPUs, GPUs, MPUs, and transistors for volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term "nanosheet" refers to a two-dimensional nanostructure having a thickness ranging from about 0.1 nm to about 1000 nm.

[0031]

[0042] One or more embodiments of this disclosure relate to a method for forming a gate-all-around (GAA) device. One or more embodiments advantageously provide a method for forming a gate-all-around (GAA) device in which a dielectric inner spacer is absent.

[0032]

[0043] Embodiments of this disclosure advantageously provide selective oxidation processes useful in front-end-of-line (FEOL) and back-end-of-line (BEOL) applications and processes.

[0033]

[0044] Generally, the front-end of line (FEOL) refers to the first part of integrated circuit manufacturing, including transistor manufacturing; the middle of line (MOL) refers to the connection of the transistor and interconnect parts of the chip using a series of contact structures; and the back-end of line (BEOL) refers to the series of process steps from transistor manufacturing to the completion of the wafer.

[0034]

[0045] In GAA transistors with dielectric inner spacers, the silicon (Si) channel can be etched with high selectivity relative to the dielectric inner spacer. In such cases, the dielectric inner spacer protects the silicon germanium (SiGe) superlattice structure. However, if a dielectric inner spacer is not present, a process is needed to protect the silicon germanium (SiGe) recesses within the silicon (Si) channel. For example, in the FEOL process, the silicon germanium (SiGe) layer is protected within the silicon (Si) channel recesses by selective oxidation.

[0035]

[0046] In one or more embodiments, the selective oxidation process described herein has been found to be advantageous in helping to reduce the junction resistance of semiconductor devices.

[0036]

[0047] In the BEOL process, the selective oxidation process described herein favorably protects the growth of silicon germanium (SiGe) layers on the sidewalls of the superlattice structure during bottom-up epitaxial growth, in order to obtain direct bottom contact to the source / drain region without an etching stop layer and to obtain a self-aligned bottom contact structure.

[0037]

[0048] Embodiments of the present disclosure are illustrated by diagrams illustrating one or more embodiments of the present disclosure of a device (e.g., a transistor) and a process for forming a transistor. The processes shown are merely illustrative of possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the applications shown.

[0038]

[0049] One or more embodiments of this disclosure will be described with reference to the drawings. In the methods of one or more embodiments, a transistor (e.g., a gate-all-around (GAA) transistor) is manufactured using a standard process flow.

[0039]

[0050] Figure 1A shows a process flow diagram of Method 10 for forming a semiconductor device 100 according to one or more embodiments of the present disclosure. Method 10 is described below with respect to Figures 2A-2C, which show the stages of manufacturing a semiconductor structure, in particular a gate-all-around (GAA) device, according to several embodiments of the present disclosure. Method 10 of one or more embodiments may be part of a multi-step manufacturing process for a semiconductor device. Thus, Method 10 may be performed in any suitable process chamber coupled to a cluster tool. The cluster tool may include process chambers for manufacturing a semiconductor device, such as a chamber configured for etching, deposition, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber used for manufacturing a semiconductor device.

[0040]

[0051] Figure 1B shows a process flow diagram of Method 50 for forming a semiconductor device 200 according to one or more embodiments of the present disclosure. Method 50 is described below with respect to Figures 3A-3F, which show the stages of manufacturing a semiconductor structure, in particular a gate-all-around (GAA) device, according to several embodiments of the present disclosure. Method 50 of one or more embodiments may be part of a multi-step manufacturing process for a semiconductor device (in particular, during back-side power supply (BPD)). Thus, Method 50 may be performed in any suitable process chamber coupled to a cluster tool. The cluster tool may include process chambers for manufacturing semiconductor devices, such as chambers configured for etching, deposition, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chambers used for manufacturing semiconductor devices.

[0041]

[0052] Referring again to Figures 1A and 2A-2C, Method 10 begins in step 12 by selectively oxidizing the superlattice structure 103 formed on the upper surface 102A of the semiconductor substrate 102 to form a plurality of silicon germanium oxide (SiGeO) layers 108.

[0042]

[0053] In some embodiments, the substrate 102 may be a bulk semiconductor substrate. The term "bulk semiconductor substrate" refers to a substrate in which the entire substrate is composed of semiconductor material. A bulk semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> The semiconductor material may include one or more materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In some embodiments, the semiconductor material may be a doped material such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In some embodiments, the substrate may be doped using any suitable process such as an ion implantation process. In some embodiments, in order to prevent the turn-on of parasitic bottom devices, the substrate may be doped to provide a high dose of dopant at first locations on the surface of the substrate 102. A superlattice structure is formed on top of the first locations. For example, in some embodiments, the surface of the substrate is about 10 18 atoms / cm 3 ~about 10 19 atoms / cm 3 It may have a dopant density of [value].

[0043]

[0054] In some embodiments, the source / drain region 101 is formed within the semiconductor substrate 102. The source / drain region 101 may, but is not limited to, any suitable semiconductor material such as silicon (Si), germanium (Ge), or silicon-germanium (SiGe). In some embodiments, the source / drain region 101 may be formed using any suitable deposition process, such as an epitaxial deposition process. In some embodiments, the source / drain region 101 has a depth ranging from 30 nm to 60 nm.

[0044]

[0055] At least one superlattice structure 103 is formed on the upper surface 102A of the semiconductor substrate 102. The superlattice structure 103 is formed above a source / drain region 101 formed within the semiconductor substrate 102. The superlattice structure 103 includes a plurality of first layers 104 and a plurality of corresponding second layers 106, which are arranged alternately to form a plurality of stacking pairs. In some embodiments, the plurality of stacking groups include silicon (Si) and silicon germanium (SiGe) groups.

[0045]

[0056] In some embodiments, a plurality of first layers 104 comprise a first material, and a corresponding plurality of second layers 106 comprise a second material. In some embodiments, the first material comprises silicon germanium (SiGe), and the second material comprises silicon (Si). In some embodiments, the first material comprises silicon (Si), and the second material comprises silicon germanium (SiGe). In some embodiments, the plurality of first layers 104 and the corresponding plurality of second layers 106 may comprise any number of lattice-matched material pairs suitable for forming a superlattice structure. In some embodiments, the plurality of first layers 104 and the corresponding plurality of second layers 106 comprise 2 to 50 pairs, or 2 to 20 pairs, of lattice-matched materials.

[0046]

[0057] Typically, parasitic devices will reside at the bottom of the superlattice structure 103. In some embodiments, dopant injection into the substrate is used, as described above, to suppress the turn-on of parasitic devices. In some embodiments, the substrate 102 is etched to include a portion of the substrate where the bottom of the superlattice structure 103 is not removed, allowing the substrate portion to act as a bottom release layer for the superlattice structure.

[0047]

[0058] In some embodiments, the thicknesses of the first layer 104 and the second layer 106 are in the range of about 2 nm to about 50 nm, or about 3 nm to about 20 nm. In some embodiments, the average thickness of the first layer 104 is within 0.5 to 2 times the average thickness of the second layer 106.

[0048]

[0059] In some embodiments, a dielectric material (not shown) is deposited on the substrate 102 using a conventional chemical vapor deposition (CVD) method. In some embodiments, the dielectric material is recessed below the upper surface 102A of the substrate 102 such that the bottom of the superlattice structure 103 is formed from the substrate 102.

[0049]

[0060] In some embodiments, a replacement gate structure (e.g., a dummy gate structure 110) is formed on the superlattice structure 103. The dummy gate structure 110 defines the channel region of the transistor device. The dummy gate structure 110 can be formed using any suitable conventional deposition and patterning process known in the art.

[0050]

[0061] In some embodiments, the sidewall spacer 112 is formed along the outer sidewall of the dummy gate structure 110. In some embodiments, the sidewall spacer 112 includes suitable insulating materials known in the art, such as silicon nitride (SiN), silicon oxide (SiOx), silicon oxynitride (SiON), and silicon carbide (SiC). In some embodiments, the sidewall spacer 112 is formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, or low-pressure chemical vapor deposition.

[0051]

[0062] In one or more embodiments, multiple silicon germanium oxide (SiGeO) layers 108 are advantageously selectively formed on multiple first layers 104. In other words, the multiple silicon germanium oxide (SiGeO) layers 108 are not formed on multiple second layers 106. In some embodiments, method 10 includes selectively oxidizing the superlattice structure 103 for any suitable period of time until the multiple silicon germanium oxide (SiGeO) layers 108 are formed to a predetermined thickness in step 12.

[0052]

[0063] In one or more embodiments, any selective oxidation process known to those skilled in the art may be used. In some embodiments, selective oxidation is carried out at a temperature in the range of 300°C to 1000°C, a pressure in the range of 100T to 1000T, and in a process gas containing one or both of water (H2O) and hydrogen (H2).

[0053]

[0064] In some embodiments, method 10 includes selectively oxidizing the superlattice structure 103 for a period of time ranging from 10 seconds to 1000 seconds in step 12. In some embodiments, the selective oxidation is carried out at a temperature above 600°C, or above 700°C, or above 800°C, or above 900°C. In some embodiments, each of the multiple silicon germanium oxide (SiGeO) layers 108 has a thickness ranging from 0.5 nm to 3.0 nm (including all values ​​and sub-ranges in between).

[0054]

[0065] In some embodiments, method 10 includes selectively oxidizing the superlattice structure 103 in step 12 at a temperature in the range of 400°C to 900°C (including all values ​​and subranges in between).

[0055]

[0066] Referring to Figures 1A and 2B, Method 10 includes, in step 14, laterally etching each of the plurality of second layers 106 to form a plurality of recessed second layers 106' having recessed regions 105 adjacent to the recessed second layer 106' and adjacent to the source / drain region 101.

[0056]

[0067] For example, if the superlattice structure 103 is composed of a plurality of second layers 106 containing silicon (Si) and a plurality of first layers 104 containing silicon germanium (SiGe), the plurality of second layers 106 are etched laterally to form a plurality of recessed second layers 106'. The plurality of second layers 106 can be etched laterally using a known etchant that is selective for the plurality of second layers 106, which etches the plurality of second layers 106 at a much faster rate than the plurality of first layers 104. In some embodiments, selective dry etching or wet etching processes may be used. In one or more embodiments, the dry etching process includes exposing the plurality of second layers 106 to reactive ion etching (RIE) with common gases for etching silicon, a remote plasma source, ammonia (NH3), nitrogen trifluoride (NF3), and hydrogen (H2). In some embodiments, multiple second layers 106 may be etched using wet etchants such as aqueous carboxylic acid / nitric acid / HF solutions and aqueous citrate / nitric acid / HF solutions, but are not limited thereto.

[0057]

[0068] In one or more embodiments, each of the plurality of recessed second layers 106' has a recessed region 105 having a recess amount 105a relative to the plurality of second layers 106 before etching. In other words, the recess amount 105a refers to the amount of second material removed from the plurality of second layers 106 to form the plurality of recessed second layers 106'. In some embodiments, each of the plurality of recessed second layers 106' has a recess amount 105a in the range of 1 nm to 4 nm. In some embodiments, the recess amount 105a is 3 nm.

[0058]

[0069] In one or more embodiments, lateral etching of the release layer (second material 106) leaves a void between the semiconductor material layers (first material 104). The void between the semiconductor material layers (first material 104) can be defined by the amount of recess 105a. In some embodiments, if each of the multiple recessed second layers 106' has a recess amount 105a in the range of 1 nm to 4 nm, then the void between the semiconductor material layers (first material 104) is in the range of 1 nm to 4 nm.

[0059]

[0070] Referring to Figures 1A and 2C and Method 10, in step 16, the silicon germanium oxide (SiGeO) layer 108 is removed from each of the plurality of first layers 104. The silicon germanium oxide (SiGeO) layer 108 can be removed by any known etching or patterning process. In some embodiments, selective dry etching or wet etching processes are used to remove the silicon germanium oxide (SiGeO) layer 108.

[0060]

[0071] In some embodiments, removing the silicon germanium oxide (SiGeO) layer 108 from each of the multiple first layers 104 in step 16 does not affect the thickness of the multiple first layers 104. In some embodiments, when the silicon germanium oxide (SiGeO) layer 108 is removed in step 16, less than 1 nm of the multiple first layers 104 is removed.

[0061]

[0072] In one or more embodiments, without intending to be constrained by theory, selectively forming SiGeO108 on a SiGe layer (e.g., a second layer 106) is considered to favorably protect the SiGe layer between lateral recesses of a uniform and controllable Si channel (e.g., a first layer 104).

[0062]

[0073] In one or more embodiments, a back-side contact structure is provided for manufacturing a back-side power supply network (BSPDN) for a gate-all-around (GAA) device. Referring to Figures 1B and 3A-3F, Method 50 begins in step 52 by recessing a source / drain region 201 within a semiconductor substrate 202 to form a recessed source / drain region 201'. In some embodiments, recessing the source / drain region 201 in step 52 increases the depth of the source / drain region 201 to form a recessed source / drain region 201'. Figure 3A shows a source / drain region 201 with a depth D1, and Figure 3B shows a recessed source / drain region 201' with a depth D2 after recessing the source / drain region 201 in step 52. In some embodiments, the depth D1 of the source / drain region 201 is in the range of 30 nm to 60 nm. In some embodiments, the depth D2 of the recessed source / drain region 201' is in the range of 30 nm to 150 nm.

[0063]

[0074] The recessed source / drain region 201' has an upper and a lower section. Depth D2 encompasses the entire lower section of the recessed source / drain region 201'. Depth D2 extends from the lower surface of the recessed source / drain region 201' to the upper surface 202A of the semiconductor substrate 202. The upper section of the recessed source / drain region 201' extends from the upper surface 202A of the semiconductor substrate 202 to the upper surface of the superlattice structure. The upper surface of the superlattice structure is defined by the lower surface of the replacement gate structure (e.g., dummy gate structure 210) and the sidewall spacers 212 formed along the outer sidewalls of the dummy gate structure 210 formed on the superlattice structure. The depth of the upper section of the recessed source / drain region 201' can be defined by the height of the superlattice structure 203. In some embodiments, the superlattice structure 203, which includes a plurality of first layers 204 and a corresponding plurality of second layers 206, may include any number of lattice-matched material pairs suitable for forming the superlattice structure. In some embodiments, the plurality of first layers 204 and the corresponding plurality of second layers 206 include 2 to 50 pairs of lattice-matched material, or 2 to 10 pairs of lattice-matched material. In other words, the depth of the top of the recessed source / drain region 201' can be defined by the total thickness of 2 to 50 pairs, or 2 to 10 pairs of lattice-matched material.

[0064]

[0075] Referring to Figures 1B and 3C, in step 54 of method 50, advantageously, the superlattice structure 203 formed on the upper surface 202A of the semiconductor substrate 202 above the recessed source / drain region 201' is selectively oxidized to form a plurality of silicon germanium oxide (SiGeO) layers 208. In one or more embodiments, the plurality of silicon germanium oxide (SiGeO) layers 208 are selectively formed on a plurality of first layers 204. The selective oxidation process of step 54 is shown in Figures 1A and 2A and may include the same process as step 12 of method 10 described above.

[0065]

[0076] Referring to Figures 1B and 3D, in step 56 of Method 10, a silicon germanium (SiGe) layer 220 is epitaxially grown from the bottom of the recessed source / drain region 201' to fill a portion of the recessed source / drain region 201'. The epitaxial growth process in step 56 may include any suitable epitaxial growth or deposition process known to those skilled in the art, such as those described herein.

[0066]

[0077] In some embodiments, the silicon-germanium (SiGe) layer 220 has any suitable thickness. In some embodiments, the silicon-germanium (SiGe) layer 220 fills a portion of the lower part of the recessed source / drain region 201'. In some embodiments, the silicon-germanium (SiGe) layer 220 fills the entire lower part of the recessed source / drain region 201'. In other words, in some embodiments, the silicon-germanium (SiGe) layer 220 fills a depth D2 extending from the lower surface of the recessed source / drain region 201' to the upper surface 202A of the semiconductor substrate 202. In embodiments where the silicon-germanium (SiGe) layer 220 fills the entire depth D2 extending from the lower surface of the recessed source / drain region 201' to the upper surface 202A of the semiconductor substrate 202, the silicon-germanium (SiGe) layer 220 has a depth in the range of 30 nm to 150 nm.

[0067]

[0078] Referring to Figures 1B and 3E, Method 50 includes pre-cleaning the recessed source / drain region 201' in step 58 to remove multiple silicon germanium oxide (SiGeO) layers 208.

[0068]

[0079] The pre-cleaning process of step 58 may include any suitable etching process known to those skilled in the art. In one or more embodiments, the pre-cleaning process of step 58 may include the same process as step 16 of method 10 described above, as shown in Figures 1A and 2C. In some embodiments, removing the silicon germanium oxide (SiGeO) layer 208 from each of the plurality of first layers 204 does not affect the thickness of the plurality of first layers 204.

[0069]

[0080] Referring to Figures 1B and 3F, Method 50 includes epitaxial growth of a source / drain layer 230 on a silicon germanium (SiGe) layer 230 in step 60. The epitaxial growth process in step 60 may include any suitable deposition process, such as those described herein.

[0070]

[0081] In some embodiments, the source / drain layer 230 has any suitable thickness. In some embodiments, the source / drain layer 230 fills a portion of the upper part of the recessed source / drain region 201'. In some embodiments, the source / drain layer 230 fills the entire upper part of the recessed source / drain region 201'. In other words, in some embodiments, the source / drain layer 230 fills the upper depth of the recessed source / drain region 201', which can be defined by the height of the superlattice structure 203 (total thickness of 2 to 50 pairs, or 2 to 10 pairs of lattice-matched material).

[0071]

[0082] In one or more embodiments, without intending to be constrained by theory, selectively forming a SiGeO layer 208 on a SiGe layer (e.g., a second layer 206) is considered to help protect SiGe growth on the sidewalls of the superlattice structure 203 during bottom-up SiGe growth while fabricating a back-side power supply network (BSPDN).

[0072]

[0083] Some embodiments of this disclosure relate to integrated processes performed within a single cluster tool. Figure 4 is a schematic top view of an exemplary multi-chamber processing system 400 according to one or more embodiments. Figure 4 shows a schematic top view of an example of a multi-chamber processing system 400 according to embodiments of this disclosure. The processing system 400 generally includes a factory interface 402, load lock chambers 404, 406, transfer chambers 408, 410 having respective transfer robots 412, 414, holding chambers 416, 418, and processing chambers 420, 422, 424, 426, 428, 430. As described in detail herein, wafers in the processing system 400 can be processed in various chambers and transferred between various chambers without exposing the wafers to the ambient environment outside the processing system 400 (e.g., the atmospheric environment that may be present in a factory). For example, wafers can be processed in various chambers under low pressure (e.g., approximately 40-80 Torr or less) or vacuum conditions, and can be transferred between these chambers, without disrupting the low-pressure or vacuum environment during the various processes performed on the wafers within the processing system 400. Thus, the processing system 400 can provide an integrated solution for processing a portion of a wafer.

[0073]

[0084] In the example shown in Figure 4, the factory interface 402 includes a docking station 440 and a factory interface robot 442 to facilitate wafer transfer. The docking station 440 is configured to receive one or more forward-opening unified pods (FOUPs) 444. In some examples, each factory interface robot 442 generally includes a blade 448 located at one end of the factory interface robot 442, configured to transfer wafers from the factory interface 402 to load lock chambers 404, 406.

[0074]

[0085] The load lock chambers 404 and 406 each have ports 450 and 452 connected to the factory interface 402, and ports 454 and 456 connected to the transfer chamber 408. The transfer chamber 408 further has ports 458 and 460 connected to the holding chambers 416 and 418, and ports 462 and 464 connected to the processing chambers 420 and 422. Similarly, the transfer chamber 410 has ports 466 and 468 connected to the holding chambers 416 and 418, and ports 470, 472, 474, and 476 connected to the processing chambers 424, 426, 428, and 430. Ports 454, 456, 458, 460, 462, 464, 466, 468, 470, 472, 474, and 476 may be slit valve openings equipped with slit valves to allow wafers to pass through, for example, by transfer robots 412 and 414, and to provide a seal between each chamber to prevent gas from passing between them. Generally, any port is open for wafer transfer; otherwise, the port is closed.

[0075]

[0086] The load lock chambers 404, 406, transfer chambers 408, 410, holding chambers 416, 418, and processing chambers 420, 422, 424, 426, 428, 430 may be fluidly connected to a gas and pressure control system (not shown). The gas and pressure control system may include one or more gas pumps (e.g., turbopumps, cryopumps, roughing pumps), a gas source, various valves, and conduits fluidly connected to the various chambers. During operation, the factory interface robot 442 transfers wafers from the FOUP 444 to the load lock chamber 404 or 406 via port 450 or 452. The gas and pressure control system then pumps down the load lock chamber 404 or 406. The gas and pressure control system further maintains the transfer chambers 408, 410 and the holding chambers 416, 418 in an internal low-pressure or vacuum environment (which may include an inert gas). Therefore, pumping down the load lock chamber 404 or 406 facilitates the passage of the wafer between, for example, the atmospheric environment of the factory interface 402 and the low-pressure or vacuum environment of the transfer chamber 408.

[0076]

[0087] With the wafer in load lock chamber 404 or 406 pumped down, the transfer robot 412 transfers the wafer from load lock chamber 404 or 406 to transfer chamber 408 via port 454 or 456. The transfer robot 412 can then transfer the wafer to either processing chamber 420 or 422 via their respective processing ports 462 or 464, or to holding chambers 416 or 418 via their respective ports 458 or 460 to hold it awaiting further transfer. Similarly, the transfer robot 414 can access the wafer in holding chamber 416 or 418 via port 466 or 468 and transfer the wafer to either processing chamber 424, 426, 428 or 430 via their respective processing ports 470, 472, 474 or 476, or to holding chambers 416 or 418 via their respective ports 466 or 468 to hold it awaiting further transfer. Wafer transfer and holding within and between various chambers can be performed in a low-pressure or vacuum environment provided by a gas and pressure control system.

[0077]

[0088] Processing chambers 420, 422, 424, 426, 428, and 430 can be any suitable chamber for processing wafers. In some embodiments, processing chamber 420 can perform an annealing process, processing chamber 422 can perform a cleaning process, and processing chambers 424, 426, 428, and 430 can perform an epitaxial growth process. In some embodiments, processing chamber 422 can perform a cleaning process, processing chamber 420 can perform an etching process, and processing chambers 424, 426, 428, and 430 can perform their respective epitaxial growth processes.

[0078]

[0089] The system controller 490 is connected to the processing system 400 to control the processing system 400 or its components. For example, the system controller 490 can control the operation of the processing system 400 by using direct control of the chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 426, 428, and 430 of the processing system 400, or by controlling controllers associated with the chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 426, 428, and 430. During operation, the system controller 490 enables data collection and feedback from each chamber to adjust the performance of the processing system 400.

[0079]

[0090] The system controller 490 generally includes a central processing unit (CPU) 492, memory 494, and support circuitry 496. The CPU 492 may be one of any form of general-purpose processor that may be used in an industrial environment. The memory 494, or non-temporary computer-readable medium, is accessible by the CPU 492 and may be one or more of the following types of memory: random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or other forms of local or remote digital storage. The support circuitry 496 is connected to the CPU 492 and may include a cache, clock circuitry, input / output subsystems, power supply, etc. Various methods disclosed herein can generally be implemented by the CPU 492 executing computer instruction code stored, for example, as software routines in memory 494 (or memory of a particular process chamber) under the control of the CPU 492. Once the computer instruction code is executed by the CPU 492, the CPU 492 controls the chamber to execute a process according to various methods.

[0080]

[0091] Other processing systems can be implemented in other configurations. For example, more or fewer processing chambers may be connected to the transfer device. In the illustrated example, the transfer device includes transfer chambers 408, 410 and holding chambers 416, 418. In other embodiments, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as the transfer device within the processing system.

[0081]

[0092] One or more embodiments provide a non-temporary computer-readable medium (e.g., memory 494) containing instructions, which, when executed by a controller (e.g., controller 490) of a processing chamber (or multi-chamber processing system 400), cause the processing chamber to perform the steps of Method 10. Further embodiments provide a non-temporary computer-readable medium (e.g., memory 494) containing instructions, which, when executed by a controller (e.g., controller 490) of a processing chamber (or multi-chamber processing system 400), cause the processing chamber (or multi-chamber processing system 400) to perform the steps of Method 50.

[0082]

[0093] Throughout this specification, any reference to “one embodiment,” “a particular embodiment,” “one or more embodiments,” or “a certain embodiment” means that a particular feature, structure, material, or property described in relation to an embodiment is included in at least one embodiment of this disclosure. Therefore, phrases such as “in one or more embodiments,” “in a particular embodiment,” “in one embodiment,” or “in a certain embodiment” appearing in various places throughout this specification do not necessarily refer to the same embodiment of this disclosure. Furthermore, particular features, structures, materials, or properties may be combined in any suitable manner in one or more embodiments.

[0083]

[0094] While the disclosure herein is described with reference to specific embodiments, those skilled in the art will understand that the described embodiments are merely illustrative of the principles and uses of the disclosure. It will be obvious to those skilled in the art that various modifications and changes can be made to the methods and apparatus of the disclosure without departing from the essence and scope of the disclosure. Accordingly, the disclosure may include modifications and changes within the scope of the appended claims and their equivalents.

Claims

1. A method for forming a semiconductor device, The method involves selectively oxidizing a superlattice structure formed on the upper surface of a semiconductor substrate to form a plurality of silicon germanium oxide (SiGeO) layers, wherein the superlattice structure includes a plurality of first layers of a first material and a plurality of corresponding second layers of a second material, which are alternately arranged to form a plurality of stacked pairs, and the plurality of silicon germanium oxide (SiGeO) layers are formed selectively on the plurality of first layers. Each of the aforementioned plurality of second layers is etched laterally to form a plurality of recessed second layers, Removing the silicon germanium oxide (SiGeO) layer from each of the plurality of first layers and Methods that include...

2. The method according to claim 1, wherein the first material comprises silicon germanium (SiGe) and the second material comprises silicon (Si).

3. The method according to claim 1, wherein the first material comprises silicon (Si) and the second material comprises silicon germanium (SiGe).

4. The method according to claim 1, wherein each of the plurality of recessed second layers has a recess amount in the range of 1 nm to 4 nm.

5. The method according to claim 4, wherein the amount of recess is 3 nm.

6. The method according to claim 1, wherein each of the plurality of silicon germanium oxide (SiGeO) layers has a thickness in the range of 0.5 nm to 3.0 nm.

7. The method according to claim 1, comprising selectively oxidizing the superlattice structure at a temperature in the range of 400°C to 900°C.

8. The method according to claim 1, wherein when the silicon germanium oxide (SiGeO) layer is removed, 1 nm or less of the plurality of first layers is removed.

9. The method according to claim 1, wherein the semiconductor device is a gate-all-around (GAA) device.

10. A method for forming a semiconductor device, This involves creating recesses in the source / drain regions within the semiconductor substrate to form recessed source / drain regions, The method involves selectively oxidizing a superlattice structure formed on the upper surface of the semiconductor substrate above the recessed source / drain region to form a plurality of silicon germanium oxide (SiGeO) layers, wherein the superlattice structure includes a plurality of first layers of a first material and a plurality of corresponding second layers of a second material, arranged alternately to form a plurality of stacked pairs, and the plurality of silicon germanium oxide (SiGeO) layers are formed selectively on the plurality of first layers. A silicon germanium (SiGe) layer is epitaxially grown from the bottom of the recessed source / drain region to fill a portion of the recessed source / drain region. The recessed source / drain region is pre-cleaned to remove the plurality of silicon germanium oxide (SiGeO) layers, The process involves epitaxially growing a source / drain layer on the aforementioned silicon germanium (SiGe) layer. Methods that include...

11. The method according to claim 10, wherein the source / drain region has a depth in the range of 30 nm to 60 nm, and the recessed source / drain region has a depth in the range of 30 nm to 150 nm.

12. The method according to claim 10, wherein the first material comprises silicon germanium (SiGe) and the second material comprises silicon (Si).

13. The method according to claim 10, wherein the first material comprises silicon (Si) and the second material comprises silicon germanium (SiGe).

14. The method according to claim 10, wherein each of the plurality of silicon germanium oxide (SiGeO) layers has a thickness in the range of 0.5 nm to 3.0 nm.

15. The method according to claim 10, comprising selectively oxidizing the superlattice structure at a temperature in the range of 400°C to 900°C.

16. The method according to claim 10, wherein the source / drain layer comprises one or more semiconductors selected from silicon (Si), germanium (Ge), silicon germanium (SiGe), or Group III / V compounds.

17. The method according to claim 10, wherein the semiconductor device is a gate-all-around (GAA) device.

18. A non-temporary computer-readable medium containing instructions, wherein, when the instructions are executed by the controller of the processing chamber, the processing chamber is configured to: This involves creating recesses in the source / drain regions within the semiconductor substrate to form recessed source / drain regions, The method involves selectively oxidizing a superlattice structure formed on the upper surface of the semiconductor substrate above the recessed source / drain region to form a silicon germanium oxide (SiGeO) layer, wherein the superlattice structure includes a plurality of silicon germanium (SiGe) layers and a corresponding plurality of silicon (Si) layers, which are alternately arranged to form a plurality of stacked pairs, and the silicon germanium oxide (SiGeO) layer is formed selectively on the plurality of silicon germanium (SiGe) layers. A silicon germanium (SiGe) layer is epitaxially grown from the bottom of the recessed source / drain region to fill a portion of the recessed source / drain region. The recessed source / drain region is pre-cleaned to remove the silicon germanium oxide (SiGeO) layer, The process involves epitaxially growing a source / drain layer on the aforementioned silicon germanium (SiGe) layer. A non-temporary computer-readable medium that forms semiconductor devices.

19. The non-temporary computer-readable medium according to claim 18, wherein each of the plurality of silicon germanium oxide (SiGeO) layers has a thickness in the range of 0.5 nm to 3.0 nm.

20. The non-transient computer-readable medium according to claim 18, wherein the source / drain layer comprises one or more semiconductors selected from silicon (Si), germanium (Ge), silicon germanium (SiGe), or Group III / V compounds.

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