Integrated dipole region for transistors

Abstract

Methods for manufacturing and processing semiconductor devices (i.e., electronic devices) are described. Embodiments of this disclosure advantageously provide electronic devices that are thin, meet low thermal budget and Vt requirements, and also have improved device performance and reliability. The electronic devices described herein include a source region, a drain region, and a channel separating the source region and the drain region; an interface layer provided on the upper surface of the channel; a high dielectric constant dielectric layer provided on the interface layer; a dipole layer provided on the high dielectric constant dielectric layer; and a capping layer provided on the dipole layer. In some embodiments, the dipole layer comprises a metallic oxynitride (MON), such as aluminum oxynitride (AlON). In some embodiments, the method includes annealing a substrate to introduce atoms from the dipole layer into one or more of the interface layer or the high dielectric constant dielectric layer.

Description

[Technical Field]

[0001]

[0001] Embodiments of the present disclosure relate to the field of electronic device manufacturing, and more particularly to transistors. More specifically, embodiments of the present disclosure relate to FinFET devices and methods for manufacturing FinFET devices. [Background technology]

[0002]

[0002] Integrated circuits have evolved into complex devices that can house millions of transistors, capacitors, and resistors on a single chip. In the course of integrated circuit evolution, the functional density (i.e., the number of interconnected devices per chip area) has increased overall, while the shape dimensions (i.e., the smallest component (or line) that can be manufactured using the manufacturing process) have decreased.

[0003]

[0003] A transistor is a circuit component or circuit element that is often formed on a semiconductor device. Many transistors can be formed on a semiconductor device, in addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements, depending on the circuit design. Integrated circuits incorporate planar field-effect transistors (FETs) through which current flows in a semiconductor channel between the source and drain in response to a voltage applied to the control gate.

[0004]

[0004] As device dimensions shrink, the shape dimensions and materials of the devices make it difficult to maintain switching speed without failure. Several new technologies have emerged that allow chip designers to continuously reduce gate length. Dimensional control of device structures remains a challenging issue in current and future generations of technology.

[0005]

[0005] The miniaturization of materials currently used as negative metal-oxide-semiconductor (N-MOS) transistors and positive metal-oxide-semiconductor (P-MOS) transistors has led to a threshold voltage (V tThis has become a challenge due to changes in fundamental characteristics such as ). In addition, as transistor technology has transitioned from planar FETs to FinFETs and then to GAA devices, multiple threshold voltages (multi-V) have become a problem. t A conformal work function layer is needed for ). t The adjustment range will be limited by variations in film thickness as the device size becomes even smaller.

[0006]

[0006] There are also problems associated with conventional dipole engineering techniques. In order to obtain the desired dipole effect, the desired element is introduced from the deposited film by spike annealing and then removed. Spike annealing can result in a penalty to the equivalent oxide thickness (EOT) and a high thermal budget because free oxygen atoms in the gate dielectric layer and the dipole stack stacked on top of it diffuse downward, oxidizing the silicon layer below.

[0007]

[0007] Furthermore, precisely controlling the amount of dipole species in a metal gate stack, such as a high dielectric constant metal gate stack, is important for achieving the desired V of the transistor. t (or MultiV) t This is extremely important for achieving [the desired result]. Conventional atomic layer deposition (ALD) processes can grow films to a thickness of about 3 Å, but even that can be too thick, resulting in undesirable excess V t This can cause adjustments, EOT penalties, and / or device leaks. Below this thickness, film growth is typically discontinuous (e.g., island growth), and is therefore considered unattainable with ALD processes. As GAA structures become even more refined, the distance between nanosheets will be less than 4 nm, making multi-V at advanced GAA nodes. t To achieve this, further reduction in film thickness may no longer be feasible.

[0008]

[0008] Therefore, thinning, low thermal budget, and V t Requirements (Multi-Vt There is a need for a method of manufacturing an electronic device that satisfies (including) and has a minimum EOT penalty even if there is an EOT penalty. SUMMARY OF THE INVENTION

[0009]

[0009] One or more embodiments are directed to a method of manufacturing an electronic device. In some embodiments, the method includes depositing an interface layer on the upper surface of a channel located between a source and a drain on a semiconductor substrate, depositing a high-k dielectric layer on the interface layer, and depositing a dipole layer on the high-k dielectric layer. In some embodiments, the dipole layer includes metal oxygen nitride (MON). The method further includes depositing a capping layer on the dipole layer.

[0010]

[0010] Additional embodiments are directed to a method of manufacturing an electronic device. In some embodiments, the method includes depositing an interface layer on the upper surface of a channel located between a source and a drain on a semiconductor substrate. The interface layer includes a dielectric material selected from one or more of silicon (Si), silicon oxide (SiOx), doped silicon, doped silicon oxide, or spin-on dielectric. The method further includes depositing a high-k dielectric layer on the interface layer. The high-k dielectric layer includes one or more of hafnium oxide (HfOx), zirconium oxide (ZrOx), or hafnium zirconium oxide (HfZrOx). The method further includes depositing a dipole layer (e.g., aluminum oxynitride (AlON)) on the high-k dielectric layer and depositing a capping layer on the dipole layer. The capping layer includes one or more of amorphous silicon, metal, metal carbide, metal nitride, or metal oxide.

[0011]

[0011] To better understand the features of the Disclosure described above, a more detailed description of the Disclosure, which has been briefly summarized above, can be obtained by referring to the embodiments. Some of these embodiments are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only typical embodiments of the Disclosure and therefore should not be considered limiting in scope, as the Disclosure may allow for other equally valid embodiments. The embodiments described herein are shown in the accompanying drawings for illustrative purposes only, not limitation, and similar elements in the drawings are indicated by similar reference numerals. [Brief explanation of the drawing]

[0012] [Figure 1]

[0012] This is a process flow diagram of a method according to one or more embodiments. [Figure 2]

[0013] The diagram shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 3A]

[0014] The diagram shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 3B]

[0015] The diagram shows a cross-sectional view of a semiconductor substrate according to one or more embodiments. [Figure 4]

[0016] This disclosure shows a cluster tool according to one or more embodiments thereof. [Modes for carrying out the invention]

[0013]

[0017] Before describing some exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the structural or process step details described below. Other embodiments of this disclosure are possible and can be implemented or performed in a variety of ways.

[0014]

[0018] As used herein, the term "about" means approximately or nearly, and in reference to a stated numerical value or range, means a variation of up to ±15% of that numerical value. For example, values that differ by up to ±14%, ±10%, ±5%, ±2%, or ±1% would satisfy the definition of about.

[0015]

[0019] As used herein, the terms "substrate" or "wafer" refer to the surface or a portion of the surface on which processing acts. Also, it will be understood by those skilled in the art that, unless the context clearly indicates otherwise, a reference to a substrate may refer to only a part of the substrate. Further, when reference is made to deposition on a substrate, it may mean both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0016]

[0020] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during a manufacturing process. For example, a substrate surface on which processing can be performed can include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, etc., as well as any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. A substrate can be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to performing film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps may be performed on an underlying layer formed on a substrate, which is more particularly disclosed below, and the term "substrate surface" is intended to include such underlying layers as the context indicates. Thus, for example, when a film / layer or a partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0017]

[0021] As used in this specification and the appended claims, terms such as "precursor", "reactant", "reactive gas", etc. are used interchangeably and refer to any gas species that can react with the surface of the substrate.

[0018]

[0022] The term "on" indicates that there is direct contact between elements. The term "directly on ~" indicates that there is direct contact between elements without any intervening elements.

[0019]

[0023] As used in this specification, "atomic layer deposition" or "periodic deposition" refers to sequentially exposing two or more reactive compounds to deposit a layer of material on the surface of a substrate. The substrate or a part of the substrate is separately exposed to two or more reactive compounds introduced into the reaction zone of the processing chamber. In a time-domain ALD process, the exposure to each reactive compound is separated by a time delay such that each compound can adhere to and / or react on the surface of the substrate and then be purged from the processing chamber. These reactive compounds are said to be sequentially exposed to the substrate. In a spatial ALD process, different parts of the substrate surface, or the material on the substrate surface, are exposed to two or more reactive compounds such that any given point on the substrate is not substantially simultaneously exposed to a plurality of reactive compounds. As used in this specification and the appended claims, the term "substantially" in this context means that, as understood by those skilled in the art, a small portion of the substrate may be potentially simultaneously exposed to a plurality of reactive gases by diffusion and that this simultaneous exposure is not intended.

[0020]

[0024] In one embodiment of a time-domain ALD process, a first time delay is introduced after a first reactive gas (i.e., a first precursor or compound A) is pulsed into the reaction zone. Next, a second delay is introduced after a second precursor or compound B is pulsed into the reaction zone. At each time delay, a purge gas (such as argon) is introduced into the processing chamber to purge the reaction zone or to remove any remaining reactive compounds or reaction byproducts from the reaction zone. Alternatively, the purge gas may flow continuously throughout the entire deposition process so that only the purge gas flows during the time delays between pulsed deliveries of the reactive compounds. The reactive compounds are pulsed alternately until a desired film or thickness is formed on the substrate surface. In either case, one ALD process consists of pulsed delivery of compound A, purge gas, compound B, and purge gas. A cycle can begin with either compound A or compound B, and each sequence of cycles can continue until a film of a predetermined thickness is achieved.

[0021]

[0025] In an embodiment of the spatial ALD process, a first reactive gas and a second reactive gas (e.g., nitrogen gas) are supplied simultaneously to the reaction zone but separated by an inert gas curtain and / or a vacuum curtain. The substrate is moved relative to the gas supply device so that any given point on the substrate is exposed to the first and second reactive gases.

[0022]

[0026] A transistor is a circuit component or element that is often formed on a semiconductor device. Depending on the circuit design, a transistor is formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive wires, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped regions of the substrate (such as a semiconductor substrate) and exhibit a doping profile suitable for the particular application. The gate is located above the channel region and includes a gate dielectric interposed between the gate electrode of the semiconductor substrate and the channel region.

[0023]

[0027] As used herein, the terms “field-effect transistor” or “FET” refer to a transistor that uses an electric field to control the electrical behavior of a device. A field-effect transistor is a voltage-controlled device whose ability to conduct current changes when an electric field is applied. Field-effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field within the device, which is generated by the voltage difference between the body and the gate of the device. The three terminals of an FET are the source (S) where carriers enter the channel, the drain (D) where carriers exit the channel, and the gate (G) which adjusts the conductivity of the channel. In the conventional method, the current entering the channel at the source (S) is I S The following is displayed, and the current entering the channel at the drain (D) is I D This is what is displayed. The drain-source voltage is V DS This is displayed. By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., I D ) can be controlled.

[0024]

[0028] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are a type of field-effect transistor (FET) used in integrated circuits and high-speed switching applications. MOSFETs have an insulated gate, and the voltage of this gate determines the device's ability to conduct current. This ability to change conductivity depending on the magnitude of the applied voltage is used to amplify or switch electronic signals. MOSFETs are based on the modulation of charge concentration by metal-oxide-semiconductor (MOS) capacitance between a body electrode and a gate electrode located above the body and isolated from all other device regions by a gate dielectric layer. Compared to MOS capacitors, MOSFETs include two additional terminals (source and drain), each connected to a separate, highly doped region separated by the body region. These regions can be p-type or n-type, but both are the same type, the opposite type to the body region. The source and drain are highly doped (unlike the body), and the doping type is indicated by a "+" sign.

[0025]

[0029] If the MOSFET is an n-channel type, i.e., an nMOS FET, the source and drain are in the n+ region, and the body is in the p-type substrate region. If the MOSFET is a p-channel type, i.e., a pMOS FET, the source and drain are in the p+ region, and the body is in the n-type substrate region. The source is named as such because it is the source of charge carriers (electrons in the case of n-channels, and holes in the case of p-channels) flowing through the channel. Similarly, the drain is where charge carriers exit the channel.

[0026]

[0030] An nMOS FET consists of an n-type source and drain, and a p-type substrate. When a voltage is applied to the gate, holes in the body (p-type substrate) are pushed away from the gate. This creates an n-type channel between the source and drain, and electrons carry current from the source to the drain through this induced n-type channel. Logic gates and other digital devices implemented using NMOS are said to have NMOS logic. NMOS has three operating modes called cutoff, triode, and saturation. Circuits with NMOS logic gates consume static power when the circuit is idle. This is because a DC current flows through the logic gate when the output is low.

[0027]

[0031] A pMOS FET consists of a p-type source and drain, and an n-type substrate. When a positive voltage is applied between the source and gate (or a negative voltage between the gate and source), a p-type channel with opposite polarity is formed between the source and drain. Current is carried from the source to the drain through the induced p-type channel by holes. When a high voltage is applied to the gate, the PMOS does not conduct, and when a low voltage is applied to the gate, it conducts. Logic gates and other digital devices implemented using PMOS are said to have PMOS logic. PMOS technology is low-cost and has excellent noise immunity.

[0028]

[0032] In NMOS, the carriers are electrons, while in PMOS, the carriers are holes. When a high voltage is applied to the gate, an NMOS will conduct, but a PMOS will not. Furthermore, when a low voltage is applied to the gate, an NMOS will not conduct, while a PMOS will. NMOS is considered faster than PMOS. This is because the electrons, which are the carriers in NMOS, move twice as fast as the holes, which are the carriers in PMOS. However, PMOS devices are more resistant to noise than NMOS devices. In addition, NMOS ICs are smaller than PMOS ICs (given the same functionality). This is because NMOS can provide half the impedance offered by PMOS (with the same shape and operating conditions).

[0029]

[0033] As used herein, the term “fin field-effect transistor (FinFET)” refers to a MOSFET transistor built on a substrate in which the gate is located on two, three, or four sides of the channel, or wrapped around the channel, forming a double-gate structure. FinFET devices are given the general name FinFET because the source / drain regions form “fins” on the substrate. FinFET devices have fast switching times and high current densities.

[0030]

[0034] As used herein, the term “gate all around (GAA)” is used to refer to an electronic device (e.g., a transistor) in which the gate material surrounds the channel region on all four sides. The channel region of a GAA transistor may include nanowires or nanoslabs, nanosheets, rod-shaped channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device has a plurality of horizontal nanowires or horizontal bars spaced vertically apart, making the GAA transistor a stacked horizontal gate all around (hGAA) transistor.

[0031]

[0035] As used herein, the term "nanowire" refers to a nanometer (10⁻¹⁰) -9 The term "nanowire" refers to a nanostructure having a diameter in units of meters. A nanowire can also be defined as having a length-to-width ratio greater than 1000. Alternatively, a nanowire can be defined as a structure whose thickness and diameter are limited to tens of nanometers or less, but whose length is not limited. Nanowires are used in transistors and some laser applications, and in one or more embodiments, they are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in logic CPUs, GPUs, MPUs, and transistors for volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term "nanosheet" refers to a two-dimensional nanostructure having a thickness in the range of about 0.1 nm to about 1000 nm, or 0.5 nm to 500 nm, or 0.5 nm to 100 nm, or 1 nm to 500 nm, or 1 nm to 100 nm, or 1 nm to 50 nm.

[0032]

[0036] Embodiments of the present disclosure are advantageous in that they enable thinning, a low thermal budget, and Vt The present invention provides a method for manufacturing electronic devices that meet requirements and have improved device performance and reliability. One or more embodiments can be advantageously used as effective dipoles for p-FETs, and V t This invention aims to improve materials that do not affect the oxide-to-thickness (EOT) film thickness. Embodiments of the new class of materials can be advantageously used in p-dipoles without increasing the EOT. Embodiments of the present disclosure, through a new integration scheme, can achieve V without incurring an EOT penalty. t This significantly improves the EOT increase while reducing the V to at least 50mV. Embodiments of this disclosure minimize the increase in EOT. t Includes dipole material that provides shift.

[0033]

[0037] The embodiments of this disclosure are advantageous in that they do not result in an increase in EOT compared to metal oxide films and metal nitride films. t This provides methods to improve the situation.

[0034]

[0038] For example, many metal oxide films, such as AlOx, are formed with an EOT penalty. This is because the high dissociation energy of the Al-O bond makes it more difficult to introduce aluminum atoms into the high dielectric layer during the spike annealing process.

[0035]

[0039] Many metal nitride films, such as AlN, have low bond dissociation energies, allowing aluminum atoms to be introduced into the high-dielectric-constant dielectric layer during the spike annealing process, minimizing or eliminating the EOT penalty. However, spike annealing also introduces nitrogen atoms into the high-dielectric-constant dielectric layer, forming a mid-gap material and negating the advantage of forming an effective dipole. Furthermore, excess nitrogen reduces the benefits of the V-flat band and can cause leakage.

[0036]

[0040] Embodiments of the present disclosure advantageously provide a deposition method for controlling the amounts of oxygen and / or nitrogen in a deposited dipole layer.

[0037]

[0041] Embodiments of this disclosure are described by diagrams illustrating devices (e.g., transistors) and processes for forming transistors according to one or more embodiments of this disclosure. The illustrated processes merely illustrate possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the illustrated uses.

[0038]

[0042] Figure 1 shows a flowchart of a method 100 for manufacturing an electronic device according to one or more embodiments of the present disclosure. Method 100 begins in step 102 by depositing an interface layer on the upper surface of a channel located between a source and a drain on a semiconductor substrate. In step 104, a high dielectric constant layer is deposited on the interface layer. In step 106, a dipole layer is deposited on the high dielectric constant layer. In step 108, a capping layer is deposited on the dipole layer. In step 110, method 100 optionally includes annealing the semiconductor substrate. In step 112, method 100 optionally includes performing an etching process to remove one or more of the capping layer or the dipole layer.

[0039]

[0043] In some embodiments, the interface layer is deposited in step 102 using a deposition technique such as ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art (but not limited to these). In one or more embodiments, the interface layer may be formed by etching and the formation of an oxide on the surface.

[0040]

[0044] In some embodiments, a wet chemical technique is performed in step 102 to form an interfacial layer. The wet chemical technique can be any suitable technique known to those skilled in the art. In some embodiments, the wet chemical technique includes a pre-cleaning process. In some embodiments, the pre-cleaning process includes using an SC-1 solution containing one or more of ozone, ammonium hydroxide, or hydrogen peroxide. In some embodiments, the pre-cleaning process includes using an SC-1 solution that does not contain ozone, ammonium hydroxide, or hydrogen peroxide. In some embodiments, after using the SC-1 solution, the pre-cleaning process uses diluted hydrofluoric acid (diluted HF). This diluted HF includes a dilution greater than 100:1, for example, 130:1, which removes native oxides on the substrate by etching and forms a hydrophobic surface (i.e., an interfacial layer).

[0041]

[0045] In some embodiments, a high dielectric layer is deposited in step 104 using a deposition technique such as ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art. In some embodiments, the high dielectric layer is conformally deposited by ALD in step 104.

[0042]

[0046] In some embodiments, in step 106, the dipole layer is deposited on a high dielectric layer using a deposition technique such as (but not limited to) ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art.

[0043]

[0047] Embodiments of the present disclosure advantageously provide a deposition method for controlling the amount of oxygen and / or nitrogen in a deposited dipole layer. The deposited dipole layer advantageously has a nitrogen content of 5% or less, 2% or less, or 1% or less on an atomic basis.

[0044]

[0048] The dipole layer can be deposited as a single layer or as a multilayer. The dipole layer can be deposited to a predetermined thickness.

[0045]

[0049] In some embodiments, depositing a dipole layer involves exposing a semiconductor substrate to a cycle comprising pulses of a metal-containing precursor, a nitrogen-containing reactant, and an oxygen-containing reactant. In some embodiments, the semiconductor substrate is purged after each pulse. In specific embodiments, the nitrogen content in the deposited dipole layer can be adjusted to a desired content. In specific embodiments, after each cycle, the metal and oxygen content increases and the nitrogen content decreases. This cycle may be repeated until the dipole layer is deposited to a predetermined thickness.

[0046]

[0050] In some embodiments, depositing a dipole layer involves exposing a semiconductor substrate to a cycle comprising pulses of a metal-containing precursor, an oxygen-containing reactant, and a nitrogen-containing reactant. In some embodiments, the semiconductor substrate is purged after each pulse. In specific embodiments, the oxygen content in the deposited dipole layer can be adjusted to a desired content. In specific embodiments, after each cycle, the metal and oxygen content increases, and the nitrogen content decreases. This cycle may be repeated until the dipole layer is deposited to a predetermined thickness.

[0047]

[0051] In some embodiments, depositing the dipole layer involves exposing the semiconductor substrate to a co-flow of a metal-containing precursor and a nitrogen-containing reactant, pulses of the metal-containing precursor, and pulses of the oxygen-containing reactant. In some embodiments, the semiconductor substrate is purged after each pulse. In specific embodiments, the nitrogen content in the deposited dipole layer can be adjusted to a desired content. In specific embodiments, after each deposition cycle, the metal and oxygen content increases and the nitrogen content decreases. This cycle may be repeated until the dipole layer is deposited to a predetermined thickness.

[0048]

[0052] In some embodiments, the metal-containing precursor comprises one or more of titanium (Ti), tantalum (Ta), aluminum (Al), niobium (Nb), antimony (Sb), tellurium (Te), lanthanum (La), yttrium (Y), strontium (Sr), and scandium (Sc). In some embodiments, the metal-containing precursor is an aluminum-containing precursor. The aluminum-containing precursor can be any suitable aluminum precursor. In some embodiments, the aluminum-containing precursor comprises trimethylaluminum (TMA) or aluminum chloride (AlCl3).

[0049]

[0053] In some embodiments, the oxygen-containing reactant includes one or more of oxygen (O2), ozone (O3), or water (H2O). In some embodiments, the oxygen-containing reactant includes water (H2O).

[0050]

[0054] In some embodiments, the nitrogen-containing reactant is nitrogen (N2), ammonia (NH3), hydrazine (N2H4), or nitrogen radical (N2H4). * ) and hydrogen radicals (H * The reaction includes one or more of the following: ) and co-flow. In some embodiments, the nitrogen-containing reactant comprises a substituted or unsubstituted alkylhydrazine. In some embodiments, the alkylhydrazine comprises a structure with 1 to 6 carbon atoms. In one or more embodiments, the alkylhydrazine is t-butylhydrazine. In some embodiments, the nitrogen-containing reactant comprises plasma. In some embodiments, the nitrogen-containing reactant comprises ammonia (NH3).

[0051]

[0055] In some embodiments, the deposited dipole layer contains one or more of the following: titanium oxynitride (TiON), tantalum oxynitride (TaON), aluminum oxynitride (AlON), niobium oxynitride (NbON), antimony oxynitride (SbON), tellurium oxynitride (TeON), lanthanum oxynitride (LaON), yttrium oxynitride (YON), antimony oxynitride (SbON), strontium oxynitride (SrON), and scandium oxynitride (ScON). In some embodiments, the dipole layer contains aluminum oxynitride (AlON).

[0052]

[0056] In some embodiments, the metal-containing precursor comprises trimethylaluminum (TMA), the oxygen-containing reactant comprises water (H2O), and the nitrogen-containing reactant comprises ammonia (NH3).

[0053]

[0057] In some embodiments, the metal-containing precursor includes aluminum chloride (AlCl3), the oxygen-containing reactant includes water (H2O), and the nitrogen-containing reactant includes ammonia (NH3). In embodiments in which the metal-containing precursor includes aluminum chloride (AlCl3), the chlorine (Cl) content of the deposited dipole layer is 2% or less or 1% or less on an atomic basis.

[0054]

[0058] In some embodiments, a dipole layer with a nitrogen content of 1% or less on an atomic basis is formed by exposing a semiconductor substrate to pulses of a metal-containing precursor (e.g., trimethylaluminum (TMA)), an oxygen-containing reactant (e.g., water (H2O)), and a nitrogen-containing reactant (e.g., ammonia (NH3)). In one or more embodiments, the dipole layer has an aluminum (Al) content of about 31.65%, an oxygen (O2) content of about 64.19%, and a nitrogen (N) content of about 0.16% on an atomic basis.

[0055]

[0059] In some embodiments, a dipole layer with an atomic nitrogen content (ammonia (NH3)) of 1% or less is formed by exposing a semiconductor substrate to pulses of a metal-containing precursor (e.g., trimethylaluminum (TMA)), an oxygen-containing reactant (e.g., water (H2O)), and a nitrogen-containing reactant (e.g., ammonia (NH3)). In one or more embodiments, the dipole layer has an atomic aluminum (Al) content of about 27.45%, an oxygen (O2) content of about 65.80%, and a nitrogen (N) content of about 0.42%.

[0056]

[0060] In some embodiments, a dipole layer with a nitrogen content of 1% or less is formed by exposing a semiconductor substrate to co-flow of a metal-containing precursor (e.g., trimethylaluminum (TMA)) and a nitrogen-containing reactant (e.g., ammonia (NH3)), pulses of the metal-containing precursor (e.g., trimethylaluminum (TMA)), and pulses of the oxygen-containing reactant (e.g., water (H2O)). In one or more embodiments, the dipole layer has an aluminum (Al) content of about 27.15%, an oxygen (O2) content of about 66.7%, and a nitrogen (N) content of about 0.20% on an atomic basis.

[0057]

[0061] In step 106, the dipole layer is deposited on the high-dielectric-constant dielectric layer. The dipole layer can be deposited on the high-dielectric-constant dielectric layer at any suitable temperature and any suitable pressure. In some embodiments, in step 106, the dipole layer is deposited on the high-dielectric-constant dielectric layer at a temperature of 500°C or less and a pressure of 50 Torr or less. In some embodiments, the temperature is in the range of 100°C to 500°C, or 150°C to 450°C, 200°C to 400°C, or 250°C to 350°C. In some embodiments, the pressure is in the range of 0 mTorr to 50 Torr, or 100 mTorr to 50 Torr, or 1 Torr to 40 Torr, 10 Torr to about 35 Torr, or 20 Torr to 30 Torr. While there is no intention to be bound by theory, for example, if a dipole layer is deposited on a high-dielectric-constant dielectric layer at a temperature of 450°C or 500°C, it is thought that atoms from the dipole layer will be introduced into the high-dielectric-constant dielectric layer.

[0058]

[0062] In some embodiments, in step 108, the capping layer is deposited on the dipole layer using a deposition technique such as (but not limited to) ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art.

[0059]

[0063] In some embodiments, step 110 of method 100 optionally includes annealing the semiconductor substrate at a temperature of 1100°C or less to introduce atoms from the dipole layer into the high dielectric layer. In some embodiments, step 110 of method 100 includes annealing the semiconductor substrate at a temperature of 1050°C or less to introduce atoms from the dipole layer into the high dielectric layer. In some embodiments, the temperature is in the range of 500°C to 1100°C (including the range of 500°C to 1050°C, 600°C to 1025°C, 700°C to 1000°C, 750°C to 950°C, or 800°C to 900°C).

[0060]

[0064] While not intended to be theoretical, it is believed that annealing the semiconductor substrate according to step 110 increases the number of atoms introduced from the dipole layer into one or more interface layers or high dielectric layers compared to a method in which annealing is not performed. In one or more embodiments, annealing the semiconductor substrate in step 110 includes a rapid thermal process (RTP). The RTP can be any suitable process known to those skilled in the art. While not intended to be theoretical, it is believed that RTP contributes to densification and improved physical properties of the deposited dipole layer.

[0061]

[0065] While not intended to be constrained by theory, a dipole region containing a channel with n-type or p-type material and the aforementioned dipole layer is thought to simplify existing annealing flows and reduce annealing costs. Furthermore, it is thought that when atoms in the dipole layer (such as metal atoms) are embedded in the interface layer and / or a high-dielectric-constant dielectric layer, a dipole region is formed, and oxidation can be suppressed. As a result, the required annealing temperature may be reduced.

[0062]

[0066] In some embodiments, in step 112, method 100 optionally includes performing an etching process to remove one or more of the capping layer or dipole layer. The etching process may be any suitable etching process known to those skilled in the art. In some embodiments, the etching process includes a wet etching process or a dry etching process. In some embodiments, the etching process includes a wet etching process. In some embodiments, the wet etching process includes a pre-cleaning process. In some embodiments, the pre-cleaning process includes using one or more of ammonium hydroxide (NH4OH) or water (H2O). In some embodiments, water (H2O) is deionized water (DI). In some embodiments, the pre-cleaning process includes using a ratio of DI:NH4OH in the range of 100:1 to 5:1.

[0063]

[0067] While not intended to be theoretical, in step 110, method 100 includes annealing the semiconductor substrate at a temperature of 1050°C or less to introduce atoms from the dipole layer into a high-dielectric-constant dielectric layer containing the properties of the dipole layer. In other words, after performing an etching process in step 112 to remove the capping layer and / or dipole layer, the high-dielectric-constant dielectric layer has dipole properties, which is a result of the annealing process performed in step 110.

[0064]

[0068] Embodiments of the present disclosure advantageously provide a deposition method for controlling the amount of oxygen and / or nitrogen in a deposited dipole layer and a high dielectric constant dielectric layer having dipole properties as a result of the annealing process in step 110.

[0065]

[0069] In one or more embodiments, the capping layer and dipole layer are removed, and a gate comprising one or more gate metals (not shown) or gate contacts (not shown) may optionally be formed or deposited on the exposed surface of a high dielectric layer. In one or more embodiments, the gate metal may be any suitable material known to those skilled in the art. In one or more embodiments, the gate metal comprises one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), ruthenium (Ru), iridium (Ir), aluminum (Al), or platinum (Pt). In one or more specific embodiments, the gate metal comprises a metal selected from one or more of nitrogen (N), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), iridium (Ir), aluminum (Al), or platinum (Pt). In other specific embodiments, the gate metal comprises a metal or metal alloy selected from one or more of nitrogen (N), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), or zirconium (Zr). In embodiments where the gate metal is formed on a high dielectric layer, the gate metal is deposited as a gate metal layer (not shown). The gate metal layer may be deposited using deposition techniques such as ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art (but not limited to these). The gate metal layer may have any suitable thickness. In some embodiments, the gate metal layer has a thickness ranging from 1 nm to 3 nm. In embodiments where the gate metal is formed on a high dielectric layer, the gate metal layer has a capping layer on it. The capping layer on the gate metal layer may have any suitable thickness.In some embodiments, the capping layer on the gate metal layer has a thickness in the range of 0.5 nm to 2 nm (including the ranges of 0.6 nm to 1.9 nm, 0.7 nm to 1.8 nm, 0.8 nm to 1.7 nm, 0.9 nm to 1.6 nm, 1 nm to 1.5 nm, 1.1 nm to 1.4 nm, or 1.2 nm to 1.3 nm).

[0066]

[0070] In one or more embodiments, the gate contact may be any suitable material known to those skilled in the art. In one or more embodiments, the gate contact may include an element or alloy selected from one or more of the following: nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), iridium (Ir), tantalum (Ta), aluminum (Al), or platinum (Pt).

[0067]

[0071] Figures 2, 3A, and 3B are cross-sectional views of an electronic device (e.g., a transistor) 200 according to one or more embodiments. The electronic devices 200 shown in Figures 2, 3A, and 3B may be manufactured by the method 100 shown in Figure 1.

[0068]

[0072] In one or more embodiments, the electronic device 200 comprises a semiconductor substrate 202 having an upper surface 203. In one or more embodiments, the semiconductor substrate 202 can be any suitable substrate material. In one or more embodiments, the semiconductor substrate 202 comprises a semiconductor material (e.g., silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphide (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), germanium (Ge), silicon germanium (SiGe), copper indium gallium selenide (CIGS), other semiconductor materials, or any combination thereof). In one or more embodiments, the semiconductor substrate 202 comprises one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), indium (In), phosphorus (P), copper (Cu), or selenium (Se). While some examples of materials that can form a semiconductor substrate 202 are described herein, any material that can serve as a foundation upon which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) can be constructed is included in the spirit and scope of this disclosure.

[0069]

[0073] In one or more embodiments, the semiconductor substrate 202 is a p-type or n-type substrate. As used herein, the term “n-type” refers to a semiconductor produced by doping an intrinsic semiconductor with electron-donating elements during manufacturing. The term “n-type” derives from the negative charge of electrons. In an n-type semiconductor, electrons are the majority carriers and holes are the minority carriers. As used herein, the term “p-type” refers to the positive charge (or hole) in the wells. In contrast to an n-type semiconductor, a p-type semiconductor has a hole concentration greater than the electron concentration. In a p-type semiconductor, holes are the majority carriers and electrons are the minority carriers.

[0070]

[0074] In some embodiments, the source region 204a is located on the upper surface 203 of the semiconductor substrate 202. In one or more embodiments, the source region 204a has a source and a source contact (not shown). On the upper surface 203 of the semiconductor substrate 202, opposite to the source region 204a, is a drain region 204b. In one or more embodiments, the drain region 204b has a drain and a drain contact (not shown).

[0071]

[0075] In one or more embodiments, the source region 204a and / or the drain region 204b can be any suitable material known to those skilled in the art. In one or more embodiments, the source region 204a and / or the drain region 204b may have two or more layers. For example, the source region 204a and / or the drain region 204b independently comprise three layers. In one or more embodiments, the source region 204a and the drain region 204b independently comprise one or more of the following: copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), platinum (Pt), phosphorus (P), germanium (Ge), silicon (Si), aluminum (Al), or zirconium (Zr). In some embodiments, the source region 204a and the drain region 204b may independently include a silicon bottom layer having a doped epitaxial material (epi) (e.g., SiGe, SiP, etc.), a second silicide layer which may include nickel (Ni), titanium (Ti), aluminum (Al), etc., and a third layer, i.e., an uppermost layer which may be (but not limited to) a metal such as cobalt, tungsten, or ruthenium.

[0072]

[0076] In some embodiments, the source region 204a and drain region 204b may be raised source / drain regions formed by epitaxial growth. In one or more embodiments, the source contact and / or drain contact may be independently selected from one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt). In one or more embodiments, the formation of the source contact and / or drain contact may be carried out by any suitable process known to those skilled in the art, including but not limited to ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art.

[0073]

[0077] In one or more embodiments, channel 206 is located between source 204a and drain 204b. In one or more embodiments, dipole region 208 covers channel 206 and is in contact with one or more of channel 206, source region 204a, and drain region 204b. In one or more embodiments, dipole region 208 has a thickness ranging from 2 nm to 6 nm (including the ranges of 2.5 nm to 5.5 nm, 3 nm to 5 nm, or 3.5 nm to 4.5 nm).

[0074]

[0078] In one or more embodiments, the dipole region 208 includes one or more of the interface layer 210, the high dielectric constant layer 212, the dipole layer 214, and the capping layer 216. In some embodiments, the dipole region 208 includes the interface layer 210, the high dielectric constant layer 212, the dipole layer 214, and the capping layer 216. In some embodiments, the dipole region 208 includes the interface layer 210, the high dielectric constant layer 212, and the dipole layer 214.

[0075]

[0079] In one or more embodiments, the interface layer 210 is deposited on the upper surface 205 of the channel 206. In some embodiments, the interface layer 210 is deposited on the upper surface 205 of the channel 206 according to step 102 of method 100. In some embodiments, the interface layer 210 comprises a dielectric material selected from one or more of silicon (Si), silicon oxide (SiOx), doped silicon, doped silicon oxide, or spin-on dielectrics.

[0076]

[0080] The interface layer 210 may have any suitable thickness. In some embodiments, the interface layer 210 has a thickness in the range of 0.2 nm to 0.8 nm (including the range of 0.3 nm to 0.7 nm or the range of 0.4 nm to 0.6 nm).

[0077]

[0081] In one or more embodiments, a high dielectric constant dielectric layer 212 is deposited on the upper surface 211 of the interface layer 210. In some embodiments, the high dielectric constant dielectric layer 212 is deposited on the upper surface 211 of the interface layer 210 according to step 104 of method 100. The high dielectric constant dielectric layer 212 can be any suitable high dielectric constant dielectric material known to those skilled in the art. In one or more embodiments, the high dielectric constant dielectric layer 212 includes one or more of hafnium oxide (HfOx), zirconium oxide (ZrOx), hafnium-zirconium oxide (HfZrOx), or spin-on dielectrics.

[0078]

[0082] The high dielectric layer 212 can have any suitable thickness. In some embodiments, the high dielectric layer 212 has a thickness in the range of 1 nm to 2 nm (including the range of 1.1 nm to 1.9 nm, 1.2 nm to 1.8 nm, 1.3 nm to 1.7 nm, or 1.4 nm to 1.6 nm).

[0079]

[0083] In one or more embodiments, a dipole layer 214 is deposited on the upper surface 213 of the high dielectric constant dielectric layer 212. In some embodiments, the dipole layer 214 is deposited on the upper surface 213 of the high dielectric constant dielectric layer 212 according to one of the processes described with respect to step 106 of Method 100. The dipole layer 214 may have any suitable thickness. In some embodiments, the dipole layer 214 has a thickness in the range of 0.3 nm to 1.5 nm (including the range of 0.4 nm to 1.4 nm, 0.5 nm to 1.3 nm, 0.6 nm to 1.2 nm, 0.7 nm to 1.1 nm, or 0.8 nm to 1.0 nm).

[0080]

[0084] In some embodiments, the dipole layer 214 comprises one or more of the following: titanium oxynitride (TiON), tantalum oxynitride (TaON), aluminum oxynitride (AlON), niobium oxynitride (NbON), antimony oxynitride (SbON), tellurium oxynitride (TeON), lanthanum oxynitride (LaON), yttrium oxynitride (YON), antimony oxynitride (SbON), strontium oxynitride (SrON), and scandium oxynitride (ScON). In some embodiments, the dipole layer 214 comprises aluminum oxynitride (AlON). In some embodiments, the deposited dipole layer 214 advantageously has a nitrogen content of 5% or less, 2% or less, or 1% or less on an atomic basis.

[0081]

[0085] In one or more embodiments, a capping layer 216 is deposited after the deposition of the dipole layer 214 to control oxidation of the film. In one or more embodiments, the capping layer 216 is deposited on the upper surface 215 of the dipole layer 214 according to step 108 of method 100. In one or more embodiments, the electronic device 200 does not include the capping layer 216.

[0082]

[0086] In one or more embodiments in which the electronic device 200 includes a capping layer 216, the capping layer 216 is an in-situ capping layer. In some embodiments, the capping layer 216 includes one or more amorphous silicon, metals, metal carbides, metal nitrides, or metal oxides. In some embodiments, the capping layer 216 includes aluminum oxide (AlOx). The capping layer 216 may have any suitable thickness. In some embodiments, the capping layer has a thickness in the range of 0.5 nm to 2 nm (including the ranges of 0.6 nm to 1.9 nm, 0.7 nm to 1.8 nm, 0.8 nm to 1.7 nm, 0.9 nm to 1.6 nm, 1 nm to 1.5 nm, 1.1 nm to 1.4 nm, or 1.2 nm to 1.3 nm).

[0083]

[0087] In one or more embodiments, the electronic device 200 includes hafnium oxide (HfOx) as a high dielectric constant dielectric layer 212, aluminum oxynitride (AlON) as a dipole layer 214, and aluminum oxide (AlOx) as a capping layer 216.

[0084]

[0088] Referring to Figure 3A, in one or more embodiments, the capping layer 216 on the PFET side 250 is removed by patterning (optional step 112). Referring to Figure 3B, in one or more embodiments, the dipole layer 214 and the capping layer 216 on the PFET side 250 are removed by patterning (optional step 112).

[0085]

[0089] In one or more embodiments, after removing the capping layer and dipole layer, a gate comprising, optionally, one or more gate metals (not shown) or gate contacts (not shown) may be formed or deposited on the exposed surface of the high dielectric layer. The gate metal may be any material known to those skilled in the art. In one or more embodiments, the gate metal comprises one or more of nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), ruthenium (Ru), iridium (Ir), aluminum (Al), or platinum (Pt). In one or more specific embodiments, the gate metal comprises a metal selected from one or more of nitrogen (N), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), iridium (Ir), aluminum (Al), or platinum (Pt). In other specific embodiments, the gate metal 226 includes a metal or metallic alloy selected from one or more of nitrogen (N), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), or zirconium (Zr).

[0086]

[0090] In embodiments where the gate metal is formed on a high dielectric layer 212, the gate metal is deposited as a gate metal layer (not shown). The gate metal layer may be deposited using deposition techniques such as ALD, CVD, PVD, MBE, MOCVD, spin-on, or other insulating layer deposition techniques known to those skilled in the art (but not limited to these). The gate metal layer may have any suitable thickness. In some embodiments, the gate metal layer has a thickness ranging from 1 nm to 3 nm. In embodiments where the gate metal is formed on a high dielectric layer 212, the gate metal layer has a capping layer thereon. The capping layer formed on the gate metal layer may have the same or similar properties as the illustrated capping layer 216. The capping layer on the gate metal layer (e.g., capping layer 216) may have any suitable thickness. In some embodiments, the capping layer on the gate metal layer (e.g., capping layer 216) has a thickness in the range of 0.5 nm to 2 nm (including the ranges of 0.6 nm to 1.9 nm, 0.7 nm to 1.8 nm, 0.8 nm to 1.7 nm, 0.9 nm to 1.6 nm, 1 nm to 1.5 nm, 1.1 nm to 1.4 nm, or 1.2 nm to 1.3 nm).

[0087]

[0091] In one or more embodiments, the gate contact may be any suitable material known to those skilled in the art. In one or more embodiments, the gate contact may include an element or alloy selected from one or more of the following: nitrogen (N), copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), iridium (Ir), tantalum (Ta), aluminum (Al), or platinum (Pt).

[0088]

[0092] Further embodiments of this disclosure, as shown in Figure 4, relate to a processing tool 900 for forming the described electronic devices and methods.

[0089]

[0093] The cluster tool 900 includes at least one central transfer station 921, 931 having multiple sides. Robots 925, 935 are positioned within the central transfer stations 921, 931 and are configured to move robot blades and wafers to each of the multiple sides.

[0090]

[0094] The cluster tool 900 comprises several processing chambers 902, 904, 906, 908, 910, 912, 914, 916, and 918, also called process stations, connected to a central transfer station. The various processing chambers provide separate processing areas isolated from adjacent processing stations. The processing chambers include, but are not limited to, any suitable chambers including, pre-cleaning chambers, buffer chambers, one or more transfer spaces, wafer orientation / degassing chambers, cryogenic cooling chambers, deposition chambers, annealing chambers, etching chambers, heat treatment (RTP) chambers, plasma oxidation chambers, plasma nitriding chambers, and atomic layer deposition (ALD) chambers. Specific arrangements of process chambers and components may vary depending on the cluster tool and should not be considered limiting to the scope of this disclosure.

[0091]

[0095] In the embodiment shown in Figure 4, the factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on the front 951 of the factory interface 950. The loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, but those skilled in the art will understand that this is merely a typical example of one possible configuration.

[0092]

[0096] The size and shape of the loading chamber 954 and unloading chamber 956 may vary, for example, depending on the substrates being processed within the cluster tool 900. In the shown embodiment, the loading chamber 954 and unloading chamber 956 are sized to hold a wafer cassette in which multiple wafers are arranged within the cassette.

[0093]

[0097] Robot 952 is located within the factory interface 950 and can move between the loading chamber 954 and the unloading chamber 956. Robot 952 can transfer wafers from a cassette in the loading chamber 954 to the load lock chamber 960 through the factory interface 950. Robot 952 can also transfer wafers from the load lock chamber 962 to a cassette in the unloading chamber 956 through the factory interface 950. As will be understood by those skilled in the art, the factory interface 950 may have multiple robots 952. For example, the factory interface 950 may have a first robot that transfers wafers between the loading chamber 954 and the load lock chamber 960, and a second robot that transfers wafers between the load lock 962 and the unloading chamber 956.

[0094]

[0098] The illustrated cluster tool 900 has a first section 920 and a second section 930. The first section 920 is connected to the factory interface 950 through load lock chambers 960, 962. The first section 920 includes a first transfer chamber 921 in which at least one robot 925 is located. The robot 925 is also called a robotic wafer transfer mechanism. The first transfer chamber 921 is centrally located relative to the load lock chambers 960, 962, process chambers 902, 904, 916, 918, and buffer chambers 922, 924. In some embodiments, the robot 925 is a multi-arm robot capable of independently moving multiple wafers at once. In one or more embodiments, the first transfer chamber 921 comprises multiple robotic wafer transfer mechanisms. The robot 925 within the first transfer chamber 921 is configured to move wafers between chambers around the first transfer chamber 921. Each wafer is transported on a wafer transport blade located at the distal end of the first robotic mechanism.

[0095]

[0099] After processing the wafer in the first section 920, the wafer can pass through a pass-through chamber to the second section 930. For example, chambers 922, 924 may be unidirectional or bidirectional pass-through chambers. Pass-through chambers 922, 924 can be used, for example, to cool the wafer to a low temperature before processing in the second section 930, or to allow cooling or post-processing of the wafer before returning it to the first section 920.

[0096]

[0100] The system controller 990 communicates with the first robot 925, the second robot 935, the first set of processing chambers 902, 904, 916, 918, and the second set of processing chambers 906, 908, 910, 912, 914. The system controller 990 can be any suitable component capable of controlling the processing chambers and robots. For example, the system controller 990 may be a computer including a central processing unit, memory, appropriate circuitry, and storage.

[0097]

[0101] The process is generally stored as a software routine in the memory of the system controller 990 and, when executed by the processor, causes the process chamber to execute the process of the present disclosure. The software routine may also be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of the present disclosure may be executed in hardware. Therefore, the process may be implemented in software and executed in hardware using a computer system, for example, as an application-specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. When the software routine is executed by the processor, it transforms a general-purpose computer into an application-specific computer (controller) that controls the chamber operation so that the process can be executed.

[0098]

[0102] In one or more embodiments, the processing tool 900 includes a central transfer station 921, 931 including at least one robot 925, 935 configured to deposit an interface layer on the upper surface of a channel located between a source and a drain on a semiconductor substrate, deposit a high dielectric constant layer on the interface layer, deposit a dipole layer on the high dielectric constant layer, deposit a capping layer on the dipole layer, optionally anneal the semiconductor substrate, or optionally perform an etching process to remove one or more of the capping layer or dipole layer. In embodiments where a capping layer is absent, at least one robot 925, 935 is configured to perform an etching process to remove the dipole layer. In one or more embodiments, at least one robot 925, 935 is configured to form or deposit a gate, including one or more of a gate metal (not shown) or gate contacts (not shown), on the exposed surface of the high dielectric constant layer after removing one or more of the capping layer or dipole layer.

[0099]

[0103] One or more embodiments of the present disclosure relate to a non-transient computer-readable medium that, when executed by a processing chamber controller, causes the processing chamber to perform the steps of Method 100. In some embodiments, the non-transient computer-readable medium, when executed by a processing chamber controller, includes instructions that cause the processing chamber to perform the following steps: depositing an interface layer on the upper surface of a channel located between a source and a drain on a semiconductor substrate (step 102); depositing a high-dielectric-constant dielectric layer on the interface layer (step 104); depositing a dipole layer on the high-dielectric-constant dielectric layer (step 106); depositing a capping layer on the dipole layer (step 108); optionally annealing the semiconductor substrate (step 110); or optionally performing an etching process to remove one or more of the capping layer or the dipole layer (step 112).

[0100]

[0104] In embodiments where a capping layer is absent, the non-temporary computer-readable medium, when executed by the processing chamber controller, includes an instruction to cause the processing chamber to perform an etching process to remove the dipole layer (step 112).

[0101]

[0105] In a further embodiment, a non-transient computer-readable medium, when executed by the controller of the processing chamber, includes instructions to the processing chamber to form or deposit a gate, comprising one or more gate metals (not shown) or gate contacts (not shown), on the exposed surface of a high dielectric layer after removing one or more of the capping layer and dipole layer.

[0102]

[0106] Spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to facilitate explanation in describing the relationship between one element or feature and one or more other elements or features, as shown in the drawings. It will be understood that spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the drawings. For example, if the device in the drawing is upside down, an element described as “below” or “directly below” another element or feature would be facing “above” the other element or feature. Thus, the exemplary term “below” may encompass both up and down orientations. The device may be oriented differently (rotated 90 degrees or oriented in other orientations), and the spatially relative descriptions used herein may be interpreted accordingly.

[0103]

[0107] In the context of describing the materials and methods discussed herein (in particular in the context of the following claims), the use of “a” and “an,” “the,” and similar references should be interpreted as encompassing both singular and plural, unless otherwise indicated herein or unless the context clearly contradicts this interpretation. The range descriptions of values ​​herein are merely intended to serve as abbreviations for each individual value within the range, unless otherwise indicated herein, and each individual value is incorporated into the specification as if it were individually described herein. All methods described herein may be performed in any suitable order, unless otherwise indicated herein or unless the context clearly contradicts this interpretation. Any and all examples or exemplary language provided herein (e.g., “such as”) is merely intended to more preferably describe the materials and methods and does not limit their scope unless specifically asserted. The language herein should not be interpreted as indicating that non-claimed elements are essential for the implementation of the disclosed materials and methods.

[0104]

[0108] Throughout this specification, any reference to “one embodiment,” “a particular embodiment,” “one or more embodiments,” or “embodiment” means that a particular feature, structure, material, or property described in relation to an embodiment is included in at least one embodiment of this disclosure. Therefore, expressions such as “in one or more embodiments,” “in one embodiment,” “in one embodiment,” or “in an embodiment” appearing in various places throughout this specification do not necessarily refer to the same embodiment of this disclosure. In one or more embodiments, the particular features, structure, material, or property are combined in any suitable manner.

[0105]

[0109] Although the disclosure herein has been described with reference to specific embodiments, these embodiments should be understood to be merely illustrative of the principles and applications of the disclosure. Those skilled in the art will see that various modifications and changes can be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Therefore, the disclosure is intended to include modifications and variations that fall within the scope of the appended claims and their equivalents.

Claims

1. A method for manufacturing electronic devices, Depositing an interface layer on the upper surface of the channel located between the source and drain on the semiconductor substrate, Depositing a high dielectric constant layer on the aforementioned interface layer, A dipole layer containing metal oxygen nitride (MON) is deposited on the aforementioned high dielectric layer, Depositing a capping layer on the aforementioned dipole layer and Methods that include...

2. The method according to claim 1, wherein the interface layer comprises a dielectric material selected from one or more of silicon (Si), silicon oxide (SiOx), doped silicon, doped silicon oxide, or a spin-on dielectric.

3. The method according to claim 1, wherein the high dielectric constant dielectric layer comprises one or more of hafnium oxide (HfOx), zirconium oxide (ZrOx), or hafnium-zirconium oxide (HfZrOx).

4. The method according to claim 1, wherein depositing the dipole layer includes exposing the semiconductor substrate to pulses of a metal-containing precursor, pulses of a nitrogen-containing reactant, and pulses of an oxygen-containing reactant.

5. The method according to claim 1, wherein depositing the dipole layer includes exposing the semiconductor substrate to pulses of a metal-containing precursor, pulses of an oxygen-containing reactant, and pulses of a nitrogen-containing reactant.

6. The method according to claim 1, wherein depositing the dipole layer includes exposing the semiconductor substrate to co-flow of a metal-containing precursor and a nitrogen-containing reactant, pulses of the metal-containing precursor, and pulses of the oxygen-containing reactant.

7. The method according to claim 1, wherein the dipole layer has a nitrogen content of 1% or less on an atomic basis.

8. The method according to claim 4, wherein the metal-containing precursor comprises one or more of titanium (Ti), tantalum (Ta), aluminum (Al), niobium (Nb), antimony (Sb), tellurium (Te), lanthanum (La), yttrium (Y), strontium (Sr), and scandium (Sc).

9. The metal-containing precursor is trimethylaluminum (TMA) or aluminum chloride (AlCl ３ The method according to claim 8, including ).

10. The nitrogen-containing reactant is ammonia (NH ３ The method according to claim 4, including )

11. The oxygen-containing reactant is water (H ２ The method according to claim 4, including O).

12. The method according to claim 1, wherein the capping layer comprises one or more of amorphous silicon, metal, metal carbide, metal nitride, or metal oxide.

13. The method according to claim 1, further comprising annealing the semiconductor substrate at a temperature of 1100°C or less in order to move atoms from the dipole layer into the high dielectric layer.

14. The method according to claim 1, further comprising performing an etching process to remove one or more of the capping layer or the dipole layer after annealing the semiconductor substrate.

15. A method for manufacturing electronic devices, The method involves depositing an interface layer on the upper surface of a channel located between a source and a drain on a semiconductor substrate, wherein the interface layer comprises a dielectric material selected from one or more of silicon (Si), silicon oxide (SiOx), doped silicon, doped silicon oxide, or a spin-on dielectric. A high dielectric layer is deposited on the interface layer, wherein the high dielectric layer contains one or more of hafnium oxide (HfOx), zirconium oxide (ZrOx), or hafnium-zirconium oxide (HfZrOx). A dipole layer containing aluminum oxynitride (AlON) is deposited on the aforementioned high dielectric layer, The method involves depositing a capping layer on the dipole layer, wherein the capping layer comprises one or more amorphous silicon, metal, metal carbide, metal nitride, or metal oxide. Methods that include...

16. The method according to claim 15, wherein depositing the dipole layer includes exposing the semiconductor substrate to pulses of an aluminum-containing precursor, a nitrogen-containing reactant, and an oxygen-containing reactant.

17. The method according to claim 15, wherein depositing the dipole layer includes exposing the semiconductor substrate to pulses of an aluminum-containing precursor, pulses of an oxygen-containing reactant, and pulses of a nitrogen-containing reactant.

18. The method according to claim 15, wherein depositing the dipole layer involves exposing the semiconductor substrate to co-flow of an aluminum-containing precursor and a nitrogen-containing reactant, pulses of the aluminum-containing precursor, and pulses of the oxygen-containing reactant.

19. The aluminum-containing precursor is trimethylaluminum (TMA) or aluminum chloride (AlCl ３ The method according to claim 16, including ).

20. The method according to claim 15, wherein the dipole layer has a nitrogen content of 1% or less on an atomic basis.

Images