Storing continuous display content in each DRAM for power saving of static screens during idle periods.

Abstract

The present invention provides an apparatus and method for efficiently managing power consumption between multiple replication functional blocks of an integrated circuit. The integrated circuit includes multiple replication memories using separate power domains. Data of a predetermined type is stored interleaved between the multiple memories. When the control circuit detects an idle state, commands are sent to the multiple memories specifying that data of a predetermined type be stored sequentially in the memories connected to the multiple functional blocks. The control circuit then puts all memories except the specified memory into a sleep state. The memories cycle among themselves and process requests based on which of the predetermined types of data is targeted by the request and which of the memories is active.

Description

Background Art

[0001] (Description of Related Art) Both planar transistors (devices) and non-planar transistors are manufactured for use in integrated circuits within semiconductor chips. For integrating multiple types of integrated circuits, there are various options for placing processing circuits in system packaging. Some examples are system-on-chip (SOC), multi-chip module (MCM), and system-in-package (SiP). Mobile devices, desktop systems, and servers use these packages. Regardless of the options for system packaging, in some applications, the power consumption of state-of-the-art integrated circuits has become a design issue that increases with each generation of semiconductor chips.

[0002] As power consumption increases, more expensive cooling systems such as larger fans and heat sinks are utilized to remove excess heat and prevent failure of the integrated circuit. However, the cooling system increases the system cost. The constraint of power waste in integrated circuits is a problem not only for portable computers and mobile communication devices but also for high-performance desktop computers and server computers. The power management circuit specifies operating parameters for various partitions of the integrated circuit. The operating parameters include at least the operating power supply voltage and the operating clock frequency.

[0003] A partition cannot have computational tasks to be performed during a specific period while an application is running, but the power management circuit cannot specify a sleep state for that partition due to the infrequent maintenance tasks that target that partition. Modern integrated circuits include multiple duplicate functional blocks within a partition to increase throughput. Each functional block includes one or more subblocks for data processing, one or more levels of cache, and an interface for communicating with local memory. For example, if an integrated circuit is running a video graphics application, a partition containing multiple functional blocks responsible for rendering video frame data has no further computational tasks to be performed when there are no updates to the image presented on the display device. The image remains unchanged during application pauses, while waiting for user input information, or during other states where the application is still running but does not require an image update. However, the power management circuit cannot specify a sleep state for those multiple functional blocks due to periodic refresh operations that require retrieving data from the multiple functional blocks and sending it to the display device.

[0004] In light of the above, a method and mechanism for efficiently managing the power consumption of multiple replication function blocks in an integrated circuit is desired. [Brief explanation of the drawing]

[0005] [Figure 1] This is a schematic block diagram of an integrated circuit that manages power consumption between replicated memories. [Figure 2] This is a schematic block diagram of an integrated circuit that manages power consumption between duplicated memories. [Figure 3] This is a schematic block diagram of an integrated circuit that manages power consumption between duplicated memories. [Figure 4] This is a schematic block diagram of an integrated circuit that manages power consumption between duplicated memories. [Figure 5] This is a schematic block diagram of an integrated circuit that manages power consumption between duplicated memories. [Figure 6] This is a schematic block diagram of a power manager that manages power consumption between duplicate memories of an integrated circuit. [Figure 7] This is a schematic diagram illustrating a method for efficiently managing power consumption between duplicate memories in an integrated circuit. [Figure 8] This is a schematic diagram illustrating a method for efficiently managing power consumption between duplicate memories in an integrated circuit. [Modes for carrying out the invention]

[0006] While the present invention is open to various modifications and alternative forms, specific embodiments are shown in the drawings as examples and described in detail herein. However, it should be understood that the drawings and their detailed description are not intended to limit the invention to any particular form disclosed, but rather, the invention encompasses all modifications, equivalents, and alternatives that fall within the scope of the invention as defined by the appended claims.

[0007] The following specification includes numerous specific details to provide a full understanding of the invention. However, those skilled in the art should recognize that the invention can be carried out without these specific details. In some examples, well-known circuits, structures, and techniques are not shown in detail to avoid obscuring the invention. Furthermore, for the sake of simplicity and clarity of explanation, please understand that the elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some elements are exaggerated relative to others.

[0008] An apparatus and method for efficiently managing power consumption between multiple duplicate memories of an integrated circuit is contemplated. In various embodiments, the integrated circuit includes multiple duplicate memories using separate power domains. The multiple memories store a predetermined type of data in an interleaved manner. In one embodiment, the predetermined type of data is video frame data of a frame buffer rendered by multiple functional blocks of the integrated circuit. The system idle state represents a static screen of a display device connected to a display controller, and the only memory access being performed is to refresh the content displayed on the display device. When the control circuit detects the system idle state, it sends commands to the multiple memories specifying that the predetermined type of data be stored sequentially in the memories connected to the multiple functional blocks. The control circuit then puts one or more memories into a sleep state. In one embodiment, the control circuit puts all but one of the memories into a sleep state.

[0009] In one embodiment, the sleep state is the component idle state among one or more component idle states that has the lowest available voltage. The corresponding memory in the sleep state has reduced power consumption, but it also retains enough configuration information (or context information) to return to the active state without restarting the operating system. In another embodiment, the sleep state is a component idle state that has a voltage amplitude lower than that provided by the active state, but higher than the lowest available voltage amplitude among one or more component idle states. In some embodiments, in the sleep state, the control circuit further turns off the power reference level to the corresponding memory interface used by this memory. For example, the control circuit sends a control signal to a power switch that disconnects the power reference level used by the corresponding memory interface from the physical voltage plane. A functional block processes a request that targets a given type of data using a specific memory that is currently in the active state and targeted by the request.

[0010] Referring here to Figure 1, a schematic block diagram of an integrated circuit 100 that manages power consumption between multiple memories is shown. In the illustrated embodiment, the integrated circuit 100 includes a system-on-chip (SoC) 110 which includes multiple memory interfaces 112, 122, 132, 142 that connect to multiple memories 114, 124, 134, 144. In addition, in some embodiments, the SoC 110 includes a cache 150, while in other embodiments, no cache is provided. In various embodiments, each of the memories 114, 124, 134, 144 is one of various types of dynamic random-access memory (DRAM). Although omitted for convenience in the figure, the SoC 110 includes one or more functional blocks and subblocks that provide various functions and generate memory access requests targeting content stored in the memories 114, 124, 134, 144. As used herein, “functional blocks” are also called “intellectual property blocks” (or IP blocks). Furthermore, one or more functional blocks can generate requests targeting another functional block, and can process requests from other functional blocks.

[0011] One or more functional blocks are manufactured on a larger semiconductor die, such as a system-on-a-chip (SoC) 110. Examples of functional blocks include central processing units (CPUs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), multimedia engines, graphics processing units (GPUs), and digital signal processors (DSPs), which are processing units with highly parallel microarchitectures. The SoC 110 may also and is intended to include one or more of various other types of functional blocks. Due to the limited on-die area of ​​the SoC 110, the size of the cache 150 of the SoC 110 is limited, regardless of whether the SoC includes a single functional block or multiple functional blocks. Thus, in one embodiment, the integrated circuit 100 includes a microprocessor having a cache of limited size, such as cache 150, and a circuit that executes firmware instructions, including instructions for an algorithm that manages power consumption among multiple memories 114, 124, 134, 144.

[0012] Various computing devices use the integrated circuit 100. Examples of these computing devices include desktop computers, laptop computers, server computers, tablet computers, smartphones, gaming devices, smartwatches, etc. The following description describes the power management of multiple duplicate memory chiplets 114, 124, 134, and 144 connected to the SoC 110, but the following description is also applicable to the power management of multiple duplicate memory chiplets arranged in a multi-chip module (MCM). When using an MCM, one or more of the memory chiplets are connected to separate power rails and therefore can use separate power domains. Similarly, in the case of the integrated circuit 100, one or more of the memory chiplets 114, 124, 134, and 144 are connected to separate power rails and therefore can use separate power domains.

[0013] Each of the multiple power domains includes at least operating parameters such as the operating power supply voltage and the operating clock frequency. Each power domain also includes control signals for enabling and disabling connections to the clock generation circuit and power reference. In various embodiments, each of the memories 114, 124, 134, and 144 may utilize a separate power rail and be set in a separate power domain. The functional blocks and subblocks of the SoC 110, as well as the memories 114, 124, 134, and 144, utilize transistors. As used herein, “transistor” is also referred to as “semiconductor device” or “device.” Transistors include n-type metal oxide semiconductor (NMOS) field-effect transistors (FETs) (or nFETs), as well as p-type metal oxide semiconductor (PMOS) FETs (or pFETs). In some embodiments, the devices (or transistors) within the integrated circuit 100 are planar devices.

[0014] In other embodiments, the devices (or transistors) within the integrated circuit 100 are non-planar devices. Examples of non-planar transistors include tri-gate transistors, fin-type field-effect transistors (FETs), and gate-all-around (GAA) transistors. In some embodiments, the integrated circuit 100 includes one or more three-dimensional integrated circuits (3D ICs). A 3D IC includes two or more layers of active electronic elements integrated into a single circuit both vertically and / or horizontally. In one embodiment, interposer-based integration is used, thereby placing the 3D IC next to a central processing unit (CPU) containing one or more general-purpose processor cores. Alternatively, the 3D IC is stacked directly on top of another IC.

[0015] As illustrated, each of the memories 114, 124, 134, and 144 stores a copy of one or more portions of a predetermined type of data. Each of the memories 114, 124, 134, and 144 is one of various types of dynamic random access memory (DRAM). In one embodiment, the predetermined type of data is video frame data stored in a frame buffer realized by the memories 114, 124, 134, and 144. The data portions of the predetermined type are indicated by numbered boxes, and the numbers are used to identify the data portions. In some embodiments, each portion of data is a contiguous portion compared to a previous portion of a larger dataset (such as a video frame buffer), and the previous portion has an identifying number that is one less than the identifying number of the current portion. For example, portion "2" is the next contiguous portion following portion "1". In one embodiment, each portion has the same size, such as the size of a page in the DRAM. In other embodiments, one or more portions have different sizes.

[0016] In the illustrated embodiment, memory 114 stores copies of parts "1", "2", "3", and "4". Memory 124 stores copies of parts "5", "6", "7", and "8". Memory 134 stores copies of parts "9" to "12", and memory 144 stores copies of parts "13" to "16". In an embodiment in which SoC 110 utilizes cache 150, cache 150 can store copies of the data stored in memories 114, 124, 134, and 144. However, the size of cache 150 is smaller than any combination of parts of memory 114, 124, 134, and 144. For example, cache 150 cannot store parts "1" to "4" simultaneously. Similarly, cache 150 cannot store parts "5" to "8". The floor plan of the SoC110 does not provide enough on-die area to accommodate the larger size of the cache 150.

[0017] In one embodiment, the SoC 110 handles tasks of a video graphics workload, such as rendering video frame data for a display device (not shown). A predetermined type of data is video frame data in a frame buffer that is rendered and then stored in memories 114, 124, 134, and 144. This predetermined type of data is transmitted from memories 114, 124, 134, and 144 to a display controller via the SoC 110 and then to the display device. In some embodiments, memories 114, 124, 134, and 144 store a predetermined type of data contiguously, as shown in the illustrated embodiment. Storing data contiguously involves more latency for access, but this storage arrangement reduces latency for the transition of the integrated circuit 100 to an idle state. Typically, data is stored in memories 114, 124, 134, and 144 in an interleaved manner to hide the overhead latency (penalty) of the memory devices used to implement memories 114, 124, 134, and 144. For example, each of the steps of opening a page in DRAM, storing the target page in a row buffer, accessing that row buffer, and closing the page involves considerable latency or penalty. When a certain type of new data is obtained from the DMA engine or another unit and sent to memories 114, 124, 134, and 144, the new data of the given type is stored contiguously in memories 114, 124, 134, and 144, rather than being interleaved between them.

[0018] In one embodiment, the control circuit 160 is part of a power management circuit (not shown), such as a power manager. The control circuit 160 determines or assigns an idle state to the integrated circuit 100, or receives an indicator of an idle state. For example, a video graphics application stops updating the frame data visible on the display device. The video graphics application may be paused or waiting for further user input, and during the waiting period, the scene or image is not updated on the display device. Therefore, the video processing subsystem of the computing system utilizing memories 114, 124, 134, and 144 enters an idle state even though the execution of the video graphics application has not stopped.

[0019] As shown, by static allocation that continuously stores a predetermined type of data, the control circuit 160 causes one or more of the memories 114, 124, 134, and 144 to enter a sleep state. In one embodiment, the sleep state is a minimum power consumption state in which the power supply is not turned off. If the memories 114, 124, 134, and 144 utilize DRAM, then the memories 114, 124, 134, and 144 are volatile memories. In some embodiments, the sleep state is the component idle state among one or more component idle states that has the lowest available voltage. One of the memories 114, 124, 134, and 144 has reduced power consumption, but retains enough configuration information (or context information) to return to an active state without restarting the operating system.

[0020] In another embodiment, the sleep state is a component idle state having a voltage amplitude lower than that provided by the active state, but higher than the lowest available voltage amplitude among one or more component idle states. In one embodiment, in the sleep state, the control circuit 160 (or power manager or other circuit) further turns off the power reference level to one or more corresponding memory interfaces among memory interfaces 112, 122, 132, and 142. For example, the control circuit 160 (or power manager or other circuit) sends a control signal to a power switch that disconnects the power reference level used by one or more corresponding memory interfaces among memory interfaces 112, 122, 132, and 142 from the physical voltage plane. The sleep state and one or more active states may be associated with one or more power performance states (P states) that represent the respective power domains managed by the power management circuit. The sleep state and one or more active states may be associated with one or more states of the Advanced Configuration and Power Interface (ACPI) standard. States of other standards are also possible and intended. The control circuit 160 does not put memory 114 into a sleep state, but maintains memory 114 in one of several active states. In one embodiment, the control circuit 160 puts each of memories 124, 134, and 144 into a sleep state.

[0021] During the idle state of the video subsystem, memory 114, which stores data of a predetermined type (parts "1" to "4"), processes any generated requests targeting data of that predetermined type. For example, the display device of the computing system may still perform a refresh operation even though it is not requesting the rendering of new frame data. In this case, data of a predetermined type (parts "1" to "4") is a subset of the entire rendering data (parts "1" to "16") of the last frame processed before transitioning to an idle state that shows a static screen of the display device.

[0022] To perform the refresh operation, the display device requests data of a predetermined type (parts "1" to "16") from memories 114, 124, 134, and 144. After accessing parts "1" to "4" from memory 114, the control circuit 160 shifts memory 124 from the sleep state to the active state and shifts memory 114 from the active state to the sleep state. Thus, one memory is in the active state and the remaining memories are in the sleep state. Similarly, after accessing parts "5" to "8" from memory 124, the control circuit 160 shifts memory 134 from the sleep state to the active state and shifts memory 124 from the active state to the sleep state.

[0023] Furthermore, after accessing parts "9" to "12" from memory 134, the control circuit 160 shifts memory 144 from the sleep state to the active state and shifts memory 134 from the active state to the sleep state. Subsequently, after accessing parts "13" to "16" from memory 144, the control circuit 160 shifts memory 114 from the sleep state to the active state and shifts memory 144 from the active state to the sleep state. These steps are repeated during the video refresh operation. Thus, one memory is in the active state and the remaining memories are in the sleep state. While still supporting the refresh operation, the integrated circuit 100 reduces power consumption by maintaining a single one of the memories 114, 124, 134, 144 in the active state and maintaining the remaining ones of the memories 114, 124, 134, 144 in the sleep state.

[0024] Referring to FIG. 2, a schematic block diagram of an integrated circuit 200 that manages power consumption between replicated memories is shown. The signals and circuits described above are similarly labeled. Here, each of the memories 114, 124, 134, 144 stores corresponding copies of successive portions "1" to "16" as described above. The control circuit 160 determines that the integrated circuit 200 has ended the idle state. For example, a video graphics workload ends an idle state showing a still image on a display device and resumes rendering video frame data for the display device. The control circuit 160 assigns each of the memories 114, 124, 134, 144 to an active state so that none of the memories 114, 124, 134, 144 are still in the sleep state. In addition, the control circuit 160 ensures that none of the memory interfaces 112, 122, 132, 142 are left off or disconnected from the corresponding power reference level. Rather, each of the memory interfaces 112, 122, 132, 142 is turned on and in an active state. When new data of a predetermined type is acquired from the DMA engine or other unit and transmitted to the integrated circuit 200, the new data of the predetermined type continues to be successively stored in the memories 114, 124, 134, 144. Accordingly, the latency until transitioning back to the idle state is reduced.

[0025] Referring now to Figure 3, a schematic block diagram of the integrated circuit 300 that manages power consumption between duplicate memories is shown. The signals and circuits described earlier are similarly labeled. Here, each of the memories 114, 124, 134, and 144 stores corresponding copies of parts "1" to "16" in an interleaved manner. For example, the first part (part "1") of a predetermined type of data is stored in the first memory (memory 114), and a second part (part "2") that is different from the first part (part "1") of the predetermined type of data is stored in the second memory (memory 124). A third part (part "3") that is different from the first and second parts of the predetermined type of data is stored in the third memory (memory 134), and so on. If the last of the multiple memories (memory 144) has a part (part "4") of a predetermined type of data stored therein, the next part (part "5") of the predetermined type of data is stored in the first memory (memory 114). Data storage of a given type of data is continued in this manner.

[0026] Memories 114, 124, 134, and 144 store portions "1" through "16" in an interleaved manner to mask the overhead latency (penalty) of the memory devices used to implement memories 114, 124, 134, and 144. For example, each of the steps of opening a page in DRAM, storing the target page in a row buffer, accessing that row buffer, and closing the page involves considerable latency or penalty. The control circuit 160 determines or assigns an idle state to the integrated circuit 300, or receives an indicator of an idle state. For example, a video graphics application stops updating the frame data seen on the display device. The control circuit 160 changes the data storage arrangement from interleaved storage to contiguous storage. The control circuit 160 sends a command or indicator of this change to the direct memory access (DMA) engine or circuit and one or more of the memory interfaces 112, 122, 132, and 142.

[0027] In one embodiment, the next frame containing portions "17" to "32" is the last frame rendered before the integrated circuit 300 enters an idle state. Due to the changes initiated by the control circuit 160, memory interfaces 112, 122, 132, and 142 store these portions sequentially in memories 114, 124, 134, and 144. For example, memory 114 stores portions "17" to "20", memory 124 stores portions "21" to "24", and so on. In one embodiment, the control circuit 160 puts each of the memories 124, 134, and 144 into a sleep state while keeping memory 114 active. Furthermore, the control circuit 160 cuts the power to memory interfaces 122, 132, and 142 or turns off the corresponding power reference levels to memory interfaces 122, 132, and 142. The memory interface 112 remains connected to the corresponding power reference level and remains operational in an active state together with the memory 114.

[0028] To perform a refresh operation, the display device requests a predetermined type of data (parts "17" to "32") from memories 114, 124, 134, and 144. After accessing parts "17" to "20" from memory 114 and sending these parts to the display device, the control circuit 160 transitions memory 124 from sleep state to active state and memory 114 from active state to sleep state. In addition, the control circuit 160 powers on memory interface 122 and powers off memory interface 112. For example, the control circuit 160 reconnects the corresponding power reference level to memory interface 122 and disconnects the corresponding power reference level from memory interface 112. Thus, in some embodiments, one memory is in an active state and the remaining memories are in a sleep state. Similarly, after accessing parts "21" to "24" from memory 124, the control circuit 160 transitions memory 134 from sleep state to active state and memory 124 from active state to sleep state. In addition, the control circuit 160 powers on the memory interface 132 and powers off the memory interface 122. These steps continue as the refresh operation for the display device continues.

[0029] In another embodiment, the video frame containing portions "1" through "16" is the last frame rendered before the integrated circuit 300 enters an idle state. In this case, memory interfaces 112, 122, 132, and 142 transfer data between memories 114, 124, 134, and 144 to store portions "1" through "16" consecutively. The control circuit 160 then puts each of the memories 124, 134, and 144 into a sleep state, while keeping memory 114 active. Furthermore, the control circuit 160 either cuts the power to the memory interfaces 122, 132, and 142 or turns off the corresponding power reference levels to the memory interfaces 122, 132, and 142. Memory interface 112 remains connected to the corresponding power reference level and remains operational in an active state along with memory 114. The integrated circuit 300 then performs the refresh operation steps as described above.

[0030] Referring to Figure 4, a schematic block diagram of the integrated circuit 400 that manages power consumption between duplicate memories is shown. The signals and circuits described earlier are similarly labeled. Here, each of the memories 114, 124, 134, and 144 stores the corresponding copies of portions "17" to "32" consecutively, as described above. The control circuit 160 determines when the integrated circuit 400 has finished its idle state. For example, a video graphics workload finishes its idle state of showing a static screen on the display device and resumes rendering video frame data for the display device. The control circuit 160 assigns each of the memories 114, 124, 134, and 144 to an active state so that none of the memories 114, 124, 134, and 144 remain in a sleep state. In addition, the control circuit 160 ensures that none of the memory interfaces 112, 122, 132, and 142 remain off or disconnected from the corresponding power reference level. Rather, each of the memory interfaces 112, 122, 132, and 142 is turned on and in an active state. When new data of a predetermined type is acquired from the DMA engine or other unit and transmitted to the integrated circuit 400, the new data of a predetermined type is continuously stored in the memories 114, 124, 134, and 144 in an interleaved manner. Thus, access latency in non-idle states is reduced.

[0031] Referring to Figure 5, a schematic block diagram of a device 500 for managing power consumption between duplicate memories of an integrated circuit is shown. In the illustrated embodiment, the device 500 includes an SoC 510 and memories 530A to 530B. The SoC 510 includes a memory controller 520, memory interfaces 522A and 526A for transferring data to local memory 530A via communication channels 524A and 528A, and memory interfaces 522B and 526B for transferring data to local memory 530B via communication channels 524B and 528B. The SoC 510 also includes a power manager 540, a display controller 550, a direct memory access (DMA) circuit 560 (or DMA engine 560), and a network interface 570.

[0032] In various embodiments, the SoC 510 includes one or more functional blocks (not shown) for handling various types of tasks. Examples of functional blocks include central processing units (CPUs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), multimedia engines, graphics processing units (GPUs), and processing units with highly parallel microarchitectures such as digital signal processors (DSPs). In some embodiments, one or more of these functional blocks render video frame data that is later transmitted to the display controller 550. Other components of the device 500 are not shown for the sake of clarity. For example, an off-chip memory controller, one or more input / output (I / O) interface units, an interrupt controller, one or more phase-locked loops (PLLs) or other clock generation circuits, and various other functional blocks may be used by the device 500 but are not shown. In various embodiments, the device 500 is used in desktops, portable computers, mobile devices, servers, peripheral devices, and the like.

[0033] Although only two memories 530A and 530B are shown, it is possible and intended that other numbers of memories may be used by the device 500, and the number will depend on the design requirements. In one embodiment, an optional cache 522 is the final-level cache in the cache memory subsystem hierarchy. However, due to the limited on-die area of ​​the SoC 510, the size of the cache 522 is also limited. The memory controller 520 uses local memory controllers 522A and 526A to transfer data to and from local memory 530A via communication channels 524A and 528A. Local memory 530A includes memory devices 532A and 534A. In some embodiments, each of memory devices 532A and 534A is one of various types of synchronous dynamic random-access memory (SDRAM) specifically designed for applications requiring both high memory data bandwidth and high memory data rate. In other embodiments, each of memory devices 532A and 534A is another type of DRAM.

[0034] In various embodiments, each of the communication channels 524A and 528A is a point-to-point (P2P) communication channel. A point-to-point communication channel is a dedicated communication channel between a single source and a single destination. Therefore, a point-to-point communication channel transfers data only between a single source and a single destination. Address information, command information, response data, payload data, header information, and other types of information are transferred over a metal trace or wire accessible only by a single source and a single destination. In one embodiment, the local memory controllers 522A and 526A support any of various types of Graphics Double Data Rate (GDDR) communication protocols.

[0035] Although communication channels 524A and 528A use the term "communication channel," it should be noted that each of these channels can transfer data across multiple memory channels supported by the corresponding memory device. For example, a single memory channel of a particular memory device may contain more than 60 individual signals, 32 of which are dedicated to response data or payload data. The memory controller or interface of a memory device can support multiple memory channels. Each of these memory channels is contained within either communication channel 524A or 528A.

[0036] The components of the SoC510 communicate with each other via one or more of the following used for transferring data and commands: a communication bus, a point-to-point channel, a communication fabric, etc. The network interface 570 supports communication protocols for communication with any of the various types of networks. The DMA circuit 560 supports memory mapping and communication protocols used for communication with any of the various types of system memory. The display controller 550 receives rendered video frame data from memories 530A-530B and prepares this data to present the image on the corresponding display device. Each of the memory devices 532A-532B and 534A-34B is designated by the power manager 540, with each power domain including at least operating parameters such as the operating power supply voltage and operating clock frequency. Each power domain also includes control signals for enabling and disabling connections to the clock generation circuit and power reference.

[0037] In some embodiments, hardware such as the power manager 540 circuitry determines when a workload task enters an idle state. In other embodiments, the power manager 540 receives an indicator of the idle state. The idle state may indicate a static screen on a display device connected to the display controller 550. For example, a video graphics application stops updating the frame data viewed on the display device. The video graphics application may be paused or waiting for further user input, and during the waiting period, the scene or image is not updated on the display device. Thus, the video processing subsystem of the computing system enters an idle state even though the execution of the video graphics application has not stopped. The power manager 540 transmits operating parameters and data storage commands 542 to one or more of the DMA circuitry 560 and the memory controller 520. For example, the power manager 540 includes the functionality of the control circuit 160 of the integrated circuits 100-400 (Figures 1-4). In another embodiment, other circuitry besides the power manager 540 includes this functionality.

[0038] Referring here to Figure 6, a schematic block diagram of a power manager 600 that manages power consumption between the replicated memories of an integrated circuit is shown. In various embodiments, the power manager 600 includes the functions of the control circuit 160 of the integrated circuits 100-400 (Figures 1-4). As shown, the power manager 600 includes a table 610 and a control circuit 630. The control circuit 630 includes several components 632-636 used to generate operational parameters and data storage commands 640 for updating power domains of multiple memories. The table 610 includes several table entries (or entries), each storing information in at least several fields such as fields 612-618. The table 610 is implemented using one of the following: a flip-flop circuit, random-access memory (RAM), associative memory (content addressable memory, CAM), etc. While it is shown that certain information is stored in fields 612-618 in a specific adjacent order, in other embodiments, a different order may be used and a different number and type of information may be stored. As shown in the figure, field 612 stores status information, such as at least the valid bit. Field 614 stores an identifier that specifies one of several memories, such as DRAM.

[0039] Field 616 stores a value indicating whether the corresponding memory, such as DRAM used as local memory, stores a predetermined type of data contiguously or in an interleaved manner. Field 618 stores a current value indicating the latest P state or power domain of the corresponding memory. The control circuit 630 receives usage measurements and indicators (indicators) 624 representing the activity level of the memory, and power consumption measurements or parameters used to determine the latest power consumption value of the memory. The power performance state (P state) selector 632 selects the following operating parameters to be used for the memory and the corresponding memory interface. The data storage placement allocator 634 (or allocator 634) includes a circuit to determine whether the memory stores a predetermined type of data contiguously or in an interleaved manner.

[0040] In some embodiments, a predetermined type of data is video frame data. Based on one or more of the following, the allocator 634 determines whether the cache and memory store the predetermined type of data contiguously or interleaved. One or more components of the power manager 600 use values ​​stored in the configuration and status register (CSR) 636. The CSR 636 stores examples of the above values ​​used by the allocator 634. In some embodiments, one or more components of the power manager 600 and their corresponding functions are located in a separate external circuit rather than within the power manager 600.

[0041] Referring to Figure 7, a schematic block diagram of method 700 for efficiently managing power consumption between duplicate memories of an integrated circuit is shown. For illustrative purposes, the steps of this embodiment (and Figure 8) are shown in order. However, in other embodiments, some steps occur in a different order than illustrated, some steps are performed simultaneously, some steps are combined with others, and some steps are absent.

[0042] Hardware such as the circuits of multiple memories in an integrated circuit processes the workload tasks using specified operating parameters (block 702). In various embodiments, the multiple memories include memory devices such as any of various types of DRAM. In various embodiments, a power manager assigns a power domain to each of the multiple memories in the integrated circuit. Each power domain includes at least operating parameters such as the operating power supply voltage and the operating clock frequency. Each power domain also includes control signals for enabling and disabling connections to the clock generation circuit and power reference. In one embodiment, the integrated circuit processes the tasks of a video graphics workload, such as rendering video frame data for a display device. A predetermined type of data is video frame data in a rendered frame buffer. This predetermined type of data is transmitted from the multiple memories to the display device.

[0043] Multiple memories store data of a predetermined type in an interleaved manner (block 704). In some embodiments, a power manager or other control circuit determines when a workload task causes the integrated circuit to enter an idle state. In other embodiments, the power manager or other control circuit receives an indicator of the idle state. The idle state may indicate a static screen on a display device. For example, a video graphics application stops updating the frame data seen on the display device. The video graphics application may be paused or waiting for further user input, and during the waiting period, the scene or picture is not updated on the display device. Thus, the video processing subsystem of a computing system with multiple memories enters an idle state even though the execution of the video graphics application has not stopped.

[0044] If the control circuit determines that a transition to an idle state has not yet occurred (conditional branch 706: "no"), the control flow of method 700 returns to block 702, and the integrated circuit processes the workload tasks using the assigned operating parameters. However, if the control circuit determines that a transition to an idle state has occurred (conditional branch 706: "yes"), the control circuit sends commands to multiple memories to transfer a given type of data between memories until a given type of data is stored contiguously in the memories (block 708). In another embodiment, the control circuit sends commands to multiple memories to store new data contiguously.

[0045] The control circuit sends a command or indicator to a memory specifying that the operating parameters of a predetermined memory should be kept active (block 710). The control circuit puts each of the multiple memories, excluding the predetermined memory, into a sleep state (block 712). In addition, in some embodiments, the control circuit powers off the memory interface corresponding to each of the multiple memories, excluding the predetermined memory. For example, in one embodiment, the control circuit removes the corresponding power reference level for each of the multiple memories, excluding the predetermined memory. While idle, the memory uses the predetermined memory to process requests targeting a predetermined type of data (block 714). The control circuit cycles through the multiple memories to activate a single memory and processes the request based on which of the predetermined types of data is targeted by the request (block 716). In one embodiment, the control circuit powers on only the single memory interface associated with the single active memory. The other memory interfaces are powered off.

[0046] Referring to Figure 8, a schematic block diagram of method 800 for efficiently managing power consumption between duplicate memories of an integrated circuit is shown. The control circuit sends a command or indicator to the memory specifying that a predetermined type of data be stored sequentially across multiple memories (block 802). The control circuit determines that a transition to an idle state has occurred (block 804). The control circuit sends a command or indicator to the memory specifying that the operating parameters of the active state be maintained for a predetermined memory among the multiple memories (block 808). The control circuit transitions each of the multiple memories, excluding the predetermined memory, to a sleep state (block 810). In addition, in some embodiments, the control circuit powers off the memory interface corresponding to each of the multiple memories, excluding the predetermined memory. For example, in one embodiment, the control circuit removes the corresponding power reference level for each of the multiple memories, excluding the predetermined memory. During the idle state, the memory uses the predetermined memory to process requests targeting a predetermined type of data (block 812). The control circuit cycles through the multiple memories to activate a single memory and processes the request based on which of the predetermined types of data is targeted by the request (block 814). In one embodiment, the control circuit powers on only one memory interface associated with a single active memory. Other memory interfaces are powered off.

[0047] It should be noted that one or more of the embodiments described above include software. In such embodiments, program instructions for performing the method and / or mechanism are carried on or stored on a computer-readable medium. Numerous types of media configured to store program instructions are available, including hard disks, floppy disks, CD-ROMs, DVDs, flash memory, programmable ROM (ROM, PROM), random access memory (RAM), and various other forms of volatile or non-volatile storage devices. Generally speaking, computer-accessible storage media include any storage media that is accessible by a computer during use to provide instructions and / or data to the computer. For example, computer-accessible storage media include magnetic or optical media, such as disks (fixed or removable), tapes, CD-ROMs, DVD-ROMs, CD-Rs, CD-RWs, DVD-Rs, DVD-RWs, or Blu-Ray® discs. Examples of storage media include volatile or non-volatile memory media such as RAM (e.g., synchronous dynamic RAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, low power DDR (LPDDR2, etc.) SDRAM, Rambus DRAM (Rambus DRAM, RDRAM), static RAM (static RAM, SRAM), etc.), ROM, and flash memory, as well as non-volatile memory (e.g., flash memory) accessible via peripheral interfaces such as the Universal Serial Bus (USB) interface. Other examples of storage media include microelectromechanical systems (MEMS) and storage media accessible via communication media such as networks and / or wireless links.

[0048] Additionally, in various embodiments, program instructions include operational-level or register-transfer-level (RTL) descriptions of hardware functions in a high-level programming language such as C, or a design language (HDL) such as Verilog or VHDL, or a database format such as the GDSII Stream Format (GDSII). In some cases, the descriptions are read by a synthesis tool that synthesizes the descriptions to generate a netlist containing a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functions of the hardware, including the system. The netlist can then be arranged and routed to generate a dataset describing the geometric shapes applied to a mask. The mask can then be used in various semiconductor manufacturing processes to generate semiconductor circuits or circuits corresponding to the system. Alternatively, instructions on a computer-accessible storage medium may be a netlist (with or without a synthesis library) or a dataset, as needed. Additionally, instructions are used for emulation by hardware-based emulators from vendors such as Cadence®, EVE®, and Mentor Graphics®.

[0049] Although the embodiments described above are explained in considerable detail, numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully understood. The following claims are intended to be construed as encompassing all such variations and modifications.

Claims

1. It is an integrated circuit, Equipped with a control circuit, The control circuit, depending on the idle state of the integrated circuit, Assigning the active operating parameters to a first memory that stores a predetermined type of data that is the target of one or more requests, among multiple memories, Assigning the sleep state operation parameters to one or more of the plurality of memories other than the first memory, Processing the request by accessing the first memory during the idle state, It is configured to do, Integrated circuit.

2. The control circuit is configured to transmit an indicator configured such that data of a predetermined type is stored sequentially in the plurality of memories, depending on the idle state. The integrated circuit according to claim 1.

3. The control circuit is configured to transmit the indicator in response to the termination of the idle state. The integrated circuit according to claim 2.

4. The aforementioned control circuit is Prior to the idle state, an indicator configured to store data of a predetermined type in the plurality of memories in an interleaved manner is transmitted to the plurality of memories, Depending on the idle state, an indicator configured to transfer data of a predetermined type between the multiple memories and to continuously store data of a predetermined type in the multiple memories is transmitted to the multiple memories, It is configured to do, The integrated circuit according to claim 1.

5. The control circuit is configured to transmit an indicator to the plurality of memories that, upon the termination of the idle state, causes data of a predetermined type to be transferred between the plurality of memories and to store the data of the predetermined type in the plurality of memories in an interleaved manner. The integrated circuit according to claim 4.

6. The aforementioned predetermined type of data is video frame data stored in a frame buffer. The integrated circuit according to claim 1.

7. The aforementioned idle state corresponds to the state of the display device. The integrated circuit according to claim 1.

8. It is a method, An integrated circuit containing multiple memories processes a task, Depending on the idle state of the aforementioned integrated circuit, The control circuit assigns the active operating parameters to a first memory among multiple memories that stores a predetermined type of data that is the target of one or more requests. The control circuit assigns the sleep state operation parameters to one or more of the plurality of memories other than the first memory, This includes processing the request using the first memory during the idle state, method.

9. The control circuit includes transmitting an indicator configured such that data of a predetermined type is stored sequentially in the plurality of memories, depending on the idle state. The method of claim 8.

10. The control circuit includes transmitting the indicator in response to the termination of the idle state, The method of claim 9.

11. The control circuit transmits an indicator configured to store data of a predetermined type in the plurality of memories in an interleaved manner to the plurality of memories before the idle state, The control circuit includes, in accordance with the idle state, transmitting an indicator to the plurality of memories configured to transfer data of a predetermined type between the plurality of memories and to continuously store data of the predetermined type in the plurality of memories, The method of claim 8.

12. The control circuit includes transmitting an indicator to the plurality of memories configured to transfer data of a predetermined type between the plurality of memories and to store data of a predetermined type in the plurality of memories in an interleaved manner, in response to the termination of the idle state. The method according to claim 11.

13. The aforementioned predetermined type of data is video frame data stored in a frame buffer. The method of claim 8.

14. The aforementioned idle state corresponds to the state of the display device. The method of claim 8.

15. A computing system, A memory configured to store instructions for one or more tasks and source data processed by the one or more tasks, The system comprises an integrated circuit configured to execute the instruction using the source data, The aforementioned integrated circuit is Equipped with a control circuit, The control circuit, depending on the idle state of the integrated circuit, Assigning the active operating parameters to a first memory that stores a predetermined type of data that is the target of one or more requests, among multiple memories, Assigning the sleep state operation parameters to one or more of the plurality of memories other than the first memory, Processing the request by accessing the first memory during the idle state, It is configured to do, Computing system.

16. The control circuit is configured to transmit an indicator configured such that data of a predetermined type is stored sequentially in the plurality of memories, depending on the idle state. The computing system according to claim 15.

17. The control circuit is configured to transmit the indicator in response to the termination of the idle state. The computing system according to claim 16.

18. The aforementioned control circuit is Prior to the idle state, an indicator configured to store data of a predetermined type in the plurality of memories in an interleaved manner is transmitted to the plurality of memories, Depending on the idle state, an indicator configured to transfer data of a predetermined type between the multiple memories and to continuously store data of a predetermined type in the multiple memories is transmitted to the multiple memories, It is configured to do, The computing system according to claim 15.

19. The control circuit is configured to transmit an indicator to the plurality of memories that, upon the termination of the idle state, causes data of a predetermined type to be transferred between the plurality of memories and to store the data of the predetermined type in the plurality of memories in an interleaved manner. The computing system according to claim 18.

20. The aforementioned predetermined type of data is video frame data stored in a frame buffer. The computing system according to claim 15.

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