High electron mobility transistor and its drive device

Abstract

Embodiments of the present invention provide a HEMT (high electron mobility transistor) comprising: a first drain terminal; a gate terminal; a second drain terminal; a channel layer in which a first drift region is formed between the first drain terminal and the gate terminal, a channel region is formed at a position corresponding to the gate terminal, and a second drift region is formed between the second drain terminal and the gate terminal; and a ground plate disposed between the gate terminal and the second drain terminal.

Description

Technical Field

[0001] This embodiment relates to a high electron mobility transistor and its driving technology.

Background Art

[0002] Power application devices such as battery chargers, DC-DC converters, AC-DC inverters, motor controllers, and LED lighting devices require the use of power devices with low on-resistance Ron and high breakdown voltage BV in order to improve the overall power efficiency. However, according to the well-known scaling law of silicon-based power devices, Ron is proportional to the 2.5th power of BV. This means that it is substantially impossible to obtain a low Ron while maintaining a high BV. This is because a high BV makes Ron higher.

[0003] Ron is composed of a number of resistance elements in a power transistor. Among them, the drift resistance in the drift region is the main resistance and increases linearly compared to the length. In order to enhance BV, a generally longer drift length is used, which is to prevent a sharp increase in the critical electric field due to a short resistance path. As a result, there is a natural trade-off of a high on-resistance due to a longer drift length.

[0004] To overcome this limitation, wide-bandgap (WBG) semiconductors such as GaN (gallium nitride) and SiC (silicon carbide) are widely used in the field of power applications. These have a wide energy bandgap similar to a high critical electric breakdown field and have a relationship where the critical electric field is proportional to the square of the energy bandgap. The WBG transistor can significantly shorten the drift length without an early BV avalanche, thereby reducing the on-resistance.

[0005] In the low and medium voltage ranges (≤650V), GaN HEMTs (High Electron Mobility Transistors) are commonly chosen due to their near-perfect balance between voltage, current, and on-resistance. Similar to silicon power transistors, the on-resistance of GaN HEMTs scales proportionally to the breakdown voltage (BV), although the relationship between Ron and BV is weaker.

[0006] Unlike silicon transistors, GaN HEMTs lack a body diode and can operate in both directions using D1 and D2 terminals. Thanks to this unique characteristic, GaN HEMTs can offer two different functions in each direction. In one direction, the device with terminal D1 is used as a voltage interrupter, while in the other direction, the device with terminal D2 performs a general switching function.

[0007] Since the on-resistance of a GaN HEMT is the sum of the drift resistance and the channel resistance, the drift length must be kept as short as possible in D1 and D2 to reduce the overall Ron and maximize power efficiency. In D2, the switching side, the adjustment of the drift length is limited by various performance issues such as thermionic injection (HCI) and internal capacitance. However, in D1, the cutoff side, the drift length can be minimized simply by its cutoff function, depending on the manufacturer's photolithography capabilities. The drift length is defined by the cutoff voltage requirement and can be designed at twice the voltage of the switching side to satisfy the cutoff function.

[0008] As is known, the breakdown voltage (BV) of a GaN HEMT is proportional to the drift length. Therefore, the drift length of D1 must be long enough to support the required cutoff voltage, but at the same time it can be twice as large as that of D2. Since the Ron of bidirectional GaN (bi-GaN) is the sum of the Rons of D1 and D2, the large Ron added to support the cutoff function on the D1 side can significantly degrade the switching performance on the D2 side. A longer D1 drift length can further degrade switching performance by increasing the parasitic capacitance of the D1 drain and the capacitance included in the all-metal routing. [Overview of the project] [Problems that the invention aims to solve]

[0009] Against this backdrop, an objective of this embodiment is, in one aspect, to provide a technique that overcomes the limitations of short drift lengths that make it difficult to support BV and achieves optimal power efficiency at low Ron. In another aspect, an objective of this embodiment is to provide a novel technique that improves bi-GaN device performance and reduces parasitic capacitance in the D1 drain and metal routing without sacrificing BV characteristics. [Means for solving the problem]

[0010] To achieve the above objective, one embodiment provides a HEMT (High Electron Mobility Transistor) comprising: a first drain terminal; a gate terminal; a second drain terminal; a channel layer in which a first drift region is formed between the first drain terminal and the gate terminal, a channel region is formed at a position corresponding to the gate terminal, and a second drift region is formed between the second drain terminal and the gate terminal; and a grounding plate disposed between the gate terminal and the second drain terminal.

[0011] The first drain terminal, the gate terminal, and the region in the channel layer corresponding to the position from the first drain terminal to the gate terminal form a first element, and the second drain terminal, the gate terminal, and the region in the channel layer corresponding to the position from the second drain terminal to the gate terminal form a second element, the first element can operate as a voltage blocking element, and the second element can operate as a switching element.

[0012] In the direction from the second drain terminal toward the gate terminal, the length of the grounding plate may be the minimum length specified by the Design Rules (DR).

[0013] The HEMT is of a horizontal type, in which the channel layer is positioned below the first drain terminal, the gate terminal and the second drain terminal in the vertical direction, and the first drain terminal, the gate terminal and the second drain terminal are positioned in that order in the horizontal direction, and the grounding plate may be positioned between the gate terminal and the second drain terminal in the horizontal direction.

[0014] A portion of the second drift region may be formed below the grounding plate.

[0015] An insulating layer may be placed between the grounding plate and the channel layer.

[0016] At least one of the buffer layer and the substrate layer may be placed below the channel layer.

[0017] The grounding plate is positioned between the gate terminal and the second drain terminal, but does not need to be positioned between the gate terminal and the first drain terminal.

[0018] The length between the first drain terminal and the gate terminal on the upper surface of the channel layer may be the same as the minimum allowable length for a predetermined photolithography process.

[0019] The channel layer may include 2DEGs formed at the interfaces of adjacent AlGaN / GaN structures.

[0020] Another embodiment provides a drive device for driving an HEMT including a channel layer in which a first drift region is formed between a first drain terminal and a gate terminal, a channel region is formed at a position corresponding to the gate terminal, and a second drift region is formed between a second drain terminal and the gate terminal, the drive device including a gate driver that supplies a voltage lower than that of the second drain terminal to the gate terminal when the HEMT is turned off.

[0021] The first drain terminal, the gate terminal, and the region in the channel layer corresponding to the position from the first drain terminal to the gate terminal form a first element, and the second drain terminal, the gate terminal, and the region in the channel layer corresponding to the position from the second drain terminal to the gate terminal form a second element, the first element may operate as a voltage blocking element, and the second element may operate as a switching element.

[0022] The HEMT may further include a grounding plate positioned between the gate terminal and the second drain terminal.

[0023] The length between the first drain terminal and the gate terminal on the upper surface of the channel layer may be the same as the minimum allowable length for a predetermined photolithography process.

[0024] In the direction from the second drain terminal toward the gate terminal, the length of the grounding plate may be the minimum length specified by the Design Rules (DR).

[0025] Another embodiment is a HEMT (high electron mobility transistor), comprising a first drain terminal, a gate terminal, a second drain terminal, a first drift region formed between the first drain terminal and the gate terminal, a channel region formed at a position corresponding to the gate terminal, and a channel layer in which a second drift region is formed between the second drain terminal and the gate terminal. When turned off, negative biases are applied to the gate voltage between the gate terminal and the second drain terminal to provide a HEMT.

[0026] The HEMT may further include a ground plate disposed between the gate terminal and the second drain terminal.

[0027] In the direction from the second drain terminal towards the gate terminal, the length of the ground plate may be the minimum length of a predetermined design rule (DR: Design Rules).

[0028] The HEMT may be an E-mode (Enhancement-mode) HEMT showing a normally-off state.

[0029] The length between the first drain terminal and the gate terminal on the upper surface of the channel layer may be the same as the minimum allowable length of a predetermined photolithography process.

Advantages of the Invention

[0030] As described above, according to this embodiment, it is possible to exceed the limit of a short drift length where it is difficult to assist BV in power devices and achieve optimal power efficiency with a low Ron. And according to this embodiment, it is possible to improve the bi-GaN device performance without sacrificing the BV characteristics and reduce the parasitic capacitance in the D1 drain and metal routing.

Brief Description of the Drawings

[0031] [Figure 1] This is a cross-sectional view of a HEMT according to one embodiment. [Figure 2] This is a cross-sectional view of a GaN HEMT according to one embodiment, showing a further enlargement of the terminal and channel layers. [Figure 3] This figure shows the configuration of a switching element according to one embodiment. [Figure 4] This figure shows the configuration of a voltage blocking element according to one embodiment. [Figure 5] This is a circuit model of a GaN HEMT according to one embodiment. [Figure 6] This graph shows the breakdown voltage of a GaN HEMT in relation to the gate voltage on a linear scale. [Figure 7] This graph shows the breakdown voltage of GaN HEMTs in relation to gate voltage on a logarithmic scale. [Figure 8] This figure shows the configuration of a GaN HEMT drive device according to one embodiment. [Modes for carrying out the invention]

[0032] Hereinafter, some embodiments of the present invention will be described in detail with reference to illustrative drawings. Note that in assigning reference numerals to the components in each drawing, the same component will, to the greatest extent possible, have the same reference numeral even if shown in other drawings. Furthermore, in the description of the present invention, if a specific description of a related known configuration or function is deemed to obscure the gist of the present invention, such detailed description will be omitted.

[0033] Furthermore, when describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc., may be used. Such terms are used to distinguish a component from other components, and do not limit the properties, order, sequence, etc., of the component. When it is stated that a component is "connected," "joined," or "connected" to another component, it should be understood that the component may be directly connected or connected to the other component, but other components may also be "connected," "joined," or "connected" to each other.

[0034] Figure 1 is a cross-sectional view of a HEMT according to one embodiment.

[0035] Referring to Figure 1, a high electron mobility transistor (HEMT) may include a first drain terminal D1, a gate terminal GT, and a second drain terminal D2. For convenience of explanation, the side where terminals D1, GT, and D2 are located will be referred to as the upper side, and the side where the substrate layer 162 is formed will be referred to as the lower side.

[0036] HEMT100 is a semiconductor device with high electron mobility and is known to exhibit excellent performance in high-speed switching and high-frequency ranges. HEMT100 is based on a two-dimensional electron gas (2DEG). Spontaneous polarization and strain polarization couple at the interface between the barrier layer 102 and the channel layer 132 contained in HEMT100, forming a strong electric field. This phenomenon induces abundant electrons into the channel layer 132, enabling the formation of 2DEG.

[0037] 2DEG electrons have a very low effective mass and less scattering due to lattice defects and impurities, allowing them to have high mobility. These characteristics of 2DEG enable the HEMT100 to operate at higher frequencies and also improve switching speed.

[0038] Based on the characteristics described above, HEMT100 is known to have low noise and high energy efficiency. It also has relatively low on-resistance, which can improve the efficiency of power application devices. Furthermore, HEMT100 can withstand high power densities due to the 2DEG formed by a strong electric field.

[0039] HEMT100 can be manufactured using a GaN (Gallium Nitride) base.

[0040] GaN HEMTs are high-performance electronic devices that can possess characteristics particularly suitable for high-power and high-frequency applications. GaN HEMTs are known to have superior electrical characteristics compared to conventional silicon-based transistors, which is due to the physical and electrical properties of the GaN material. Below, one embodiment will be described, focusing on an example where the HEMT is GaN HEMT100.

[0041] The barrier layer 102 can be made of AlGaN, and the channel layer 132 can be made of GaN.

[0042] GaN HEMT100 can contain a two-dimensional electron gas (2DEG). In an AlGaN / GaN structure, GaN HEMT100 can form a 2DEG at the interface between the barrier layer 102 and the channel layer 132. Such a 2DEG creates a channel in which electrons have very high mobility and can move.

[0043] GaN has a very high breakdown voltage (BV) and high thermal conductivity. As a result, GaN HEMT100 can operate stably even at high voltages, effectively dissipates heat, and is suitable for use in high-power applications.

[0044] The GaN HEMT100 can have a high electron channel density due to the large number of electrons provided through the barrier layer 102, thereby achieving low on-resistance Ron and high current capacity. Furthermore, the GaN HEMT100 can have very fast switching speeds due to GaN's high electron mobility and 2DEG channel characteristics.

[0045] GaN material itself is known to have a breakdown voltage (BV) approximately 10 times higher than silicon, and possesses high thermal conductivity, making it advantageous for heat management. Furthermore, GaN has high electron mobility, making it suitable for high-frequency applications, and its wide bandgap allows it to maintain stable electrical properties even at high temperatures.

[0046] The GaN HEMT100 may further include a substrate layer 162. The substrate layer 162 can be formed from a single crystal substrate of SiC (Silicon Carbide), Si, GaN, or AIN (Aluminum Nitride). In one embodiment, the substrate layer 162 can be made of silicon Si.

[0047] A buffer layer 152 can be placed on the substrate layer 162. The buffer layer 152 can be formed from AIN (Aluminum Nitride).

[0048] An AlGaN layer 142 is placed on top of the buffer layer 152, and a channel layer 132 is placed on top of the AlGaN layer 142.

[0049] Furthermore, a barrier layer 102 can be placed on the channel layer 132. The channel layer 132, which is made of GaN, and the barrier layer 102, which is made of AlGaN, are layers formed from different bandgap semiconductor elements, and a region (or channel) of electrons with varying density can be formed at the interface between the two layers.

[0050] The channel layer 132 contains the first drain terminal D1, the gate terminal GT, and the second drain terminal D2. The GaN HEMT100 is a horizontal type, and in the vertical direction, the channel layer 132 can be positioned below the first drain terminal D1, the gate terminal GT, and the second drain terminal D2. In the horizontal direction, the first drain terminal D1, the gate terminal GT, and the second drain terminal D2 can be positioned in that order.

[0051] A p-GaN layer 112 may be further arranged between the gate terminal GT and the barrier layer 102, or between the gate terminal GT and the channel layer 132.

[0052] A grounding plate 122 is placed between the gate terminal GT and the second drain terminal D2. In the horizontal direction, the grounding plate 122 can be placed between the gate terminal GT and the second drain terminal D2. The grounding plate 122 does not come into direct contact with the channel layer 132, and an insulating layer can be placed between them. A barrier layer 102 can be placed between the insulating layer and the channel layer 132.

[0053] Figure 2 is a cross-sectional view of a GaN HEMT according to one embodiment, showing a more magnified view of the terminals and channel layer.

[0054] Referring to Figure 2, the channel layer 132 has a first drift region 202, a second drift region 204, and a channel region 212.

[0055] A first drift region 202 may be formed in the channel layer 132 between the first drain terminal D1 and the gate terminal GT. A second drift region 204 may be formed in the channel layer 132 between the second drain terminal D2 and the gate terminal GT. A channel region 212 may be formed in the channel layer 132 at a position corresponding to the gate terminal GT (for example, below the gate terminal GT). If a p-GaN layer 112 is placed below the gate terminal GT, the p-GaN layer 112 can be placed on the channel region 212.

[0056] When the GaN HEMT100 is turned on, the resistance Ron to the current flowing from the first drain terminal D1 to the second drain terminal D2 can have the same resistance value as the series combination of the first drift resistance Ron1 formed in the first drift region 202, the channel resistance Rch formed in the channel region 212, and the second drift resistance Ron2 formed in the second drift region 204. Ron = Ron1 + Rch + Ron2

[0057] The magnitude of the first drift resistance Ron1 can be proportional to the length lgd1 of the first drift region 202. The length lgd1 of the first drift region 202 can be measured by the minimum distance between the edge of the first drain terminal D1 and the edge of the gate terminal GT, which are in contact with the upper surface of the channel layer 132. The shorter the length lgd1 of such a first drift region 202, the smaller the magnitude of the first drift resistance Ron1 can be.

[0058] The magnitude of the second drift resistance Ron2 can be proportional to the length lgd2 of the second drift region 204. The length lgd2 of the second drift region 204 can be measured by the minimum distance between the end of the second drain terminal D2 and the end of the gate terminal GT, which are in contact with the upper surface of the channel layer 132. The shorter the length lgd2 of such a second drift region 204, the smaller the magnitude of the second drift resistance Ron2 can be.

[0059] Functionally, the GaN HEMT100 can be configured as two elements, DEV1 and DEV2.

[0060] The first element DEV1 can consist of a first drain terminal D1, a gate terminal GT, and a region in the channel layer 132 corresponding to the position from the first drain terminal D1 to the gate terminal GT.

[0061] The second element DEV2 can be composed of a second drain terminal D2, a gate terminal GT, and a region in the channel layer 132 corresponding to the position from the second drain terminal D2 to the gate terminal GT.

[0062] The first element DEV1 can operate as a voltage blocking element, and the second element DEV2 can operate as a switching element. The operation of the second element DEV2 determines whether the GaN HEMT100 is on or off, and in the turned-off state, the breakdown voltage characteristics of the GaN HEMT100 can be determined by the first element DEV1.

[0063] Figure 3 shows the configuration of a switching element according to one embodiment.

[0064] Referring to Figure 3, the second element (DEV2, switching element) included in the GaN HEMT may include a second drain terminal D2, a gate terminal GT, a grounding plate 122, a barrier layer 102, a channel layer 132, etc.

[0065] The on / off state of the GaN HEMT can be determined by the magnitude of the voltage (hereinafter referred to as the gate voltage) formed between the gate terminal GT and the second drain terminal D2 in the second element DEV2. For example, if the gate voltage is higher than the threshold voltage, the GaN HEMT may be turned on. Conversely, if the gate voltage is lower than the threshold voltage, the GaN HEMT may be turned off.

[0066] On the other hand, if the gate voltage is higher than the threshold voltage, a channel is formed in the channel region of the GaN HEMT, allowing electrons to move from the second drain terminal D2 to the first drain terminal. In this case, the electrons can be in a very high-energy state. This state is sometimes called a "hot" state. When these high-energy electrons collide with the lattice inside the GaN HEMT, several adverse effects can occur. For example, the magnitude of the threshold voltage may change, the device may degrade, and leakage current may be generated that flows through the insulator of the gate terminal GT. This adverse effect is called the HCI (Hot Carrier Injection) phenomenon.

[0067] The grounding plate 122 can mitigate such HCI phenomena. The grounding plate 122 can be connected to ground. Such a grounding plate 122 can reduce the peak electric field, thereby mitigating the aforementioned HCI phenomenon.

[0068] A parasitic capacitance called feedback capacitance can form between the gate terminal GT and the second drain terminal D2. Such capacitance can reduce the voltage gain and / or frequency response of the second element DEV2. The ground plate 122 also has the effect of mitigating such feedback capacitance.

[0069] The grounding plate 122 has the effect of reducing the second drift resistance in addition to the HCI relaxation effect and feedback capacitance relaxation effect described above. However, if the length of the grounding plate 122 increases, the length of the second drift region increases, which may increase the magnitude of the second drift resistance.

[0070] To reduce the magnitude of the second drift resistance, the designer can determine the length lgfp of the grounding plate 122 in the direction from the second drain terminal D2 to the gate terminal GT as the minimum length according to the Design Rules (DR).

[0071] The design rule DR can pre-determine the minimum width or length that can be manufactured in the production process for the second element DEV2. This design rule DR can define the minimum size of wires, gates, holes, etc. The length lgfp of the grounding plate 122 in the direction from the second drain terminal D2 to the gate terminal GT can be determined by the minimum length of the predetermined design rule DR, thereby minimizing the increase in the second drift resistance due to the length of the grounding plate 122.

[0072] Figure 4 shows the configuration of a voltage blocking element according to one embodiment.

[0073] Referring to Figure 4, the first element (DEV1, voltage blocking element) included in the GaN HEMT may include a first drain terminal D1, a gate terminal GT, a barrier layer 102, a channel layer 132, etc.

[0074] Unlike the second element, the first element DEV1 does not need to include a grounding plate. The grounding plate is located between the gate terminal and the second drain terminal, but does not need to be located between the gate terminal GT and the first drain terminal D1.

[0075] To reduce the first drift resistance, the length lgd1 of the first drift region can be designed to be shorter.

[0076] The length lgd1 between the first drain terminal D1 and the gate terminal GT, relative to the upper surface of the channel layer 132, may be the same as the minimum allowable length for a predetermined photolithography process. By minimizing the length lgd1 of such a first drift region, the first drift resistance can be reduced.

[0077] Incidentally, if the length of the first drift region lgd1 decreases, the magnitude of the breakdown voltage BV may decrease. The breakdown voltage BV may increase depending on the length of the drift region, and as mentioned above, shortening the length of the first drift region lgd1 may have the effect of lowering the breakdown voltage BV.

[0078] To compensate for this effect, one embodiment may apply negative biases as the gate voltage.

[0079] Figure 5 shows a circuit model of a GaN HEMT according to one embodiment.

[0080] Referring to Figure 5, a gate voltage Vg can be formed between the gate terminal GT and the second drain terminal D2. When this gate voltage Vg becomes greater than the threshold voltage, a channel is formed in the GaN HEMT, and a current Id1 can flow from the first drain terminal D1 to the second drain terminal D2 through the channel.

[0081] When the gate voltage Vg falls below the threshold voltage, the channel of the GaN HEMT closes, and a blocking voltage Vd1 can be formed between the first drain terminal D1 and the second drain terminal D2 without current flowing.

[0082] In one embodiment, when turning off a GaN HEMT to increase the limit of the blocking voltage Vd1 (withstand voltage, BV) that the GaN HEMT can withstand, a voltage lower than that of the second drain terminal D2 can be supplied to the gate terminal GT. As a result, the gate voltage Vg becomes a negative voltage, and this state can be called negative bias.

[0083] When a negative bias is applied to the gate voltage Vg, the breakdown voltage BV of a GaN HEMT can be increased.

[0084] Figure 6 is a graph showing the breakdown voltage of a GaN HEMT with respect to gate voltage on a linear scale, and Figure 7 is a graph showing the breakdown voltage of a GaN HEMT with respect to gate voltage on a logarithmic scale.

[0085] Referring to Figures 6 and 7, it can be seen that the limit of the blocking voltage Vd1 of the GaN HEMT increases as the magnitude of the absolute value of the gate voltage increases when the gate voltage is negative.

[0086] Therefore, in one embodiment, the magnitude of the breakdown voltage BV can be increased by applying a negative bias to the gate voltage, thereby shortening the length of the drift region and lowering the on-resistance Ron.

[0087] Figure 8 shows the configuration of a GaN HEMT drive device according to one embodiment.

[0088] Referring to Figure 8, the drive unit 800 may have a first drift region formed between the first drain terminal D1 and the gate terminal GT, a channel region formed at a position corresponding to the gate terminal GT, and a second drift region formed between the second drain terminal D2 and the gate terminal GT.

[0089] The drive unit 800 may include a gate driver 810 and a negative bias generator 820.

[0090] The gate driver 810 may include a VDD terminal, a VSS terminal, a signal input terminal, and a gate connection terminal.

[0091] A control signal CTS instructing the GaN HEMT500 to be turned off can be supplied as a signal input terminal to the gate driver 810. The gate driver 810 can supply a gate voltage Vg to the GaN HEMT500 that will turn off the GaN HEMT500 according to the control signal CTS.

[0092] The VSS terminal of the gate driver 810 can be connected to the second drain terminal D2 of the GaN HEMT500. This connection allows the VSS voltage of the gate driver 810 and the second drain voltage of the GaN HEMT500 to share a common voltage level.

[0093] The VDD terminal of the gate driver 810 can be supplied with a negative bias voltage output from the negative bias generator 820. The gate driver 810 can then amplify the voltage formed between the VDD terminal and the VSS terminal and supply it to the gate voltage Vg.

[0094] According to these embodiments, complex device manufacturing processes, including new layout designs and possible process step adjustments, may no longer be required. This can result in significant reductions in time and manufacturing costs.

[0095] According to these embodiments, when a negative bias is applied to the gate voltage to obtain a higher breakdown voltage BV, the on-resistance Ron may not change. This means that the on-resistance Ron is even lower compared to devices with the same rated voltage.

[0096] Furthermore, a lower on-resistance Ron can improve the overall efficiency of the system. Therefore, according to one embodiment, the system can reduce power consumption and employ a simpler circuit design, thereby saving system-level costs.

[0097] The length of the path forming the on-resistance Ron can account for a significant portion of the overall element pitch. One embodiment can significantly increase the total die per wafer (GDW) and reduce die costs by employing the lowest possible resistance path length.

[0098] The terms "contains," "constitutes," or "possesses," as used above, mean, unless otherwise specified, that the constituent element may be inherent, and should be interpreted as potentially including other constituent elements rather than excluding them. All terms, including technical or scientific terms, have the same meaning as generally understood by a person of ordinary skill in the art to which this invention pertains, unless otherwise defined. Commonly used terms, such as those defined in advance, should be interpreted as having their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this invention.

[0099] The above description is merely illustrative of the technical concept of the present invention, and any person with ordinary skill in the art to which the present invention pertains will be able to make various modifications and variations without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed herein are for illustrative purposes only and not to limit the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. The scope of protection of the present invention should be interpreted in accordance with the following claims, and all technical concepts within an equivalent scope should be interpreted as being included in the scope of the rights of the present invention.

Claims

1. HEMT (high electromobility transistor), The first drain terminal and Gate terminal and The second drain terminal, A channel layer having a first drift region formed between the first drain terminal and the gate terminal, a channel region formed at a position corresponding to the gate terminal, and a second drift region formed between the second drain terminal and the gate terminal, A grounding plate is positioned between the gate terminal and the second drain terminal, HEMT, characterized by containing [something].

2. The first drain terminal, the gate terminal, and the region in the channel layer corresponding to the position from the first drain terminal to the gate terminal form a first element. The second drain terminal, the gate terminal, and the region in the channel layer corresponding to the position from the second drain terminal to the gate terminal form a second element. The HEMT according to claim 1, characterized in that the first element operates as a voltage blocking element and the second element operates as a switching element.

3. The HEMT according to claim 1, characterized in that, in the direction from the second drain terminal toward the gate terminal, the length of the grounding plate is the minimum length of a predetermined design rule (DR).

4. The aforementioned HEMT is of the horizontal type, The HEMT according to claim 1, characterized in that the channel layer is positioned vertically below the first drain terminal, the gate terminal, and the second drain terminal, the first drain terminal, the gate terminal, and the second drain terminal are positioned horizontally in that order, and the grounding plate is positioned horizontally between the gate terminal and the second drain terminal.

5. The HEMT according to claim 4, characterized in that a portion of the second drift region is formed below the grounding plate.

6. The HEMT according to claim 4, characterized in that an insulating layer is disposed between the grounding plate and the channel layer.

7. The HEMT according to claim 1, characterized in that at least one of a buffer layer and a substrate layer is disposed below the channel layer.

8. The HEMT according to claim 1, characterized in that the grounding plate is disposed between the gate terminal and the second drain terminal, and is not disposed between the gate terminal and the first drain terminal.

9. The HEMT according to claim 1, characterized in that the length between the first drain terminal and the gate terminal on the upper surface of the channel layer is the same as the minimum allowable length for a predetermined photolithography process.

10. The HEMT according to claim 1, characterized in that the channel layer includes 2DEG formed at the interface of adjacent AlGaN / GaN structures.

11. A device for driving a HEMT including a channel layer in which a first drift region is formed between a first drain terminal and a gate terminal, a channel region is formed at a position corresponding to the gate terminal, and a second drift region is formed between a second drain terminal and the gate terminal, A drive device including a gate driver that supplies a voltage lower than that of the second drain terminal to the gate terminal when the HEMT is turned off.

12. The first drain terminal, the gate terminal, and the region in the channel layer corresponding to the position from the first drain terminal to the gate terminal form the first element. The second drain terminal, the gate terminal, and the region in the channel layer corresponding to the position from the second drain terminal to the gate terminal form a second element. The drive device according to claim 11, characterized in that the first element operates as a voltage blocking element and the second element operates as a switching element.

13. The drive device according to claim 11, wherein the HEMT further includes a grounding plate disposed between the gate terminal and the second drain terminal.

14. The drive device according to claim 13, characterized in that the length between the first drain terminal and the gate terminal on the upper surface of the channel layer is the same as the minimum allowable length of a predetermined photolithography process.

15. The drive device according to claim 13, characterized in that, in the direction from the second drain terminal toward the gate terminal, the length of the grounding plate is the minimum length of a predetermined design rule (DR).

16. HEMT (high electromobility transistor), The first drain terminal and Gate terminal and The second drain terminal, The system includes a channel layer in which a first drift region is formed between the first drain terminal and the gate terminal, a channel region is formed at a position corresponding to the gate terminal, and a second drift region is formed between the second drain terminal and the gate terminal. A HEMT characterized in that, when turned off, a negative bias is applied to the gate voltage between the gate terminal and the second drain terminal.

17. The HEMT according to claim 16, further comprising a grounding plate disposed between the gate terminal and the second drain terminal.

18. The HEMT according to claim 16, characterized in that, in the direction from the second drain terminal toward the gate terminal, the length of the grounding plate is the minimum length of a predetermined design rule (DR).

19. The HEMT according to claim 16, which is an E-mode (Enhancement-mode) HEMT indicating a normally-off state.

20. The HEMT according to claim 16, characterized in that the length between the first drain terminal and the gate terminal on the upper surface of the channel layer is the same as the minimum allowable length of a predetermined photolithography process.

Images