Gallium nitride high electron mobility transistor and method of making the same
By simultaneously forming electrode vias using the same mask, the separate fabrication of ohmic contact electrodes is eliminated, simplifying the HEMT fabrication process, reducing costs, and improving the contact performance of the conductive structure.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- INNOSCIENCE (SUZHOU) SEMICON CO LTD
- Filing Date
- 2026-03-20
- Publication Date
- 2026-06-26
AI Technical Summary
The fabrication process of existing high electron mobility transistors (HEMTs) is complex, and different masks are required for ohmic contact electrodes and conductive components in vias, resulting in high costs.
By using the same mask to simultaneously form the first electrode via and the second electrode via, the process of separately preparing the ohmic contact electrode is eliminated, and the bottom of the first conductive structure extends directly into the barrier layer, simplifying the process and reducing costs.
The fabrication process was simplified, the cost was reduced, and the contact performance of the conductive structure was improved through large-area ohmic contacts.
Smart Images
Figure CN122294527A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and more particularly to gallium nitride high electron mobility transistors and their fabrication methods. Background Technology
[0002] Due to their high electron mobility, high breakdown voltage, and high frequency characteristics, high electron mobility transistors (HEMTs) are widely used in fields such as radio frequency communication and power electronics.
[0003] However, existing high electron mobility transistors (HEMTs) still need improvement. Summary of the Invention
[0004] The purpose of this application is to provide a gallium nitride high electron mobility transistor and a method for fabricating the same.
[0005] This application discloses a gallium nitride high electron mobility transistor, comprising: Substrate; A channel layer and a barrier layer are sequentially disposed along a direction away from the substrate; A gate electrode is disposed on the side of the barrier layer away from the substrate; An etch stop layer is formed, covering the gate electrode and the barrier layer, and in direct contact with the gate electrode and the barrier layer; A passivation layer covers the etch stop layer; the etch rate of the etch stop layer is less than the etch rate of the passivation layer. Two first electrode vias are disposed on opposite sides of the gate electrode in a first direction. Each first electrode via penetrates the passivation layer and the etch stop layer, and in a direction toward the substrate and perpendicular to the substrate, the bottom of the first electrode via extends at least into the barrier layer. The first direction is parallel to the substrate. The two first electrode vias are a source electrode via and a drain electrode via, respectively. Two first conductive structures are filled one-to-one with the two first electrode vias. The bottom of the first conductive structure is in direct contact with the bottom of the first electrode via. The bottom of the first conductive structure is in contact with the barrier layer to form an ohmic contact. The second electrode via penetrates the passivation layer and the portion of the etch stop layer located above the gate electrode to expose the gate electrode; A second conductive structure is used to fill the via of the second electrode. A first wiring layer is disposed on the surface of the passivation layer away from the substrate and covers each of the first electrode vias. The first wiring layer is in direct contact with the top of the first conductive structure and the top of the first electrode via. The first wiring layer also covers the second electrode via and is in contact with the second conductive structure. The first conductive structure and the second conductive structure are made of the same material.
[0006] In some alternative embodiments, both the first conductive structure and the second conductive structure include a plurality of conductive layers stacked together along a direction away from the substrate, wherein the plurality of conductive layers of the first conductive structure and the plurality of conductive layers of the second conductive structure are disposed in the same layer, corresponding one-to-one.
[0007] In some alternative embodiments, the stacked plurality of conductive layers includes a first conductive layer and a second conductive layer, wherein the second conductive layer is located on the side of the first conductive layer away from the substrate, and the resistivity of the first conductive layer is less than the resistivity of the second conductive layer.
[0008] In some alternative embodiments, the material of the first conductive layer includes aluminum, and the material of the second conductive layer includes tungsten.
[0009] In some alternative embodiments, the stacked plurality of conductive layers further includes a third conductive layer located between the first conductive layer and the second conductive layer, the third conductive layer being used to block fluorine atoms from diffusing from the second conductive layer to the first conductive layer.
[0010] In some alternative embodiments, the material of the third conductive layer includes titanium nitride.
[0011] In some alternative embodiments, the stacked plurality of conductive layers further includes a fourth conductive layer, a portion of which is disposed on the side of the first conductive layer facing the substrate, and another portion of which surrounds the remaining conductive layers.
[0012] In some alternative embodiments, the fourth conductive layer forms an alloy structure with the first conductive layer.
[0013] In some alternative implementations, it also includes: At least one field plate structure is disposed within the passivation layer along a direction away from the substrate, and each field plate structure includes a field plate and an etch barrier layer stacked together; the etch rate of the etch barrier layer is less than the etch rate of the passivation layer; At least one electrical connection via, each of the electrical connection vias penetrating the etch barrier layer of the corresponding field plate structure and the passivation layer located above the etch barrier layer; At least one third conductive structure, each of the third conductive structures filling the corresponding electrical connection via, and the first wiring layer also covering the electrical connection via and contacting the third conductive structure.
[0014] In some alternative embodiments, the third conductive structure includes a plurality of conductive layers stacked together, wherein the plurality of conductive layers of the first conductive structure and the plurality of conductive layers of the third conductive structure are disposed on the same layer, each corresponding to one of the plurality of conductive layers of the third conductive structure.
[0015] In some alternative embodiments, the material of the etch barrier layer is the same as the material of the etch stop layer.
[0016] In some alternative embodiments, the material of the etch stop layer includes aluminum nitride.
[0017] In some alternative embodiments, the cross-sectional area of the first electrode via gradually increases in a direction away from and perpendicular to the substrate, and the cross-sectional area of the second electrode via gradually increases.
[0018] In some alternative embodiments, the bottom of the first electrode via extends into the channel layer, and the bottom of the first conductive structure contacts the channel layer to form an ohmic contact.
[0019] This application discloses a method for fabricating a gallium nitride high electron mobility transistor, comprising: Provide substrate; A channel layer and a barrier layer are formed sequentially along a direction away from the substrate; A gate electrode, an etch stop layer, and a passivation layer are sequentially formed on the side of the barrier layer away from the substrate. Two first electrode vias and one second electrode via are formed simultaneously using the same mask. In a first direction, the two first electrode vias are located on opposite sides of the gate electrode. Each first electrode via penetrates the passivation layer and the etch stop layer, and in a direction facing the substrate and perpendicular to the substrate, the bottom of the first electrode via extends at least into the barrier layer. The first direction is parallel to the substrate. The second electrode via penetrates the passivation layer and the portion of the etch stop layer located above the gate electrode to expose the gate electrode. Two first conductive structures and a second conductive structure are formed simultaneously. The two first conductive structures fill the two first electrode vias in a one-to-one correspondence. The bottom of the first conductive structure is in direct contact with the bottom of the first electrode via. The bottom of the first conductive structure is in contact with the barrier layer to form an ohmic contact. The second conductive structure fills the second electrode via. A first wiring layer is formed on the surface of the passivation layer away from the substrate. The first wiring layer covers each of the first electrode vias. The first wiring layer is in direct contact with the top of the first conductive structure and the top of the first electrode via. The first wiring layer also covers the second electrode via and is in contact with the second conductive structure.
[0020] In some alternative embodiments, along a direction away from the substrate, the passivation layer includes a first passivation sublayer, a second passivation sublayer, a third passivation sublayer, and a fourth passivation sublayer sequentially disposed, and the step of forming the passivation layer includes: A first passivation sublayer is formed covering the etch stop layer; A second passivation sublayer is formed, covering a portion of the first passivation sublayer; A first field plate structure is formed covering the first passivation sublayer and the second passivation sublayer; A third passivation sublayer is formed to cover the first field plate structure, and the top surface of the third passivation sublayer is provided with a step; A second field plate structure is formed to cover the step; along the direction away from the substrate, both the first field plate structure and the second field plate structure include a stacked field plate and an etch barrier layer; the etching rate of the etch barrier layer is less than the etching rate of the passivation layer. A fourth passivation sublayer is formed covering the second field plate structure.
[0021] In some alternative embodiments, the step of simultaneously forming two first electrode vias and one second electrode via using the same mask includes: Two first electrode vias, one second electrode via, and two electrical connection vias are formed simultaneously using the same mask. One of the electrical connection vias penetrates the etch barrier layer of the first field plate structure and the passivation layer located above the etch barrier layer. The other electrical connection via penetrates the etch barrier layer of the second field plate structure and the passivation layer located above the etch barrier layer.
[0022] In some optional embodiments, the portion of the first electrode via located in the passivation layer is a first segment, and the portion of the second electrode via located in the passivation layer is a second segment. The step of simultaneously forming two first electrode vias and one second electrode via using the same mask includes: Using the same mask, the passivation layer is etched based on the first etching medium to form the first hole segment and the second hole segment; Using the same photomask, the etching stop layer is etched based on a second etching medium to form a first electrode via and a second electrode via, wherein the second etching medium is different from the first etching medium.
[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description
[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this specification and, together with the description, serve to explain the principles of this specification.
[0025] Figure 1 This is a schematic diagram showing the formation of an etch stop layer in the fabrication method of the gallium nitride high electron mobility transistor of this application.
[0026] Figure 2 This is a schematic diagram showing the formation of the second passivation sublayer in the fabrication method of the gallium nitride high electron mobility transistor of this application.
[0027] Figure 3 This is a schematic diagram showing the formation of the third passivator in the fabrication method of the gallium nitride high electron mobility transistor of this application.
[0028] Figure 4 This is a schematic diagram of the second field plate structure formed in the method for fabricating the gallium nitride high electron mobility transistor of this application.
[0029] Figure 5 This is a schematic diagram showing the formation of the fourth passivator in the fabrication method of the gallium nitride high electron mobility transistor of this application.
[0030] Figure 6 This is a schematic diagram showing the formation of the first, second, and third hole segments in the method for fabricating the gallium nitride high electron mobility transistor of this application.
[0031] Figure 7 This is a schematic diagram showing the formation of the first electrode via, the second electrode via, and the electrical connection via in the fabrication method of the gallium nitride high electron mobility transistor of this application.
[0032] Figure 8 This is a schematic diagram showing the formation of the first conductive structure, the second conductive structure, and the third conductive structure in the fabrication method of the gallium nitride high electron mobility transistor of this application.
[0033] Figure 9A and Figure 9B This is a schematic diagram of a first conductive structure, a second conductive structure, or a third conductive structure.
[0034] Figure 10 This is a schematic diagram of the gallium nitride high electron mobility transistor fabrication method of this application after the formation of the first wiring layer.
[0035] Figure 11 This is a top view of the gallium nitride high electron mobility transistor of this application.
[0036] Reference numerals: 1. First conductive structure; 101. First conductive layer; 102. Second conductive layer; 103. Third conductive layer; 104. Fourth conductive layer; 2. Second conductive structure; 3. First wiring layer; 301. First conductive block; 302. Second conductive block; 303. Third conductive block; 4. Passivation layer; 401. First passivation sublayer; 402. Second passivation sublayer; 403. Third passivation sublayer; 404. Fourth passivation sublayer; 5. Substrate; 6. Channel layer 7. Barrier layer; 8. Gate electrode; 801. Semiconductor section; 802. Metal section; 9. Field plate structure; 9A. First field plate structure; 9B. Second field plate structure; 901. Field plate; 902. Etching barrier layer; 10. Etching stop layer; 11. First electrode via; 111. First hole segment; 12. Second electrode via; 121. Second hole segment; 13. Electrical connection via; 131. Third hole segment; 14. Third conductive structure; 15. Step; X, First direction. Detailed Implementation
[0037] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.
[0038] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.
[0039] In related technologies, such as referring to Chinese patent application document CN113287200A, when fabricating a high electron mobility transistor (HEMT), it is first necessary to use a mask to form the ohmic contact electrode of the HEMT (in the patent application with publication number CN113287200A). Figure 1 (The source 112A and drain 112C of C) In order for the formed HEMT to be connected to other external circuits, an insulating layer covering the source and drain also needs to be formed (in patent application publication number CN113287200A). Figure 1 The passivation layer 130 of C needs to be etched to form a via that exposes the source and drain (in patent application CN113287200A). Figure 1Contact via 132 of C), then fill the via with conductive material and form at least one wiring layer on the insulating layer (in patent application CN113287200A). Figure 1 The patterned conductive layer 134 of C is then used, and source and drain pads are designed on top of the wiring layer to connect the source and drain to other external circuits through conductive elements, wiring layers, and pads. This fabrication process is complex, and different masks are used to fabricate the ohmic contact electrodes and conductive elements in the vias, resulting in high device manufacturing costs.
[0040] To address the aforementioned problems, this application provides a method for fabricating a gallium nitride high electron mobility transistor. This method may include: Step S10, as follows Figure 1 As shown, substrate 5 is provided; Step S20: Form a channel layer 6 and a barrier layer 7 sequentially arranged along a direction away from the substrate 5; Step S30, as Figure 5 As shown, a gate electrode 8 and a passivation layer 4 covering the gate electrode 8 are formed on the side of the barrier layer 7 away from the substrate 5. Step S40, as Figure 7 As shown, two first electrode vias 11 are formed. The two first electrode vias 11 are disposed on opposite sides of the gate electrode 8 in the first direction X. Each first electrode via 11 penetrates the passivation layer 4. In the direction facing the substrate 5 and perpendicular to the substrate 5, the bottom of the first electrode via 11 extends at least into the barrier layer 7. The first direction X is parallel to the substrate 5. The two first electrode vias 11 are the source electrode via and the drain electrode via, respectively. Step S50, as follows Figure 8 As shown, a first conductive structure 1 is formed in each first electrode via 11; the bottom of the first conductive structure 1 is in direct contact with the bottom of the first electrode via 11. Step S60, as follows Figure 10 As shown, a first wiring layer 3 is formed on the surface of the passivation layer 4 away from the substrate 5. The first wiring layer 3 covers each first electrode via 11. The first wiring layer 3 is in direct contact with the top of the first conductive structure 1 and the top of the first electrode via 11.
[0041] The first wiring layer 3 mentioned above is also the metallized interconnect layer. The metallized interconnect layer connects all the sources or drains of multiple unit transistors together through the wiring arrangement, and spreads the current more evenly from the pads (such as source pads or drain pads) to the entire device working area.
[0042] This application also provides a gallium nitride high electron mobility transistor. This gallium nitride high electron mobility transistor can be fabricated using the methods described above. For example... Figure 10 As shown, the gallium nitride high electron mobility transistor may include: a substrate 5; a channel layer 6 and a barrier layer 7 sequentially disposed along a direction away from the substrate 5; a gate electrode 8 disposed on the side of the barrier layer 7 away from the substrate 5; a passivation layer 4 covering the gate electrode 8 and the barrier layer 7; and two first electrode vias 11 disposed on opposite sides of the gate electrode 8 in a first direction X, each first electrode via 11 penetrating the passivation layer 4, and in a direction toward the substrate 5 and perpendicular to the substrate 5, the bottom of the first electrode via 11 extending at least into the barrier layer 7, the two first electrode vias 11 being source electrodes. Vias and drain electrode vias; the first direction X is parallel to the substrate 5; two first conductive structures 1, which fill the two first electrode vias 11 one by one, the bottom of the first conductive structure 1 is in direct contact with the bottom of the first electrode via 11, and the bottom of the first conductive structure 1 is in contact with the barrier layer 7 to form an ohmic contact; a first wiring layer 3 is disposed on the surface of the passivation layer 4 away from the substrate 5, and covers each first electrode via 11 and is connected to the first conductive structure 1, the first wiring layer 3 is in direct contact with the top of the first conductive structure 1, and the first wiring layer 3 is in direct contact with the top of the first electrode via 11.
[0043] Compared with related technologies, such as Figure 10 As shown, the first electrode via 11 extends directly from the top of the passivation layer 4 into the barrier layer 7, so that the top of the first conductive structure 1 formed in the two first electrode vias 11 directly contacts the first wiring layer 3, and the bottom of the first conductive structure 1 extends into the barrier layer 7. Thus, the two first conductive structures 1 act as the source and drain, respectively, eliminating the need for additional masks to fabricate the source and drain. In other words, in related technologies, the conductive components in the vias and the ohmic contact electrodes (source and drain) are fabricated using different masks. However, this application eliminates the process of separately fabricating the ohmic contact electrodes in related technologies. The bottom of the first conductive structure 1 extends directly into the barrier layer 7, making it easier for the bottom of the first conductive structure 1 to form a large-area ohmic contact with the barrier layer 7. This simplifies the process and reduces costs.
[0044] The following is a detailed description of each part of the embodiments of this application: like Figure 1 As shown, the substrate 5 can be a Si substrate or a SiC substrate. Si or SiC substrates have high thermal conductivity and matching lattice constants, which can improve the heat dissipation performance and heterojunction quality of the device. In other embodiments, the substrate 5 can also be made of other materials.
[0045] like Figure 1As shown, this application can grow a GaN layer on substrate 5 using a deposition process to form a channel layer 6. It should be noted that before forming the channel layer 6, this application can first form a GaN buffer layer, and then form the channel layer 6 on the GaN buffer layer. The function of the channel layer 6 is to provide a high-mobility two-dimensional electron gas (2DEG) channel. This application can grow an AlGaN layer on the channel layer 6 to form a barrier layer 7. The barrier layer 7 and the channel layer 6 form a heterojunction, inducing 2DEG through a polarization effect.
[0046] The barrier layer 7 and the channel layer 6 can also be selected from other different nitrogen-based semiconductor materials. Exemplary materials for the channel layer 6 may include, but are not limited to, nitrides or III-V compounds, such as gallium nitride, aluminum nitride, and indium nitride. Exemplary materials for the barrier layer 7 may include, but are not limited to, nitrides or III-V compounds, such as gallium nitride, aluminum nitride, indium nitride, and aluminum gallium nitride. Exemplary materials for the channel layer 6 and the barrier layer 7 can be selected such that the barrier layer 7 has a larger band gap (i.e., bandgap width) than the channel layer 6, resulting in different electron affinities and forming a heterojunction between them. For example, when the channel layer 6 is an undoped gallium nitride layer (with a band gap of approximately 3.4 eV), the barrier layer 7 can be selected as an aluminum gallium nitride layer (with a band gap of approximately 4.0 eV). A triangular potential well is generated at the interface between the channel layer 6 and the barrier layer 7, allowing electrons to accumulate in the triangular potential well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction.
[0047] like Figure 2 As shown, the gate electrode 8 can be formed by a deposition process. The gate electrode 8 can be strip-shaped, and its extension direction can be parallel to the substrate 5. Along a direction away from the substrate 5, the gate electrode 8 can include a semiconductor portion 801 and a metal portion 802 stacked together. The material of the semiconductor portion 801 can include p-type gallium nitride.
[0048] like Figure 10 As shown, this application may further include a conformal etch stop layer 10 covering the gate electrode 8 and the barrier layer 7, the etch stop layer 10 being in direct contact with the gate electrode 8 and the barrier layer 7. The aforementioned passivation layer 4 may cover the etch stop layer 10. The etch rate of the etch stop layer 10 is lower than the etch rate of the passivation layer 4. The material of the etch stop layer 10 may include aluminum, such as aluminum nitride. This application can form the etch stop layer 10 through a deposition process.
[0049] Along a direction away from the substrate 5, the passivation layer 4 may include a plurality of stacked passivation sublayers. In one embodiment, such as Figure 10As shown, along the direction away from the substrate 5, the multiple passivation sublayers may include a first passivation sublayer 401, a second passivation sublayer 402, a third passivation sublayer 403, and a fourth passivation sublayer 404. The passivation sublayers can be formed by depositing oxides (e.g., silicon oxide) or nitrides (e.g., silicon nitride) using a deposition process. The materials of the different passivation sublayers can be the same, or they can be different.
[0050] like Figure 10 As shown, this application also includes at least one field plate structure 9. The field plate structure 9 is disposed within the passivation layer 4, i.e., the passivation layer 4 encloses the field plate structure 9. Each field plate structure 9 includes a stacked field plate 901 and an etch stop layer 902; the etch rate of the etch stop layer 902 is less than the etch rate of the passivation layer 4. The material of the etch stop layer 902 may be the same as or different from the material of the etch stop layer 10. The field plate 901 can be a source field plate, a drain field plate, or a gate field plate, etc. The aforementioned at least one field plate structure 9 may include two field plate structures 9, such as a first field plate structure 9A and a second field plate structure 9B.
[0051] The steps for forming the passivation layer 4 and the field plate structure 9 may include: Figure 2 As shown, a first passivation sublayer 401 is formed covering the etch stop layer 10; a second passivation sublayer 402 is formed covering a portion of the first passivation sublayer 401; as shown Figure 3 As shown, a first field plate structure 9A is formed covering the first passivation sublayer 401 and the second passivation sublayer 402; a third passivation sublayer 403 is formed covering the first field plate structure 9A, and a step 15 is provided on the top surface of the third passivation sublayer 403; as shown Figure 4 As shown, a second field plate structure 9B is formed to cover the step 15; as Figure 5 As shown, a fourth passivation sublayer 404 is formed covering the second field plate structure 9B. The thickness of the first passivation sublayer 401 is greater than the thickness of the etch stop layer 10, and the first passivation sublayer 401 plays a planarization role, that is, the surface of the first passivation sublayer 401 away from the substrate 5 can be a plane and parallel to the substrate 5.
[0052] like Figure 7 and Figure 8As shown, the first direction X is parallel to the substrate 5 and perpendicular to the extension direction of the gate electrode 8. Two first electrode vias 11 are disposed on opposite sides of the gate electrode 8 along the first direction X. The opening of each first electrode via 11 is located on the surface of the passivation layer 4 away from the substrate 5, and each first electrode via 11 penetrates the passivation layer 4 and the etch stop layer 10. In a direction toward and perpendicular to the substrate 5, the bottom of the first electrode via 11 extends at least into the barrier layer 7. Furthermore, the bottom of the first electrode via 11 may extend to the interface between the barrier layer 7 and the channel layer 6. The bottom of the first electrode via 11 can also extend into the channel layer 6. When the bottom of the first conductive structure 1 extends directly into the channel layer 6, the bottom of the first conductive structure 1 forms a large-area ohmic contact with the channel layer 6 and the barrier layer 7, which facilitates the transmission of 2DEG. This can effectively reduce the difficulty of depositing the first conductive structure 1 in the first electrode via 11. In other words, when the bottom of the first electrode via 11 extends directly into the channel layer 6, even if the hole depth of the first electrode via 11 is large and the bottom hole diameter is small, making it difficult to fill, or if the material properties of the first conductive structure 1 are poor and it is difficult to deposit to the bottom of the first electrode via 11, resulting in poor deposition quality of the bottom of the first conductive structure 1, the bottom of the first conductive structure 1 can still form a good ohmic contact with the channel layer 6 and the barrier layer 7. Figure 11 This is a top view of a gallium nitride high electron mobility transistor. Figure 10 for Figure 11 A cross-sectional view along the AA direction. (See diagram.) Figure 11 As shown, the orthogonal projection of the first electrode via 11 on the substrate 5 can be strip-shaped, and its extension direction is perpendicular to the first direction X.
[0053] This application can use dry etching to form two first electrode vias 11. The aforementioned first electrode vias 11 are fabricated using the same mask; that is, this application uses one mask during the dry etching process to form the first electrode vias 11. In related technologies, the formation processes of connecting holes and ohmic contact electrodes use two masks. Because the first electrode vias 11 are fabricated using the same mask, the sidewalls of the first electrode vias 11 are continuously formed from the bottom to the opening (top) of the first electrode vias 11; that is, the sidewalls of the first electrode vias 11 are continuously fabricated using a single etching process.
[0054] In one implementation, such as Figure 7As shown, in a direction away from and perpendicular to the substrate 5, the cross-sectional area of the first electrode via 11 parallel to the substrate 5 gradually increases. For example, in the first direction X, the first electrode via 11 includes two opposing sidewalls, each sidewall being inclined, and the distance between the two sidewalls gradually increases along the direction away from the substrate 5, which is more conducive to forming a first conductive structure 1 with good filling quality. In another embodiment, in a direction away from and perpendicular to the substrate 5, the cross-sectional area of at least a portion of the first electrode via 11 monotonically increases, monotonically decreases, or remains unchanged, that is, the distance between the two sidewalls of at least a portion of the first electrode via 11 monotonically increases, monotonically decreases, or remains unchanged. One of the two first electrode vias 11 is used to define the source region, and the other is used to define the drain region.
[0055] In addition, such as Figure 7 As shown, during the formation of the two first electrode vias 11, this application can also simultaneously form a second electrode via 12, that is, the second electrode via 12 and the first electrode via 11 are formed using the same mask in a synchronous etching process. The orthogonal projection of the second electrode via 12 onto the substrate 5 can be strip-shaped (e.g., ...). Figure 11 As shown in the diagram, the second electrode via 12 extends perpendicularly to the first direction X. The depth of the second electrode via 12 is less than the depth of the first electrode via 11. The opening of the second electrode via 12 is located on the surface of the passivation layer 4 away from the substrate 5. The second electrode via 12 penetrates the passivation layer 4 and the portion of the etch stop layer 10 located above the gate electrode 8 to expose the gate electrode 8. The orthographic projection of the bottom of the second electrode via 12 onto the substrate 5 is located within the orthographic projection area of the gate electrode 8 onto the substrate 5. The bottom of the second electrode via 12 can extend to the top surface of the gate electrode 8. Furthermore, in the first direction X, the top width of the second electrode via 12 can be less than the top width of the first electrode via 11, meaning the width of the first electrode via 11 is larger. This configuration reduces the aspect ratio of the deeper first electrode via 11.
[0056] like Figure 7 and Figure 8As shown, this application may further include at least one electrical connection via 13. This at least one electrical connection via 13 corresponds to at least one field plate structure 9, and each electrical connection via 13 penetrates the etch stop layer 902 of the corresponding field plate structure 9 and the passivation layer 4 located above the etch stop layer 902. The depth of the electrical connection via 13 may be less than the depth of the second electrode via 12. In one embodiment, in a direction away from the substrate 5 and perpendicular to the substrate 5, the cross-sectional area of the electrical connection via 13 parallel to the substrate 5 gradually increases. Taking at least one field plate structure 9 including a first field plate structure 9A and a second field plate structure 9B as an example, the number of electrical connection vias 13 can be two: one electrical connection via 13 penetrates the etch stop layer 902 of the first field plate structure 9A and the passivation layer 4 located above the etch stop layer 902, and the other electrical connection via 13 penetrates the etch stop layer 902 of the second field plate structure 9B and the passivation layer 4 located above the etch stop layer 902. During the process of simultaneously forming a first electrode via 11 and a second electrode via 12, this application can also simultaneously form at least one electrical connection via 13 using the same mask. That is, the second electrode via 12, the first electrode via 11, and the electrical connection via 13 are formed using the same mask in a synchronous etching process.
[0057] like Figure 6 and Figure 7 As shown, the portion of the first electrode via 11 located in the passivation layer 4 is the first via segment 111, the portion of the second electrode via 12 located in the passivation layer 4 is the second via segment 121, and the portion of the electrical connection via 13 located in the passivation layer 4 is the third via segment 131. The steps of simultaneously forming two first electrode vias 11, one second electrode via 12, and two electrical connection vias 13 using the same mask may include: as follows... Figure 6 As shown, the same mask is used, and the passivation layer 4 is etched based on the first etching medium to form the first hole segment 111, the second hole segment 121, and the third hole segment 131; as Figure 7 As shown, using the same photomask described above, the etch stop layer 10 and the etch barrier layer 902 are etched based on the second etch medium to form the first electrode via 11, the second electrode via 12, and the electrical connection via 13. The first and second etch media are different. The first etch medium may include one or more of carbon tetrafluoride (CF4) and trifluoromethane (CHF4). The second etch medium may include boron trichloride (BCl3).
[0058] like Figure 8 As shown, the two first conductive structures 1 fill the two first electrode vias 11 in a one-to-one correspondence. Along the direction away from the substrate 5, the first conductive structure 1 includes multiple conductive layers stacked together. For example... Figure 9A and Figure 9BAs shown, the stacked conductive layers include a first conductive layer 101 and a second conductive layer 102. The second conductive layer 102 is located on the side of the first conductive layer 101 away from the substrate 5. The resistivity of the first conductive layer 101 is lower than that of the second conductive layer 102. For example, the material of the first conductive layer 101 may be aluminum, and the material of the second conductive layer 102 may be tungsten. This arrangement can reduce ohmic contact resistance and improve the via filling performance of the first conductive structure 1 (tungsten has good filling performance). The surface of the second conductive layer 102 away from the substrate 5 is coplanar with the surface of the passivation layer 4 away from the substrate 5. The stacked conductive layers also include a third conductive layer 103 located between the first conductive layer 101 and the second conductive layer 102. The material of the third conductive layer 103 may include titanium nitride. The stacked conductive layers also include a fourth conductive layer 104. The material of the fourth conductive layer 104 may include at least one of titanium and titanium nitride. A portion of the fourth conductive layer 104 directly contacts the bottom of the first electrode via 11, while another portion of the fourth conductive layer 104 extends from the bottom of the first electrode via 11 to its opening and contacts the first wiring layer 3, surrounding the remaining conductive layers. The outer surface of the fourth conductive layer 104 surrounding the remaining conductive layers forms the outer surface of the first conductive structure 1. This fourth conductive layer 104 can conformally cover the first electrode via 11. In a direction away from and perpendicular to the substrate 5, the cross-sectional area of the first conductive structure 1 gradually increases. Furthermore, the top surface of the first conductive layer 101 is located on the side of the top surface of the barrier layer 7 away from the substrate 5. This arrangement better increases the ohmic contact area between the first conductive layer 101 and the channel layer 6 and the barrier layer 7.
[0059] like Figure 8 and Figure 10 As shown, the gallium nitride high electron mobility transistor of this application may further include a second conductive structure 2. This second conductive structure 2 fills a second electrode via 12, and a first wiring layer 3 covers the second electrode via 12 and is connected to the second conductive structure 2. The gallium nitride high electron mobility transistor of this application may further include at least one third conductive structure 14. Each third conductive structure 14 fills a corresponding electrical connection via 13. The first conductive structure 1, the second conductive structure 2, and the third conductive structure 14 are made of the same material. For example, along the direction away from the substrate 5, the first conductive structure 1, the third conductive structure 14, and the second conductive structure 2 each include a plurality of stacked conductive layers. The plurality of conductive layers of the first conductive structure 1 are co-layered with the plurality of conductive layers of the second conductive structure 2, and the plurality of conductive layers of the first conductive structure 1 are co-layered with the plurality of conductive layers of the third conductive structure 14. In the direction away from the substrate 5 and perpendicular to the substrate 5, the cross-sectional area of the second conductive structure 2 gradually increases, and the cross-sectional area of the third conductive structure 14 gradually increases.
[0060] For example, the formation of the first conductive structure 1, the second conductive structure 2, and the third conductive structure 14 may include steps S501-S502: Step S501: A plurality of conductive material layers are formed on the passivation layer 4, and the plurality of conductive material layers fill the first electrode via 11, the electrical connection via 13 and the second electrode via 12. Along the direction away from the substrate 5, the stacked conductive material layers may include a first conductive material layer and a second conductive material layer. Further, along the direction away from the substrate 5, the stacked conductive material layers may include a fourth conductive material layer, a first conductive material layer, a third conductive material layer, and a second conductive material layer, each conductive material layer being formed by a deposition process. The fourth conductive material layer conformally covers the first electrode via 11, the electrical connection via 13, and the second electrode via 12. The material of the fourth conductive material layer includes at least one of titanium nitride and titanium. The first conductive material layer conformally covers the fourth conductive material layer. The material of the first conductive material layer includes aluminum, which can form good ohmic contacts with semiconductor materials such as the barrier layer 7 and the channel layer 6; in another embodiment, the first conductive material layer may also be selected from other metallic materials that can form good ohmic contacts with semiconductor materials such as the barrier layer 7 and the channel layer 6. The third conductive material layer conformally covers the first conductive material layer. An alloy structure can be formed at the interface between the first conductive material layer and the fourth conductive layer. The material of the third conductive layer includes titanium nitride. In another embodiment, a first conductive material layer covers a fourth conductive material layer located on the bottom wall of the first electrode via 11 and a portion of the fourth conductive material layer located on the side wall of the first electrode via 11; a third conductive material layer covers the first conductive material layer and a portion of the fourth conductive material layer located on the side wall of the first electrode via 11.
[0061] The third conductive material layer is made of a material that can block the diffusion of fluorine atoms. This third conductive material layer prevents fluorine atoms from diffusing from the second conductive material layer to the first conductive material layer, thus preventing degradation of the ohmic contact performance of the first conductive material layer. The second conductive material layer is made of tungsten, which can be deposited well in the first electrode via 11, forming a high-quality filled structure in the via 11. This second conductive material layer can be formed by chemical vapor deposition (CVD). During the CVD deposition process of the second conductive material layer, tungsten-containing halides (e.g., tungsten hexafluoride) are deposited, introducing halogen atoms such as fluorine atoms. The third conductive material layer is positioned between the first and second conductive material layers, and fluorine atoms are essentially unable to diffuse within this third conductive material layer, thus protecting the first conductive material layer. Furthermore, each of the aforementioned conductive material layers extends from the first electrode via 11 and the second electrode via 12.
[0062] Step S502: Remove the portions of multiple conductive material layers located outside the first electrode via 11, the electrical connection via 13, and the second electrode via 12, so as to form a first conductive structure 1 in the first electrode via 11, a second conductive structure 2 in the second electrode via 12, and a third conductive structure 14 in the electrical connection via 13.
[0063] This application utilizes a grinding process to remove portions of multiple conductive material layers located outside the first electrode via 11, the electrical connection via 13, and the second electrode via 12. The remaining fourth conductive material layer forms the fourth conductive layer 104, the remaining first conductive material layer forms the first conductive layer 101, the remaining third conductive material layer forms the third conductive layer 103, and the remaining second conductive material layer forms the second conductive layer 102. The surface of the second conductive layer 102 away from the substrate 5 is coplanar or flush with the surface of the passivation layer 4 away from the substrate 5. Specifically, the multiple conductive layers stacked within the first electrode via 11 form the first conductive structure 1, the multiple conductive layers stacked within the second electrode via 12 form the second conductive structure 2, and the multiple conductive layers stacked within the electrical connection via 13 form the third conductive structure 14. As can be seen from the above, the first conductive structure 1 is prepared using the same deposition process. This means that the multiple conductive layers of the first conductive structure 1 are formed by continuous deposition. However, in related technologies, after depositing the ohmic contact electrode, an insulating layer covering the ohmic contact electrode needs to be formed, and a via is formed on the insulating layer. Then, a conductive element within the via is formed through a deposition process. Therefore, the ohmic contact electrode and the conductive element within the via are not formed by continuous deposition. Furthermore, the resistivity of the first conductive layer 101 is lower than that of the second conductive layer 102, which can achieve a lower ohmic contact resistance between the first conductive layer 101 and semiconductor materials such as the barrier layer 7 and the channel layer 6. For example, the resistivity of the first conductive layer 101, such as aluminum, can be approximately 2.82 × 10⁻⁻⁻⁻⁶. 8 The resistivity of the second conductive layer 102, such as tungsten, can be approximately 5.6 × 10⁻⁻ Ω•m (ohm-meter). 8 Approximately Ω•m (ohm-meter).
[0064] like Figure 10 and Figure 11As shown, the first wiring layer 3 can be formed by a deposition process. The first wiring layer 3 can be in direct contact with the second conductive layer 102, and the material of the first wiring layer 3 is different from that of the second conductive layer 102. Taking the second conductive layer 102 as an example, the material of the first wiring layer 3 can include at least one of aluminum and copper. The resistivity of the first wiring layer 3 is less than that of the second conductive layer 102, that is, the resistivity of the first wiring layer 3 is less than that of the second conductive material layer (the top conductive material layer among multiple conductive material layers). The first wiring layer 3 includes multiple first conductive blocks 301, each first conductive block 301 covering a first electrode via 11 and connected to the top of a first conductive structure 1, that is, the first conductive block 301 is directly formed on the top of the first conductive structure 1. The first wiring layer 3 is in direct contact with the top of the first electrode via 11, that is, the first wiring layer 3 seals the opening of the first electrode via 11. The first wiring layer 3 also covers the second electrode via 12 and the electrical connection via 13. The first wiring layer 3 covering the second electrode via 12 is in contact with the second conductive structure 2, and the first wiring layer 3 covering the electrical connection via 13 is in contact with the third conductive structure 14. For example, the first wiring layer 3 also includes a second conductive block 302 and a third conductive block 303, the second conductive block 302 being in contact with the second conductive structure 2, and the third conductive block 303 being in contact with the third conductive structure 14. In the second direction, which is parallel to the substrate 5 and perpendicular to the first direction X, the length of the first wiring layer 3 covering the second electrode via 12 (i.e., the second conductive block 302) is different from the length of the first wiring layer 3 covering the first electrode via 11 (i.e., the first conductive block 301). For example, the length of the first wiring layer 3 covering the second electrode via 12 is greater than the length of the first wiring layer 3 covering the first electrode via 11.
[0065] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A gallium nitride high electron mobility transistor, characterized in that, include: Substrate; A channel layer and a barrier layer are sequentially disposed along a direction away from the substrate; A gate electrode is disposed on the side of the barrier layer away from the substrate; An etch stop layer is formed, covering the gate electrode and the barrier layer, and in direct contact with the gate electrode and the barrier layer; A passivation layer covers the etch stop layer; the etch rate of the etch stop layer is less than the etch rate of the passivation layer. Two first electrode vias are disposed on opposite sides of the gate electrode in a first direction. Each first electrode via penetrates the passivation layer and the etch stop layer, and in a direction toward the substrate and perpendicular to the substrate, the bottom of the first electrode via extends at least into the barrier layer. The first direction is parallel to the substrate; The two first electrode vias are the source electrode via and the drain electrode via, respectively. Two first conductive structures are filled one-to-one with the two first electrode vias. The bottom of the first conductive structure is in direct contact with the bottom of the first electrode via. The bottom of the first conductive structure is in contact with the barrier layer to form an ohmic contact. The second electrode via penetrates the passivation layer and the portion of the etch stop layer located above the gate electrode to expose the gate electrode; A second conductive structure is used to fill the via of the second electrode. A first wiring layer is disposed on the surface of the passivation layer away from the substrate and covers each of the first electrode vias. The first wiring layer is in direct contact with the top of the first conductive structure and the top of the first electrode via. The first wiring layer also covers the second electrode via and is in contact with the second conductive structure. The first conductive structure and the second conductive structure are made of the same material.
2. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, Along a direction away from the substrate, both the first conductive structure and the second conductive structure include a plurality of conductive layers stacked together, wherein the plurality of conductive layers of the first conductive structure and the plurality of conductive layers of the second conductive structure are disposed in the same layer, corresponding one-to-one.
3. The gallium nitride high electron mobility transistor according to claim 2, characterized in that, The stacked conductive layers include a first conductive layer and a second conductive layer, wherein the second conductive layer is located on the side of the first conductive layer away from the substrate, and the resistivity of the first conductive layer is less than that of the second conductive layer.
4. The gallium nitride high electron mobility transistor according to claim 3, characterized in that, The first conductive layer is made of aluminum, and the second conductive layer is made of tungsten.
5. The gallium nitride high electron mobility transistor according to claim 3, characterized in that, The stacked conductive layers also include a third conductive layer located between the first conductive layer and the second conductive layer, the third conductive layer being used to block fluorine atoms from diffusing from the second conductive layer to the first conductive layer.
6. The gallium nitride high electron mobility transistor according to claim 5, characterized in that, The material of the third conductive layer includes titanium nitride.
7. The gallium nitride high electron mobility transistor according to claim 5, characterized in that, The stacked conductive layers also include a fourth conductive layer, part of which is disposed on the side of the first conductive layer facing the substrate, and another part of which surrounds the remaining conductive layers.
8. The gallium nitride high electron mobility transistor according to claim 7, characterized in that, The fourth conductive layer forms an alloy structure with the first conductive layer.
9. The gallium nitride high electron mobility transistor according to claim 2, characterized in that, Also includes: At least one field plate structure is disposed within the passivation layer, and along the direction away from the substrate, each field plate structure includes a stacked field plate and an etching barrier layer. The etching rate of the etching barrier layer is less than the etching rate of the passivation layer; At least one electrical connection via, each of the electrical connection vias penetrating the etch barrier layer of the corresponding field plate structure and the passivation layer located above the etch barrier layer; At least one third conductive structure, each of the third conductive structures filling the corresponding electrical connection via, and the first wiring layer also covering the electrical connection via and contacting the third conductive structure.
10. The gallium nitride high electron mobility transistor according to claim 9, characterized in that, The third conductive structure includes multiple conductive layers stacked together, and the multiple conductive layers of the first conductive structure and the multiple conductive layers of the third conductive structure are disposed on the same layer, corresponding one-to-one.
11. The gallium nitride high electron mobility transistor according to claim 9, characterized in that, The material of the etching barrier layer is the same as the material of the etching stop layer.
12. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, The material of the etching stop layer includes aluminum nitride.
13. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, In a direction away from and perpendicular to the substrate, the cross-sectional area of the first electrode via gradually increases, and the cross-sectional area of the second electrode via gradually increases.
14. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, The bottom of the first electrode via extends into the channel layer, and the bottom of the first conductive structure contacts the channel layer to form an ohmic contact.
15. A method for fabricating a gallium nitride high electron mobility transistor, characterized in that, include: Provide substrate; A channel layer and a barrier layer are formed sequentially along a direction away from the substrate; A gate electrode, an etch stop layer, and a passivation layer are sequentially formed on the side of the barrier layer away from the substrate. Two first electrode vias and one second electrode via are formed simultaneously using the same mask. In a first direction, the two first electrode vias are located on opposite sides of the gate electrode. Each first electrode via penetrates the passivation layer and the etch stop layer. In a direction facing the substrate and perpendicular to the substrate, the bottom of the first electrode via extends at least into the barrier layer. The first direction is parallel to the substrate; The second electrode via penetrates the passivation layer and the portion of the etch stop layer located above the gate electrode to expose the gate electrode; Two first conductive structures and a second conductive structure are formed simultaneously. The two first conductive structures fill the two first electrode vias in a one-to-one correspondence. The bottom of the first conductive structure is in direct contact with the bottom of the first electrode via. The bottom of the first conductive structure is in contact with the barrier layer to form an ohmic contact. The second conductive structure fills the via of the second electrode; A first wiring layer is formed on the surface of the passivation layer away from the substrate. The first wiring layer covers each of the first electrode vias. The first wiring layer is in direct contact with the top of the first conductive structure and the top of the first electrode via. The first wiring layer also covers the second electrode via and is in contact with the second conductive structure.
16. The method for fabricating a gallium nitride high electron mobility transistor according to claim 15, characterized in that, Along a direction away from the substrate, the passivation layer includes a first passivation sublayer, a second passivation sublayer, a third passivation sublayer, and a fourth passivation sublayer sequentially disposed therefrom. The steps for forming the passivation layer include: A first passivation sublayer is formed covering the etch stop layer; A second passivation sublayer is formed, covering a portion of the first passivation sublayer; A first field plate structure is formed covering the first passivation sublayer and the second passivation sublayer; A third passivation sublayer is formed to cover the first field plate structure, and the top surface of the third passivation sublayer is provided with a step; A second field plate structure is formed to cover the step; along the direction away from the substrate, both the first field plate structure and the second field plate structure include a stacked field plate and an etch barrier layer; the etching rate of the etch barrier layer is less than the etching rate of the passivation layer. A fourth passivation sublayer is formed covering the second field plate structure.
17. The method for fabricating a gallium nitride high electron mobility transistor according to claim 16, characterized in that, The step of simultaneously forming two first electrode vias and one second electrode via using the same mask includes: Two first electrode vias, one second electrode via, and two electrical connection vias are formed simultaneously using the same mask. One of the electrical connection vias penetrates the etch barrier layer of the first field plate structure and the passivation layer located above the etch barrier layer. The other electrical connection via penetrates the etch barrier layer of the second field plate structure and the passivation layer located above the etch barrier layer.
18. The method for fabricating a gallium nitride high electron mobility transistor according to claim 15, characterized in that, The portion of the first electrode via located in the passivation layer is the first via segment, and the portion of the second electrode via located in the passivation layer is the second via segment. The step of simultaneously forming two first electrode vias and one second electrode via using the same mask includes: Using the same mask, the passivation layer is etched based on the first etching medium to form the first hole segment and the second hole segment; Using the same photomask, the etching stop layer is etched based on a second etching medium to form a first electrode via and a second electrode via, wherein the second etching medium is different from the first etching medium.