A low-latency high-reliability enhanced gallium nitride monolithic integrated driving circuit
By integrating OR gate modules and inverter modules into a gallium nitride monolithic integrated driver circuit, the problem of excessive propagation delay is solved, and a low-latency, high-reliability driver circuit is realized, ensuring the safety and reliability of gallium nitride devices in short-circuit events.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2026-02-13
- Publication Date
- 2026-06-09
AI Technical Summary
Existing gallium nitride monolithic integrated driver circuits have excessive propagation delays under short-circuit conditions, which may lead to thermal runaway and burnout of power devices. In addition, although conventional OR gate cross-interconnection schemes improve reliability, the delays are too large and cannot shut down the devices in time.
A low-latency, high-reliability enhanced gallium nitride monolithic integrated driver circuit is adopted. By integrating OR gates into the pre-drive circuit, and using first and second inverter modules, driver-enhanced OR gate modules, and low-voltage gallium nitride devices, the signal transmission link is shortened and the reliability is improved.
It effectively reduces signal propagation delay, improves the reliability of the drive circuit, avoids short circuits between the upper and lower transistors in the output stage, ensures that power devices shut down in time during short circuit events, and reduces the risk of thermal runaway.
Smart Images
Figure CN122178885A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of circuit technology, specifically relating to a low-latency, high-reliability enhanced gallium nitride monolithic integrated driver circuit. Background Technology
[0002] Gallium nitride (GaN) power devices demonstrate great potential in next-generation power conversion systems due to their high switching speed, low on-resistance, and high breakdown voltage. They outperform their silicon counterparts, enabling higher efficiency, higher power density, and smaller size for the overall system. However, to unlock the full potential of GaN devices, the driver circuitry needs to be monolithically integrated with the power GaN HEMT, as discrete GaN HEMT strategies on PCBs introduce unwanted parasitics. This integration achieves greater energy efficiency and reliability.
[0003] Because gallium nitride (GaN) devices typically operate at high power densities, their temperature rise is more rapid under short-circuit conditions. Therefore, the short-circuit withstand time of GaN devices is lower than that of comparable silicon products, which places higher demands on the response time of protection circuits. The propagation delay of the drive circuit is a major factor in the response time of the protection circuit. The magnitude of the propagation delay directly affects the reliability of GaN devices in the event of a short circuit. A higher propagation delay leads to a longer response time for the protection circuit. When the response time exceeds the withstand time of the GaN device, there is a risk of thermal runaway and burnout. Furthermore, in conventional GaN monolithic integrated circuit designs, the output of the drive circuit typically consists of two N-channel low-voltage GaN devices connected in series. During output switching, the two low-voltage GaN devices may conduct simultaneously for a short period, posing a risk of short circuit in the output stage of the drive circuit. Therefore, avoiding this short circuit in the drive circuit is a crucial step in improving the reliability of the power supply system. To solve these problems, the drive circuit needs to achieve both low propagation delay and high reliability.
[0004] To avoid current congestion caused by the simultaneous conduction of the upper and lower transistors in the output stage of the driver circuit, a conventional solution is to use two OR gates interconnected in a cross manner. The sequence of changes in the drive signal is as follows: the gate signal of the upper transistor in the output stage can only be high after the gate signal of the lower transistor in the output stage goes low, and similarly, the gate signal of the upper transistor in the output stage can only be high after the gate signal of the lower transistor in the output stage goes low. This avoids short circuits between the upper and lower transistors in the output stage of the driver circuit.
[0005] While the conventional scheme of cross-interconnecting two OR gates can improve the reliability of the drive circuit, it doubles the signal transmission delay, resulting in a large propagation delay. In the event of a short circuit, the large propagation delay prevents the power device from being turned off in time, and the power device is at risk of thermal runaway and burnout. Summary of the Invention To address the aforementioned problems in the prior art, this invention provides a low-latency, high-reliability enhanced gallium nitride monolithic integrated driver circuit.
[0006] The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a low-latency, high-reliability enhanced gallium nitride monolithic integrated driver circuit, comprising: The system comprises a first inverter module, a second inverter module, a first drive-enhanced OR gate module, a second drive-enhanced OR gate module, a first low-voltage gallium nitride device Q1, and a second low-voltage gallium nitride device Q2. In this configuration, the output of the first inverter module is connected to the first input of the first drive-enhanced OR gate module and the input of the second inverter module. The input of the first inverter module is connected to the second input of the second drive-enhanced OR gate module and serves as the drive signal input port Vin. The output of the first drive-enhanced OR gate module is connected to the gate of the first low-voltage gallium nitride device Q1. The output of the second inverter module is connected to the first input of the second drive-enhanced OR gate module and the output of the second drive-enhanced OR gate module is connected to the second input of the first drive-enhanced OR gate module and the gate of the second low-voltage gallium nitride device Q2. The source of the first low-voltage gallium nitride device Q1 and the drain of the second low-voltage gallium nitride device Q2 are connected to serve as the drive output port Vout. The drain of the first low-voltage gallium nitride device Q1 is connected to the external power supply VCC, and the source of the second low-voltage gallium nitride device Q2 is connected to GND.
[0007] In some embodiments, the circuit logic of the first inverter module and the second inverter module is any one of RTL logic, bootstrap capacitor driven logic, and complementary logic.
[0008] In some embodiments, both the first drive-enhanced OR gate module and the second drive-enhanced OR gate module adopt a bootstrap capacitor drive mode.
[0009] In some embodiments, both the first inverter module and the second inverter module adopt a bootstrap capacitor drive mode.
[0010] In some embodiments, the first drive-enhanced OR gate module includes: HEMT device Q3_H, HEMT device Q4_H, HEMT device Q5_H, HEMT device Q6_H, HEMT device Q7_H, HEMT device Q8, HEMT device M1_H, HEMT device M2_H, capacitor C1, capacitor C2_H, capacitor C3_H, and resistor R1_H; Specifically, the gate of Q5_H is connected to the gate of Q4_H and one end of C3_H to serve as the first input terminal of the first drive enhancement OR gate module; the gate of M1_H is connected to the gate of M2_H to serve as the second input terminal of the first drive enhancement OR gate module; the source of Q3_H is connected to the drain of Q4_H, one end of C2_H and the drain of M2_H to serve as the output terminal of the first drive enhancement OR gate module. The other end of C3_H is connected to the drain of Q6_H, the gate of Q7_H, and the gate of Q8; the source of Q6_H is connected to the gate of Q6_H, the source of Q7_H, and the source of Q8, all of which are connected to the external power supply VCC; the drain of Q7_H is connected to the other end of C2_H and one end of R1_H; the other end of R1_H is connected to the drain of Q5_H, the drain of M1_H, and the gate of Q3_H; the sources of Q5_H, Q4_H, M1_H, and M2_H are all connected to GND; the drain of Q3_H is connected to the drain of Q8 and one end of C1; the other end of C1 is connected to the source of the first low-voltage gallium nitride device Q1.
[0011] In some embodiments, the second drive-enhanced OR gate module includes: HEMT device Q3_L, HEMT device Q4_L, HEMT device Q5_L, HEMT device Q6_L, HEMT device Q7_L, HEMT device M1_L, HEMT device M2_L, capacitor C2_L, capacitor C3_L, and resistor R1_L. In this configuration, the gate of Q5_L is connected to the gate of Q4_L and one end of C3_L, serving as the first input terminal of the second drive enhancement OR gate module; the gate of M1_L is connected to the gate of M2_L, serving as the second input terminal of the second drive enhancement OR gate module; and the source of Q3_L is connected to the drain of Q4_L, one end of C2_L, and the drain of M2_L, serving as the output terminal of the second drive enhancement OR gate module. The other end of C3_L is connected to the drain of Q6_L, the gate of Q7_L, and the gate of Q8; the source of Q6_L is connected to the gate of Q6_L, the source of Q7_L, and the drain of Q3_L, all of which are connected to the external power supply VCC; the drain of Q7_L is connected to the other end of C2_L and one end of R1_L; the other end of R1_L is connected to the drain of Q5_L, the drain of M1_L, and the gate of Q3_L; the source of Q5_L, the source of Q4_L, the source of M1_L, and the source of M2_L are all connected to GND.
[0012] In some embodiments, Q3_H, Q4_H, Q5_H, Q6_H, Q7_H, Q8, M1_H, M2_H, Q3_L, Q4_L, Q5_L, Q6_L, Q7_L, M1_L, and M2_L are all low-voltage HEMT devices.
[0013] In some embodiments, the first inverter module / second inverter module includes: HEMT device Q9, HEMT device Q10, HEMT device Q11, HEMT device Q12, capacitor C4, and resistor R2. Wherein, the gate of Q10 is connected to the gate of Q11 and serves as the input terminal of the first inverter module / the second inverter module; one end of C4 is connected to the source of Q9 and the drain of Q10 and serves as the output terminal of the first inverter module / the second inverter module. The sources of Q10 and Q11 are both connected to GND; the drain of Q10 is connected to one end of R2 and the gate of Q9; the other end of R2 is connected to the other end of C4 and the source of Q12; the gate and drain of Q12 and the drain of Q9 are both connected to the external power supply VCC.
[0014] In some embodiments, Q9, Q10, Q11, and Q12 are all low-voltage HEMT devices.
[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: Compared to conventional drive circuit structures that use two OR gates interconnected, this invention integrates the OR gates into the pre-drive circuit, shortening the signal transmission stage. Specifically, the pre-drive circuit uses two drive-enhancing OR gate modules interconnected, which allows for a dead time in the gate signals of Q1 and Q2, improving drive reliability. Furthermore, implementing this function in the pre-drive circuit minimizes signal propagation delay.
[0016] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of an architecture of a low-latency, high-reliability enhanced gallium nitride monolithic integrated driver circuit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a circuit structure of a low-latency, high-reliability enhanced gallium nitride monolithic integrated driver circuit provided in an embodiment of the present invention; Figure 3 This is another circuit structure diagram of the low-latency, high-reliability enhanced gallium nitride monolithic integrated driver circuit provided in the embodiments of the present invention; Figure 4 This is a simulation diagram of a low-latency, high-reliability enhanced gallium nitride monolithic integrated driver circuit provided in an embodiment of the present invention; Figure 5 and Figure 6 These are simulation diagrams of short-circuit reliability verification of Q1 and Q2 in the low-latency, high-reliability enhanced gallium nitride monolithic integrated driver circuit provided in the embodiments of the present invention. Figure 7 and Figure 8 These are simulation diagrams of the propagation delay of the low-latency, high-reliability enhanced gallium nitride monolithic integrated driver circuit provided in the embodiments of the present invention. Detailed Implementation
[0018] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0019] The present invention provides a low-latency, high-reliability enhanced gallium nitride monolithic integrated driver circuit, which includes: a first inverter module, a second inverter module, a first driver enhanced OR gate module, a second driver enhanced OR gate module, a first low-voltage gallium nitride device Q1, and a second low-voltage gallium nitride device Q2. In this configuration, the output of the first inverter module is connected to the first input of the first drive-enhanced OR gate module and the input of the second inverter module. The input of the first inverter module is connected to the second input of the second drive-enhanced OR gate module, serving as the drive signal input port Vin. The output of the first drive-enhanced OR gate module is connected to the gate of the first low-voltage gallium nitride device Q1. The output of the second inverter module is connected to the first input of the second drive-enhanced OR gate module. The output of the second drive-enhanced OR gate module is connected to the second input of the first drive-enhanced OR gate module and the gate of the second low-voltage gallium nitride device Q2. The source of the first low-voltage gallium nitride device Q1 and the drain of the second low-voltage gallium nitride device Q2 are connected, serving as the drive output port Vout. The drain of the first low-voltage gallium nitride device Q1 is connected to the external power supply VCC, and the source of the second low-voltage gallium nitride device Q2 is connected to GND. For example... Figure 1 This is a schematic diagram of the drive circuit architecture provided in an embodiment of the present invention. Figure 1 In this diagram, inverter module 1 represents the first inverter module, inverter module 2 represents the second inverter module, and drive-enhanced OR gate module 1 represents the first drive-enhanced OR gate module, while drive-enhanced OR gate module 2 represents the second drive-enhanced OR gate module. In drive-enhanced OR gate module 1, "1" represents the first input terminal, and "2" represents the second input terminal; the same applies to drive-enhanced OR gate module 2. V2 represents either the output or input terminal of inverter module 1, VL represents either the second input terminal of drive-enhanced OR gate module 1 or the output terminal of drive-enhanced OR gate module 2, and VH represents the output terminal of drive-enhanced OR gate module 1.
[0020] It should be noted that low-voltage gallium nitride devices refer to power devices with a withstand voltage of less than 30V, generally referring to power devices with a withstand voltage of 12V.
[0021] In this invention, the form of inverter module 1 and inverter module 2 is not limited. For example, inverter module 1 and inverter module 2 can be implemented using any of the following logics: RTL logic, bootstrap capacitor driven logic, and complementary logic.
[0022] In this invention, both the drive-enhanced OR gate module 1 and the drive-enhanced OR gate module 2 adopt the bootstrap capacitor drive mode, and both the inverter module 1 and the inverter module 2 adopt the bootstrap capacitor drive mode.
[0023] For example, the drive-enhanced OR gate module 1 includes: HEMT device Q3_H, HEMT device Q4_H, HEMT device Q5_H, HEMT device Q6_H, HEMT device Q7_H, HEMT device Q8, HEMT device M1_H, HEMT device M2_H, capacitor C1, capacitor C2_H, capacitor C3_H, and resistor R1_H; the drive-enhanced OR gate module 2 includes: HEMT device Q3_L, HEMT device Q4_L, HEMT device Q5_L, HEMT device Q6_L, HEMT device Q7_L, HEMT device M1_L, HEMT device M2_L, capacitor C2_L, capacitor C3_L, and resistor R1_L. Q3_H, Q4_H, Q5_H, Q6_H, Q7_H, Q8, M1_H, M2_H, Q3_L, Q4_L, Q5_L, Q6_L, Q7_L, M1_L, and M2_L are all low-voltage HEMT devices. It should be noted that low-voltage HEMT devices refer to enhancement-mode (E-mode) GaN HEMT power devices used in low-voltage, high-power-density applications, with drain-source breakdown voltages typically between 12-30V.
[0024] For example, Figure 2 This is a schematic diagram of a circuit structure of a low-latency, high-reliability enhanced gallium nitride monolithic integrated driver circuit provided by the present invention. Figure 2 The diagram illustrates the internal circuit structures of drive-enhanced OR gate module 1 and drive-enhanced OR gate module 2, as well as their connections to inverter module 1, inverter module 2, Q1, and Q2. For example... Figure 2As shown, the gate of Q5_H is connected to the gate of Q4_H and one end of C3_H to serve as the first input terminal of the first driver enhancement OR gate module; the gate of M1_H is connected to the gate of M2_H to serve as the second input terminal of the first driver enhancement OR gate module; the source of Q3_H is connected to the drain of Q4_H, one end of C2_H and the drain of M2_H to serve as the output terminal of the first driver enhancement OR gate module. The other end of C3_H is connected to the drain of Q6_H, the gate of Q7_H, and the gate of Q8; the source of Q6_H is connected to the gate of Q6_H, the source of Q7_H, and the source of Q8, all of which are connected to the external power supply VCC; the drain of Q7_H is connected to the other end of C2_H and one end of R1_H; the other end of R1_H is connected to the drain of Q5_H, the drain of M1_H, and the gate of Q3_H; the sources of Q5_H, Q4_H, M1_H, and M2_H are all connected to GND; the drain of Q3_H is connected to the drain of Q8 and one end of C1; the other end of C1 is connected to the source of the first low-voltage gallium nitride device Q1. The gate of Q5_L is connected to the gate of Q4_L and one end of C3_L to serve as the first input terminal of the second drive enhancement OR gate module; the gate of M1_L is connected to the gate of M2_L to serve as the second input terminal of the second drive enhancement OR gate module; the source of Q3_L is connected to the drain of Q4_L, one end of C2_L and the drain of M2_L to serve as the output terminal of the second drive enhancement OR gate module. The other end of C3_L is connected to the drain of Q6_L, the gate of Q7_L, and the gate of Q8; the source of Q6_L is connected to the gate of Q6_L, the source of Q7_L, and the drain of Q3_L, all of which are connected to the external power supply VCC; the drain of Q7_L is connected to the other end of C2_L and one end of R1_L; the other end of R1_L is connected to the drain of Q5_L, the drain of M1_L, and the gate of Q3_L; the source of Q5_L, the source of Q4_L, the source of M1_L, and the source of M2_L are all connected to GND.
[0025] For example, both inverter module 1 and inverter module 2 include: HEMT device Q9, HEMT device Q10, HEMT device Q11, HEMT device Q12, capacitor C4, and resistor R2; Q9, Q10, Q11, and Q12 are all low-voltage HEMT devices. The gate of Q10 is connected to the gate of Q11 and serves as the input terminal of inverter module 1 / inverter module 2; one end of C4 is connected to the source of Q9 and the drain of Q10 and serves as the output terminal of inverter module 1 / inverter module 2; the sources of Q10 and Q11 are both connected to GND; the drain of Q10 is connected to one end of R2 and the gate of Q9; the other end of R2 is connected to the other end of C4 and the source of Q12; the gate and drain of Q12 and the drain of Q9 are both connected to the external power supply VCC. For example, Figure 3This is another circuit structure diagram of the low-latency, high-reliability enhanced gallium nitride monolithic integrated driver circuit provided by the present invention. Figure 3 exist Figure 2 Based on this, the internal circuit structures of inverter module 1 and inverter module 2, as well as their connections with other circuit components, are shown. For example... Figure 3 As shown, inverter module 1 includes: HEMT device Q9_H, HEMT device Q10_H, HEMT device Q11_H, HEMT device Q12_H, capacitor C4_H, and resistor R2_H; while inverter module 2 includes: HEMT device Q9_L, HEMT device Q10_L, HEMT device Q11_L, HEMT device Q12_L, capacitor C4_L, and resistor R2_L. The specific connection relationships between them are as follows... Figure 3 As shown.
[0026] It should be noted that the drive output port Vout of the drive circuit proposed in this invention is used to connect to the gate of a high-voltage gallium nitride power transistor using the same process as the drive circuit, so as to drive the high-voltage gallium nitride power transistor.
[0027] This invention is applicable to the same fields as GaN power devices, targeting industrial and automotive applications in the 200-800 V range, such as server power supplies, solar and battery power inverters, industrial automation and on-board charging for electric vehicles, as well as higher voltage / power applications.
[0028] The following circuit simulation is used to verify the technical effects of the driving circuit proposed in this invention.
[0029] The simulation example uses a p-GaN gate-enhanced low-voltage HEMT with the following parameters: gate-drain length Lgd = 1.5µm, gate length lg = 2µm, gate-source length lgs = 0.75µm, and threshold voltage Vth = 1.8V. The width of Q1 is 2.2mm, and the width of Q2 is 3mm. The parameters of the driving power transistor are: gate-drain length Lgd = 6µm, gate length lg = 2µm, gate-source length lgs = 0.75µm, threshold voltage Vth = 1.8V, and width is 70mm. The remaining low-voltage GaN HEMTs use the optimal width.
[0030] When the input signal Vin changes, the signals output at each terminal change accordingly, as follows: Figure 4 As shown. Figure 5 , Figure 6 The figures shown are simulation diagrams verifying the short-circuit reliability of Q1 and Q2 in the driving circuit proposed in this invention. Figure 7 , Figure 8 These are simulation diagrams of the propagation delay of the driving circuit proposed in this invention.
[0031] refer to Figure 4 When the signal at the Vin terminal changes from 0 to 1, the signals at the V2 and VL terminals change from VCC to GND. Since the high level at the VH terminal is controlled by the signal at the VL terminal, the VH terminal will only present a high level when the voltage of the signal at the VL terminal is lower than the threshold voltage Vth of the gallium nitride HEMT, and the Vout terminal will then output VCC. Figure 5 As shown, VGS1 is the difference between the signals output from the VH terminal and the Vout terminal. In the example waveform, when the threshold voltage of the gallium nitride device is 1.8V, the crossover point of the signal waveforms at the VGS1 and VL terminals is about 0.3V. At this time, both Q1 and Q2 are in the off state and no short circuit will occur.
[0032] Continue to refer to Figure 4 When the signal at Vin changes from 1 to 0, the signal at VL remains unchanged, and the signal at V2 changes from GND to VCC. When the signal at V2 exceeds the threshold voltage Vth of the low-voltage gallium nitride device, the signal at VH changes from VCC to GND. Simultaneously, inverter module 2 outputs a low level, which is then passed through drive enhancement OR gate module 2. The signal at VL changes from GND to a high level VCC, and the signal at Vout changes from VCC to GND. Figure 6 As shown, VGS1 is the difference between the signal at the VH terminal and the signal at the Vout terminal. The crossover point of the signal waveforms at the VGS1 and VL terminals is less than 0V. At this time, both Q1 and Q2 are in the off state, and the drive output will not be short-circuited.
[0033] refer to Figure 7 , 8 The high-level propagation delay is about 5.94ns, and the low-level propagation delay is about 5.96ns, which is obviously much lower than the short-circuit withstand time of gallium nitride devices.
[0034] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.
[0035] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0036] In this specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple instances. While different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce a good effect.
[0037] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A low-latency, high-reliability, enhanced gallium nitride monolithic integrated driver circuit, characterized in that, include: The system comprises a first inverter module, a second inverter module, a first drive-enhanced OR gate module, a second drive-enhanced OR gate module, a first low-voltage gallium nitride device Q1, and a second low-voltage gallium nitride device Q2. In this configuration, the output of the first inverter module is connected to the first input of the first drive-enhanced OR gate module and the input of the second inverter module. The input of the first inverter module is connected to the second input of the second drive-enhanced OR gate module and serves as the drive signal input port Vin. The output of the first drive-enhanced OR gate module is connected to the gate of the first low-voltage gallium nitride device Q1. The output of the second inverter module is connected to the first input of the second drive-enhanced OR gate module and the output of the second drive-enhanced OR gate module is connected to the second input of the first drive-enhanced OR gate module and the gate of the second low-voltage gallium nitride device Q2. The source of the first low-voltage gallium nitride device Q1 and the drain of the second low-voltage gallium nitride device Q2 are connected to serve as the drive output port Vout. The drain of the first low-voltage gallium nitride device Q1 is connected to the external power supply VCC, and the source of the second low-voltage gallium nitride device Q2 is connected to GND.
2. The low-latency, high-reliability enhanced gallium nitride monolithic integrated driver circuit according to claim 1, characterized in that, Both the first driver-enhanced OR gate module and the second driver-enhanced OR gate module adopt the bootstrap capacitor drive mode.
3. The low-latency, high-reliability enhanced gallium nitride monolithic integrated driver circuit according to claim 1, characterized in that, Both the first inverter module and the second inverter module adopt the bootstrap capacitor drive mode.
4. The low-latency, high-reliability enhanced gallium nitride monolithic integrated driver circuit according to claim 2, characterized in that, The first drive enhancement OR gate module includes: HEMT device Q3_H, HEMT device Q4_H, HEMT device Q5_H, HEMT device Q6_H, HEMT device Q7_H, HEMT device Q8, HEMT device M1_H, HEMT device M2_H, capacitor C1, capacitor C2_H, capacitor C3_H, and resistor R1_H; Specifically, the gate of Q5_H is connected to the gate of Q4_H and one end of C3_H to serve as the first input terminal of the first drive enhancement OR gate module; the gate of M1_H is connected to the gate of M2_H to serve as the second input terminal of the first drive enhancement OR gate module; the source of Q3_H is connected to the drain of Q4_H, one end of C2_H and the drain of M2_H to serve as the output terminal of the first drive enhancement OR gate module. The other end of C3_H is connected to the drain of Q6_H, the gate of Q7_H, and the gate of Q8; the source of Q6_H is connected to the gate of Q6_H, the source of Q7_H, and the source of Q8, all of which are connected to the external power supply VCC; the drain of Q7_H is connected to the other end of C2_H and one end of R1_H; the other end of R1_H is connected to the drain of Q5_H, the drain of M1_H, and the gate of Q3_H; the sources of Q5_H, Q4_H, M1_H, and M2_H are all connected to GND; the drain of Q3_H is connected to the drain of Q8 and one end of C1; the other end of C1 is connected to the source of the first low-voltage gallium nitride device Q1.
5. The low-latency, high-reliability enhanced gallium nitride monolithic integrated driver circuit according to claim 4, characterized in that, The second drive-enhanced OR gate module includes: HEMT device Q3_L, HEMT device Q4_L, HEMT device Q5_L, HEMT device Q6_L, HEMT device Q7_L, HEMT device M1_L, HEMT device M2_L, capacitor C2_L, capacitor C3_L, and resistor R1_L; In this configuration, the gate of Q5_L is connected to the gate of Q4_L and one end of C3_L, serving as the first input terminal of the second drive enhancement OR gate module; the gate of M1_L is connected to the gate of M2_L, serving as the second input terminal of the second drive enhancement OR gate module; and the source of Q3_L is connected to the drain of Q4_L, one end of C2_L, and the drain of M2_L, serving as the output terminal of the second drive enhancement OR gate module. The other end of C3_L is connected to the drain of Q6_L, the gate of Q7_L, and the gate of Q8; the source of Q6_L is connected to the gate of Q6_L, the source of Q7_L, and the drain of Q3_L, all of which are connected to the external power supply VCC; the drain of Q7_L is connected to the other end of C2_L and one end of R1_L; the other end of R1_L is connected to the drain of Q5_L, the drain of M1_L, and the gate of Q3_L; the source of Q5_L, the source of Q4_L, the source of M1_L, and the source of M2_L are all connected to GND.
6. The low-latency, high-reliability enhanced gallium nitride monolithic integrated driver circuit according to claim 5, characterized in that, Q3_H, Q4_H, Q5_H, Q6_H, Q7_H, Q8, M1_H, M2_H, Q3_L, Q4_L, Q5_L, Q6_L, Q7_L, M1_L, and M2_L are all low-voltage HEMT devices.
7. The low-latency, high-reliability enhanced gallium nitride monolithic integrated driver circuit according to claim 3, characterized in that, The first inverter module / second inverter module includes: HEMT device Q9, HEMT device Q10, HEMT device Q11, HEMT device Q12, capacitor C4, and resistor R2; Wherein, the gate of Q10 is connected to the gate of Q11 and serves as the input terminal of the first inverter module / the second inverter module; one end of C4 is connected to the source of Q9 and the drain of Q10 and serves as the output terminal of the first inverter module / the second inverter module. The sources of Q10 and Q11 are both connected to GND; the drain of Q10 is connected to one end of R2 and the gate of Q9; the other end of R2 is connected to the other end of C4 and the source of Q12; the gate and drain of Q12 and the drain of Q9 are both connected to the external power supply VCC.
8. The low-latency, high-reliability enhanced gallium nitride monolithic integrated driver circuit according to claim 7, characterized in that, Q9, Q10, Q11, and Q12 are all low-voltage HEMT devices.