High electron mobility transistor device and manufacturing method thereof
By using a three-mask process to form a high electron mobility transistor device, the problem of interlayer alignment misalignment was solved, enabling a low-cost, high-yield miniaturized design, optimizing the electric field distribution, and improving the breakdown voltage and reliability of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HIPER SEMICONDUCTOR INC
- Filing Date
- 2026-02-12
- Publication Date
- 2026-05-08
AI Technical Summary
Existing technologies in high electron mobility transistor devices suffer from interlayer alignment misalignment due to multiple exposures, which increases process costs and affects product yield, and makes it difficult to meet the requirements of miniaturized design.
The drain, first source field plate, and second source field plate are formed using a three-mask process. By adjusting the dielectric layer thickness and the mask design, the interlayer alignment accuracy is ensured, and the electric field concentration is alleviated by the progressive morphology, reducing the area occupied by the active region.
It simplifies the number of photomasks used, reduces production costs, improves product yield, optimizes electric field distribution, enhances breakdown voltage and reliability, and is suitable for miniaturized designs.
Smart Images
Figure CN122002846A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a high electron mobility transistor device and a method for manufacturing the same, and particularly to a high electron mobility transistor device and a method for manufacturing the same, which is formed together with a first source field plate of source / drain metal (SD Metal) layer. Background Technology
[0002] As the size of gallium nitride (GaN) power devices continues to shrink in pursuit of lower on-resistance (Rsp), multilayer source field plates (SFPs) and source / drain electrodes have become the mainstream structure within a limited gate-to-drain distance (Lgd). However, existing technologies for defining second-order source field plate structures require two exposures using different photomasks. This method has the following technical bottlenecks: First, limited by the resolution limits of the exposure equipment, it is difficult to meet the miniaturization design requirements of shortening the Lgd; second, repeated exposures not only increase process costs, but the risk of interlayer misalignment directly affects product yield. Therefore, it is necessary to simplify the process and improve alignment accuracy. Summary of the Invention
[0003] The main objective of this invention is to provide a high electron mobility transistor device and its manufacturing method, so as to reduce the number of photomasks used and thus reduce production costs.
[0004] Another major objective of this invention is to provide a high electron mobility transistor device and a method for manufacturing the same, in order to improve interlayer alignment misalignment and thus significantly improve product yield.
[0005] Another major objective of this invention is to provide a high electron mobility transistor device and a method for manufacturing the same, so as to reduce on-resistance.
[0006] To achieve the above objectives, the high electron mobility transistor device of the present invention includes a channel layer, a barrier layer, a gate structure, a dielectric layer, a drain, a first source field plate, and a second source field plate. The barrier layer is disposed on the channel layer. The gate structure is disposed on the barrier layer. The dielectric layer is disposed on the barrier layer. The drain is formed by etching a source / drain metal layer. The first source field plate is disposed on the dielectric layer and located between the gate structure and the drain, wherein the first source field plate is formed by etching a source / drain metal layer. The second source field plate is disposed on the dielectric layer, and a portion of the second source field plate covers a portion of the first source field plate.
[0007] According to an embodiment of the present invention, the dielectric layer covered by the second source field plate has a first thickness, the dielectric layer covered by the first source field plate has a second thickness, and the first thickness is less than the second thickness.
[0008] According to an embodiment of the present invention, a portion of the second source field plate is located between the gate structure and the first source field plate.
[0009] According to an embodiment of the present invention, the second source field plate is a titanium nitride (TiN) layer and the dielectric layer is a silicon nitride (SiN) layer.
[0010] The present invention also provides a method for manufacturing a high electron mobility transistor device, comprising the following steps: forming a barrier layer on a channel layer; forming a dielectric layer on the barrier layer; defining and etching the dielectric layer using a first photomask to form a drain recess; forming a source / drain metal layer on the dielectric layer, wherein the source / drain metal layer fills the drain recess; defining and etching the source / drain metal layer using a second photomask to form a drain and a first source field plate, wherein the first source field plate is located between the drain and the gate structure; forming a second source field plate metal layer, wherein the second source field plate metal layer is disposed on the dielectric layer, the drain, and the first source field plate; and defining and etching the second source field plate metal layer using a third photomask to form a second source field plate, wherein a portion of the second source field plate covers a portion of the first source field plate.
[0011] According to one embodiment of the present invention, the second photomask defines the distance between the drain and the first source field plate and the distance between the drain and the second source field plate.
[0012] According to one embodiment of the present invention, the dielectric layer covered by the second source field plate has a first thickness, and the dielectric layer covered by the first source field plate has a second thickness, wherein the first thickness is less than the second thickness.
[0013] According to one embodiment of the present invention, the second source field plate is located between the gate structure and the first source field plate.
[0014] The manufacturing method of the high electron mobility transistor device of the present invention requires only a smaller number of photomasks to form the drain, the first source field plate, and the second source field plate. This method solves the problems of misalignment and component position shift caused by multiple exposures in the prior art, ensuring that the distance between the drain and the first source field plate, as well as the distance between the drain and the second source field plate, remains constant during mass production. Furthermore, the edges of the first and second source field plates form a progressive morphology with the dielectric layer (an arc-shaped depression at the corner), which effectively alleviates the peak electric field within the high electron mobility transistor device. Moreover, the first and second source field plates are directly electrically connected during the fabrication process, eliminating the need for separate vias, thereby reducing the area occupied by the active area and facilitating miniaturization design. Attached Figure Description
[0015] Figure 1This is a flowchart illustrating the steps of an embodiment of the manufacturing method of the high electron mobility transistor device of the present invention.
[0016] Figures 2A to 2F This is a schematic diagram of an embodiment of the high electron mobility transistor manufacturing method of the present invention.
[0017] Figure 3 This is a cross-sectional schematic diagram of an embodiment of the high electron mobility transistor device of the present invention.
[0018] Figure 4 This is a schematic diagram of the electric field of an embodiment of the high electron mobility transistor device of the present invention.
[0019] Among them, the attached reference numerals
[0020] High electron mobility transistor device 1 Channel layer 10
[0021] Barrier layer 20 Gate structure 30
[0022] Gate metal 32, dielectric layer 40
[0023] Drain 50, first source field plate 60
[0024] Second source field plate 70 First photomask 81
[0025] Second light shield 82 Third light shield 83
[0026] Source / drain metal layer 91 Second source field plate metal 92
[0027] First thickness h1 Second thickness h2
[0028] Drain recess 51 First length L1
[0029] Second length L2 Two-dimensional electron gas (2DEG) 21
[0030] p-type doped gallium nitride at 31A Detailed Implementation
[0031] To better understand the technical content of this invention, preferred embodiments are described below. Please refer to the following description as well. Figure 1 , Figures 2A to 2F , Figure 3 and Figure 4 A flowchart and schematic diagram of an embodiment of the manufacturing method of the high electron mobility transistor device of the present invention, and a cross-sectional schematic diagram of an embodiment of the high electron mobility transistor device of the present invention.
[0032] like Figure 1As shown, the manufacturing method of the high electron mobility transistor device of the present invention includes steps S1 to S7. The following describes each step of the manufacturing method of the high electron mobility transistor device of the present invention.
[0033] Step S1: Form a barrier layer on the channel layer. In one embodiment of the present invention, the channel layer is formed sequentially on the buffer layer, the nucleation layer and the substrate; since the growth process from the substrate to the channel layer is prior art in the art, it will not be described in detail here.
[0034] like Figure 2A As shown, a barrier layer 20 is formed on the channel layer 10, and a gate structure 30 is formed on the barrier layer 20. A two-dimensional electron gas (2DEG) 21 exists at the interface between the barrier layer 20 and the channel layer 10. In this embodiment, the gate structure 30 includes a p-type doped gallium nitride (pGaN) 31 and a gate metal 32, wherein the gate metal 32 is titanium nitride (TiN), thereby ultimately forming an enhancement-mode high electron mobility transistor device. However, this invention is not limited to this; the gate structure 30 disclosed in this invention can also ultimately form a depletion-mode high electron mobility transistor device. Furthermore, forming the gate structure 30 on the barrier layer 20 is prior art, and this step is not the focus of this invention's improvement; therefore, its details will not be elaborated here.
[0035] Step S2: Form a dielectric layer on the barrier layer.
[0036] like Figure 2A As shown, a dielectric layer 40 is deposited on the barrier layer 20, wherein the dielectric layer 40 is a silicon nitride (SiN) layer, and in this embodiment, the dielectric layer 40 also covers the gate structure 30.
[0037] Step S3: Define and etch the dielectric layer using the first photomask to form a drain recess.
[0038] like Figure 2B As shown, in one embodiment of the present invention, the location of the drain recess 51 is defined on the dielectric layer 40 by a first photomask 81, meaning that the location of the drain recess 51 is not hidden (or covered) by the first photomask 81. Subsequently, the dielectric layer 40 not hidden by the first photomask 81 is etched to form the drain recess 51. In other embodiments, the drain recess 51 may be recessed into the barrier layer 20 or the channel layer 10. This design is not the focus of the improvement of the present invention, so its details will not be described here.
[0039] Step S4: Form source / drain metal layers on the dielectric layer, and fill the drain depression with the source / drain metal layers.
[0040] like Figure 2CAs shown, a source / drain metal layer 91 is deposited on the dielectric layer 40, and this source / drain metal layer 91 fills the drain recess 51. In this embodiment, the source / drain metal layer 91 is an aluminum copper oxide (AlCu) alloy layer. It should be noted that the formation of the source is a prior art and the source side is not the focus of this improvement; therefore, the source is not shown in the accompanying drawings, nor is its formation process described in detail.
[0041] Step S5: Define and etch the source / drain metal layers using the second photomask to form the drain and the first source field plate, wherein the first source field plate is located between the drain and the gate structure.
[0042] like Figure 2D As shown, the location of the drain 50 and the first source field plate 60 is defined on the source / drain metal layer 91 by the second photomask 82. That is, the area on the source / drain metal layer 91 that is covered by the second photomask 82 is the location of the drain 50 and the first source field plate 60. This step can determine the distance between the drain 50 and the first source field plate 60. Then, the source / drain metal layer 91 that is not covered by the second photomask 82 is etched to form the drain 50 and the first source field plate 60.
[0043] Specifically, such as Figure 2D As shown, the distance from the end of the first source field plate 60 adjacent to the drain 50 to the drain 50 is defined as the first length L1; the distance from the end of the first source field plate 60 away from the drain 50 to the drain 50 is defined as the second length L2. It is worth noting that L1 and L2 are established simultaneously in the same process step of patterning the source / drain metal layer 91 using the second photomask 82 to form the drain 50 and the first source field plate 60. This avoids misalignment caused by multiple photolithography processes. The process method of this invention ensures that the electric field distribution and device specifications of mass-produced high electron mobility transistors precisely match the original design, effectively solving the problem of inconsistent device electrical properties caused by interlayer misalignment in the prior art.
[0044] Step S6: Form a second source field plate metal layer, wherein the second source field plate metal layer is disposed on the dielectric layer, the drain and the first source field plate.
[0045] like Figure 2E As shown, a second source field plate metal layer 92 is deposited on the dielectric layer 40, the drain electrode 50 and the first source field plate 60, wherein the second source field plate metal layer 92 is a titanium nitride (TiN) layer.
[0046] Step S7: Define and etch the metal layer of the second source field plate using the third photomask to form the second source field plate, wherein a portion of the second source field plate covers a portion of the first source field plate.
[0047] like Figure 2FAs shown, the location of the second source field plate 70 is defined on the second source field plate metal layer 92 by the third photomask 83, meaning that the location of the second source field plate 70 is shielded (or covered) by the third photomask 83. Subsequently, the second source field plate metal layer 92, which is not shielded by the third photomask 83, is etched to form the second source field plate 70. In this embodiment, the second source field plate 70 is located between the gate structure 30 and the first source field plate 60. Furthermore, the dielectric layer 40 covered by the second source field plate 70 has a first thickness h1, and the dielectric layer 40 covered by the first source field plate 60 has a second thickness h2, wherein the first thickness h1 is smaller than the second thickness h2. After removing the third photomask 83, the following structure is formed: Figure 3 The high electron mobility transistor device 1 of the present invention is shown. By adjusting the thickness configuration of the dielectric layer 40 covering the first source field plate 60 and the dielectric layer 40 covering the second source field plate 70, the electric field below the first source field plate 60 can be effectively dispersed to the area below the second source field plate 70 with a greater intensity than the electric field intensity below the second source field plate 70, thereby optimizing the electric field gradient distribution between the gate 30 and the drain 50.
[0048] Referring to the electric field intensity distribution diagram in Figure 4, when the first thickness h1 is equal to the second thickness h2, the electric field distribution is uneven, and a significant electric field peak is formed on the lower right side of the first source field plate 60. In contrast, the high electron mobility transistor (HEMT) device 1 of the present invention, by utilizing the structural feature that the first thickness h1 is smaller than the second thickness h2, forms two smaller electric field peaks on the lower right side of the first source field plate 60 and the second source field plate 70, respectively; thereby dispersing the electric field concentration effect, optimizing the overall electric field gradient distribution, and improving the breakdown voltage and reliability of the device.
[0049] In addition, such as Figure 2F and Figure 3As shown, the second source field plate 70 of the high electron mobility transistor device 1 of the present invention is etched from the second source field plate metal layer 92. The second source field plate 70 is directly electrically connected to the first source field plate 60. Therefore, the second source field plate 70 and the first source field plate 60 do not need to be connected by additional vias during layout. This reduces the active region area of the high electron mobility transistor of the present invention, which is beneficial for miniaturization design and reduces the on-resistance of the high electron mobility transistor. The manufacturing method of the high electron mobility transistor device of the present invention defines the drain 50, the first source field plate 60, and the second source field plate 70 through a simplified photomask process (first photomask 81, second photomask 82, and third photomask 83). In detail, the edge of the first source field plate 60 near the drain and the edge of the drain 50 near the source are defined by the same pattern boundary of the second photomask 82.
[0050] Specifically, the relative positions of the first distance L1 and the second distance L2 are fixed during the design phase of the second photomask 82. During subsequent exposure, regardless of the degree of displacement of the photomask relative to the wafer, the relative displacement deviation between the first distance L1 and the second distance L2 remains constant at zero. This eliminates the interference of inter-layer misalignment on the field plate spacing, ensuring that the size of the electric field control region is highly consistent with the original design value, significantly improving the breakdown voltage stability of the components and mass production yield.
[0051] Furthermore, the manufacturing method of the present invention ensures that the first source field plate 60 and the second source field plate 70 are covered on the dielectric layer 40 in a stepped sequence. When the second source field plate 70 is superimposed on the sidewall edge of the first source field plate 60, the etching characteristics produce a progressive pattern, which naturally forms an arc-shaped recessed structure with a specific curvature at the junction (as shown in region A of Figure 3). This non-orthogonal transition junction interface can effectively eliminate the tip discharge effect generated by the sharp edge, disperse and alleviate the strong electric field concentration phenomenon at the drain 50, thereby optimizing the overall electric field gradient and improving the device's breakdown voltage.
[0052] Please continue to refer to the following. Figure 3 ,like Figure 3As shown, the high electron mobility transistor device 1 of the present invention includes a channel layer 10, a barrier layer 20, a gate structure 30, a dielectric layer 40, a drain 50, a first source field plate 60, and a second source field plate 70. The barrier layer 20 is disposed on the channel layer 10, the gate structure 30 is disposed on the barrier layer 20, and a two-dimensional electron gas (2DEG) 21 exists at the interface between the barrier layer 20 and the channel layer 10. The dielectric layer 40 is disposed on the barrier layer 20. The drain 50 is recessed into the dielectric layer 40 and located on the barrier layer 20. The first source field plate 60 is disposed on the dielectric layer 40 and located between the gate structure 30 and the drain 50. Both the drain 50 and the first source field plate 60 are etched from source / drain metal layers. The second source field plate 70 is disposed on the dielectric layer 40, and a portion of the second source field plate 70 covers a portion of the first source field plate 60. In this embodiment, the second source field plate 70 is a titanium nitride (TiN) layer, and the dielectric layer 40 is a silicon nitride (SiN) layer. The dielectric layer 40 covered by the second source field plate 70 has a first thickness h1, and the dielectric layer 40 covered by the first source field plate 60 has a second thickness h2, wherein the first thickness h1 is less than the second thickness h2. A portion of the second source field plate 70 is located between the gate structure 30 and the first source field plate 60. In this embodiment, the gate structure 30 includes a p-type doped gallium nitride (pGaN) 31 and a gate metal 32, wherein the gate metal 32 is titanium nitride (TiN), thereby ultimately forming an enhancement-mode (E-mode) high electron mobility transistor device. However, the present invention is not limited thereto, and the gate structure 30 disclosed in the present invention can also ultimately form a depletion-mode high electron mobility transistor device. It should be noted that the drain 50 is recessed into the dielectric layer 40 and located outside the barrier layer 20. In other embodiments, the drain 50 may also be recessed into the dielectric layer 40 and located on the channel layer 10. Furthermore, the source of the high electron mobility transistor device 1 of the present invention is prior art, and the source side is not the focus of this improvement. Figure 3 The source pole was not plotted.
[0053] The high electron mobility transistor device 1 of the present invention, by having both the drain 50 and the first source field plate 60 etched from the same source / drain metal layer 91, ensures that the relative distance (i.e., the source field plate distance) between the drain 50 and the first source field plate 60 is fixed in each process, thus ensuring that the specifications of the actual manufactured product remain highly consistent with the original design. Furthermore, the manufacturing method of the present invention also ensures that a stepped profile or inclined sidewall (e.g., a corner) is formed at the junction of the first source field plate 60 and the second source field plate 70 with the dielectric layer 40. This structure helps to smooth the electric field transition inside the high electron mobility transistor device 1 and avoid electric field concentration.
[0054] It should be noted that the above embodiments are merely examples for illustrative purposes, and the scope of the claims of this invention should be determined by the scope of the claims, and not limited to the above embodiments.
Claims
1. A high electron mobility transistor device, characterized in that, include: One channel layer; A barrier layer is provided on top of the channel layer; A gate structure is disposed on the barrier layer; A dielectric layer is disposed on the barrier layer; A drain electrode is formed by etching a source / drain metal layer; A first source field plate is disposed on the dielectric layer and located between the gate structure and the drain, wherein the first source field plate is etched from the source / drain metal layer; as well as A second source field plate is disposed on the dielectric layer and partially covers a portion of the first source field plate.
2. The high electron mobility transistor device as claimed in claim 1, characterized in that, The dielectric layer covered by the second source field plate has a first thickness, and the dielectric layer covered by the first source field plate has a second thickness, wherein the first thickness is less than the second thickness.
3. The high electron mobility transistor device as claimed in claim 1, characterized in that, Part of the second source field plate is located between the gate structure and the first source field plate.
4. The high electron mobility transistor device as claimed in claim 1, characterized in that, The second source field plate is a titanium nitride layer, and the dielectric layer is a silicon nitride layer.
5. A method for manufacturing a high electron mobility transistor device, characterized in that, Includes the following steps: A barrier layer is formed on a channel layer; A dielectric layer is formed on the barrier layer; A first photomask is used to define and etch the dielectric layer to form a drain recess; A source / drain metal layer is formed on the dielectric layer, and the source / drain metal layer fills the drain recess; A drain and a first source field plate are formed by defining and etching the source / drain metal layer using a second photomask, wherein the first source field plate is located between the drain and the gate structure. A second source field plate metal layer is formed, wherein the second source field plate metal layer is disposed on the dielectric layer, the drain and the first source field plate; as well as A second source field plate is formed by defining and etching the metal layer of the second source field plate using a third photomask, wherein a portion of the second source field plate covers a portion of the first source field plate.
6. The manufacturing method as described in claim 5, characterized in that, The second photomask defines the distance between the drain and the first source field plate, and also defines the distance between the drain and the second source field plate.
7. The manufacturing method as described in claim 5, characterized in that, The dielectric layer covered by the second source field plate has a first thickness, and the dielectric layer covered by the first source field plate has a second thickness, wherein the first thickness is less than the second thickness.
8. The manufacturing method as described in claim 5, characterized in that, The second source field plate is located between the gate structure and the first source field plate.