Error detection during iterative decoding

Abstract

A system and associated method comprising a memory and a processing circuit for receiving data and corresponding expected error detection sign values. The processing circuit processes the data in at least two parts by calculating an error detection sign value for each part and storing it in memory. The processing circuit then calculates an overall error detection sign value based on the respective error detection sign values ​​for the at least two parts. If the overall error detection sign value does not match the expected error detection sign value, the processing circuit processes the corrected parts by correcting at least one part, calculating an updated error detection sign value for each of the corrected parts, and calculating an updated overall error detection sign value based on the updated error detection sign values ​​for each corrected part and the stored error detection sign values.

Description

Technical Field

[0001] The present disclosure is directed to systems and methods for processing error detection codes (e.g., cyclic redundancy check (CRC) checksums) by repeatedly updating or modifying portions of a data codeword.

Summary of the Invention

[0002] According to the present disclosure, in a system such as a storage device (e.g., a solid state drive device), systems and methods for processing error detection code checksums such as cyclic redundancy check (CRC) are provided by repeatedly updating portions of a data codeword. Cyclic redundancy check (CRC) is a linear error detection code that verifies the value of data by expanding the data with additional data without adding useful data information. The systems and methods disclosed herein enable the use of memory and repeated updating or modification of data portions to reduce the latency and amount of power consumption for processing error detection code checksums.

[0003] In some embodiments, a system (e.g., a storage device) is provided having memory and processing circuits that are communicatively coupled to one another. In some embodiments, the system can be distributed between the storage device and another device separate from the storage device (e.g., a host device such as a storage controller device), where the host device provides processing circuits for implementing, for example, at least some of the functions described herein. In some embodiments, the processing circuit receives data and an expected error detection code value corresponding to the data. The processing circuit processes the data in at least two parts by calculating an error detection code value for each part and storing the error detection code value for each part in memory. The processing circuit further calculates an overall error detection code value based on the respective error detection code values ​​for each part and compares the overall error detection code value with an expected error detection code value. In some embodiments, if the overall error detection code value does not match the expected error detection code value, the processing circuit corrects at least one of the parts of the data to generate at least two corrected parts. The processing circuit further processes at least two corrected portions of the data by calculating an updated error detection sign value for each corrected portion and then calculating an updated overall error detection sign value based on the updated error detection sign values ​​for each corrected portion and the stored error detection sign value. In some embodiments, the updated overall error detection sign value does not match the expected error detection sign value, and therefore the processing circuit is configured to correct at least one portion of the data and recalculate the updated overall error detection sign value until the updated overall error detection sign value matches the expected error detection sign value. [Brief explanation of the drawing]

[0004] The following description includes discussion of the figures, which have examples given as implementations of embodiments of the embodiments of this disclosure. The drawings should be understood as examples, not limitations. Where used herein, references to one or more “embodiments” should be understood to describe specific features, structures, and / or characteristics contained in at least one implementation. Thus, phrases such as “in one embodiment” or “in an alternative embodiment” appearing herein describe various embodiments and implementations, and not all necessarily refer to the same embodiment. However, these are not necessarily mutually exclusive.

[0005] [Figure 1] The diagrams below illustrate exemplary systems of storage devices having processing circuits and memory according to some embodiments of the present disclosure.

[0006] [Figure 2] This disclosure illustrates the exemplary progress of a CRC checksum process for data divided into four parts, according to several embodiments of this disclosure.

[0007] [Figure 3] The flowcharts illustrate exemplary steps for processing a CRC checksum by iteratively updating a portion of a data codeword, according to some embodiments of the present disclosure.

[0008] [Figure 4] The flowchart shows exemplary steps for processing data from at least two portions of the data shown in Figure 3, by calculating and storing error detection sign values ​​for each portion of the data according to some embodiments of the present disclosure.

[0009] [Figure 5] The flowchart shows exemplary steps for processing data from at least two parts of the data shown in Figure 3, by determining and storing the error detection code state corresponding to each part of the data, according to some embodiments of the present disclosure.

[0010] [Figure 6] Figure 3 shows an exemplary flowchart of steps for modifying at least one of at least two portions of data to generate at least two modified portions, according to some embodiments of the present disclosure.

[0011] [Figure 7] The flowchart shows exemplary steps for correcting at least one of the at least two portions of data shown in Figure 3, for setting the error detection code state corresponding to each of the at least two corrected portions to the correct error detection code state according to some embodiments of the present disclosure.

[0012] [Figure 8] The following flowcharts illustrate exemplary steps for processing at least two modified portions of the data shown in Figure 3, according to some embodiments of the present disclosure.

[0013] [Figure 9] The flowcharts of exemplary steps for determining the rewound error detection code state of a data codeword, according to some embodiments of the present disclosure, are shown. [Figure 10] The flowcharts of exemplary steps for determining the rewound error detection code state of a data codeword, according to some embodiments of the present disclosure, are shown. [Figure 11] The flowcharts of exemplary steps for determining the rewound error detection code state of a data codeword, according to some embodiments of the present disclosure, are shown.

[0014] [Figure 12] The flowcharts below illustrate exemplary steps for updating the error detection code state of an N-bit complete codeword according to some embodiments of the present disclosure. [Modes for carrying out the invention]

[0015] This disclosure provides a system and method for iterative error-detection code value (e.g., checksum) processing of storage devices (e.g., solid-state drive (SSD) devices). In some embodiments, the error-detection code value is associated with a corresponding data codeword that is processed as a whole. By processing the entire data codeword, the error-detection code value associated with the data codeword is calculated from the beginning to the end of the data codeword. If an error is detected, the data codeword is corrected, and the entire corrected data codeword is reprocessed. Processing of the error-detection code value does not terminate until the last data bit of the corrected data codeword has been processed, which can result in longer redundant processing time and unnecessary power consumption.

[0016] If the error detection code value is a linear error detection code value (e.g., a CRC checksum), the process of correcting and calculating the updated overall error detection code value, e.g., the CRC checksum, can be completed sequentially. However, in some cases of corrupted data, there may be only one error at the beginning of the data codeword, causing the processing circuit to unnecessarily continue performing CRC checksum calculations for the rest of the data codeword.

[0017] This process of correcting and calculating the updated overall error detection sign value may also be performed iteratively, where the data codeword is divided into at least two parts. The system's processing circuitry may process each part and store the error detection sign value for each part in memory. Thus, when a corrupted or erroneous part of the data is corrected, the processing circuitry determines the updated overall error detection sign value by recalculating the error detection sign value for the corrupted part and then using the error detection sign value for each uncorrupted part stored in memory.

[0018] By repeatedly executing this process, the processing circuit can end the iteration or end the process in the middle part of the data codeword at the end of the iteration. This results in an increased possibility of reducing the number of iterations required to execute the error detection code checksum, thereby improving the throughput of the processing circuit and reducing the latency and power consumption of the system. Further, by storing the error detection code value of at least one part of the data in memory, the methods and systems disclosed herein reduce redundant and unnecessary processing performed by the processing circuit.

[0019] For the purpose of brevity and clarity, the features of the present disclosure described herein are in the context of an SSD having a processing circuit and a memory. However, the principles of the present disclosure may be applied to any other suitable context in which iterative error detection code checksum processing is used. The storage device may include a processing circuit and a memory, and the processing circuit and the memory are communicatively coupled by a network bus or an interface. In some embodiments, the processing circuit receives data, and the data may be driven from a source external to the storage device on a network bus or an interface, or may be transmitted from within the storage device (i.e., from the memory). In particular, the present disclosure provides systems and methods that utilize the temporal locality of previous computations stored in memory. Computations that recently processed the error detection code value of a portion are considered to be temporally local and can be accessed quickly to assist in the unprocessed operations of the storage device. Also, the iterative processing of the divided data reduces the overall latency and power consumption and improves throughput by enabling the storage device to end the procedure after processing several corrected data portions when processing the error detection code value.

[0020] For example, an SSD device having a processing circuit receives data that is processed in at least two parts by the processing circuit. The received data includes corresponding error detection codes and expected error detection code values, which are used by the processing circuit to verify the integrity of the received data and ensure that the received data is valid. Invalid data may cause further errors, which can affect the performance or operation of the storage device. In some cases, data may be corrupted during transmission or storage, and thus error detection codes are used to ensure that the data received by the processing circuit is the same as the data originally stored in memory or transmitted from the source. In some situations of this example, a portion of the data and a portion of the corresponding error detection code value are corrupted during data transmission. To detect this error, the processing circuit calculates the overall error detection code value and compares it with the expected error detection code value. If the two values do not match, the processing circuit determines that at least one portion of the data is corrupted and must be corrected.

[0021] In some embodiments, each portion of the data corresponds to an error detection code state, which indicates whether each portion of the data is corrupted. The error detection code state of each portion may be one of a correct error detection code state or an incorrect error detection code state. In some implementations, each error detection code state is a single bit, which reduces the amount of memory required when compared to storing an error detection code value for each portion of the data.

[0022] In some embodiments, the processor of the processing circuit can be a highly parallelized processor capable of quickly processing high-bandwidth input data (e.g., by starting simultaneous processing of data portions before the previous data portion is complete).

[0023] In some embodiments, the systems and methods of the present disclosure may refer to storage device systems (e.g., SSD storage systems) having storage devices such as solid-state drive devices that are communicably coupled to processing circuits by a network bus or interface.

[0024] An SSD is a data storage device that uses an integrated circuit assembly as memory for permanently storing data. SSDs have no moving mechanical parts, and this characteristic distinguishes them from conventional electromechanical magnetic disks such as hard disk drives (HDDs) or floppy disks, which include rotating disks and moving read / write heads. Compared to electromechanical disks, SSDs are generally more resistant to physical shocks, operate quietly, have shorter access times, and have lower latency.

[0025] Many types of SSDs use NAND-based flash memory, including types of non-volatile storage technology, to retain data without power. The Quality of Service (QoS) of an SSD can relate to predictable low latency and consistent high input / output operations per second (IOPS) while handling read / write input / output (I / O) workloads. This means that latency or the completion time of I / O commands should be within a certain range without unexpected outliers. Throughput or I / O speed may also need to be tightly controlled without causing sudden drops in performance levels.

[0026] The subject matter of this disclosure can be better understood by referring to Figures 1 to 12.

[0027] Figure 1 shows an exemplary diagram of a system 100 of a storage device 102 having a processing circuit 104 and a memory 106, according to some embodiments of the present disclosure. In some embodiments, the storage device 102 may be a solid-state storage device (e.g., a solid-state drive device). In some embodiments, the processing circuit 104 may include a processor or any suitable processing unit. In some embodiments, the memory 106 may be non-volatile memory. It is understood that embodiments of the present disclosure are not limited to SSDs. For example, in some embodiments, the storage device 102 may include a hard disk drive (HDD) device in addition to, or instead of, an SSD.

[0028] In some embodiments, the processing circuit 104 is configured to receive data 108 containing an expected error detection sign value for data integrity verification. In some embodiments, the data 108 is transmitted to the processing circuit 104 over a network bus or interface. In some embodiments, the data 108 is transmitted from an external source (e.g., a host). In some embodiments, the processing circuit 104 receives data (e.g., data 108) from both internal and external sources of the storage device 102. There may also be a temporary memory (e.g., a cache or queue) located within the processing circuit 104, which is configured to store any pending data that will be processed by the processing circuit 104.

[0029] Furthermore, the storage device 102 includes a memory 106. In some embodiments, the memory 106 includes one or more non-volatile memories such as Phase Change Memory (PCM), PCM and switch (PCMS), Ferroelectric Random Access Memory (FeRAM), or Ferroelectric Transistor Random Access Memory (FeTRAM), Magnetoresistive Random Access Memory (MRAM), Memlistor, Spin-Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM), and any other suitable non-volatile memories, or any combination thereof. In some embodiments, memory 106 includes any one or more of the following: flip-flops, register memory, volatile memory such as static random access memory (SRAM), dynamic random access memory (DRAM), and any other suitable volatile memory, or any combination thereof. In some embodiments, processing circuitry 104 is communicatively coupled to memory 106 to store and access data such as error detection sign values ​​relating to portions of processing data. In some embodiments, a data bus interface is used to carry data 108 or addresses associated with data 108. The data bus between memory 106 and processing circuitry 104 provides a network bus for reading or writing data (e.g., error detection sign values) through memory 106.In some embodiments, the processor or processing unit of the processing circuit 104 may include a hardware processor, a software processor (e.g., a processor emulated using a virtual machine), or any combination thereof. The processor, also referred to herein as the processing circuit 104, may include any suitable software, hardware, or both for controlling the memory 106 and the processing circuit 104. In some embodiments, the storage device 102 may further include a multicore processor. The memory 106 may also include hardware elements for the non-temporary storage of instructions, commands, or requests.

[0030] The processing circuit 104 is configured to iteratively process portions of the data 108, some of which may contain errors and need to be corrected. The processing circuit 104 also calculates and stores the error detection code value for each portion. Once the errors are corrected, the processing circuit 104 may calculate an updated error correction code value for the corrupted portion and reuse the stored error detection code values ​​for each uncorrupted portion to determine the updated overall error detection code value. This process, completed by the processing circuit 104, leverages the temporal locality of previously calculated error detection code values ​​for at least one portion of the data to reduce the overall latency and power consumption of the error detection code checksum process.

[0031] In some embodiments, the expected error detection code value corresponding to data 108 includes the expected linear error detection code corresponding to data 108. In some embodiments, the expected linear error detection code corresponding to data 108 includes the low-density parity-check (LDPC) code corresponding to data 108.

[0032] A storage device (e.g., an SSD device) may comprise one or more packages of non-volatile memory dies, where each die comprises a storage cell. In some embodiments, the storage cells are grouped into pages, and the pages are grouped into blocks. Each storage cell may store one or more bits of information.

[0033] System 100 illustrates one embodiment in which the storage device 102 is configured to have the iterative error-detection code checksum processing capability described herein, but it is understood that any other suitable device may have the iterative error-detection code checksum processing capability in a similar manner.

[0034] For the purpose of clarity and brevity, and not as an limitation, this disclosure is provided in the context of iterative error-detection code checksum processing that provides the features and functions disclosed herein. The iterative error-detection code checksum process may consist of any suitable software, hardware, or both for implementing such features and functions. Iterative error-detection code checksum processing may be implemented at least in part, for example, in a storage device 102 (e.g., as part of a processing circuit 104, or as part of any other suitable device where efficiency can be improved at higher data structure depths). For example, for a solid-state storage device (i.e., storage device 100), iterative error-detection code checksum processing may be implemented in a processing circuit 104.

[0035] Figure 2 shows an exemplary progression of a CRC checksum process 200 of data divided into four parts (e.g., a first part 204, a second part 205, a third part 207, and a fourth part 208) according to some embodiments of the present disclosure. Although the progression shown in Figure 2 relates to a CRC checksum process 200, the progression shown may be used for any form of error detection code (e.g., a linear error detection code). Each stage of the progression includes a data codeword 202 or a portion of a data codeword and a corresponding CRC value 203.

[0036] First, the entire data codeword 201 (e.g., data 108) is received by the processing circuit 104. In this implementation, the received data codeword 201 is 33 bytes long. In some embodiments, each byte of the data codeword (i.e., bytes 1 to 33) may contain a value in the range of 0 to 255. However, this disclosure is not limited to data codewords of 33 bytes in length. The data codeword includes two corrupted bytes of the data, namely the first corrupted byte 206 of the data and the second corrupted byte 209 of the data. Also, although not shown, a corresponding expected CRC checksum value is received along with the data codeword 201 and used to verify the validity of the data codeword 201.

[0037] Process 200, using the processing circuit 104, divides the entire data codeword 201 into four parts of data, including a first part 204, a second part 205, a third part 207, and a fourth part 208. As it is currently divided, the first corrupted byte 206 is located in the second part 205, and the second corrupted byte 209 is located in the fourth part 208. In some embodiments, each part of the data corresponds to an error detection code state, which indicates whether each part of the data is corrupted. The error detection code state for each part may be either a correct error detection code state or an incorrect error detection code state. Process 200, using the processing circuit 104, iteratively processes each part of the data (e.g., 204, 205, 207, 208) and determines a CRC checksum value for each part. The processing circuit 104 stores the CRC checksum value for each part in memory 106. Next, the processing circuit 104 determines that the overall CRC checksum value is the sum of the CRC checksum values ​​of each portion of the data (e.g., 204, 205, 207, 208). The processing circuit 104 compares the overall CRC checksum value with the expected CRC checksum value. The processing circuit 104 may determine that the overall CRC checksum value does not match the expected CRC checksum value because at least one of the portions of the data (e.g., the second portion 205 and the fourth portion 208) has corrupted bytes.

[0038] As part of process 200, processing circuit 104 then corrects the first corrupted byte 206 and the second corrupted byte 209 of the data. In some embodiments, processing circuit 104 requests that at least one portion of the data be retransmitted in order to correct at least one portion of the data. Once the corrupted portions of the data (e.g., the second portion 205 and the fourth portion 208 of the data) are corrected, processing circuit 104 receives the corrected second portion 210 and the corrected fourth portion 212 of the data. The corrected second portion 210 of the data includes the corrected byte 211 of the data at the same byte address as the corrupted first byte 206 of the data in the second portion 205 of the data. Furthermore, the corrected fourth portion 212 of the data includes the corrected byte 213 of the data at the same byte address as the corrupted second byte 209 of the data in the fourth portion 208 of the data. In some embodiments, once each portion of the data is corrected, the error detection code state corresponding to each portion of the data is set to the correct error detection code state.

[0039] Once the corrupted portion is corrected, the processing circuit 104 determines the updated CRC checksum value for each corrected portion (for example, the corrected second portion 210 of the data and the corrected fourth portion 212 of the data). The updated overall CRC checksum value is determined by the processing circuit 104 based on the updated CRC checksum values ​​for the corrected portions 210 and 212 of the data, and the stored CRC checksum values ​​for the first portion 204 of the data and the third portion 207 of the data. If the processing circuit 104 determines that the updated overall CRC checksum value matches the expected CRC checksum value, the process 200 is completed with respect to the data codeword 201.

[0040] Figure 3 shows a flowchart 300 of exemplary steps for processing a CRC checksum by partial, iterative updating of a portion of a data codeword, according to some embodiments of the present disclosure. In some embodiments, the storage device, processing circuit, and memory mentioned may be implemented as storage device 102, processing circuit 104, and memory 106, respectively. In some embodiments, the process 300 may be modified, for example, by rearranging, changing, adding, and / or removing steps.

[0041] In step 302, the processing circuit 104 receives data (e.g., data 108) and the expected error detection code value corresponding to that data. In some embodiments, the data is received by the processing circuit 104 via a network bus or interface. The expected error detection code value is used by the processing circuit 104 when verifying the integrity of the data. The processing circuit 104 can check that the received data is in the same state as when it was transmitted or stored in memory. The data (e.g., data 108) includes the expected error detection code value. For example, the expected error detection code value may be wrapped in the header field of the received data. In some embodiments, the storage device 102 receives one or more data. At least one of the received data may be stored in memory such as a cache or queue, or in any form of volatile memory. In some embodiments, the processing circuit 104 may include a multicore processor capable of performing iterative error detection code checksums for one or more codewords.

[0042] In step 304, the processing circuit 104 processes the data in at least two parts. In some embodiments where the data is 33 bytes long, the processing circuit 104 may process the data in up to 264 parts, so that the minimum size of one part is a single bit. In some embodiments, the maximum number of data parts may be defined as the codeword size divided by the minimum size of one part (e.g., a single bit), or the total number of bits of data. To process each part, the processing circuit 104 is configured to calculate an error detection code value for each part and store the calculated error detection code values ​​for each part in the memory 106. As seen in process 200 in Figure 2, the data may be processed in four parts, but may be further subdivided into smaller parts. Subdivision into smaller parts adds granularity and increases the number of partial iterations required to process the entire data codeword (e.g., data 108). However, smaller data parts result in less latency than larger parts, and therefore the processor can operate at a higher frequency. In some embodiments, each portion of the data has an equal length, which can be measured by the number of bytes or bits. In some embodiments, when processing at least two portions, including a first portion of a first length and a second portion of a second length, the processing circuit 104 may determine that the second length is greater than the first length. The processing circuit 104 then pads the first portion with zeros so that the first portion has an equal length to the second portion. Once each portion has been processed, the processing circuit 104 has processed the entire data codeword and can calculate the overall error detection code value in step 306.

[0043] In step 306, the processing circuit 104 calculates an overall error detection code value based on the respective error detection code values ​​of at least two parts of the data (e.g., data 108). In some embodiments, the error detection code transmitted with the data (e.g., data 108) is a linear error detection code, such as a CRC code, which allows the overall detection code value to be calculated by summing the error detection code values ​​for each part of the data. In some embodiments, the overall error detection code value is stored in memory 106. The overall error detection code value is used by the processing circuit 104 when verifying the integrity of the data by comparing the overall error detection code with an expected error detection code value, as shown in step 308.

[0044] In step 308, the processing circuit determines whether the overall error detection code value matches the expected error detection code value included with the transmitted data (e.g., data 108). If the overall error detection code value matches the expected error detection code value, the processing circuit 104 can reliably verify that the data was not corrupted during transmission over the network bus or interface before being received by the processing circuit 104. In such cases, the error detection code checksum process is completed with respect to that data codeword. In contrast, if the overall error detection code value does not match the expected error detection code value, the processing circuit 104 determines that there is at least one corrupted or erroneous portion of the data. Therefore, the processing circuit 104 then corrects at least one of the portions of the data in step 310 so that it has a valid data codeword for further processing.

[0045] In step 310, the processing circuit is configured to correct at least one of at least two portions of the data (e.g., data 108) to generate at least two corrected portions. In some embodiments, the processing circuit 104 is configured to request that a portion of the data be retransmitted. This allows the processing circuit 104 to request a portion of the data to replace the corrupted portion with the corrected portion of the data. In some embodiments, the processing circuit 104 is configured to request that the entire data codeword be retransmitted. Furthermore, this disclosure is not limited to data correction by data retransmission. In some embodiments, an LDPC decoder may be used to determine that certain data bits or subsets of data are incorrect and therefore certain data bits or subsets of data should be inverted. In step 312, the processing circuit 104 corrects at least one portion of the data and then processes the corrected portion of the data.

[0046] In step 312, the processing circuit 104 processes at least two corrected portions. The processing circuit 104 calculates an updated error detection sign value for each of the at least two corrected portions. In some embodiments, the processing circuit 104 is then configured to calculate an updated overall error detection sign value based on each of the updated error detection sign values ​​for each of the at least two corrected portions and each error detection sign value stored in memory 106. The processing circuit 104 then determines in step 308 whether the updated overall error detection sign value matches the expected error detection sign value. If the updated overall error detection sign value matches the expected overall error detection sign value, the data (e.g., data 108) is corrected and verified as valid data. However, in some embodiments, at least one corrupted portion of the data remains, which may cause the updated overall error detection sign value to not match the expected overall error detection sign value. In some embodiments, the retransmitted data seen in step 310 may be corrupted when retransmitted. The process continues sequentially through steps 308, 310, and 312 until the updated global error detection sign value matches the expected global error detection sign value.

[0047] Figure 4 shows a flowchart of process 400, which includes an exemplary step for processing data from at least two portions of the data shown in Figure 3 by calculating and storing error detection sign values ​​for each portion of the data, according to some embodiments of the present disclosure. Process 400 may also be referred to as step 304 as seen in Figure 3. In some embodiments, the storage device, processing circuit, and memory mentioned may be implemented as storage device 102, processing circuit 104, and memory 106, respectively. In some embodiments, process 400 may be modified, for example, by rearranging, changing, adding, and / or removing steps.

[0048] In step 402, the processing circuit 104 is configured to calculate error detection sign values ​​for each portion. In some embodiments, the processing circuit 104 may calculate error detection sign values ​​for each portion of the data by using a hash function (i.e., by polynomial division), fingerprinting, matrix multiplication, a linear feedback shift register, or a randomization function. Once the processing circuit 104 has calculated error detection sign values ​​for each portion of the data, in step 404, the processing circuit 104 stores the calculated error detection sign values ​​for each portion in the memory 106.

[0049] In step 404, the processing circuit 104 stores the error detection code value for each part in the memory 106. By storing the error detection code value for each part of the data 108 in memory, the processing circuit 104 can utilize the previously calculated error detection code value when it determines that a part of the data 108 is corrupted and needs to be corrected. By accessing the previously calculated error detection code value for at least one part of the data, the total latency and power consumption of the error detection code checksum process can be reduced.

[0050] Figure 5 shows a flowchart of a process 500 that includes an exemplary step for processing data from at least two parts of the data shown in Figure 3 by determining and storing error detection code states corresponding to each part of the data, according to some embodiments of the present disclosure. Process 500 may also be referred to as step 304 as seen in Figure 3. In some embodiments, the storage device, processing circuit, and memory mentioned may be implemented as storage device 102, processing circuit 104, and memory 106, respectively. In some embodiments, process 500 may be modified, for example, by rearranging, changing, adding, and / or removing steps.

[0051] In step 502, the processing circuit 104 is configured to determine the error detection code state corresponding to each part. The error detection code state may be one of a correct error detection code state or an incorrect error detection code state. In some cases, an incorrect error detection code state is determined to correspond to a part of the data when that part of the data is corrupted and should be corrected. If the error detection code state of each part of the data is an incorrect error detection code state, that part of the data is corrected before it reaches other parts of the data corresponding to the incorrect error detection code state across the data codeword. In some embodiments, the error detection code state may be implemented as a bit inversion, which uses a single bit to indicate the error detection code state for each part of the data. In some embodiments, the LDPC decoder may determine that a particular data bit is incorrect and should be inverted. Once the processing circuit 104 has determined the error detection code state corresponding to each part of the data, in step 504, the processing circuit 104 stores the error detection code states corresponding to each part in the memory 106.

[0052] In step 504, the processing circuit 104 stores the error detection code state corresponding to each part in the memory 106. By storing the error detection code state for a portion of the data 108 in memory, the processing circuit 104 can determine each portion of the data codeword corresponding to an incorrect error detection code state and correct each of these determined portions of data faster than calculating the overall error detection code value based on the corrected portion of the data and any error detection code value stored in memory 106. By using a single-bit error detection code state for each portion of the data, the amount of memory 106 required is reduced compared to storing the error detection code value.

[0053] Figure 6 shows a flowchart of a process 600, according to some embodiments of the present disclosure, which includes an exemplary step for modifying at least one of at least two portions of data shown in Figure 3 to produce at least two modified portions. Process 600 may also be referred to as step 310 as seen in Figure 3. In some embodiments, the storage device, processing circuit, and memory mentioned may be implemented as storage device 102, processing circuit 104, and memory 106, respectively. In some embodiments, process 600 may be modified, for example, by rearranging, changing, adding, and / or removing steps.

[0054] In step 602, the processing circuit 104 requests that a portion of the data 108 be retransmitted. In some embodiments, the processing circuit 104 receives the data 108 from both internal and external sources of the storage device 102. The processing circuit 104 is configured to send a request to the source of the data 108 asking that a portion of the data 108 be retransmitted. In some embodiments, the processing circuit is configured to send a request asking that the entire data codeword be retransmitted. After the processing circuit 104 has sent a request asking that at least a portion of the data source be retransmitted, in step 604, the processing circuit 104 receives the requested data.

[0055] In step 604, the processing circuit 104 is configured to receive the retransmitted portion of the data 108. In some embodiments, the retransmitted portion of the data is received by the processing circuit 104 from a network bus or interface. In some embodiments, the processing circuit receives the entire data codeword that was requested to be retransmitted. In some embodiments, the received retransmitted portion of the data may be stored in memory such as a cache or queue, or any form of volatile memory, before further processing.

[0056] Figure 7 shows a flowchart of process 700, which includes exemplary steps for correcting at least one of the at least two portions of data shown in Figure 3, for setting the error detection code state corresponding to each of the at least two corrected portions to the correct error detection code state, according to some embodiments of the present disclosure. Process 700 may also be referred to as step 310 as seen in Figure 3. In some embodiments, the storage device, processing circuit, and memory mentioned may be implemented as storage device 102, processing circuit 104, and memory 106, respectively. In some embodiments, process 700 may be modified, for example, by rearranging, changing, adding, and / or removing steps.

[0057] In step 702, the processing circuit 104 selects at least one of at least two portions that correspond to an incorrect error detection code state. In some embodiments, the processing circuit 106 uses a matrix to traverse the data codeword either in a forward or reverse / rewind direction. In some implementations, an update matrix may be used to traverse to the portion of data to be corrected that corresponds to an incorrect error detection code state. In some embodiments, the update matrix may be used to proceed through each portion of the data, or the update matrix may be updated by matrix multiplication to traverse to a specific portion of the data. After the processing circuit 104 has selected at least one of at least two portions that correspond to an incorrect error detection code state, in step 704, the processing circuit 104 corrects the selected at least one portion corresponding to the incorrect error detection code state to generate at least two corrected portions.

[0058] In step 704, the processing circuit 104 is configured to correct at least one selected portion corresponding to an incorrect error detection code state to generate at least two corrected portions. In some embodiments, the processing circuit 104 may correct portions of data corresponding to incorrect error detection code states by the same process shown in process 700. After the processing circuit 104 corrects at least one selected portion corresponding to an incorrect error detection code state to generate at least two corrected portions, in step 706, the processing circuit 104 sets the error detection code state corresponding to each of the at least two corrected portions to a correct error detection code state.

[0059] In step 706, the processing circuit 104 is configured to set the error detection code state corresponding to each of at least two corrected portions to the correct error detection code state. In some embodiments, the processing circuit 104 continues to traverse the data codeword and correct further portions of data corresponding to incorrect error detection code states until there are no more portions of the data codeword corresponding to incorrect error detection code states. In some implementations, there may be an error detection code state for the entire codeword, which indicates whether any one portion of the data in the data codeword corresponds to an incorrect error detection code state.

[0060] Figure 8 shows a flowchart of a process 800, which includes exemplary steps for processing at least two modified portions of the data shown in Figure 3, according to some embodiments of the present disclosure. Process 800 may also be referred to as step 312 as seen in Figure 3. In some embodiments, the storage device, processing circuit, and memory mentioned may be implemented as storage device 102, processing circuit 104, and memory 106, respectively. In some embodiments, process 800 may be modified, for example, by rearranging, changing, adding, and / or removing steps.

[0061] In step 802, the processing circuit 104 calculates updated error detection sign values ​​for each of the two corrected portions of the data 108. In some embodiments, the processing circuit 104 calculates the updated error detection sign values ​​for each corrected portion of the data 108 in a manner similar to how the error detection sign values ​​are calculated (as seen in step 402 of Figure 4). In some embodiments, the processing circuit 104 overwrites the error detection sign values ​​for the corrected portions of the data 108 at addresses in memory 106 with the updated error detection sign values ​​for the corrected portions of the data. The processing circuit 104 is then configured to calculate an updated overall error detection sign value in step 804 based on at least each of the updated error detection sign values.

[0062] In step 804, the processing circuit 104 is configured to calculate an updated overall error detection sign value based on the updated error detection sign values ​​for each of the at least two corrected portions and the stored error detection sign values ​​in memory 106. In some embodiments, the error detection sign value is a linear error detection sign value, such as a CRC checksum. In some implementations, the processing circuit 104 calculates the updated overall error detection sign value by using a linear error detection sign value to calculate the sum of the updated error detection sign values ​​for at least one corrected portion and the stored error detection sign values ​​for each undamaged portion. In other implementations, the processing circuit 104 calculates the updated overall error detection sign value by using a linear error detection sign value to calculate the sum of the stored overall error detection sign values ​​before the most recent partial correction and the respective differences between the updated error detection sign value and the stored error detection sign value for each damaged portion of the data.

[0063] Figures 9 to 11 show flowcharts of a process (e.g., 900, 1000, and 1100) that includes exemplary steps for determining the rewound error detection code states (e.g., 912, 1014, and 1112) of a data codeword, according to some embodiments of the present disclosure. By implementing the use of error detection code states for each portion of the data, the processing circuit 104 can determine each portion of the data corresponding to an incorrect error detection code state, correct each of these determined portions of the data, and calculate an overall error detection code value based on the corrected portions of the data and any error detection code values ​​stored in memory 106. The total memory required can be reduced by storing a single-bit error detection code state for access, rather than an error detection code value for each portion of the data.

[0064] The flowchart for process 900 includes a fixed N-bit × N-bit matrix 902, which may be used to determine the updated N-bit × N-bit matrix 906. In some implementations, N is the number of bits in the error detection code state (e.g., 908 and 912). The fixed N × N matrix 902 may be stored in memory 106 and used to traverse one step in the reverse direction, where a step refers to a fixed distance between two bit positions in the data codeword. In some implementations, to traverse multiple parts of the data, the fixed N × N matrix 902 may be multiplied 904 to generate the updated N × N matrix 906. In some implementations, the updated N × N matrix 906 may be multiplied 904 to further update the updated N × N matrix 906. Process 900 shows that the rewound N-bit error detection code state 912 is generated by multiplying the updated N × N matrix 906 and the N-bit error detection code state 908 by 910.

[0065] The flowchart for process 1000 shows a simplified logic for generating a rewound N-bit error detection code state 1014 with fewer logic gates required. Process 1000 shows the first row 1006 of the updated N×N matrix 1008, where the first row 1006 is used to determine any subsequent row of the updated N×N matrix 1008. The first row 1006 is multiplied 1004 by the fixed N×N matrix 1002 to generate the second row, which is used for the updated N×N matrix 1008 and to generate the third row. Process 1000 then shows that the rewound N-bit error detection code state 1014 is generated by multiplying the updated N×N matrix 1008 and the N-bit error detection code state 1010.

[0066] The flowchart of process 1100 shows an unordered rewinder logic including a lookup table 1102, which may be used to determine each row (i.e., the first row 1104) of the updated N×N matrix 1106. In some embodiments, the logic may include a multiplier to reduce the number of rows stored in the lookup table 1102. For example, the multiplier allows all odd rows to be stored in the lookup table 1102, and any subsequent rows can be determined by matrix multiplication of a fixed N×N matrix. Process 1100 then shows generating a rewound N-bit error detection code state 1112 by multiplying the updated N×N matrix 1008 and the N-bit error detection code state 1108.

[0067] Figure 12 shows a flowchart of a process 1200 that includes exemplary steps for updating the error detection code state 1208 of an N-bit complete codeword according to some embodiments of the present disclosure. Process 1200 shows updating the error detection code state of an N-bit complete codeword by adding 1204 a rewound N-bit error detection code state 1202 (such as 912, 1014, and 1112) to the previous error detection code state of the N-bit complete codeword. After the error detection code state 1208 of the N-bit complete codeword has been updated by the rewound N-bit error detection code state 1202, the processing circuit 104 may determine whether there are any further portions of data corresponding to an incorrect error detection code state. If any bit of the error detection code state 1208 of the N-bit complete codeword indicates an incorrect error detection code state, the processing circuit 104 proceeds with correcting the further data portions.

[0068] The terms “an embodiment,” “embodiment,” “embodiments,” “the embodiment,” “the embodiments,” “one or more embodiments,” “some embodiments,” and “one embodiment” mean “one or more (but not all) embodiments” unless explicitly stated otherwise.

[0069] The terms "including," "comprising," and "having," and their variations, mean "including but not limited to," unless explicitly stated otherwise.

[0070] The listed items do not imply that any or all of them are mutually exclusive unless explicitly stated otherwise.

[0071] The terms "a," "an," and "the" mean "one or more" unless explicitly stated otherwise.

[0072] Devices that are communicating with each other do not need to communicate with each other continuously unless explicitly stated otherwise. Furthermore, devices that are communicating with each other may communicate directly or indirectly through one or more intermediates.

[0073] Descriptions of embodiments having multiple components that communicate with each other do not imply that all such components are necessary. On the contrary, various optional components are described to illustrate a variety of conceivable embodiments. Furthermore, while process stages, method stages, algorithms, or the like may be described in order, such processes, methods, and algorithms may be configured to function in alternative orders. In other words, any sequence or order of stages that may be described does not necessarily indicate that the stages must be performed in that order. The stages of the processes described herein may be performed in any practical order. Furthermore, some stages may be performed simultaneously.

[0074] Where a single device or article is described herein, it will be readily apparent that one or more devices / articles (whether they cooperate or not) may be used instead of a single device / article. Similarly, where one or more devices or articles (whether they cooperate or not) are described herein, it will be readily apparent that a single device / article may be used instead of one or more devices or articles, or that a different number of devices / articles may be used instead of the number of devices or programs indicated. The functions and / or features of a device may be carried out by one or more other devices not explicitly stated to have such functions / features. Therefore, other embodiments do not need to include the device itself.

[0075] At least some of the operations, which may be shown in the diagrams, indicate that several events occur in a specific order. In alternative embodiments, some operations may be performed in a different order, modified, or omitted. Furthermore, steps may be added to the logic described above and still conform to the embodiments described. Moreover, the operations described herein may occur sequentially, or certain operations may be processed in parallel. Furthermore, operations may be performed by a single processing unit or by distributed processing units.

[0076] The above description of various embodiments is presented for illustrative and explanatory purposes only. It is not intended to be exhaustive or to limit the invention to the exact form disclosed. In light of the above teachings, many modifications and variations are possible.

Claims

1. (a) The step of receiving data and the expected error detection sign value corresponding to the data; (b) A step of processing the data in at least two parts, wherein each of the processing in the at least two parts is: A step of calculating an error detection code value for each of the aforementioned parts; and Steps to store the error detection code value for each of the aforementioned parts in memory. Having; (c) A step of calculating an overall error detection sign value based on the respective error detection sign values ​​for at least two of the parts; (d) If the overall error detection sign value, or the updated overall error detection sign value, does not match the expected error detection sign value: A step of modifying at least one of the two aforementioned parts to generate at least two modified parts; and The step of processing the at least two modified portions, wherein the step of processing the at least two modified portions is: A step of calculating an updated error detection sign value for each of the at least two corrected portions; and A step of calculating an updated overall error detection sign value based on the updated error detection sign value for each of the at least two corrected portions and the stored error detection sign value. including; and (e) Repeat step (d) until the updated overall error detection sign value matches the expected error detection sign value. A method for providing this.

2. The step of modifying at least one of the two aforementioned parts to generate at least two modified parts is: A step of requesting that a portion of the aforementioned data be retransmitted; and The step of receiving the retransmitted portion of the aforementioned data. The method according to claim 1, comprising:

3. The method according to claim 1 or 2, wherein the step of receiving data and the expected error detection sign value corresponding to the data comprises the step of receiving the expected linear error detection sign value corresponding to the data.

4. The method according to claim 3, wherein the step of receiving the expected linear error detection code value corresponding to the data includes the step of receiving a low-density parity check codeword corresponding to the data.

5. The method according to claim 1 or 2, wherein the at least two portions are similarly equal in length.

6. The process of processing the aforementioned data in at least two parts is further: A step of determining that the first portion of the at least two portions has a first length, and that the second portion of the at least two portions has a second length greater than the first length; and A step of padding the first portion of the at least two portions with zeros so that the first portion has a length equal to the second portion. The method according to claim 1 or 2, comprising:

7. The processing of each of the at least two parts further: The step of determining the error detection code state corresponding to each of the above parts, where the error detection code state is one of (a) a correct error detection code state and (b) an incorrect error detection code state; and Steps to store the error detection code state corresponding to each of the above parts in memory. The method according to claim 1 or 2, comprising:

8. The step of modifying at least one of the two aforementioned parts to generate the two modified parts is: A step of selecting at least one of the at least two parts that corresponds to an incorrect error detection code state; A step of correcting the selected at least one of the at least two portions corresponding to an incorrect error detection code state to generate at least two corrected portions; and Steps to set the error detection code state corresponding to each of the at least two corrected portions to the correct error detection code state. The method according to claim 7, having the following characteristics.

9. The method according to claim 1 or 2, wherein the step of storing the error detection code value for each of the aforementioned parts in memory includes the step of overwriting the error detection code value previously stored for a part.

10. The step of calculating the updated overall error detection sign value based on the updated error detection sign value for each of the at least two corrected portions and the stored error detection sign value is: A step of determining the difference between the updated error detection code value and the stored error detection code value for the updated portion; and A step of calculating the updated overall error detection code value based on the updated error detection code value, the difference between the stored error detection code value for the updated portion, and the stored error detection code values ​​for at least two portions. The method according to claim 1 or 2, including the method described in claim 1 or 2.

11. It is a system, memory; and The system includes a processing circuit, and the processing circuit is: (a) receive the data and the expected error detection sign value corresponding to the data; (b) Processing the data in at least two parts, where each of the processing in the at least two parts is: Calculating error detection code values ​​for each of the aforementioned parts; and This includes storing the error detection sign value for each of the aforementioned parts in the memory, (c) Based on the respective error detection sign values ​​for the at least two portions, calculate an overall error detection sign value; (d) If the overall error detection sign value, or the updated overall error detection sign value, does not match the expected error detection sign value: Modify at least one of the two aforementioned parts to generate at least two modified parts; Processing the at least two modified portions, where processing the at least two modified portions means: Calculating an updated error detection sign value for each of the at least two corrected portions; and This includes calculating an updated overall error detection sign value based on the updated error detection sign values ​​for each of the at least two modified portions and the stored error detection sign values; (e) Repeat (d) until the updated overall error detection sign value matches the expected error detection sign value. A system that is configured in such a way.

12. To modify at least one of the two aforementioned parts and generate at least two modified parts, the processing circuit: Requesting that a portion of the aforementioned data be retransmitted; The system according to claim 11, which receives the retransmitted portion of the aforementioned data.

13. The system according to claim 11 or 12, wherein the expected error detection sign value corresponding to the data includes an expected linear error detection sign value corresponding to the data.

14. The system according to claim 13, wherein the expected linear error detection code value corresponding to the data includes a low-density parity check codeword corresponding to the data.

15. The system according to claim 11 or 12, wherein the at least two of the parts are similarly equal in length.

16. To process the aforementioned data in at least two parts, the processing circuit further: It is determined that the first of the at least two parts has a first length, and the second of the at least two parts has a second length greater than the first length; The system according to claim 11 or 12, wherein the first portion of the at least two portions is padded with zeros such that the first portion has a length equal to the second length.

17. To process each of the two aforementioned parts, the processing circuit further: The error detection code state corresponding to each of the above parts is determined, where the error detection code state is one of (a) a correct error detection code state and (b) an incorrect error detection code state; The system according to claim 11 or 12, wherein the error detection code state for each of the aforementioned parts is stored in memory.

18. To modify at least one of the two aforementioned parts to generate the two modified parts, the processing circuit: Select at least one of the at least two parts that corresponds to an incorrect error detection code state; To correct at least one of the selected portions corresponding to an incorrect error detection code state, thereby generating at least two corrected portions; The system according to claim 17, wherein the error detection code state corresponding to each of the at least two corrected portions is set to the correct error detection code state.

19. The system according to claim 11 or 12, wherein the processing circuit overwrites previously stored error detection code values ​​for a portion in memory in order to store the error detection code values ​​for each of the portions.

20. To calculate the updated overall error detection sign value based on the updated error detection sign values ​​for each of the at least two modified portions and the stored error detection sign values, the processing circuit: Determine the difference between the updated error detection code value and the stored error detection code value for the updated portion; The system according to claim 11 or 12, which calculates the updated overall error detection code value based on the updated error detection code value, the difference between the stored error detection code value for the updated portion, and the stored error detection code value for at least two portions.

21. In the processing circuit, (a) A procedure for receiving data and the expected error detection sign value corresponding to the data; (b) A procedure for processing the data in at least two parts, wherein each of the processing in the at least two parts is: Calculating error detection code values ​​for each of the aforementioned parts; and This includes storing the error detection code value for each of the aforementioned parts in memory; (c) A procedure for calculating an overall error detection sign value based on the respective error detection sign values ​​for at least two of the portions; (d) If the overall error detection sign value, or the updated overall error detection sign value, does not match the expected error detection sign value: A procedure for modifying at least one of the aforementioned two parts to generate at least two modified parts; A procedure for processing the at least two modified portions, wherein processing the at least two modified portions means: Calculating an updated error detection sign value for each of the at least two corrected portions; and This includes calculating an updated overall error detection sign value based on the updated error detection sign values ​​for each of the at least two modified portions and the stored error detection sign values; and (e) Repeating (d) until the updated overall error detection sign value matches the expected error detection sign value. A computer program designed to execute something.

22. To modify at least one of the two aforementioned parts and generate at least two modified parts, the processing circuit is subjected to the following: A procedure for requesting that a portion of the aforementioned data be retransmitted; and The procedure for receiving the retransmitted portion of the aforementioned data. A computer program according to claim 21 for causing the execution of the following:

23. The computer program according to claim 21 or 22, wherein the expected error detection sign value corresponding to the data includes the expected linear error detection sign value corresponding to the data.

24. The computer program according to claim 23, wherein the expected linear error detection code value corresponding to the data includes a low-density parity check codeword corresponding to the data.

25. The computer program according to claim 21 or 22, wherein at least two of the aforementioned portions are similarly equal in length.

26. To process the aforementioned data in at least two parts, the processing circuit includes: A procedure for determining that the first of the at least two parts has a first length, and the second of the at least two parts has a second length greater than the first length; and A procedure for padding the first portion of the at least two portions with zeros so that the first portion has a length equal to the second portion. A computer program according to claim 21 or 22 for further execution of the above.

27. To process each of the two aforementioned parts, the processing circuit includes: A procedure for determining the error detection code state corresponding to each of the above parts, wherein the error detection code state is one of (a) a correct error detection code state and (b) an incorrect error detection code state; and A procedure for storing the error detection code state for each of the aforementioned parts in memory. A computer program according to claim 21 or 22 for further execution of the above.

28. To modify at least one of the two aforementioned parts and generate the two modified parts, the processing circuit is subjected to the following: A procedure for selecting at least one of the at least two parts that corresponds to an incorrect error detection code state; A procedure for correcting at least one of the at least two selected portions corresponding to an incorrect error detection code state to generate at least two corrected portions; and A procedure for setting the error detection code state corresponding to each of the at least two corrected portions to the correct error detection code state. A computer program according to claim 27 for causing the execution of the following:

29. The computer program according to claim 21 or 22, wherein the procedure for storing the error detection code value for each of the aforementioned parts in memory includes a procedure for overwriting the error detection code value previously stored for a part.

30. To calculate the updated overall error detection code value based on the updated error detection code values ​​for each of the at least two corrected portions and the stored error detection code values, the processing circuit: A procedure for determining the difference between the updated error detection sign value and the stored error detection sign value for the updated portion; and A procedure for calculating the updated overall error detection code value based on the updated error detection code value, the difference between the stored error detection code value for the updated portion, and the stored error detection code value for at least two portions. A computer program according to claim 21 or 22 for causing execution.

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