Semiconductor equipment

Abstract

This application discloses a semiconductor device. The semiconductor device includes a substrate, a drift layer, and two sub-groove sections spaced apart in a first direction, each sub-groove section comprising a first groove containing a plurality of gate groove groups and a plurality of dummy gate groove sections, a second groove spaced apart between the two sub-grooves in a first direction, and a first connecting groove connected to one end of a dummy gate groove near the second groove, wherein the two first connecting grooves include a first connecting groove, one connecting one end of a plurality of second grooves and the other connecting the other end of a plurality of second grooves, and a second connecting groove, one end of a gate groove in a gate groove group near the second groove. This prevents the insulated gate bipolar transistor region and the fast recovery diode region from interfering with each other during the manufacturing process, ensuring the performance of each of the two regions, and improving the current guiding capability of the semiconductor device.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more specifically, to semiconductor devices. 。

Background Art

[0002] With the development of science and technology, the applications of semiconductor devices are becoming increasingly widespread. In semiconductor device design and manufacturing, grooves are provided, and gates are formed in the grooves to ensure the normal operation of the semiconductor devices.

[0003] In related technologies, the grooves are often in a stripe shape, but the electrostatic protection of the semiconductor device is likely to fail at the edges of the grooves, resulting in low stability and reliability of the semiconductor device.

Summary of the Invention

Means for Solving the Problems

[0004] According to a first aspect, the present application provides a semiconductor device. The semiconductor device The system includes an insulated-gate bipolar transistor region and a fast recovery diode region, the insulated-gate bipolar transistor region surrounding the fast recovery diode region, the fast recovery diode region including a fast recovery diode main conduction region and a fast recovery diode transition region, the portion of the fast recovery diode region located outside the fast recovery diode main conduction region being the fast recovery diode transition region, and the fast recovery diode transition region exerts a separating effect on the insulated-gate bipolar transistor region and the fast recovery diode main conduction region.

[0005] According to a second aspect, the present application provides a semiconductor device comprising: a drift layer; a ring layer installed on the upper surface of the drift layer; and a main groove portion extending in a first direction from the upper surface of the ring layer into the ring layer, wherein the main groove portion includes a plurality of gate groove groups and a plurality of dummy gate groove portions, the plurality of gate groove groups being spaced apart in a second direction, and at least one dummy gate groove portion being installed between two adjacent gate groove groups, and the gate groove groups being spaced apart in a second direction The semiconductor device further includes a main groove portion having at least two gate groove portions installed therein, a connecting groove portion penetrating from the upper surface of the ring layer into the ring layer and extending in a second direction, an active region and a terminal region circumferentially located outside the active region, wherein the main groove portion is installed in the active region and extends to the edge of the active region, the connecting groove portion is located between the active region and the terminal region, and the connecting groove portion connects at least one end of at least two of the gate groove portions of each of the gate groove groups. In one embodiment, the connecting grooves are provided at both ends of at least two of the gate grooves in each of the gate groove groups. In one embodiment, a dummy gate groove is provided between at least two of the gate grooves in each of the gate groove groups. In one embodiment, each of the gate groove groups includes two of the gate groove portions, and the connecting groove portion connects at least one end of the two of the gate groove portions in each of the gate groove groups. In one embodiment, the connecting groove connects at least one end of a plurality of gate groove groups. In one embodiment, the length of the gate groove in the first direction is greater than the length of the dummy gate groove in the first direction, both ends of the gate groove in the first direction protrude beyond both ends of the dummy gate groove in the first direction, and the connecting groove and the dummy gate groove are spaced apart from each other. In one embodiment, the connecting groove connects at least one end of a plurality of gate groove groups and a plurality of dummy gate grooves. In one embodiment, the length of the dummy gate groove in the first direction is equal to the length of the gate groove in the first direction, and both ends of the gate groove in the first direction are flush with both ends of the dummy gate groove in the first direction. In one embodiment, the connecting groove connects at least one end of a plurality of dummy gate grooves. In one embodiment, the length of the dummy gate groove in the first direction is greater than the length of the gate groove in the first direction, and both ends of the dummy gate groove in the first direction protrude beyond both ends of the gate groove in the first direction.

[0006] According to a third aspect, the present application provides a semiconductor device. The semiconductor device comprises a substrate having a first main surface and a second main surface opposite to the first main surface, a drift layer of a first conductivity type placed between the first main surface and the second main surface, and a first groove extending from the first main surface to the second main surface and reaching into the drift layer, wherein the first groove extends in a first direction and there are multiple first grooves, the multiple first grooves are spaced apart in a second direction, a portion of the multiple first grooves is a spacing groove, the spacing groove includes two sub-groove portions spaced apart in the first direction, the sub-groove portions include a plurality of gate groove groups and a plurality of dummy gate grooves, the plurality of gate groove groups are spaced apart in a second direction, at least one dummy gate groove is placed between two adjacent gate groove groups, the gate groove group includes at least two gate grooves spaced apart in a second direction, the gate grooves are electrically connected to the gates of the semiconductor device, and the dummy gate grooves are electrically connected to the emitters of the semiconductor device. A groove, a second groove extending from the first main surface to the second main surface and reaching into the drift layer, wherein the second groove extends in a first direction, the second groove portion is multiple and spaced apart from each other in a second direction, and the second groove is installed between two of the sub-groove portions in a first direction, and a first connecting groove extending from the first main surface to the second main surface and reaching into the drift layer, wherein the first connecting groove extends in a second direction, the first connecting groove is two, and the two aforementioned Each connecting groove includes a first connecting groove, one of which connects one end of a plurality of the second grooves in a first direction, and another of which connects the other end of a plurality of the second grooves in a first direction; and a second connecting groove extending from the first main surface to the second main surface and reaching into the drift layer, wherein the second connecting groove extends in a second direction, and the second connecting groove connects one end of the gate grooves in the gate groove group that is closer to the second groove, and connects one end of two adjacent gate groove groups that is closer to the second groove.

[0007] According to a fourth aspect, the present application provides a semiconductor device. The semiconductor device comprises a substrate having a first main surface and a second main surface opposite to the first main surface, a drift layer of a first conductivity type placed between the first main surface and the second main surface, and a first groove extending from the first main surface toward the second main surface and reaching into the drift layer, wherein the first groove extends in a first direction and there are multiple first grooves, the multiple first grooves are spaced apart in a second direction, some of the multiple first grooves are spacing grooves, the spacing grooves include sub-groove portions spaced apart in two first directions, the sub-groove portions include multiple gate groove groups and multiple dummy gate grooves, the multiple gate groove groups are spaced apart in a second direction, at least one dummy gate groove is placed between two adjacent gate groove groups, the gate groove groups include at least two gate grooves spaced apart in two second directions, the gate grooves are electrically connected to the gates of the semiconductor device, and the dummy gate grooves are electrically connected to the emitters of the semiconductor device. A groove, a second groove extending from the first main surface to the second main surface and reaching into the drift layer, wherein the second groove extends in a first direction, the second groove portion is multiple and spaced apart from each other in a second direction, and the second groove is installed between two of the sub-groove portions in a first direction, and a first connecting groove extending from the first main surface to the second main surface and reaching into the drift layer, wherein the first connecting groove extends in a second direction, the first connecting groove is two, and the two first connecting The connecting grooves include one connecting end of a plurality of the second grooves in a first direction, and another connecting end of a plurality of the second grooves in a first direction, wherein the first connecting groove is connected to one end of the dummy gate groove closer to the second groove, and a second connecting groove extending from the first main surface to the second main surface and reaching into the drift layer, wherein the second connecting groove extends in a second direction, and the second connecting groove connects one end of the gate grooves in the gate groove group closer to the second groove. [Brief explanation of the drawing]

[0008] [Figure 1] These are schematic diagrams of semiconductor devices according to some embodiments of the present disclosure. [Figure 2]Top view of a semiconductor device according to some embodiments of the present disclosure. [Figure 3] Partial schematic view of a semiconductor device according to some embodiments of the present disclosure. [Figure 4] Cross-sectional view of a semiconductor device according to some embodiments of the present disclosure taken along the A-A direction. [Figure 5] Cross-sectional view of a semiconductor device according to some embodiments of the present disclosure taken along the B-B direction. [Figure 6] Cross-sectional view of Structure 1 according to some embodiments of the present disclosure. [Figure 7] Cross-sectional view of Structure 2 according to some embodiments of the present disclosure. [Figure 8] Cross-sectional view of Structure 3 according to some embodiments of the present disclosure. [Figure 9] Cross-sectional view of Structure 4 according to some embodiments of the present disclosure. [Figure 10] Cross-sectional view of Structure 5 according to some embodiments of the present disclosure. [Figure 11] Cross-sectional view of Structure 6 according to some embodiments of the present disclosure. [Figure 12] Cross-sectional view of Structure 7 according to some embodiments of the present disclosure. [Figure 13] Partial schematic view of a semiconductor device according to some embodiments of the present disclosure. [Figure 14] Partial schematic view of a semiconductor device according to some embodiments of the present disclosure. [Figure 15] Cross-sectional view of a semiconductor device according to some embodiments of the present disclosure taken along the A-A direction. [Figure 16] Partial schematic view of a semiconductor device according to some embodiments of the present disclosure. [Figure 17] Partial schematic view of a semiconductor device according to some embodiments of the present disclosure. [Figure 18] Cross-sectional view of Structure 1 according to some embodiments of the present disclosure. [Figure 19] Cross-sectional view of Structure 2 according to some embodiments of the present disclosure. [Figure 20]Cross-sectional view of Structure 3 according to some embodiments of the present disclosure. [Figure 21] Cross-sectional view of Structure 4 according to some embodiments of the present disclosure. [Figure 22] Cross-sectional view of Structure 5 according to some embodiments of the present disclosure. [Figure 23] Partial schematic view of a semiconductor device according to some embodiments of the present disclosure. [Figure 24] Partial schematic view of a semiconductor device according to some embodiments of the present disclosure. [Figure 25] Cross-sectional view along the A-A direction of a semiconductor device according to some embodiments of the present disclosure. [Figure 26] Partial schematic view of a semiconductor device according to some embodiments of the present disclosure. [Figure 27] Partial schematic view of a semiconductor device according to some embodiments of the present disclosure. [Figure 28] Cross-sectional view of Structure 1 according to some embodiments of the present disclosure. [Figure 29] Cross-sectional view of Structure 2 according to some embodiments of the present disclosure. [Figure 30] Cross-sectional view of Structure 3 according to some embodiments of the present disclosure. [Figure 31] Cross-sectional view of Structure 4 according to some embodiments of the present disclosure. [Figure 32] Cross-sectional view of Structure 5 according to some embodiments of the present disclosure. [Figure 33] Top view of a semiconductor device according to some embodiments of the present disclosure. [Figure 34] Schematic view of Region A in FIG. 1. [Figure 35] Schematic view of Region B in FIG. 1. [Figure 36] Cross-sectional view along the A-A direction of a semiconductor device according to some embodiments of the present disclosure. [Figure 37] Cross-sectional view along the B-B direction of a semiconductor device according to some embodiments of the present disclosure. [Figure 38] Partial schematic view of a semiconductor device according to some embodiments of the present disclosure. [Figure 39] This is a diagram illustrating the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. [Figure 40] This is a diagram illustrating the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. [Figure 41] This is a diagram illustrating the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. [Figure 42] This is a diagram illustrating the manufacturing process of a semiconductor device according to some embodiments of the present disclosure. [Modes for carrying out the invention]

[0009] Hereinafter, several embodiments of this disclosure will be clearly and completely described in relation to the drawings. Needless to say, the embodiments described are only a selection of, and not all, embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments relating to this disclosure are all within the scope of protection of this disclosure.

[0010] Throughout the specification and claims, the term “comprise,” and other forms thereof, such as its third-person singular form “comprises” and present participle form “comprising,” shall be interpreted as “open,” “including,” or “including, but not limited to,” unless otherwise specified by context. In this description, terms such as “one embodiment,” “some embodiments,” “exemplary embodiments,” “example,” “specific example,” or “some examples” are intended to indicate that a particular feature, structure, material, or property relating to such embodiment or example is included in at least one embodiment or example of this disclosure. The schematic expressions of the above terms do not necessarily mean identical embodiments or examples. Furthermore, such particular feature, structure, material, or property may be included in any one or more embodiments or examples in any suitable form.

[0011] Hereinafter, the terms “First” and “Second” are merely descriptive and should not be understood as indicating or implying relative importance or implicitly representing the number of designated technical features. Thus, the “First” and “Second” features may explicitly or implicitly include one or more features. In the description of the embodiments of this disclosure, unless otherwise specified, “multiple” means two or more.

[0012] In describing some embodiments, the term “connection” and related expressions may be used. The term “connection” should be understood broadly; for example, a “connection” may be a fixed connection, a detachable connection, an integral connection, a direct connection, or an indirect connection via an intermediate medium. The term “bonding” indicates, for example, that two or more members are directly in physical or electrical contact. The embodiments disclosed herein are not necessarily limited by the content of this specification.

[0013] "A and / or B" includes three cases: A only, B only, and a combination of A and B.

[0014] In this specification, the use of “applies to” or “set to” means open and inclusive language and does not preclude it from being applied to or set to a device performing other tasks or steps.

[0015] Furthermore, since processes, steps, calculations, or other operations based on one or more of the aforementioned conditions or values ​​may, in practice, be based on additional conditions and may exceed the values, the use of “based on” implies openness and capacity.

[0016] RC-IGBTs (reverse conducting-insulated gate bipolar transistors) integrate IGBTs (insulated gate bipolar transistors) and FRDs (fast recovery diodes) on the same chip, possessing both forward and reverse conducting properties simultaneously. They offer many advantages, including small size, high power density, low cost, and high reliability.

[0017] In related technologies, the structure of RC-IGBTs often involves dividing the grooves to form an FRD region, thereby separating the IGBT region from the FRD region. However, in this case, the FRD region is susceptible to the manufacturing process, such as IGBT region injection, which degrades the performance of the FRD region and, consequently, the RC-IGBT.

[0018] In the semiconductor device 100 according to this application, one end of a plurality of second grooves is connected with one of the two first connection grooves, and the other end of the plurality of second grooves is connected with the other of the two first connection grooves. The first connection groove closes the plurality of second grooves, separating the insulated gate bipolar transistor region and the fast recovery diode region. This prevents the insulated gate bipolar transistor region and the fast recovery diode region from interfering with each other during the manufacturing process, guaranteeing the performance of each of the two regions and improving the reliability of the semiconductor device.

[0019] Hereinafter, semiconductor devices 100 according to several embodiments of the present disclosure will be described with reference to Figures 1 to 12. The semiconductor device 100 may be an RC-IGBT. In the following description, N and P indicate the conductivity type of the semiconductor, and in this application, the first conductivity type is described as N-type and the second conductivity type as P-type. The first direction is the X direction, the second direction is the Y direction, and the up and down direction is the Z direction.

[0020] As shown in Figures 1 to 5, the semiconductor device 100 according to this application may mainly include a substrate 180, the substrate 180 being the base member of the semiconductor device 100, and the substrate 180 can provide a base for mounting to at least some other components of the semiconductor device 100.

[0021] The semiconductor device 100 according to this application may further include a drift layer 110 of a first conductivity type, specifically, the drift layer 110 of a first conductivity type is installed in a substrate 180 and is located between a first main surface 181 and a second main surface 182, a well region 111 of a second conductivity type is further installed in the substrate 180, the well region 111 is installed on the side of the drift layer 110 closer to the first main surface 181, a emitter layer 112 of a first conductivity type is further installed in the well region 111, a field stop layer 115 of a first conductivity type is further installed in the substrate 180, the field stop layer 115 is installed on the side of the drift layer 110 closer to the second main surface 182, and a collector layer 116 of a second conductivity type and a short-circuit region 117 of a first conductivity type are installed on the side of the field stop layer 115 closer to the second main surface 182. Furthermore, a dielectric layer 113 is installed on the first main surface 181, an emitter metal layer 114 is installed on the side of the dielectric layer 113 away from the first main surface 181, and a collector metal layer 118 is installed on the side of the second main surface 182 of the substrate 180.

[0022] The semiconductor device 100 may include an active region 101. The semiconductor device 100 may further include a termination region 102 located around the active region 101. Here, both the collector layer 116 and the short-circuit region 117 are located in the active region 101, the emitter metal layer 114 may be an emitter lead to the region corresponding to the collector layer 116 as well as an anode lead to the region corresponding to the short-circuit region 117, and the collector metal layer 118 may be a collector lead to the region corresponding to the collector layer 116 as well as a cathode lead to the region corresponding to the short-circuit region 117. In this way, the region corresponding to the collector layer 116 can achieve forward conduction of the semiconductor device 100, and the region corresponding to the short-circuit region 117 can achieve reverse conduction of the semiconductor device 100, thereby the semiconductor device 100 having both forward and reverse conduction characteristics.

[0023] The semiconductor device includes an insulated gate bipolar transistor region 1011 and a fast recovery diode region 1014, wherein the insulated gate bipolar transistor region 1011 surrounds the fast recovery diode region 1014.

[0024] The fast recovery diode region 1014 includes the fast recovery diode main conduction region 1012 and the fast recovery diode transition region 1013. The portion of the fast recovery diode region 1014 located outside the fast recovery diode main conduction region 1012 is the fast recovery diode transition region 1013, and the fast recovery diode transition region 1013 exerts a disconnecting effect on the insulated gate bipolar transistor region 1011 and the fast recovery diode main conduction region 1012.

[0025] The insulated gate bipolar transistor region 1011 and the fast recovery diode region 1014 are located in the active region 101.

[0026] In some embodiments, the semiconductor device 100 according to this application is mainly, It is installed in the insulated gate bipolar transistor region 1011.It may further include a first groove 120, the first groove 120 located within the region corresponding to the collector layer 116, The first groove 120 extends in the first direction, penetrating from the first main surface 181 into the drift layer 110 (i.e., The first groove 120 extends from the first main surface 181 to the second main surface 182 and reaches into the drift layer 110, and the first groove 120 extends in the first direction. Multiple first grooves 120 are provided, and the multiple first grooves 120 are provided spaced apart in the second direction. The oxide insulating layer 170 and the polysilicon 171 are provided sequentially within the first groove 120, thereby ensuring the region corresponding to the collector layer 116 and, consequently, the normal operation of the semiconductor device 100.

[0027] Furthermore, some of the multiple first grooves 120 are first spacing grooves 121. (Specifically, the first grooves 120 located on both sides of the fast recovery diode region 1014 are the first spacing grooves 121.) There are multiple first spacing grooves 121, and each first spacing groove 121 may mainly include first sub-grooves 1211 that are spaced apart in a first direction. Each first spacing groove 121 may further include second sub-grooves 1212 that are spaced apart from the first sub-grooves 1211 in a first direction.

[0028] The semiconductor device 100 relating to this application mainly, It is installed in the fast recovery diode region 1014. Including the second groove 130, The second groove 130 extends in the first direction, penetrating from the first main surface 181 into the drift layer 110 (i.e., The second groove 130 extends from the first main surface 181 to the second main surface 182 and reaches the drift layer 110, and the second groove 130 extends in the first direction, and the second groove 130 is located in a region that corresponds at least partially to the short-circuit region 117.

[0029] By defining the region where multiple first grooves 120 are located as an insulated gate bipolar transistor region 1011, and the region where multiple second grooves 130 are located as a fast recovery diode region 1014, and by having multiple second grooves 130 and corresponding to multiple first spacing grooves 121, it is possible to ensure that the junction depth and doping concentration of the well region 111 of the insulated gate bipolar transistor region 1011 and the fast recovery diode region 1014 are the same, thereby ensuring that the two regions have the same breakdown voltage, as well as simplifying the process steps of the semiconductor device 100 and streamlining the manufacturing process of the semiconductor device 100.

[0030] Furthermore, by placing the second groove 130 with a gap between the first sub-groove 1211 and the second sub-groove 1212, the insulated gate bipolar transistor region 1011 and the fast recovery diode 1014 can be separated. This separates the region corresponding to the short-circuit region 117 from the region corresponding to the collector layer 116, thereby guaranteeing the performance of each of the two regions and ensuring the operational performance of the semiconductor device 100.

[0031] Furthermore, the number of second grooves 130 may be multiple, and the number of second grooves 130 may be greater than the number of first spacing grooves 121. This allows some of the second grooves 130 to correspond to multiple first spacing grooves 121, and also reduces the amount of substrate 180 used, thereby lowering the manufacturing cost of the semiconductor device 100 of this application.

[0032] As shown in Figures 3 to 5, the semiconductor device 100 is It is installed at the boundary between the insulated gate bipolar transistor region 1011 and the fast recovery diode region 1014. The first connecting groove 140 may further be included. The first connecting groove 140 extends in the second direction, penetrating from the first main surface 181 into the drift layer 110 (i.e., The first connecting groove 140 extends from the first main surface 181 to the second main surface 182 and reaches into the drift layer 110, and the first connecting groove 140 extends in the second direction. There may be two first connecting grooves 140, one of which connects one end of a plurality of second grooves 130 and the other connecting the other end of a plurality of second grooves 130, and the two first connecting grooves 140 may be distributed on both sides of the second grooves 130.

[0033] Specifically, the multiple second grooves 130 have one end flush with each other and the other end flush with each other, a first connecting groove 140 is installed, the first connecting groove 140 extends from the first main surface 181 to the second main surface 182 and reaches into the drift layer 110, the first connecting groove 140 is extended in a second direction, and two first connecting grooves 140 are installed, so that one of the two first connecting grooves 140 extends in a second direction and connects one end of the multiple second grooves 130, and the other extends in a second direction and connects the other ends of the multiple second grooves 130. As a result, the two first connection grooves 140 can close the multiple second grooves 130, that is, the two first connection grooves 140 can separate the insulated gate bipolar transistor region 1011 and the fast recovery diode region 1014, further preventing the insulated gate bipolar transistor region 1011 and the fast recovery diode region 1014 from interfering with each other during the manufacturing process, ensuring the performance of each of the two regions, guaranteeing the operational performance of the semiconductor device 100, and improving the reliability of the semiconductor device 100.

[0034] In this way, one of the two first connection grooves 140 connects one end of the multiple second grooves 130, and the other of the two first connection grooves 140 connects the other end of the multiple second grooves 130. This closes the multiple second grooves 130, separating the insulated gate bipolar transistor region 1011 and the fast recovery diode region 1014. This prevents the insulated gate bipolar transistor region 1011 and the fast recovery diode region 1014 from interfering with each other during the manufacturing process, ensuring the performance of each region and guaranteeing the reliability of the semiconductor device 100.

[0035] In some embodiments, as shown in Figure 3, one of the multiple second grooves 130 adjacent to the first groove 120 on one side in the second direction is defined as the first boundary groove 1321, and one of the multiple second grooves 130 adjacent to the first groove 120 on the other side in the second direction is defined as the second boundary groove 1322. In this way, the area enclosed by the first boundary groove 1321, the second boundary groove 1322, and the two first connection grooves 140 is the fast recovery diode region 1014, and the two first connection grooves 140 can be used as the boundary of the fast recovery diode region 1014 in the first direction. This closes the fast recovery diode region 1014, prevents the insulated gate bipolar transistor region 1011 and the fast recovery diode region 1014 from interfering with each other during the manufacturing process, guarantees the performance of each of the two regions, and ensures the reliability of the semiconductor device 100.

[0036] As shown in Figure 1, one of the two first connection grooves 140, corresponding to the first sub-groove 1211, is installed away from the first sub-groove 1211, and the other of the two first connection grooves 140, corresponding to the second sub-groove 1212, is installed away from the second sub-groove 1212. By installing them in this way, the first connection grooves 140 can be separated from the insulated-gate bipolar transistor region 1011, thereby separating the insulated-gate bipolar transistor region 1011 from the fast-recovery diode region 1014. In some embodiments, separating the insulated-gate bipolar transistor region 1011 from the fast-recovery diode region 1014 makes it more reliable to prevent interference between the insulated-gate bipolar transistor region 1011 and the fast-recovery diode region 1014 during the manufacturing process, guaranteeing the performance of each of the two regions and ensuring the structural reliability of the semiconductor device 100.

[0037] As shown in Figures 3 and 4, the semiconductor device 100 may further include a second connection groove 150. The second connecting groove 150 extends in the second direction, penetrating from the first main surface 181 into the drift layer 110 (i.e., The second connecting groove 150 extends from the first main surface 181 to the second main surface 182, reaching into the drift layer 110, and extends in the second direction. (ru) There are two second connecting grooves 150, one of which connects an adjacent end to a second groove 130 of a plurality of first sub-grooves 1211, and the other which connects an adjacent end to a second groove 130 of a plurality of second sub-grooves 1212.

[0038] Specifically, the second groove 130 is spaced apart between the first sub-groove 1211 and the second sub-groove 1212. That is, one end of the first sub-groove 1211 is adjacent to the second groove 130, and one end of the second sub-groove 1212 is adjacent to the second groove 130. Multiple first sub-grooves 1211 and multiple second sub-grooves 1212 have ends adjacent to the second groove 130 that are flush with each other.

[0039] Two second connection grooves 150 are provided, each extending from the surface of the drift layer 110 into the drift layer 110, and each second connection groove 150 extends in a second direction. Thus, one of the two second connection grooves 150 extends in a second direction and can connect one adjacent end to the second groove 130 of a plurality of first sub-grooves 1211, and the other second connection groove 150 extends in a second direction and can connect one adjacent end to the second groove 130 of a plurality of second sub-grooves 1212. This connects the first sub-grooves 1211 of the insulated gate bipolar transistor region 1011 and connects the second sub-grooves 1212 of the insulated gate bipolar transistor region 1011, thereby ensuring the normal operation of the insulated gate bipolar transistor region 1011.

[0040] As shown in Figures 2 and 3, the multiple first grooves 120 may include multiple first main grooves 122. The multiple first grooves 120 may further include multiple first spacing grooves 121, with the multiple first main grooves 122 located on both sides of the multiple first spacing grooves 121 in a second direction, and both ends of the second connecting groove 150 in a second direction connected to the first main grooves 122 on both sides, respectively.

[0041] In some embodiments, one of the multiple first main grooves 122 adjacent to one side of the multiple first spacing grooves 121 in the second direction is a third boundary groove 1221, and one of the multiple first main grooves 122 adjacent to the other side of the multiple first spacing grooves 121 in the second direction is a fourth boundary groove 1222, the area outside the region enclosed by the third boundary groove 1221, the fourth boundary groove 1222 and the two second connection grooves 150 is an insulated gate bipolar transistor region 1011, and the area inside the region enclosed by the third boundary groove 1221, the fourth boundary groove 1222 and the two second connection grooves 150 is a fast recovery diode region 1014.

[0042] Specifically, one of the multiple first main grooves 122 adjacent to the multiple first spacing grooves 121 on one side in the second direction is defined as the third boundary groove 1221, one of the multiple first main grooves 122 adjacent to the multiple first spacing grooves 121 on the other side in the second direction is defined as the fourth boundary groove 1222, and both ends of the second connecting groove 150 in the second direction are connected to the first main grooves 122 on both sides, that is, both ends of the second connecting groove 150 in the second direction are connected to the third boundary groove 1221 and the fourth boundary groove 1222, respectively.

[0043] On the other hand, the second connecting groove 150 allows multiple first spacing grooves 121 and the first main groove 122 to be connected, thereby ensuring the normal operation of the insulated gate bipolar transistor region 1011 and, consequently, the semiconductor device 100.

[0044] On the other hand, the area outside the region enclosed by the third boundary groove 1221, the fourth boundary groove 1222, and the two second connection grooves 150 is the insulated gate bipolar transistor region 1011. These two second connection grooves 150 form the boundary of the insulated gate bipolar transistor region 1011 in the first direction, allowing for better separation of the insulated gate bipolar transistor region 1011 and the fast recovery diode region 1014. This prevents the insulated gate bipolar transistor region 1011 and the fast recovery diode region 1014 from interfering with each other during the manufacturing process in some embodiments, thereby improving the reliability of the semiconductor device 100.

[0045] As shown in Figure 3, a portion of the second groove 130 is the second spacing groove 131. (Specifically, the portion of the second groove 130 located in the projected region of the fast recovery diode main conductive region 1012 is the second spacing groove 131.) The second spacing groove 131 may mainly include a third sub-groove 1311. The second spacing groove 131 may further include a fourth sub-groove 1312. The second spacing groove 131 may further include a fifth sub-groove 1313. The third sub-groove 1311 and the fifth sub-groove 1313 are installed at both ends of the fourth sub-groove 1312 in the first direction, and are installed at a distance from the fourth sub-groove 1312.

[0046] Specifically, the third sub-groove 1311 and the fifth sub-groove 1313 are installed at both ends of the fourth sub-groove 1312 in the first direction, and are installed at a distance from the fourth sub-groove 1312, thereby partitioning the fast recovery diode region 1014. The fourth sub-groove 1312 is located in the region corresponding to the short-circuit region 117, and the region corresponding to the short-circuit region 117 is defined as the fast recovery diode main conduction region 1012. This prevents the insulated gate bipolar transistor region 1011 and the fast recovery diode main conduction region 1012 from interfering with each other during the manufacturing process, and ensures the performance of both the insulated gate bipolar transistor region 1011 and the fast recovery diode main conduction region 1012.

[0047] As shown in Figures 3 and 4, the semiconductor device 100 may further include a third connecting groove 160. The third connecting groove 160 extends in the second direction, penetrating from the first main surface 181 into the drift layer 110 (i.e.,The third connecting groove 160 extends from the first main surface 181 to the second main surface 182, reaching into the drift layer 110, and extends in the second direction. (ru) There are two third connecting grooves 160, one of which connects one end of the multiple fourth sub-grooves 1312, and the other which connects the other end of the multiple fourth sub-grooves 1312.

[0048] Specifically, one end of each of the multiple fourth sub-grooves 1312 is flush with each other, and the other ends of each of the multiple fourth sub-grooves 1312 are flush with each other. By installing the third connecting groove 160, one of the two third connecting grooves 160 extends in the second direction and can connect one end of each of the multiple fourth sub-grooves 1312, and the other of the two third connecting grooves 160 extends in the second direction and can connect the other ends of each of the multiple fourth sub-grooves 1312.

[0049] In this way, by connecting multiple fourth sub-grooves 1312, not only is the normal operation of the fast recovery diode main conductive region 1012 guaranteed, but the multiple fourth sub-grooves 1312 can be closed, that is, the two third connecting grooves 160 can close the fast recovery diode main conductive region 1012. This allows for the separation of the fast recovery diode main conductive region 1012 and the insulated gate bipolar transistor region 1011 in some embodiments, more effectively avoiding interference between the fast recovery diode main conductive region 1012 and the insulated gate bipolar transistor region 1011 during the manufacturing process, thereby guaranteeing the performance of each of the two regions and ensuring the operational performance of the semiconductor device 100.

[0050] In some embodiments, as shown in Figures 2 and 3, two third connecting grooves 160 connect one end adjacent to a fourth sub-groove 1312 of a plurality of third sub-grooves 1311, and the other connects one end adjacent to a fourth sub-groove 1312 of a plurality of fifth sub-grooves 1313.

[0051] Specifically, the third sub-groove 1311, the fourth sub-groove 1312, and the fifth sub-groove 1313 are installed sequentially spaced apart in the first direction, with one end of the third sub-groove 1311 adjacent to the fourth sub-groove 1312, and one end of the fifth sub-groove 1313 adjacent to the fourth sub-groove 1312. The ends of the multiple third sub-grooves 1311 adjacent to the fourth sub-groove 1312 are flush with each other, and the ends of the multiple fifth sub-grooves 1313 adjacent to the fourth sub-groove 1312 are flush with each other.

[0052] One of the two third connecting grooves 160 extends in the second direction and connects one adjacent end of the multiple third sub-grooves 1311 to the fourth sub-grooves 1312, and the other of the two third connecting grooves 160 extends in the second direction and connects one adjacent end of the multiple fifth sub-grooves 1313 to the fourth sub-grooves 1312, thereby connecting the multiple third sub-grooves 1311 and the multiple fifth sub-grooves 1313, and preventing interference between the insulated gate bipolar transistor region 1011 and the fast recovery diode main conductive region 1012 during the manufacturing process.

[0053] In some embodiments, two of the multiple fourth sub-grooves 1312 located on either side in the second direction are the fifth boundary groove 13121 and the sixth boundary groove 13122, respectively. Thus, the fifth boundary groove 13121, the sixth boundary groove 13122, and the two third connection grooves 160 are all located within the fast recovery diode region 1014. The area enclosed by the fifth boundary groove 13121, the sixth boundary groove 13122, and the two third connection grooves 160 is the fast recovery diode main conduction region 1012, and the portion of the fast recovery diode region 1014 located outside the fast recovery diode main conduction region 1012 is the fast recovery diode transition region 1013.

[0054] As described above, the active region 101 of the semiconductor device 100 includes an insulated gate bipolar transistor region 1011, a fast recovery diode main conduction region 1012, and a fast recovery diode transition region 1013. The first connection groove 140, the third connection groove 160, and the fast recovery diode transition region 1013 can all exert a separating effect on the insulated gate bipolar transistor region 1011 and the fast recovery diode main conduction region 1012. This more effectively and reliably prevents interference between the insulated gate bipolar transistor region 1011 and the fast recovery diode main conduction region 1012 during the manufacturing process, guarantees the performance of the insulated gate bipolar transistor region 1011 and the fast recovery diode main conduction region 1012, and further improves the reliability of the semiconductor device 100.

[0055] As shown in Figure 5, the dielectric layer 113 may mainly include a first dielectric layer 1131, the first dielectric layer 1131 corresponding to the insulated gate bipolar transistor region 1011 and the fast recovery diode main conductive region 1012. , the Multiple spaced contact holes 11311 are provided in the dielectric layer 1131, and the emitter metal layer 114 penetrates the contact holes 11311 and contacts the first main surface 181. The dielectric layer 113 may further include a second dielectric layer 1132. The second dielectric layer 1132 corresponds to the fast recovery diode transition region 1013. The second dielectric layer 1132 is a continuous layer and is interposed between the emitter metal layer 114 and the first main surface 181.

[0056] Specifically, the dielectric layer 113 protects the well region 111 and reduces the risk of damage to the semiconductor device 100. By aligning the first dielectric layer 1131 with the insulated gate bipolar transistor region 1011 and the fast recovery diode main conduction region 1012, and by creating a plurality of spaced-apart contact holes 11311 in the first dielectric layer 1131, the emitter metal layer 114 can penetrate the contact holes 11311 and contact the emitter metal layer 114 or the well region 111 of the first main surface 181, ensuring the normal current derivation of the insulated gate bipolar transistor region 1011 and the fast recovery diode main conduction region 1012, and ensuring the normal operation of the insulated gate bipolar transistor region 1011 and the fast recovery diode main conduction region 1012.

[0057] In some embodiments, by making the second dielectric layer 1132 correspond to the fast recovery diode transition region 1013 and by making the second dielectric layer 1132 a continuous layer, the dielectric layer 113 can be interposed between the emitter metal layer 114 and the first main surface 181. As a result, the dielectric layer 113 can more reliably protect the first main surface 181 of the transition region and improve the structural reliability of the fast recovery diode transition region 1013.

[0058] As shown in Figure 3, at least a portion of one of the two first connecting grooves 140 connects one end of the third sub-groove 1311 away from the fourth sub-groove 1312, and at least a portion of the other of the two first connecting grooves 140 connects one end of the fifth sub-groove 1313 away from the fourth sub-groove 1312.

[0059] Specifically, the second groove 130 may mainly include a second main groove 132, and there may be multiple second main grooves 132. The second groove 130 may further include multiple second spacing grooves 131, and each of the multiple second main grooves 132 is located on both sides of the multiple second spacing grooves 131 in the second direction, and one end of the multiple second main grooves 132 and the end of the third sub-groove 1311 away from the fourth sub-groove 1312 are both flush with each other, and the other end of the multiple second main grooves 132 and the end of the fifth sub-groove 1313 away from the fourth sub-groove 1312 are both flush with each other.

[0060] The two first connecting grooves 140 connect one end of the plurality of second grooves 130 and the other end of the plurality of second grooves 130. That is, if one of the two first connecting grooves 140 extends in the second direction, a portion of it connects one end of the plurality of third sub-grooves 1311 away from the fourth sub-groove 1312, and the other portion connects one end of the plurality of second main grooves 132. If the other first connecting groove 140 extends in the second direction, at least a portion of it connects one end of the plurality of fifth sub-grooves 1313 away from the fourth sub-groove 1312, and the other portion connects the other end of the plurality of second main grooves 132. This ensures that the first connecting grooves 140 close the fast recovery diode main conductive region 1012 and the transient region, thereby ensuring the operational performance of the semiconductor device 100.

[0061] Furthermore, the first groove 120, the second groove 130, the first connecting groove 140, the second connecting groove 150, and the third connecting groove 160 all have the same internal process, and an oxide insulating layer 170 can be generated inside each of them to deposit polysilicon 171. In addition, the first groove 120, the second groove 130, the first connecting groove 140, the second connecting groove 150, and the third connecting groove 160 can be set to the same width and depth. As a result, the first groove 120, the second groove 130, the first connecting groove 140, the second connecting groove 150, and the third connecting groove 160 are etched simultaneously, simplifying the process steps of the semiconductor device 100.

[0062] As shown in FIG. 4, the distance in the first direction between the first connection groove 140 and the second connection groove 150 is D1, the distance in the first direction between the first connection groove 140 and the third connection groove 160 is D2, and D1 and D2 satisfy the relational expression D1 < D2.

[0063] Specifically, the second connection groove 150 is located between the insulated gate bipolar transistor region 1011 and the fast recovery diode transition region 1013, the third connection groove 160 is located between the fast recovery diode transition region 1013 and the fast recovery diode main conduction region 1012, and the first connection groove 140 is located within the fast recovery diode transition region 1013 and between the second connection groove 150 and the third connection groove 160.

[0064] By making the distance in the first direction between the first connection groove 140 and the second connection groove 150 the same as the distance in the second direction of the plurality of first grooves 120, the manufacturing of the first connection groove 140 and the second connection groove 150 can be facilitated. Also, by making the distance in the first direction between the first connection groove 140 and the second connection groove 150 smaller than the distance in the first direction between the first connection groove 140 and the third connection groove 160, the area of the fast recovery diode transition region 1013 can be increased, and the partitioning effect on the insulated gate bipolar transistor region 1011 and the fast recovery diode main conduction region 1012 can be improved.

[0065] In some embodiments, D2 satisfies the relational expression D2 ≥ 30 μm. Specifically, by setting the distance in the first direction between the first connection groove 140 and the third connection groove 160 to be 30 μm or more, the area of the fast recovery diode transition region 1013 can be set within a reasonable range, avoiding the situation where the area of the fast recovery diode transition region 1013 is too small, more effectively partitioning the insulated gate bipolar transistor region 1011 and the fast recovery diode main conduction region 1012, avoiding interference between the two regions in the manufacturing process, ensuring the performance of each of the two regions, and improving the reliability of the semiconductor device 100.

[0066] Furthermore, the greater the distance between the first connection groove 140 and the third connection groove 160 in the first direction, the better the separation effect on the insulated gate bipolar transistor region 1011 and the fast recovery diode main conduction region 1012. However, this also increases the overall area of ​​the semiconductor device 100. Therefore, in actual production, an appropriate distance between the first connection groove 140 and the third connection groove 160 in the first direction can be selected according to the actual application scene and needs, thereby achieving a balance between the separation effect on the insulated gate bipolar transistor region 1011 and the fast recovery diode main conduction region 1012 and the overall area of ​​the semiconductor device 100.

[0067] The manufacturing method of the semiconductor device 100 will be explained exemplified below with reference to Figures 6 to 12, and the semiconductor device 100 is an RC-IGBT.

[0068] As shown in Figure 6, an N-based material is provided to form structure 1.

[0069] As shown in Figure 7, based on structure 1, the first groove 120, second groove 130, first connecting groove 140, second connecting groove 150, and third connecting groove 160 are etched, and an oxide insulating layer 170 is grown within the first groove 120, second groove 130, first connecting groove 140, second connecting groove 150, and third connecting groove 160 to form structure 2.

[0070] As shown in Figure 8, polysilicon 171 is deposited based on structure 2 to form structure 3.

[0071] As shown in Figure 9, polysilicon 171 is etched based on structure 3 to form structure 4.

[0072] As shown in Figure 10, based on structure 4, the P-well region 111 and the N+ emitter layer 112 are sequentially injected to form structure 5.

[0073] As shown in Figure 11, a dielectric layer 113 is deposited based on structure 5, and contact holes 11311 are etched into the dielectric layer 113 to form structure 6.

[0074] As shown in Figure 12, based on structure 6, the emitter metal layer 114 is manufactured by metal layer sputtering, followed by the injection of a backside N+ field stop layer 115, injection of a backside P+ collector layer 116, injection of a backside FRD region N+ short circuit region 117, laser annealing, and the manufacturing of a collector metal layer 118 by backside metal sputtering. Finally, a semiconductor device 100 as in structure 7 is formed.

[0075] Other configurations and operations of the semiconductor device 100 according to some embodiments of this disclosure are known to those skilled in the art and are therefore omitted from further description.

[0076] RC-IGBTs (reverse conducting-insulated gate bipolar transistors) integrate IGBTs (insulated gate bipolar transistors) and FRDs (fast recovery diodes) on the same chip, possessing both forward and reverse conducting properties simultaneously. They offer many advantages, including small size, high power density, low cost, and high reliability.

[0077] In related technologies, the structure of RC-IGBTs often involves dividing the grooves to form an FRD region, thereby separating the IGBT region from the FRD region. However, in this case, the FRD region is susceptible to the manufacturing process, such as IGBT region injection, which degrades the performance of the FRD region and, consequently, the RC-IGBT.

[0078] In some embodiments of the present disclosure, two first connecting grooves are provided, one connecting one end of a plurality of second grooves in a first direction and the other connecting the other end of a plurality of second grooves in a first direction, the first connecting grooves are connected to one end of a second groove adjacent to a dummy gate groove, and the second connecting grooves are connected to one end of a gate groove adjacent to a second groove in a gate groove group, thereby preventing the insulated gate bipolar transistor region and the fast recovery diode region from interfering with each other during the manufacturing process, ensuring the performance of each of the two regions, improving the current guiding capability of the semiconductor device, and thus improving the operating performance of the semiconductor device.

[0079] Hereinafter, semiconductor devices 200 according to several embodiments of the present disclosure will be described with reference to Figures 13 to 22. The semiconductor device 100 may be an RC-IGBT. In the following description, N and P indicate the conductivity type of the semiconductor, and in this application, the first conductivity type is described as N-type and the second conductivity type as P-type.

[0080] As shown in Figures 13 to 19, the semiconductor device 200 of this application may mainly include a substrate 280, which is a base member of the semiconductor device 100 according to this application, and the substrate 280 can provide a base for mounting to at least some other components of the semiconductor device 100.

[0081] The semiconductor device 200 of this application may further include a drift layer 210 of a first conductivity type, specifically, the drift layer 210 of a first conductivity type is installed in a substrate 280 and is located between a first main surface 281 and a second main surface 282, a well region 211 of a second conductivity type is further installed in the substrate 280, the well region 211 is installed on the side of the drift layer 210 closer to the first main surface 281, a second emitter layer 212 of a first conductivity type is further installed in the well region 211, a field stop layer 215 of a first conductivity type is further installed in the substrate 280, the field stop layer 215 is installed on the side of the drift layer 210 closer to the second main surface 282, and a collector layer 216 of a second conductivity type and a first emitter layer 217 of a first conductivity type are installed on the side of the field stop layer 215 closer to the second main surface 282. Furthermore, a dielectric layer 213 is placed on the first main surface 281, an emitter metal layer 214 is placed on the side of the dielectric layer 213 away from the first main surface 281, and a collector metal layer 218 is further placed on the second main surface 282 of the substrate 280. In this way, the basic structure of the semiconductor device 200 can be constructed.

[0082] Here, the semiconductor device 200 may include an active region. The semiconductor device 200 may further include a termination region located around the active region, the region corresponding to the collector layer 216 being an insulated-gate bipolar transistor region 201, and the region corresponding to the first emitter layer 217 being a fast-recovery diode region 202, that is, the active region of the semiconductor device 200 includes the insulated-gate bipolar transistor region 201 and the fast-recovery diode region 202, and the emitter metal layer 214 is only the emitter lead of the insulated-gate bipolar transistor region 201. Furthermore, the collector metal layer 218 may also serve as the anode lead of the fast recovery diode region 202, and the collector metal layer 218 may serve not only as the collector lead of the insulated gate bipolar transistor region 201 but also as the cathode lead of the fast recovery diode region 202. In this way, the insulated gate bipolar transistor region 201 enables forward conduction of the semiconductor device 200, and the fast recovery diode region 202 enables reverse conduction of the semiconductor device 200, thereby giving the semiconductor device 200 both forward and reverse conduction characteristics.

[0083] In some embodiments, the semiconductor device 200 of this application may further mainly include a first groove 220 which extends from a first main surface 281 to a second main surface 282 and reaches into the drift layer 210, the first groove 220 which extends in a first direction, a plurality of first grooves 220 which are spaced apart in a second direction, a portion of the plurality of first grooves 220 which are spacing grooves 221 which are spaced apart in a first direction It may mainly include two sub-groove sections 2221, each sub-groove section 2221 may include a plurality of gate groove groups 2222 and a plurality of dummy gate grooves 2223, the plurality of gate groove groups 2222 are spaced apart in a second direction, at least one dummy gate groove 2223 is placed between two adjacent gate groove groups 2222, and each gate groove group 2222 includes at least two gate grooves 22221 spaced apart in a second direction.

[0084] Specifically, both the gate groove 22221 and the dummy gate groove 2223 are fitted with an oxide insulating layer 270, and further coated with polysilicon 271. Here, the second emitter layer 212 is fitted on both sides of the gate groove 22221 in the second direction, and the gate groove 22221 has a conductive channel and is electrically connected to the gate electrode, which can ensure the normal operation of the insulated gate bipolar transistor region 201 and thus the semiconductor device 200. However, the dummy gate groove 2223 does not have the second emitter layer 212 fitted on both sides in the second direction and does not have current-conducting capability. The dummy gate groove 2223 is electrically connected to the emitter and, assuming that the breakdown voltage capability of the semiconductor device 200 is ensured, reduces Miller capacitance and current density, thereby improving the short-circuit capability of the semiconductor device 200.

[0085] In some embodiments, the semiconductor device 200 of this application mainly includes a second groove 230, which extends from the first main surface 281 to the second main surface 282 and reaches into the drift layer 210, and the second groove 230 extends in a first direction, and multiple second grooves 230 are installed and correspond to multiple first spacing grooves 221, thereby not only ensuring that the junction depth and doping concentration of the well region 211 of the insulated gate bipolar transistor region 201 and the fast recovery diode region 202 are the same, and that the two regions have the same breakdown voltage, but also simplifying the manufacturing process of the semiconductor device 200, and by installing the second groove 230 between two sub-grooves 2221 in a first direction, the insulated gate bipolar transistor region 201 and the fast recovery diode region 202 are separated, ensuring the performance of each of the two regions, and thus ensuring the operational performance of the semiconductor device 200.

[0086] Furthermore, the number of second grooves 230 may be multiple, and the number of first grooves 230 may be greater than the number of first spacing grooves 221. This allows some of the first grooves 230 to correspond to multiple first spacing grooves 221, and also reduces the amount of substrate 280 used, thereby lowering the manufacturing cost of the semiconductor device 200 of this application.

[0087] As shown in Figures 13 to 15, the semiconductor device 200 may further include a first connecting groove 240 which extends from a first main surface 281 to a second main surface 282 and reaches into the drift layer 210, the first connecting groove 240 is extended in a second direction, there are two first connecting grooves 240, one of which connects one end of a plurality of second grooves 230 in a first direction, and the other of which connects the other end of a plurality of second grooves 230 in a first direction, and the first connecting groove 240 is connected to one end of a dummy gate groove 2223 adjacent to a second groove 230.

[0088] Specifically, the multiple second grooves 230 have one end flush with each other and the other end flush with each other, a first connecting groove 240 is installed, the first connecting groove 240 extends from the first main surface 281 to the second main surface 282 and reaches into the drift layer 210, the first connecting groove 240 is extended in a second direction, and two first connecting grooves 240 are installed, so that one of the two first connecting grooves 240 extends in a second direction and connects one end of the multiple second grooves 230, and the other extends in a second direction and connects the other ends of the multiple second grooves 230.

[0089] The two first connection grooves 240 close off the multiple second grooves 230, meaning the two first connection grooves 240 can separate the insulated gate bipolar transistor region 201 and the fast recovery diode region 202, preventing the insulated gate bipolar transistor region 201 and the fast recovery diode region 202 from interfering with each other during the manufacturing process and ensuring the performance of each of the two regions. On the other hand, the two first connection grooves 240 can increase the current conduction capability of the fast recovery diode region 202, thereby improving the operating performance of the semiconductor device 200 and enhancing the reliability of the semiconductor device 200.

[0090] In some embodiments, considering that the dummy gate groove 2223 and the second groove 230 are at the same potential and both the dummy gate groove 2223 and the second groove 230 are connected to the emitter electrode, connecting one end of the dummy gate groove 2223 adjacent to the second groove 230 to the first connecting groove 240 enables the connection between the dummy gate groove 2223 and the second groove 230 by the first connecting groove 240, facilitating the connection between each of the dummy gate groove 2223 and the second groove 230 and the emitter electrode, which not only simplifies the production process of the semiconductor device 200 but also improves the current guiding capability of the semiconductor device 200 in some embodiments.

[0091] As shown in Figures 13 to 15, the semiconductor device 200 may further include a second connecting groove 250, which extends from the first main surface 281 to the second main surface 282 and reaches into the drift layer 210, the second connecting groove 250 extends in a second direction, and connects one end adjacent to the second groove 230 of the gate groove 22221 in the gate groove group 2222.

[0092] Specifically, one end of each gate groove group 2222 adjacent to the second groove 230 of the gate groove 22221 is flush with the surface, and by installing the second connecting groove 250, if the second connecting groove 250 extends along the second direction, it is possible to connect the end of the gate groove 22221 adjacent to the second groove 230 in the gate groove group 2222, which not only improves the current guiding capability of the semiconductor device 200 but also closes the end of the gate groove group 22221 adjacent to the second groove 230 in the gate groove group 2222, thereby preventing the gate groove group 2222 and the second groove 230 from interfering with each other during the manufacturing process, that is, preventing the insulated gate bipolar transistor region 201 and the fast recovery diode region 202 from interfering with each other during the manufacturing process, and ensuring the performance of each of the two regions.

[0093] Thus, the two first connection grooves 240 connect one end of the multiple second grooves 230 in the first direction, and the other end of the multiple second grooves 230 in the first direction. The first connection grooves 240 are connected to one end of the dummy gate groove 2223 adjacent to the second groove 230, and the second connection grooves 250 are connected to one end of the gate groove 22221 in the gate groove group 2222 adjacent to the second groove 230. This prevents the insulated gate bipolar transistor region 201 and the fast recovery diode region 202 from interfering with each other during the manufacturing process, ensuring the performance of each of the two regions, improving the current conduction capability of the semiconductor device 200, and thus improving the operating performance of the semiconductor device 200.

[0094] As shown in Figures 13 to 15, one end of the dummy gate groove 2223 adjacent to the second groove 230 protrudes from the other end of the gate groove 22221 adjacent to the second groove 230, and the other end of the dummy gate groove 2223 adjacent to the second groove 230 extends into the second groove 230 and connects to the first connecting groove 240.

[0095] Specifically, assuming that one end of the dummy gate groove 2223 adjacent to the second groove 230 protrudes from the other end of the gate groove 22221 adjacent to the second groove 230, and that a second connecting groove 250 is installed to connect the gate grooves 22221 in each gate groove group 2222, extending one end of the dummy gate groove 2223 adjacent to the second groove 230 into the second groove 230 and connecting the dummy gate groove 2223 to the first connecting groove 240 facilitates the connection between the dummy gate groove 2223 and the corresponding second groove 230 and emitter, thereby simplifying the manufacturing process of the semiconductor device 200, improving the current guidance capability of the semiconductor device 200, and enhancing the operational performance of the semiconductor device 200.

[0096] As shown in Figures 13 to 15, the multiple second grooves 230 may include the first sub-grooves 232, and there may be multiple first sub-grooves 232. The multiple first sub-grooves 232 and the multiple dummy gate grooves 2223 correspond to and are connected to each other. In this way, not only can the circuit distribution of the semiconductor device 200 be made more uniform, but the dummy gate grooves 2223 and the corresponding first sub-grooves 232 can be etched synchronously, and the manufacturing process of the semiconductor device 200 can be simplified.

[0097] In some embodiments, as shown in Figures 13 to 15, the plurality of second grooves 230 may further include second sub-grooves 231, and there may be a plurality of second sub-grooves 231. The plurality of second sub-grooves 231 and the plurality of gate grooves 22221 correspond to each other in a first direction and are spaced apart from each other. In this way, while avoiding interference between the second sub-grooves 231 and the gate grooves 22221 during the manufacturing process, the circuit distribution of the semiconductor device 200 can be made more uniform, improving the operating performance of the semiconductor device 200. Furthermore, it is easier to synchronously etch the gate grooves 22221 and the corresponding second sub-grooves 231, simplifying the manufacturing process of the semiconductor device 200.

[0098] In addition, in some other embodiments of this application, as shown in Figures 16 and 17, if there is no dummy gate groove 2223 between two adjacent gate groove groups 2222, that is, if no dummy gate groove 2223 is installed in the insulated gate bipolar transistor region 201 and only gate grooves 22221 are present, then the multiple gate grooves 22221 of each sub-groove portion 2221 may be understood to form one gate groove group 2222, and the second connecting groove 250 is the second groove 230 of the multiple gate grooves 22221 By connecting adjacent ends, the two first connection grooves 240 can be configured such that one connects one end of the multiple second grooves 230 in the first direction, and the other connects the other end of the multiple second grooves 230 in the first direction. This not only prevents the insulated gate bipolar transistor region 201 and the fast recovery diode region 202 from interfering with each other during the manufacturing process and ensures the performance of each region, but also increases the current guiding capability of the two regions and improves the operating performance of the semiconductor device 200.

[0099] As described above, of the multiple second grooves 230, the two on either side in the second direction are defined as the first boundary groove 233 and the second boundary groove 234, respectively. Thus, the area enclosed by the first boundary groove 233, the second boundary groove 234 and the two first connection grooves 240 is the fast recovery diode region 202, and the area outside the area enclosed by the first boundary groove 233, the second boundary groove 234 and the two first connection grooves 240 is the insulated gate bipolar transistor region 201.

[0100] Considering that the first connection groove 240 is located at the boundary between the fast recovery diode region 202 and the insulated gate bipolar transistor region 201, by positioning the first connection groove 240 and the second connection groove 250 spaced apart in the first direction, the insulated gate bipolar transistor region 201 and the fast recovery diode region 202 are separated, more effectively and reliably preventing interference between the insulated gate bipolar transistor region 201 and the fast recovery diode region 202 during the manufacturing process. This not only ensures the performance of the insulated gate bipolar transistor region 201 and the fast recovery diode region 202, but also increases the current conduction capability of the semiconductor device 200 and improves the operating performance of the semiconductor device 200.

[0101] As shown in Figures 14 and 15, the distance between the first connecting groove 240 and the second connecting groove 250 in the first direction is D1, the distance between two adjacent first grooves 220 in the second direction is D2, and the distance between two adjacent second grooves 230 in the second direction is D3, so that D1, D2, and D3 satisfy the relationship D1=D2=D3.

[0102] Specifically, by setting the distance between the first connection groove 240 and the second connection groove 250 in the first direction, the distance between two adjacent first grooves 220 in the second direction, and the distance between two adjacent second grooves 230 in the second direction to be equal, the distribution of the first connection grooves 240 and the second connection grooves 250 can be made more uniform, thereby improving the uniformity of the circuit distribution of the semiconductor device 200 and improving the operating performance of the semiconductor device 200.

[0103] Furthermore, the first groove 220, the second groove 230, the first connecting groove 240, and the second connecting groove 250 all have the same internal process, and can all generate an oxide insulating layer 270 inside and deposit polysilicon 271. In addition, the first groove 220, the second groove 230, the first connecting groove 240, and the second connecting groove 250 can be set to the same width and depth. As a result, the first groove 220, the second groove 230, the first connecting groove 240, and the second connecting groove 250 are etched simultaneously, simplifying the process steps of the semiconductor device 200.

[0104] In some embodiments, D1 satisfies the relationship 1.5 μm ≤ D1 ≤ 2 μm. Here, D1 may be specifically set to 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, or 1.9 μm, and this application does not limit the specific numerical value of D1. This allows the distance between the first connection groove 240 and the second connection groove 250 in the first direction to be set within a reasonable range. This prevents interference between the insulated gate bipolar transistor region 201 and the fast recovery diode region 202 during the manufacturing process, as the separation effect between the insulated gate bipolar transistor region 201 and the fast recovery diode region 202 is poor if the distance between the first connection groove 240 and the second connection groove 250 in the first direction is too small. It also prevents the overall area of ​​the semiconductor device 200 from becoming too large if the distance between the first connection groove 240 and the second connection groove 250 in the first direction is too large. In this way, a balance can be achieved between the separation effect between the insulated gate bipolar transistor region 201 and the fast recovery diode region 202 and the overall area of ​​the semiconductor device 200. In some embodiments, this allows for the optimization of the structural design of the semiconductor device 200 and improves its operational performance.

[0105] The manufacturing method of the semiconductor device 200 will be explained below with reference to Figures 15 and 18-22, and the semiconductor device 200100 is an RC-IGBT.

[0106] As shown in Figure 18, an N-based material is provided, forming structure 1.

[0107] As shown in Figure 19, based on structure 1, the first groove 220, the second groove 230, the first connecting groove 240, and the second connecting groove 250 are etched, and then an oxide insulating layer 270 is grown to form structure 2.

[0108] As shown in Figure 20, based on structure 2, polysilicon 271 is deposited and etched, and then the P-well region 211 and the N+ second emitter layer 212 are sequentially injected to form structure 3.

[0109] As shown in Figure 21, a dielectric layer 213 is deposited based on structure 3, and contact holes are etched into the dielectric layer 213 to form structure 4.

[0110] As shown in Figure 22, based on structure 4, a metal layer sputtering is performed to manufacture an emitter metal layer 214 and form structure 5.

[0111] As shown in Figure 15, based on structure 5, the following steps are sequentially performed: injection of the back surface N+ field stop layer 215, injection of the back surface P+ collector layer 216, injection of the back surface FRD region N+ first emitter layer 217, laser annealing, and manufacturing of the collector metal layer 218 by back surface metal sputtering. Finally, the semiconductor device 200 is formed.

[0112] Other configurations and operations of the semiconductor device 200 according to some embodiments of this disclosure are known to those skilled in the art and are therefore omitted from further description.

[0113] RC-IGBTs (reverse conducting-insulated gate bipolar transistors) integrate IGBTs (insulated gate bipolar transistors) and FRDs (fast recovery diodes) on the same chip, possessing both forward and reverse conducting properties simultaneously. They offer many advantages, including small size, high power density, low cost, and high reliability.

[0114] In related technologies, the structure of RC-IGBTs often involves dividing the grooves to form an FRD region, thereby separating the IGBT region from the FRD region. However, in this case, the FRD region is susceptible to the manufacturing process, such as IGBT region injection, which degrades the performance of the FRD region and, consequently, the RC-IGBT.

[0115] In some embodiments of the present disclosure, the semiconductor device 300 has two first connection grooves, one connecting one end of a plurality of second grooves in a first direction and the other connecting the other end of a plurality of second grooves in a first direction, and the second connection grooves connect one end adjacent to the second groove of a gate groove in a gate groove group, and one end adjacent to the second groove of two adjacent gate groove groups. This prevents the insulated gate bipolar transistor region and the fast recovery diode region from interfering with each other during the manufacturing process, ensuring the performance of each of the two regions, improving the current guiding capability of the semiconductor device, and thus improving the operating performance of the semiconductor device.

[0116] Hereinafter, semiconductor devices 300 according to several embodiments of the present disclosure will be described with reference to Figures 23 to 32. The semiconductor device 300 may be an RC-IGBT. In the following description, N and P indicate the conductivity type of the semiconductor, and in this application, the first conductivity type is described as N-type and the second conductivity type as P-type.

[0117] As shown in Figures 23 to 25, the semiconductor device 300 of this application may mainly include a substrate 380, which is a base member of the semiconductor device 300 according to this application, and the substrate 380 can provide a base for mounting to at least some other components of the semiconductor device 300.

[0118] The semiconductor device 300 of this application may further include a drift layer 310 of a first conductivity type, specifically, the drift layer 310 of a first conductivity type is installed in a substrate 380 and is located between a first main surface 381 and a second main surface 382, ​​a well region 311 of a second conductivity type is further installed in the substrate 380, the well region 311 is installed on the side of the drift layer 310 closer to the first main surface 381, a second emitter layer 312 of a first conductivity type is further installed in the well region 311, a field stop layer 315 of a first conductivity type is further installed in the substrate 380, the field stop layer 315 is installed on the side of the drift layer 310 closer to the second main surface 382, ​​and a collector layer 316 of a second conductivity type and a first emitter layer 317 of a first conductivity type are installed on the side of the field stop layer 315 closer to the second main surface 382. Furthermore, a dielectric layer 313 is provided on the first main surface 381, an emitter metal layer 314 is provided on the side of the dielectric layer 313 away from the first main surface 381, and a collector metal layer 318 is provided on the second main surface 382 side of the substrate 380. In this way, the basic structure of the semiconductor device 300 can be constructed.

[0119] The semiconductor device 300 may include an active region. The semiconductor device 300 may further include a termination region located around the active region, the region corresponding to the collector layer 316 being an insulated gate bipolar transistor region 301, and the region corresponding to the first emitter layer 317 being a fast recovery diode region 302, that is, the active region of the semiconductor device 300 includes the insulated gate bipolar transistor region 301 and the fast recovery diode region 302, and the emitter metal layer 314 is the emitter lead-out of the insulated gate bipolar transistor region 301. Furthermore, the collector metal layer 318 may also serve as the anode lead of the fast recovery diode region 302, and the collector metal layer 318 may serve not only as the collector lead of the insulated gate bipolar transistor region 301 but also as the cathode lead of the fast recovery diode region 302. In this way, the insulated gate bipolar transistor region 301 enables forward conduction of the semiconductor device 300, and the fast recovery diode region 302 enables reverse conduction of the semiconductor device 300, so that the semiconductor device 300 has both forward and reverse conduction characteristics.

[0120] In some embodiments, the semiconductor device 300 of this application may further mainly include a first groove 320 which extends from a first main surface 381 to a second main surface 382 and reaches into the drift layer 310, the first groove 320 which extends in a first direction, a plurality of first grooves 320 which are spaced apart in a second direction, a portion of the plurality of first grooves 320 which are spacing grooves 321 which are spaced apart in a first direction It may mainly include two sub-groove sections 3221, each of which may include a plurality of gate groove groups 3222 and a plurality of dummy gate grooves 3223, the plurality of gate groove groups 3222 being spaced apart in a second direction, at least one dummy gate groove 3223 being placed between two adjacent gate groove groups 3222, and the gate groove group 3222 including at least two gate grooves 32221 being spaced apart in a second direction.

[0121] Specifically, both the gate groove 32221 and the dummy gate groove 3223 are fitted with an oxide insulating layer 370 and have polysilicon 371 deposited on them. Here, the second emitter layer 312 is fitted on both sides of the gate groove 32221 in the second direction, and the gate groove 32221 has a conductive channel and is electrically connected to the gate electrode, which can ensure the normal operation of the insulated gate bipolar transistor region 301 and thus the semiconductor device 300. However, the dummy gate groove 2223 does not have the second emitter layer 212 fitted on both sides in the second direction and does not have current-conducting capability. The dummy gate groove 2223 is electrically connected to the emitter and, assuming that the breakdown voltage capability of the semiconductor device 200 is ensured, reduces Miller capacitance and current density to improve the short-circuit capability of the semiconductor device 200.

[0122] In some embodiments, the semiconductor device 300 of this application mainly includes a second groove 330, which extends from the first main surface 381 to the second main surface 382 and reaches into the drift layer 310, the second groove 330 extends in a first direction, and multiple second grooves 330 are provided and correspond to multiple first spacing grooves 321. This not only ensures that the junction depth and doping concentration of the well region 311 of the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 are the same, so that the two regions have the same breakdown voltage, but also simplifies the manufacturing process of the semiconductor device 300. Furthermore, by providing the second groove 330 between two sub-groove portions 3221 in a first direction, the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 are separated, ensuring the performance of each of the two regions and thus guaranteeing the operational performance of the semiconductor device 300.

[0123] As shown in Figures 23 to 25, the semiconductor device 300 may further include a first connecting groove 340 which extends from a first main surface 381 to a second main surface 382 and reaches into the drift layer 310, the first connecting groove 340 which extends in a second direction, and there are two first connecting grooves 340, one of which connects one end of a plurality of second grooves 330 in a first direction, and the other of which connects the other end of a plurality of second grooves 330 in a first direction.

[0124] Specifically, the multiple second grooves 330 have one end flush with each other and the other end flush with each other, a first connecting groove 340 is installed, the first connecting groove 340 extends from the first main surface 381 to the second main surface 382 and reaches into the drift layer 310, the first connecting groove 340 is extended in a second direction, and two first connecting grooves 340 are installed, so that one of the two first connecting grooves 340 extends in a second direction and connects one end of the multiple second grooves 330, and the other extends in a second direction and connects the other ends of the multiple second grooves 330.

[0125] The two first connection grooves 340 close off the multiple second grooves 330, that is, the two first connection grooves 340 can separate the insulated gate bipolar transistor region 301 and the fast recovery diode region 302, preventing the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 from interfering with each other during the manufacturing process and ensuring the performance of each of the two regions. On the other hand, the two first connection grooves 340 can increase the current conduction capability of the fast recovery diode region 302, thereby improving the operating performance of the semiconductor device 300 and enhancing the reliability of the semiconductor device 300.

[0126] As shown in Figures 23 and 24, the semiconductor device 300 may further include a second connecting groove 350, the second connecting groove 350 extending from the first main surface 381 to the second main surface 382 and reaching into the drift layer 310, the second connecting groove 350 extending in a second direction, the second connecting groove 350 connecting one adjacent end to the second groove 330 of gate groove 32221 in gate groove group 3222, and connecting one adjacent end to the second groove 330 of two adjacent gate groove groups 3222.

[0127] Specifically, one end of each gate groove group 3222 adjacent to the second groove 330 of the gate groove 32221 is flush with the surface, and by installing the second connecting groove 350, if the second connecting groove 350 is extended along the second direction, it can connect one end of the gate groove 32221 adjacent to the second groove 330 in the gate groove group 3222. Furthermore, the ends adjacent to the second groove 330 of multiple gate grooves 32221 in two adjacent gate groove groups 3222 are flush with the surface, and the second connecting groove 350 connects one end of the gate groove 32221 adjacent to the second groove 330 in the gate groove group 3222, and can extend further to connect one end adjacent to the second groove 330 of two adjacent gate groove groups 3222.

[0128] In other words, the second connecting groove 350 can connect one end adjacent to the second groove 330 of all gate grooves 32221 in the sub-groove section 3221, and the second connecting groove 350 can leave all gate grooves 32221 in the sub-groove section 3221 outside. This not only improves the current guiding capability of the insulated gate bipolar transistor region 301 and thus the semiconductor device 300, but also closes one end adjacent to the second groove 330 of each gate groove group 3222, preventing the gate groove group 3222 and the second groove 330 from interfering with each other during the manufacturing process, and preventing the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 from interfering with each other during the manufacturing process, thereby ensuring the performance of each of the two regions.

[0129] In this way, one of the two first connecting grooves 340 connects one end of the multiple second grooves 330 in the first direction, the other connects the other end of the multiple second grooves 330 in the first direction, the second connecting groove 350 connects one end adjacent to the second groove 330 of gate groove 32221 in gate groove group 3222, and connects one end adjacent to the second groove 330 of two adjacent gate groove groups 3222. This prevents the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 from interfering with each other during the manufacturing process, ensuring the performance of each of the two regions, improving the current conduction capability of the semiconductor device 300, and thus improving the operating performance of the semiconductor device 300.

[0130] As shown in Figures 23 and 24, one end of gate groove 32221 adjacent to the second groove 330 protrudes from the other end of dummy gate groove 3223 adjacent to the second groove 330, and the dummy gate groove 3223 and the second connecting groove 350 are separated from each other in the first direction.

[0131] Specifically, one end of gate groove 32221 adjacent to the second groove 330 protrudes beyond the other end of dummy gate groove 3223 adjacent to the second groove 330, and the other end of dummy gate groove 3223 adjacent to the second groove 330 and the second connection groove 350 are also spaced apart in a first direction. This allows the second connection groove 350 to separate the dummy gate groove 3223 and the first connection groove 340 in a first direction, preventing the dummy gate groove 3223 and the first connection groove 340 or the second groove 330 from interfering with each other during the manufacturing process. In some embodiments, this prevents the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 from interfering with each other during the manufacturing process, thus ensuring the performance of each of the two regions.

[0132] In some embodiments, the semiconductor device 300 may further include a third connecting groove 360 ​​which extends from a first main surface 381 to a second main surface 382 and reaches into the drift layer 310, the third connecting groove 360 ​​which extends in a second direction and has at least two dummy gate grooves 3223 between two adjacent gate groove groups 3222, and the third connecting groove 360 ​​connects one end adjacent to the second groove 330 of the dummy gate groove 3223 between the two adjacent gate groove groups 3222.

[0133] Specifically, when at least two dummy gate grooves 3223 are installed between two adjacent gate groove groups 3222, at least two dummy gate grooves 3223 between the two adjacent gate groove groups 3222 have one end adjacent to the second groove 330 flush with the third connecting groove 360, and the third connecting groove 360 ​​extends in the second direction and is installed spaced apart from the second connecting groove 350 in the second direction, and in this way the third connecting groove 360 ​​extends in the second direction and has one end adjacent to the second groove 330 of the dummy gate groove 3223 between the two adjacent gate groove groups 3222 The ends can be connected, thereby connecting all dummy gate grooves 3223 between two adjacent gate groove groups 3222, allowing the third connecting groove 360 ​​to perform its current-guiding function and improving the current-guiding capability of the semiconductor device 300. Furthermore, one end of the dummy gate groove 3223 between two adjacent gate groove groups 3222 that is adjacent to the second groove 330 can be closed, preventing the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 from interfering with each other during the manufacturing process in some embodiments, thereby ensuring the operational performance of the semiconductor device 300.

[0134] As shown in Figure 24, the multiple second grooves 330 may include a first sub-groove 331, and the multiple first sub-grooves 331 correspond to a multiple gate groove 32221 and are spaced apart from each other. The multiple second grooves 330 may further include two sub-grooves 332, and the multiple second sub-grooves 332 and the multiple dummy gate grooves 3223 correspond to each other and are spaced apart from each other. In this way, while preventing the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 from interfering with each other during the manufacturing process, the circuit distribution of the semiconductor device 300 can be made more uniform, improving the operating performance of the semiconductor device 300. Furthermore, it is easier to synchronously etch the first sub-grooves 331 and the corresponding gate grooves 32221, and to synchronously etch the second sub-grooves 332 and the corresponding dummy gate grooves 3223, thereby simplifying the manufacturing process of the semiconductor device 300.

[0135] In addition, in some other embodiments of this application, as shown in Figures 28 and 29, if there is no dummy gate groove 3223 between two adjacent gate groove groups 3222, that is, if no dummy gate groove 3223 is installed in the insulated gate bipolar transistor region 301 and only gate grooves 32221 are present, then it is not necessary to install a third connection groove 360 ​​in the semiconductor device 300. The second connection groove 350 connects one adjacent end of the second groove 330 of the multiple gate grooves 32221, and the two first connection grooves 340 can be connected, one to one end of the multiple second grooves 330 in the first direction and the other to the other end of the multiple second grooves 330 in the first direction. This not only prevents the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 from interfering with each other during the manufacturing process and ensures the performance of each of the two regions, but also increases the current guiding capability of the two regions and improves the operating performance of the semiconductor device 300.

[0136] As described above, of the multiple second grooves 330, the two on either side in the second direction are defined as the first boundary groove 333 and the second boundary groove 334, respectively. Thus, the area enclosed by the first boundary groove 333, the second boundary groove 334 and the two first connection grooves 340 is the fast recovery diode region 302, and the area outside the area enclosed by the first boundary groove 333, the second boundary groove 334 and the two first connection grooves 340 is the insulated gate bipolar transistor region 301.

[0137] Considering that the first connection groove 340 is located at the boundary between the fast recovery diode region 302 and the insulated gate bipolar transistor region 301, by positioning the first connection groove 340 and the second connection groove 350 spaced apart in the first direction, the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 are separated, effectively and reliably preventing interference between the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 during the manufacturing process. This not only ensures the performance of the insulated gate bipolar transistor region 301 and the fast recovery diode region 302, but also increases the current conduction capability of the semiconductor device 300 and improves the operating performance of the semiconductor device 300.

[0138] As shown in Figures 24 and 25, the distance between the first connecting groove 340 and the second connecting groove 350 in the first direction is D1, the distance between two adjacent first grooves 320 in the second direction is D2, and the distance between two adjacent second grooves 330 in the second direction is D3, so that D1, D2, and D3 satisfy the relationship D1=D2=D3.

[0139] Specifically, by setting the distance between the first connection groove 340 and the second connection groove 350 in the first direction, the distance between two adjacent first grooves 320 in the second direction, and the distance between two adjacent second grooves 330 in the second direction to be equal, the distribution of the first connection grooves 340 and the second connection grooves 350 can be made more uniform, improving the uniformity of the circuit distribution of the semiconductor device 300 and improving the operating performance of the semiconductor device 300.

[0140] Furthermore, the first groove 320, the second groove 330, the first connecting groove 340, the second connecting groove 350, and the third connecting groove 360 ​​all have the same internal process, and can all generate an oxide insulating layer 370 inside and deposit polysilicon 371. In addition, the first groove 320, the second groove 330, the first connecting groove 340, the second connecting groove 350, and the third connecting groove 360 ​​can be set to the same width and depth. As a result, the first groove 320, the second groove 330, the first connecting groove 340, the second connecting groove 350, and the third connecting groove 360 ​​are etched simultaneously, simplifying the process steps of the semiconductor device 300.

[0141] In some embodiments, D1 satisfies the relationship 1.5 μm ≤ D1 ≤ 2 μm. Here, D1 may be specifically set to 1.5 μm, 1.6 μm, 1.7 μm, 1.8 μm, or 1.9 μm, and this application does not limit the specific numerical value of D1. This allows the distance between the first connection groove 340 and the second connection groove 350 in the first direction to be set within a reasonable range. This prevents the distance between the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 from being too small, which would cause them to interfere with each other during the manufacturing process. It also prevents the overall area of ​​the semiconductor device 300 from becoming too large, which would cause the distance between the first connection groove 340 and the second connection groove 350 to be too small. In this way, a balance can be achieved between the separation effect on the insulated gate bipolar transistor region 301 and the fast recovery diode region 302 and the overall area of ​​the semiconductor device 300. In some embodiments, this allows for the optimization of the structural design of the semiconductor device 300 and improves its operational performance.

[0142] The manufacturing method of the semiconductor device 300 will be explained below with reference to Figures 25 and 28-32, and the semiconductor device 300 is an RC-IGBT.

[0143] As shown in Figure 28, prepare an N-based material. Form structure 1.

[0144] As shown in Figure 29, based on structure 1, the first groove 320, the second groove 330, the first connecting groove 340, the second connecting groove 350, and the third connecting groove 360 ​​are etched, and an oxide insulating layer 370 is further grown to form structure 2.

[0145] As shown in Figure 30, based on structure 2, polysilicon 371 is deposited and etched, and then the P-well region 311 and the N+ second emitter layer 312 are sequentially injected to form structure 3.

[0146] As shown in Figure 31, a dielectric layer 313 is deposited based on structure 3, and contact holes are etched into the dielectric layer 313 to form structure 4.

[0147] As shown in Figure 32, based on structure 4, a metal layer sputtering is performed to manufacture an emitter metal layer 314 and form structure 5.

[0148] As shown in Figure 25, based on structure 5, the following steps are sequentially performed: injection of the back surface N+ field stop layer 315, injection of the back surface P+ collector layer 316, injection of the back surface FRD region N+ first emitter layer 317, laser annealing, and manufacturing of the collector metal layer 318 by back surface metal sputtering. Finally, the semiconductor device 300 is formed.

[0149] Other configurations and operations of the semiconductor device 300 according to some embodiments of this disclosure are known to those skilled in the art and are therefore omitted from further description.

[0150] With the advancement of science and technology, the applications of semiconductor devices are becoming increasingly broad. In the design and manufacture of semiconductor devices, grooves are incorporated, and gates are formed in these grooves to ensure the proper operation of the semiconductor device.

[0151] In related technologies, grooves often form stripes, but the electrostatic protection of semiconductor devices is easily lost at the edges of the grooves, resulting in reduced stability and reliability of the semiconductor device.

[0152] In some embodiments of the present disclosure, a connecting groove is provided, the connecting groove is provided in a ring layer and extends in a second direction, the connecting groove is located at the edge of the active region of the semiconductor device, and the connecting groove connects at least one end of at least two gate grooves in each gate groove group, thereby optimizing the electric field distribution of the semiconductor device and improving the electrostatic protection capability and dielectric breakdown voltage capability of the semiconductor device, as well as improving the turn-on speed and reducing turn-on losses of the semiconductor device.

[0153] Hereinafter, semiconductor devices 400 according to several embodiments of the present disclosure will be described with reference to Figures 33 to 42. In the following description, N and P indicate the conductivity type of the semiconductor, and in this application, the first conductivity type is described as P-type and the second conductivity type as N-type.

[0154] As shown in Figures 33 to 38, the semiconductor device 400 of this application mainly comprises a semiconductor substrate 410, the substrate 410 being the base member of the semiconductor device 400, and the substrate 410 can provide a base for mounting to at least some other components of the semiconductor device 400. Here, the semiconductor substrate 410 has a first main surface 401 and a second main surface 402 opposite to the first main surface 401.

[0155] The semiconductor device 400 of this application may further include a drift layer 411, which is placed between a first main surface 401 and a second main surface 402.

[0156] The semiconductor device 400 of this application may further include a ring layer 412, which is also installed on the semiconductor substrate 410 and located between the first main surface 401 and the second main surface 420. Specifically, the ring layer 412 is installed on the side of the drift layer 411 facing the first main surface 401, and the surface of the ring layer 412 away from the drift layer 411 constitutes part of the first main surface 401. (That is, the ring layer 412 is placed on the upper surface of the drift layer 411.)On top of the ring layer 412, an oxide insulating layer 413, a polycrystalline layer 414, and an interlayer dielectric layer 415 are further stacked, and a field stop layer 417 and a collector layer 418 are further placed below the drift layer 411.

[0157] A main groove 420 may be further provided in the ring layer 412 of the semiconductor device 400 of this application, and the main groove 420 extends in a first direction. (That is, the main groove 420 extends in the first direction, penetrating from the upper surface of the ring layer 412 into the ring layer 412.) This allows a gate electrode to be formed in the main groove 420, and by placing the emitter metal layer 416 on top of the interlayer dielectric layer 415 and a collector metal layer (not shown) below the collector layer 418, the basic structure of the semiconductor device 400 can be formed, and the normal operation of the semiconductor device 400 can be guaranteed.

[0158] The main groove 420 may mainly include a plurality of gate groove groups 423, which are spaced apart in a second direction and perpendicular to the second direction in a first direction. The main groove 420 may further include a plurality of dummy gate grooves 422, with at least one dummy gate groove 422 installed between two adjacent gate groove groups 423, and each gate groove group 423 includes at least two gate grooves 421 that are spaced apart in a second direction.

[0159] Specifically, both the gate groove 421 and the dummy gate groove 422 are fitted with an oxide insulating layer 413 and have polysilicon deposited. However, a first conductivity type dopant is injected into the gate groove 421 and a second conductivity type well region is provided. The gate groove 421 may have a gate formed in it, has a conductive channel, has current-conducting capability, and ensures the normal operation of the semiconductor device 400. The dummy gate groove 422 does not have a first conductivity type dopant injected into it, does not have a second conductivity type well region, does not have a conductive channel, and does not have current-conducting capability. The dummy gate groove 422 is connected to the emitter electrode, which can reduce the Miller capacitance and decrease the current density.

[0160] At least two gate grooves 421 form one gate groove group 423, and at least one dummy gate groove 422 forms one dummy gate groove group 424. Furthermore, multiple gate groove groups 423 and dummy gate groove groups 424 are installed, and the multiple gate groove groups 423 and multiple dummy gate groove groups 424 are installed sequentially and alternately spaced apart in a second direction. This allows the multiple gate grooves 421 and multiple dummy gate grooves 422 to be installed more rationally in the second direction, and in some embodiments, the operating performance of the semiconductor device 400 can be improved.

[0161] As shown in Figures 33 to 36 and Figure 38, the semiconductor device 400 of this application further includes a connecting groove 430, which is installed in the ring layer 412 and extends in a second direction. (That is, the connecting groove 430 extends in the second direction, penetrating from the upper surface of the ring layer 412 into the ring layer 412.) The connecting groove 430 is located at the edge of the active region 403 of the semiconductor device 400. (Specifically, the main groove 420 is located in the active region 403 and extends to the edge of the active region 403.) The connecting groove 430 connects at least one end of at least two gate grooves 421 in each gate groove group 423, and the first direction is perpendicular to the second direction.

[0162] Specifically, at least two gate grooves 421 in each gate groove group 423 are spaced apart in the second direction, that is, the ends of at least two gate grooves 421 in each gate groove group 423 are also spaced apart in the second direction, and considering that the electric field distribution is concentrated in the region where the ends of the gate grooves 421 are located, the electric field distribution is non-uniform, electrostatic discharge protection failure is likely to occur, and dielectric breakdown withstand voltage is low, the connecting groove 430 is installed in the ring layer 412, and the connecting groove 430 is Extending in two directions, the connecting groove 430 is located at the edge of the active region 403 of the semiconductor device 400, and the connecting groove 430 connects at least one end of at least two gate grooves 421 in each gate groove group 423, so that within each gate groove group 423, the connecting groove 430 surrounds at least one end of its at least two gate grooves 421 in the first direction, and the connecting groove 430 can be connected to at least two gate grooves 421 in each gate groove group 423.

[0163] On the other hand, the connecting groove portion 430 surrounds the outside of at least two ends of gate groove portions 421 in each gate groove group 423, optimizing the electric field distribution at the ends of at least two gate groove portions 421 in each gate groove group 423, making the electric field distribution at the ends of at least two gate groove portions 421 in each gate groove group 423 more uniform, effectively improving the electrostatic protection capability of the semiconductor device 400, preventing electrostatic discharge breakdown at the ends of the main groove portion 420, improving the dielectric breakdown capability of the semiconductor device 400, and ultimately improving the reliability of the semiconductor device 400.

[0164] On the other hand, the connecting groove 430 may also serve as a gate passage, which can increase the number of gate passages, thereby improving the turn-on speed of the semiconductor device 400 and reducing turn-on losses.

[0165] As a result, a connecting groove 430 is provided, which is located in the ring layer 412 and extends in a second direction, is located at the edge of the active region 403 of the semiconductor device 400, and connects at least one end of at least two gate grooves 421 in each gate groove group 423, thereby optimizing the electric field distribution of the semiconductor device 400, improving the electrostatic protection capability and dielectric breakdown withstand voltage capability of the semiconductor device 400, as well as improving the turn-on speed of the semiconductor device 400 and reducing turn-on losses.

[0166] As shown in Figure 38, at least two gate grooves 421 in each gate groove group 423 are each provided with connecting grooves 430. Specifically, each gate groove 421 has both ends in a first direction, and at least two gate grooves 421 in each gate groove group 423 are each provided with connecting grooves 430. This allows one connecting groove 430 to connect at least two gate grooves 421 to communicate with each other, and the other connecting groove 430 to connect at least two gate grooves 421 to communicate with each other. As a result, all ends of each gate groove group 423 are connected to the connecting grooves 430, avoiding the existence of any ends that are not connected to each gate groove group 423. In some embodiments, this optimizes the electric field distribution of the semiconductor device 400, improves the electrostatic discharge protection capability and dielectric breakdown capability of the semiconductor device 400, and improves the turn-on speed of the semiconductor device 400.

[0167] Furthermore, the semiconductor device 400 may further include a gate pad 440, which is connected to the gate and used as a gate lead-out end. Since the gate groove 421 and the dummy gate groove 422 are separated by the gate pad 440, a connecting groove 430 can also be provided at the end of the gate groove group 423 closest to the gate pad 440. By connecting the connecting groove 430 to the end of the gate groove group 423 closest to the gate pad 440, the electrostatic discharge protection capability of the semiconductor device 400 can be more reliably improved, and the turn-on speed of the semiconductor device 400 can be increased.

[0168] In some embodiments of this application, a dummy gate groove 422 is provided between at least two gate grooves 421 in each gate groove group 423. Specifically, a dummy gate groove 422 may be provided between at least two gate grooves 421 in each gate groove group 423, and the length of the dummy gate groove 422 in the first direction is less than or equal to the length of the gate groove 421, thereby preventing the provision of the dummy gate groove 422 from affecting the connection of the connecting groove 430 to at least one end of at least two gate grooves 421 in each gate groove group 423.

[0169] In one specific embodiment of this application, as shown in Figure 38, each gate groove group 423 may mainly include two gate groove portions 421, and a connecting groove portion 430 connects at least one end of the two gate groove portions 421 in each gate groove group 423. Specifically, each gate groove group 423 may mainly include two gate groove portions 421, and a connecting groove portion 430 connects at least one end of the two gate groove portions 421 in each gate groove group 423, thereby allowing for a more rational arrangement of the number of gate groove portions 421 in each gate groove group 423 and facilitating the installation of the groove portions 430.

[0170] As shown in Figures 33 to 35, the connecting groove 430 connects at least one end of a plurality of gate groove groups 423.

[0171] Specifically, when the connecting groove 430 connects at least two gate grooves 421 in each gate groove group 423, the electric field distribution of the semiconductor device 400 can be optimized to some extent, improving the electrostatic protection capability and dielectric breakdown capability of the semiconductor device 400. However, considering that the multiple gate groove groups 423 are not yet in communication with each other, and each gate groove group 423 still has an end region in the second direction where the electric field is still concentrated, there is still room to improve the electrostatic protection capability and dielectric breakdown capability of the semiconductor device 400.

[0172] By connecting at least one end of a plurality of gate groove groups 423, the connecting groove 430 can be easily connected to at least one end of all gate grooves 421 of the semiconductor device 400, and the connecting groove 430 can surround at least one end of all gate grooves 421 of the semiconductor device 400, thereby enabling the connecting groove 430 to communicate with at least one end of all gate grooves 421 of the semiconductor device 400.

[0173] On the other hand, the connecting groove portion 430 surrounds the outside of all the ends of the gate groove portions 421, optimizing the electric field distribution at all the ends of the gate groove portions 421 and making the electric field distribution at all the ends of the gate groove portions 421 more uniform. Not only does this prevent electric field concentration at all the ends of the gate groove portions 421, but it also increases the gate oxide film thickness at all the ends of the gate groove portions 421, effectively improving the electrostatic protection capability of the semiconductor device 400, preventing electrostatic discharge breakdown at the ends of the gate groove portions 421, and improving the reliability of the semiconductor device 400.

[0174] On the other hand, the connecting groove 430 can be used as a gate passage, increasing the number of gate passages, which can improve the turn-on speed of the semiconductor device 400, reduce turn-on losses, and improve the operating performance of the semiconductor device 400.

[0175] Furthermore, in order to ensure that the current is properly discharged, it is necessary to install contact holes 419 in the semiconductor device 400. The contact holes 419 connect the gate electrode to other materials to realize the function of the circuit. By installing connection grooves 430 and connecting the connection grooves 430 to the ends of multiple gate grooves 421, the normal operation of the semiconductor device 400 can be ensured. The contact holes 419 can be directly installed in the connection grooves 430, making it easier to manufacture the contact holes 419 and thus reducing the difficulty of manufacturing the contact holes 419 and the semiconductor device 400.

[0176] In this way, the electric field distribution of the semiconductor device 400 can be optimized, improving its electrostatic protection capability. Furthermore, the turn-on speed of the semiconductor device 400 can be increased, turn-on losses can be reduced, and the manufacturing difficulty of the semiconductor device 400 can be lowered.

[0177] In some embodiments of this application, as shown in Figures 33 to 35, the length of the gate groove 421 in the first direction is greater than the length of the dummy gate groove 422 in the first direction, and both ends of the gate groove 421 in the first direction protrude beyond both ends of the dummy gate groove 422 in the first direction. The connecting groove 430 and the dummy gate groove 422 are spaced apart from each other (specifically, The connecting groove 430 is elongated and spaced apart from the dummy gate groove 422.

[0178] Specifically, considering that the dummy gate groove 422 has no conductive ability and that electrostatic discharge does not occur at the ends of the dummy gate groove 422, if the length of the gate groove 421 in the first direction is greater than the length of the dummy gate groove 422 in the first direction, and both ends of the gate groove 421 in the first direction protrude beyond both ends of the dummy gate groove 422 in the first direction, then it is sufficient to connect the connecting groove 430 to each gate groove group 423, eliminating the need to connect multiple dummy gate groove groups 424. The connecting groove 430 is long and spaced apart from the dummy gate groove 422, thereby improving the electrostatic discharge protection capability of the semiconductor device 400, increasing the turn-on speed of the semiconductor device 400, and reducing the manufacturing cost of the semiconductor device 400.

[0179] In some other embodiments of this application, the connecting groove 430 connects at least one end of a plurality of gate groove groups 423 and a plurality of dummy gate grooves 422. Specifically, the connecting groove 430 can connect at least one end of a plurality of gate groove groups 423 and a plurality of dummy gate grooves 422, that is, the connecting groove 430 can connect at least one end of all of the main grooves 420, thereby making it easy to create the connecting groove 430 on the premise of optimizing the electric field distribution of the semiconductor device 400, and reducing the difficulty of manufacturing the semiconductor device 400.

[0180] In some embodiments, the length of the dummy gate groove 422 in the first direction is equal to the length of the gate groove 421 in the first direction, and both ends of the gate groove 421 in the first direction are flush with both ends of the dummy gate groove 422 in the first direction. Specifically, when the length of the dummy gate groove 422 of the semiconductor device 400 in the first direction is equal to the length of the gate groove 421 in the first direction, and both ends of the gate groove 421 in the first direction are flush with both ends of the dummy gate groove 422 in the first direction, the connecting groove 430 can be directly connected between the end of the gate groove 421 and the end of the dummy gate groove 422, the connecting groove 430 penetrates the active region 403 of the semiconductor device 400 in the first direction, and the structure of the semiconductor device 400 is simpler and more reliable.

[0181] In other embodiments of this application, the connecting groove 430 connects at least one end of a plurality of dummy gate grooves 422. Specifically, assuming that the connecting groove 430 is installed to connect at least one end of a plurality of gate grooves 421 in each gate groove group 423, the connecting groove 430 may be installed separately and connect at least one end of a plurality of dummy gate grooves 422 between two adjacent gate groove groups 423. This allows the connecting groove 430 to optimize the electric field distribution at at least one end of the plurality of dummy gate grooves 422, avoid electric field concentration, and improve the reliability of the semiconductor device 400. At the same time, the connecting groove 430 and the dummy gate grooves 422 can be easily designed individually, expanding the application scenarios of the semiconductor device 400.

[0182] In some embodiments, the length of the dummy gate groove 422 in the first direction is greater than the length of the gate groove 421 in the first direction, and both ends of the dummy gate groove 422 in the first direction protrude beyond both ends of the gate groove 421 in the first direction. Specifically, when the length of the dummy gate groove 422 of the semiconductor device 400 in the first direction is greater than the length of the gate groove 421 in the first direction, and both ends of the dummy gate groove 422 in the first direction protrude beyond both ends of the gate groove 421 in the first direction, a connecting groove 430 can be individually installed within each gate groove group 423, and a connecting groove 430 can also be individually installed between multiple dummy gate grooves 422 between two adjacent gate groove groups 423, thereby preventing mutual influence between the two and ensuring the electrostatic discharge protection capability and dielectric breakdown withstand voltage capability of the semiconductor device 400.

[0183] As shown in Figures 36 and 37, both the main groove 420 and the connecting groove 430 extend in the direction from the first main surface 401 toward the second main surface 402. In the direction from the first main surface 401 toward the second main surface 402, the depth of the main groove 420 is L, and the depth of the connecting groove 430 is L2, and L1 and L2 satisfy the relationship L1 ≤ L2.

[0184] Specifically, the connecting groove 430 is installed such that its depth is greater than or equal to the depth of the main groove 420 in the direction from the first main surface 401 to the second main surface 402. In this way, the connecting groove 430 can completely connect to the main groove 420 in the direction from the first main surface 401 to the second main surface 402. This avoids the problem where the depth of the connecting groove 430 is insufficient, preventing communication between the lower part of the main groove 420 and the connecting groove 430, resulting in an uneven electric field distribution below the main groove 420 and making the electrostatic protection of the semiconductor device 400 still prone to failure. Thus, optimization of the electric field at each position of the end of the main groove 420 can be guaranteed, and in some embodiments, the electrostatic protection capability of the semiconductor device 400 can be improved.

[0185] As shown in Figures 36 and 37, the width of the main groove 420 in the second direction is W1, and the width of the connecting groove 430 in the first direction is W2, and W1 and W2 satisfy the relationship: W1 ≤ W2.

[0186] Specifically, the width of the connecting groove 430 in the first direction affects the size of the passage of the connecting groove 430. By setting the width of the connecting groove 430 in the first direction to be greater than or equal to the width of the main groove 420 in the second direction, the passage capacity of the connecting groove 430 can be increased in some embodiments, assuming that the gate passage is increased by the connecting groove 430. This improves the turn-on speed of the semiconductor device 400 and reduces losses in the semiconductor device 400 in some embodiments.

[0187] In some embodiments, the depth of the connecting groove 430 may be set to be the same as the depth of the main groove 420 in the direction from the first main surface 401 to the second main surface 402, and the width of the connecting groove 430 in the first direction may be set to be the same as the width of the main groove 420 in the second direction. This improves the electrostatic protection capability of the semiconductor device 400 and, assuming an improvement in the switching speed of the semiconductor device 400, facilitates synchronous etching of the main groove 420 and the connecting groove 430. Furthermore, because the structures are identical or nearly identical, the complexity of processing can be reduced and production efficiency can be improved.

[0188] As shown in Figures 36 and 37, both the main groove 420 and the connecting groove 430 are installed at a distance from the drift layer 411. Specifically, the main groove 420 and the connecting groove 430 are formed by etching on the ring layer 412, and by installing both the main groove 420 and the connecting groove 430 at a distance from the drift layer 411, that is, by not penetrating the ring layer 412 and installing the main groove 420 and the connecting groove 430 at a distance from the drift layer 411, it is possible to guarantee the presence of a field ring layer 412 between the main groove 420 and the connecting groove 430 and the drift layer 411, thereby guaranteeing the electrical performance of the semiconductor device 400.

[0189] As shown in Figures 33 and 35, the semiconductor substrate 410 may include an active region 403. The semiconductor substrate 410 may further include a termination region 404, the termination region 404 being located outside the active region 403, the main groove 420 being located in the active region 403, and the connecting groove 430 being located between the active region 403 and the termination region 404.

[0190] Specifically, the active region 403 can bear most of the forward current when conducting forward and bear a high cutoff voltage when a reverse voltage is applied, while the termination region 404 can alleviate electric field congestion at the edge of the active region 403 when a reverse voltage is applied to the semiconductor device 400, thereby achieving the objective of improving the reverse breakdown voltage of the semiconductor device 400.

[0191] In some embodiments, the main groove 420 is located in the active region 403, the end of the main groove 420 is located between the active region 403 and the termination region 404, and the connecting groove 430 is located between the active region 403 and the termination region 404. The connecting groove 430 can block the diffusion of the electric field in the active region 403, thereby more effectively and reliably preventing the loss of electrostatic protection in the region between the active region 403 and the termination region 404, and improving the electrostatic protection capability of the semiconductor device 400.

[0192] The semiconductor device 40 is described below with reference to Figures 39 to 42. 0 The manufacturing method is illustrated below.

[0193] As shown in Figure 39, a base is provided, which is an N-type drift layer 411, and a P-type dopant is further injected onto the substrate to form an N-type drift layer 411 and a P-type ring layer 412.

[0194] As shown in Figure 40, the connecting groove portion 430 is etched into the ring layer 412, and an oxide insulating layer 413 is grown on top of the ring layer 412.

[0195] As shown in Figure 41, polysilicon deposition and polycrystalline etching are performed on the oxide insulating layer 413 to form a polycrystalline layer 414.

[0196] As shown in Figure 42, an interlayer dielectric layer 415 is formed by growing an interlayer dielectric layer 414 on top of the polycrystalline layer 414, an emitter metal layer 416 is formed by metal sputtering on top of the interlayer dielectric layer 415, a field stop layer 417, a collector layer 418 and a collector metal layer are fabricated below the drift layer 411, and finally the semiconductor device 400 is formed.

[0197] Furthermore, this manufacturing method, using the manufacturing of the connecting groove 430 as an example, can simultaneously etch the connecting groove 430 on the ring layer 412 and synchronously etch the main groove 420, but this will not be explained here. Also, this manufacturing method only shows a part of the manufacturing process, and other configurations and operations of the semiconductor device 400 according to some embodiments of this disclosure are known to those skilled in the art, so a detailed explanation will not be provided here.

[0198] A person skilled in the art can make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if such modifications and modifications of this application fall within the scope of the claims of this application and the equivalent art, this application is intended to include such changes and modifications. (Other possible items) (Item 1) A semiconductor device, A substrate having a first principal surface and a second principal surface on the side opposite to the first principal surface, A first conductive drift layer is placed between the first main surface and the second main surface, A first groove extending from the first main surface to the second main surface and reaching into the drift layer, wherein the first groove extends in a first direction and there are multiple first grooves, the multiple first grooves are spaced apart in a second direction, a portion of the multiple first grooves is a first spacing groove, the first spacing groove is multiple, and the first groove includes a first sub-groove and a second sub-groove that are spaced apart in the first direction, A second groove extending from the first main surface to the second main surface and reaching into the drift layer, wherein the second groove extends in a first direction and there are multiple second grooves, and the second groove is installed spaced apart between the first sub-groove and the second sub-groove in the first direction, A first connecting groove extending from the first main surface to the second main surface and reaching into the drift layer, wherein the first connecting groove extends in a second direction, and there are two first connecting grooves, the two first connecting grooves including one connecting one end of a plurality of second grooves and the other connecting the other end of a plurality of second grooves, Semiconductor equipment. (Item 2) Of the plurality of second grooves, one adjacent to the first groove on one side in the second direction is the first boundary groove, and of the plurality of second grooves, one adjacent to the first groove on the other side in the second direction is the second boundary groove, and the area enclosed by the first boundary groove, the second boundary groove and the two first connection grooves is the fast recovery diode area. Semiconductor device as described in item 1. (Item 3) Of the two first connecting grooves, one corresponding to the first sub-groove is installed at a distance from the first sub-groove, and of the two first connecting grooves, one corresponding to the second sub-groove is installed at a distance from the second sub-groove. Semiconductor device as described in item 2. (Item 4) A second connecting groove extending from the first main surface to the second main surface and reaching into the drift layer, wherein the second connecting groove extends in a second direction, and there are two second connecting grooves, the two second connecting grooves further include a second connecting groove in which one connects one end adjacent to the second groove of a plurality of first sub-grooves, and the other connects one end adjacent to the second groove of a plurality of second sub-grooves. Semiconductor device as described in item 3. (Item 5) The plurality of first grooves include a first main groove and a plurality of first spacing grooves, the first main grooves are plurality and each is located on both sides in the second direction of the plurality of first spacing grooves, and both ends of the second connecting groove in the second direction are connected to the first main grooves on both sides. Semiconductor device as described in item 4. (Item 6) Of the plurality of first main grooves, one adjacent to one side of the plurality of first spacing grooves in the second direction is a third boundary groove, and of the plurality of first main grooves, one adjacent to the other side of the plurality of first spacing grooves in the second direction is a fourth boundary groove, and the area outside the region enclosed by the third boundary groove, the fourth boundary groove and the two second connecting grooves is an insulated gate bipolar transistor region. Semiconductor device as described in item 5. (Item 7) Further including a third connecting groove, A portion of the second groove is a second spacing groove, the second spacing groove includes a third sub-groove, a fourth sub-groove, and a fifth sub-groove, the third sub-groove and the fifth sub-groove are each located at both ends of the fourth sub-groove in the first direction and are each spaced apart from the fourth sub-groove, the third connecting groove extends from the first main surface to the second main surface and reaches into the drift layer, the third connecting groove extends in the second direction, there are two third connecting grooves, one of which connects one end of the plurality of fourth sub-grooves and the other connecting the other end of the plurality of fourth sub-grooves. Semiconductor device as described in item 6. (Item 8) The two third connecting grooves connect one end of a plurality of third sub-grooves adjacent to the fourth sub-grooves, and the other connects one end of a plurality of fifth sub-grooves adjacent to the fourth sub-grooves. Semiconductor device as described in item 7. (Item 9) Of the plurality of fourth sub-grooves, the two fourth sub-grooves located on both sides in the second direction are the fifth boundary groove and the sixth boundary groove, respectively, and the fifth boundary groove, the sixth boundary groove and the two third connection grooves are all located within the fast recovery diode region, and the interior of the region enclosed by the fifth boundary groove, the sixth boundary groove and the two third connection grooves is the fast recovery diode main conduction region. Semiconductor device as described in item 7. (Item 10) In the fast recovery diode region, the portion located outside the fast recovery diode main conductivity region is the fast recovery diode transition region. Semiconductor device as described in item 9. (Item 11) A dielectric layer is provided on the first main surface, and an emitter metal layer is provided on the side of the dielectric layer that is away from the first main surface. The dielectric layer includes a first dielectric layer and a second dielectric layer, the first dielectric layer corresponds to the insulated gate bipolar transistor region and the fast recovery diode main conduction region, the second dielectric layer corresponds to the fast recovery diode transition region, a plurality of spaced-apart contact holes are provided in the first dielectric layer, the emitter metal layer penetrates the contact holes and contacts the first main surface, and the second dielectric layer is a continuous layer interposed between the emitter metal layer and the first main surface. Semiconductor device as described in item 10. (Item 12) At least a part of one of the two first connection grooves connects one end of the third sub-groove away from the fourth sub-groove, and at least a part of the other of the two first connection grooves connects one end of the fifth sub-groove away from the fourth sub-groove. The semiconductor device according to item 7. (Item 13) The distance in the first direction between the first connection groove and the second connection groove is D1, the distance in the first direction between the first connection groove and the third connection groove is D2, and D1 and D2 satisfy the relational expression D1 < D2. The semiconductor device according to item 7. (Item 14) D2 satisfies the relational expression D2 ≥ 30 μm. The semiconductor device according to item 13.

Claims

1. A semiconductor device, A substrate having a first principal surface and a second principal surface on the side opposite to the first principal surface, A first conductive drift layer is installed between the first main surface and the second main surface, A first groove extending from the first main surface to the second main surface and reaching into the drift layer, wherein the first groove extends in a first direction and there are multiple first grooves, the multiple first grooves are spaced apart in a second direction, a portion of the multiple first grooves is a first spacing groove, the first spacing groove is multiple, and the first groove includes a first sub-groove and a second sub-groove that are spaced apart in the first direction, A second groove extending from the first main surface to the second main surface and reaching into the drift layer, wherein the second groove extends in a first direction and there are multiple second grooves, and the second groove is installed spaced apart between the first sub-groove and the second sub-groove in the first direction, A first connecting groove extending from the first main surface to the second main surface and reaching into the drift layer, wherein the first connecting groove extends in a second direction, and there are two first connecting grooves, the two first connecting grooves including one connecting one end of a plurality of second grooves and the other connecting the other ends of the plurality of second grooves, Semiconductor equipment.

2. Of the plurality of second grooves, one adjacent to the first groove on one side in the second direction is the first boundary groove, and of the plurality of second grooves, one adjacent to the first groove on the other side in the second direction is the second boundary groove, and the area enclosed by the first boundary groove, the second boundary groove and the two first connection grooves is the fast recovery diode area. The semiconductor device according to claim 1.

3. Of the two first connecting grooves, one corresponding to the first sub-groove is installed at a distance from the first sub-groove, and of the two first connecting grooves, one corresponding to the second sub-groove is installed at a distance from the second sub-groove. The semiconductor device according to claim 2.

4. A second connecting groove extending from the first main surface to the second main surface and reaching into the drift layer, wherein the second connecting groove extends in a second direction, and there are two second connecting grooves, each of which further includes a second connecting groove, one of which connects one end adjacent to the second groove of a plurality of first sub-grooves, and the other of which connects one end adjacent to the second groove of a plurality of second sub-grooves. The semiconductor device according to claim 3.

5. The plurality of first grooves include a first main groove and a plurality of first spacing grooves, the first main grooves are plurality and each is located on both sides in the second direction of the plurality of first spacing grooves, and both ends of the second connecting groove in the second direction are connected to the first main grooves on both sides. The semiconductor device according to claim 4.

6. Of the plurality of first main grooves, one adjacent to one side of the plurality of first spacing grooves in the second direction is a third boundary groove, and of the plurality of first main grooves, one adjacent to the other side of the plurality of first spacing grooves in the second direction is a fourth boundary groove, and the area outside the region enclosed by the third boundary groove, the fourth boundary groove and the two second connecting grooves is an insulated gate bipolar transistor region. The semiconductor device according to claim 5.

7. Further including a third connecting groove, A portion of the second groove is a second spacing groove, the second spacing groove includes a third sub-groove, a fourth sub-groove, and a fifth sub-groove, the third sub-groove and the fifth sub-groove are each located at both ends of the fourth sub-groove in the first direction and are each spaced apart from the fourth sub-groove, the third connecting groove extends from the first main surface to the second main surface and reaches into the drift layer, the third connecting groove extends in the second direction, there are two third connecting grooves, one of which connects one end of the plurality of fourth sub-grooves and the other connecting the other end of the plurality of fourth sub-grooves. The semiconductor device according to claim 6.

8. The two third connecting grooves are such that one connects one end of a plurality of third sub-grooves adjacent to the fourth sub-grooves, and the other connects one end of a plurality of fifth sub-grooves adjacent to the fourth sub-grooves. The semiconductor device according to claim 7.

9. Of the plurality of fourth sub-grooves, the two fourth sub-grooves located on both sides in the second direction are the fifth boundary groove and the sixth boundary groove, respectively, and the fifth boundary groove, the sixth boundary groove and the two third connection grooves are all located within the fast recovery diode region, and the interior of the region enclosed by the fifth boundary groove, the sixth boundary groove and the two third connection grooves is the fast recovery diode main conduction region. The semiconductor device according to claim 7.

10. In the fast recovery diode region, the portion located outside the fast recovery diode main conductivity region is the fast recovery diode transition region. The semiconductor device according to claim 9.

11. A dielectric layer is provided on the first main surface, and an emitter metal layer is provided on the side of the dielectric layer that is away from the first main surface. The dielectric layer includes a first dielectric layer and a second dielectric layer, the first dielectric layer corresponds to the insulated gate bipolar transistor region and the fast recovery diode main conduction region, the second dielectric layer corresponds to the fast recovery diode transition region, a plurality of spaced-apart contact holes are provided in the first dielectric layer, the emitter metal layer penetrates the contact holes and contacts the first main surface, and the second dielectric layer is a continuous layer interposed between the emitter metal layer and the first main surface. The semiconductor device according to claim 10.

12. At least a portion of one of the two first connecting grooves connects one end of the third sub-groove away from the fourth sub-groove, and at least a portion of the other of the two first connecting grooves connects one end of the fifth sub-groove away from the fourth sub-groove. The semiconductor device according to claim 7.

13. The distance between the first connecting groove and the second connecting groove in the first direction is D1, and the distance between the first connecting groove and the third connecting groove in the first direction is D2, and D1 and D2 satisfy the relationship D1 < D2. The semiconductor device according to claim 7.

14. D2 satisfies the relationship D2 ≥ 30 μm. The semiconductor device according to claim 13.

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