Doping by molecular layer deposition

Abstract

Molecular layer deposition (MLD) is used to provide a uniform doping technique suitable for HAR and reentrant structures. MLD is used to deposit a conformal carbon-based film containing doping elements. Then, thermal annealing is used to diffuse the doping elements into the semiconductor material. For HAR structures, a conformal layer with low-temperature doping and precise control is used, allowing for easy removal of the carbon-based film during or after doping. The amount of doping can be controlled by changing the thickness of the MLD carbon-based film.

Description

[Technical Field]

[0001]

[0001] Embodiments of this disclosure relate to doping technology. In particular, embodiments of this disclosure relate to a method of semiconductor doping by molecular layer deposition (MLD) of conformal films containing doping elements. [Background technology]

[0002]

[0002] Semiconductor technology relies on the ability to tune the electrical properties of a substrate by controllingly introducing substitutional impurities (doping) into the crystal lattice of a semiconductor host material, thereby customizing its electronic, optical, and / or magnetic properties. However, current ex situ doping strategies cannot be easily extended to the nanoscale. As the size of semiconductor devices shrinks to the nanoscale, the assumption of a uniform doping distribution becomes invalid, and the standard random distribution of individual atoms within the semiconductor becomes important. Currently, the scientific community is making great efforts to develop new techniques to demonstrate deterministic doping of semiconductor structures at the nanoscale.

[0003]

[0003] Conventional doping techniques are primarily based on ion implantation, which means irradiating the target semiconductor with ions containing high-energy dopants and then using high-temperature heat treatment to induce the replacement of atoms in the lattice. The main advantage of this technique is that the amount of dopant and the depth distribution of impurity atoms in the semiconductor host can be controlled independently. This approach has been widely studied and has become a staple in microelectronics because it ensures excellent doping uniformity over a wide range of areas.

[0004]

[0004] However, ion implantation technology has several drawbacks, including damage to the crystal lattice during ion bombardment and the promotion of transient diffusion caused by defects during heat treatment. Furthermore, most of the source gases commonly used in ion implantation are harmful from a health and environmental standpoint. Moreover, this technology is incompatible with 3D nanostructure materials because it does not provide dopant incorporation suitable for non-planar nanostructures. Therefore, there is a need in the field of art for improved doping techniques that can precisely control elemental doping into high aspect ratio (HAR) semiconductor structures such as 3D-DRAM and gate-all-around. [Overview of the project]

[0005]

[0005] One or more embodiments of the present disclosure relate to a semiconductor doping method, the method comprising: flowing a first precursor over a substrate including a semiconductor surface and a dielectric surface in order to form a first portion of a carbon-containing layer doped on a semiconductor surface and a dielectric surface, wherein the first precursor comprises a first reactive group; removing a first precursor effluent containing the first precursor from the substrate; flowing a second precursor containing one or more of phosphorus (P), boron (B), aluminum (Al), arsenic (As), gallium (Ga), indium (In), or zinc (Zn) over the substrate in order to react with the first reactive group to form a carbon-containing layer doped on the semiconductor surface and a dielectric surface; and removing a second precursor effluent containing the second precursor from the substrate.

[0006]

[0006] One or more embodiments of the present disclosure relate to a semiconductor doping method, the method comprising flowing a first precursor onto a substrate including a semiconductor surface and a dielectric surface, wherein the first precursor is of general formula R 1 -(X) n (In the formula, R 1Xn comprises one or more alkyl groups, alkenyl groups, aryl groups, aromatic groups, and cycloalkyl groups, and Xn comprises one or more hydroxide groups, aldehyde groups, ketone groups, acid groups, amino groups, isocyanate groups, thiocyanate groups, and acyl chloride groups, and n is an integer in the range of 1 to 6. The first precursor reacts with the reactive groups of one or more semiconductor and dielectric surfaces to form a first portion of a carbon-containing layer doped on one or more semiconductor and dielectric surfaces. The method comprises flowing a precursor, removing a first precursor outflow containing the first precursor from the substrate, and flowing a second precursor onto the substrate, wherein the second precursor comprises one or more of phosphorus (P), boron (B), aluminum (Al), arsenic (As), gallium (Ga), indium (In), and zinc (Zn), and the second precursor reacts with the first part to form a doped carbon-containing layer, and removing a second precursor outflow containing the second precursor from the substrate.

[0007]

[0007] To enable a more detailed understanding of the features of the present disclosure described above, a more detailed description of the present disclosure, which has been briefly summarized above, can be obtained by referring to the embodiments. Some embodiments are shown in the accompanying drawings. However, it should be noted that the accompanying drawings merely illustrate typical embodiments of the present disclosure and should not be considered to limit the scope of the present disclosure, as the present disclosure may also permit other equally valid embodiments. Embodiments described herein are shown in the figures of the accompanying drawings as examples, not as limitations, and similar reference numerals indicate similar elements. [Brief explanation of the drawing]

[0008] [Figure 1]

[0008] A process flow diagram of a semiconductor doping method by molecular layer deposition (MLD) of a conformal film containing a doping element, according to one or more embodiments, is shown. [Figure 2]

[0009] This is a cross-sectional view of a substrate according to one or more embodiments. [Figure 3A]

[0010] Figure 3A shows a cross-sectional view of a substrate according to one or more embodiments. [Figure 3B] Figure 3B shows a cross-sectional view of a substrate according to one or more embodiments. [Figure 4]

[0011] A cross-sectional view of a substrate according to one or more embodiments is shown. [Figure 5]

[0012] A cross-sectional view of a substrate according to one or more embodiments is shown. [Modes for carrying out the invention]

[0009]

[0013] Before describing some exemplary embodiments of the present invention, it should be understood that the present invention is not limited to the configuration or process step details specified in the following description. Other embodiments of the present invention are possible and can be implemented or carried out in various ways.

[0010]

[0014] As used in this book, the term "approximately" means roughly or nearly, and refers to a variation of no more than ±15% of a given number or range. For example, values ​​that differ by only ±14%, ±10%, ±5%, ±2%, or ±1% satisfy the definition of "approximately."

[0011]

[0015] As used herein and in the appended claims, the terms “substrate” or “wafer” refer to the surface or portion of a surface on which a process is performed. Furthermore, unless the context clearly indicates otherwise, a reference to a substrate may refer only to a portion of the substrate. In addition, when a reference is made to deposition on a substrate, it may mean both a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0012]

[0016] As used herein, the term "substrate" or "substrate surface" refers to any part of a substrate or any part of the surface of a material formed on a substrate where film processing is performed. For example, the substrate surface on which processing can be performed may include materials such as silicon, silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. The substrate includes, but is not limited to, semiconductor wafers. The substrate may be subjected to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure, and / or bake the substrate surface. In addition to directly performing film processing on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps may be performed on a lower layer formed on the substrate, as will be disclosed in more detail below, and the term "substrate surface" is intended to include such a lower layer as the context indicates. Thus, for example, when a film / layer or a partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer is the substrate. The substrate may have various dimensional shapes such as wafers with a diameter of 200 mm or 300 mm, and rectangular or square panels. In some embodiments, the substrate includes a rigid individual material.

[0013]

[0017] The term "on" indicates that there is direct contact between elements. The term "directly on" indicates that there is direct contact between elements without intervening elements.

[0014]

[0018] As used in this specification and the appended claims, terms such as "precursor", "reactant", "reactive gas", etc. are used interchangeably to refer to any gas species that can react with the substrate surface.

[0015]

[0019] As used in this specification and the appended claims, terms such as "reactive compound", "reactive gas", "reactive species", "precursor", "process gas" are used interchangeably to mean a substance having species that can react with a substrate or a material on the substrate in a surface reaction (e.g., chemisorption, oxidation, reduction). The substrate or a part of the substrate is continuously exposed to two or more reactive compounds introduced into the reaction zone of the processing chamber.

[0016]

[0020] Carbon-containing materials can be used in the manufacture of semiconductor devices for various structures and processes, including applications such as mask materials, etch-resistant materials, trench filling materials. More detailed application examples of carbon-containing materials include the formation of hot implant hard masks, metal gate (MG) cut hard masks, metal gate manufacturing, reverse stone patterning, self-aligned patterning.

[0017]

[0021] In one or more embodiments, molecular layer deposition (MLD) is used to provide a uniform doping technique suitable for HAR and reentrant structures. MLD is used to deposit a conformal carbon-based film containing doping elements. Next, thermal annealing is used to diffuse the doping elements into the semiconductor material. In the case of HAR structures, a conformal layer with low-temperature doping and precise control is used, and the carbon-based film can be easily removed during or after doping. In one or more embodiments, the amount of doping can be controlled by changing the thickness of the MLD carbon-based film.

[0018]

[0022] In certain embodiments, a carbon-containing film is deposited using molecular layer deposition (MLD). These methods may include flowing a first deposition precursor into the substrate processing region to form a first portion of an initial compound layer. The first deposition precursor can have the general formula R 1 -(X) n (where n is an integer in the range of 1 to 6, and R 1 includes one or more of aryl, aromatic groups, and cycloalkyl groups). X nThis includes one or more hydroxide groups, aldehyde groups, ketone groups, acid groups, amino groups, isocyanate groups, thiocyanate groups, and acyl chloride groups. Specific first deposition precursors include terephthalaldehyde, phenylenediamine, ethylenediamine, hexamethylenediamine, terephthaloyl chloride, 1,3,5-benzenetricarbonyl trichloride, and pyromellitic dianhydride.

[0019]

[0023] These methods may include removing a first deposit waste containing a first deposit precursor from the substrate processing area. The method may also include flowing a second precursor into the substrate processing area. The second precursor includes one or more of phosphorus (P), boron (B), aluminum (Al), arsenic (As), gallium (Ga), indium (In), or zinc (Zn). Specific second precursors can be selected from tris(dimethylamino)phosphine, phosphorus trichloride, phosphorus oxychloride (V), tris(hydroxymethyl)phosphine, boron trichloride, trimethylaluminum, tris(dimethylamino)arsine, trimethylindium, diethylzinc, and the like.

[0020]

[0024] The second precursor can react with the reactive groups of the first precursor to form a second portion of the initial compound layer. The method may include removing the second deposit containing the second precursor from the substrate processing area. The method may also include annealing the initial compound layer to form an annealed, doped carbon-containing material on the surface of the substrate.

[0021]

[0025] In some embodiments, the method may include one or more of the following: etching the MLD film in a non-target region; removing the MLD carbon film; thermal annealing to drive the dopant into the semiconductor layer; and removing the residual MLD layer using wet etching or plasma etching.

[0022]

[0026] Embodiments of this technology include molecular layer deposition (MLD) methods and systems for depositing doped carbon-based films. An exemplary MLD method includes providing a first deposition precursor on the surface of a semiconductor substrate, the precursor forming a first layer (e.g., a first monolayer) on the surface. During or after the formation of the first layer, unbound deposition effluent, which may contain unbound molecules of the first deposition precursor, is removed from the processing area where the semiconductor substrate is exposed. Next, a second deposition precursor is introduced onto the semiconductor substrate, and molecules of the second deposition precursor bind to reactive portions on the first layer to form a second layer (e.g., a second monolayer) on the surface. The second precursor includes one or more of phosphorus (P), boron (B), aluminum (Al), arsenic (As), gallium (Ga), indium (In), or zinc (Zn). During or after the formation of the second layer, unbound deposition effluent, which may contain unbound molecules of the second deposition precursor, is removed from the processing area. A semiconductor substrate is provided with a doped carbon-containing material layer bonded to its surface. Additional compound layers, the first and second layers, can be constructed on top of the deposited layer until the number of constructed compound layers reaches the desired thickness of the doped carbon-containing material on the surface of the semiconductor substrate. The compound layers can then be annealed to introduce one or more of the following into the semiconductor: phosphorus (P), boron (B), aluminum (Al), arsenic (As), gallium (Ga), indium (In), or zinc (Zn).

[0023]

[0027] One or more embodiments offer advantageous solutions to problems associated with conventional doping methods. For example, the technology avoids crystal lattice damage caused by ion implantation during ion bombardment and transient enhanced diffusion caused by defects during subsequent heat treatment. Plasma immersion ion implantation also causes crystal damage, posing challenges for high aspect ratio (HAR) structures, but this can be avoided by the technology of one or more embodiments. Gas-phase doping has fundamental limitations in terms of controlling and achieving uniformity of dopant concentration near the surface. Solid-phase diffusion presents challenges in terms of HAR structures, residue removal, and thermal budget. Therefore, one or more embodiments offer advantageous uniform doping, particularly suited to high aspect ratio (HAR) structures with deep, concave structures such as 3D-DRAM. In some embodiments, a low thermal budget (≤800°C) is possible, and residues can be easily removed after doping.

[0024]

[0028] Embodiments of the present disclosure are illustrated by drawings showing processes for forming devices (e.g., transistors) and semiconductor structures according to one or more embodiments of the present disclosure. The illustrated processes are merely illustrative of possible applications of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the illustrated applications.

[0025]

[0029] A process flow diagram of semiconductor doping method 10 by molecular layer deposition (MLD) of a conformal film containing doping elements is shown according to one or more embodiments. Figures 2 to 5 show cross-sectional views of a semiconductor substrate processed according to the method of one or more embodiments. Referring to Figures 1 and 2 to 5, in one or more embodiments, the substrate is provided in operation 12. As used herein and in the appended claims, the term “provided” means that the substrate is made available for processing (e.g., placed in a processing chamber).

[0026]

[0030] Referring to FIG. 2, in one or more embodiments, the substrate includes a semiconductor surface 102 and a dielectric surface 104. The semiconductor surface 102 may include any suitable semiconductor material known to those skilled in the art. In one or more embodiments, the semiconductor surface 102 includes one or more of silicon (Si), silicon germanium (SiGe), germanium (Ge), silicon carbide (SiC), indium gallium zinc oxide (InGaZnO), and the like.

[0027]

[0031] In one or more embodiments, the dielectric surface 104 may include any suitable dielectric material known to those skilled in the art. As used herein, "dielectric surface" refers to any portion of the substrate or a portion of the material surface formed of a dielectric material. Non-limiting examples of dielectric materials include silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon (Si), silicon oxynitride (SiON), carbides, oxycarbides, nitrides, oxynitrides, oxycarbonitrides, polymers, phosphosilicate glass, silicon oxyfluoride (SiOF) glass, organosilicate glass (SiOCH), aluminum oxide (AlO x ), hafnium oxide (HfO x ), zirconium oxide (ZrO2), titanium oxide (TiO x ), titanium nitride (TiN), tantalum oxide (TaxO3), yttrium oxide (Y2O3), lanthanum oxide (La2O3), aluminum nitride (AlN), magnesium oxide (MgO), calcium fluoride (CaF2), lithium fluoride (LiF), strontium oxide (SrO), barium oxide (BaO), hafnium silicate (HfSiO3), and the like. Lanthanum aluminate (LaAlO3), niobium pentoxide (Nb2O5), barium titanate (BaTiO3), strontium titanate (SrTiO3), bismuth titanate (Bi4Ti3O 12 ), lead zirconate titanate (Pb(Zr,Ti)O3), calcium copper titanate (CaCu3Ti4O 12), lithium niobate (LiNbO3), barium titanate (BaTiO3), potassium niobate (KNbO3). In one or more specific embodiments, the dielectric surface 104 is silicon dioxide (SiO2). x ), silicon carbide (SiOC), silicon carbonitride (SiOCN), silicon nitride (SiN), silicon oxynitride (SiON), aluminum oxide (AlO x ), aluminum nitride (AlN), and hafnium oxide (HfO x ) including one or more of the following.

[0028]

[0032] In one or more embodiments, the substrate on which the carbon-containing material is formed may include a material on which one or more features 103 can be formed. The features 103 of the substrate may be characterized by any shape or configuration according to the Art. In some embodiments, the features 103 may be or include trench structures, via structures, or openings formed in the substrate. While the features 103 of the substrate can be characterized by any shape or size, in some embodiments, the features of the substrate can be characterized by a higher aspect ratio or by the ratio of the depth of the feature 103 to the width of the feature 103. For example, in some embodiments, the features 103 of the substrate can be characterized by an aspect ratio of 5:1 or greater, and can also be characterized by an aspect ratio of 10:1 or greater, 15:1 or greater, 20:1 or greater, 25:1 or greater, 30:1 or greater, 40:1 or greater, 50:1 or greater, or greater. Furthermore, feature 103 can be characterized by narrow widths or diameters such as critical dimensions of 100 nm or less, 90 nm or less, 80 nm or less, 70 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, and 10 nm or less, across the entire feature 103, including between the two sidewalls.

[0029]

[0033] In one or more embodiments, in operation 14, one or more of the semiconductor surface 102 and dielectric surface 104 may be pre-cleaned as necessary. In addition to pre-cleaning the semiconductor surface 102 and / or dielectric surface 104 themselves, in this disclosure, any of the disclosed treatments or pre-treatments may also be performed on the underlying metal surface, and the term “dielectric surface” is intended to include such underlying layers as the context indicates.

[0030]

[0034] In one or more embodiments, the substrate is pre-cleaned by one or more of the following: high-temperature annealing, plasma treatment, and gas annealing. Plasma treatment may include treatment with one or more selected from hydrogen (H2), oxygen (O2), ammonia (NH3), nitrogen (N2), carbon dioxide (CO2), nitrous oxide (N2O), argon (Ar), etc. Gas annealing may include annealing in one or more atmospheres such as hydrogen (H2), oxygen (O2), ozone (O3), nitrous oxide (N2O), water (H2O), hydrogen peroxide (H2O2), etc. In one or more embodiments, the pre-cleaning process of operation 14 removes layers from the substrate.

[0031]

[0035] In some embodiments, the semiconductor surface 102 is cleaned / pre-cleaned with plasma. In some embodiments, the plasma is a conductively coupled plasma (CCP). In some embodiments, the plasma is an inductively coupled plasma (ICP).

[0032]

[0036] Referring to Figures 1 and 3, in operation 16, the first type of precursor is introduced / flowed into the substrate processing area of ​​the processing chamber and onto the substrate surface. The first precursor strongly bonds to the semiconductor surface 102 and the dielectric surface 104.

[0033]

[0037] In one or more embodiments, the first precursor may be a carbon-containing precursor having at least two reactive groups that can form bonds with groups attached to the semiconductor surface 102 and dielectric surface 104 of the substrate. The first precursor molecule reacts with the surface groups of the semiconductor surface 102 and dielectric surface 104 to form bonds that link the first precursor molecule to the semiconductor surface 102 and dielectric surface 104 of the substrate. The reaction between the first precursor molecule and the groups on the semiconductor surface 102 and dielectric surface 104 of the substrate continues until most or all of the surface groups bond to the reactive groups on the first precursor molecule. A first portion 105a of the doped carbon-containing layer 106 is formed, preventing further reaction between the first precursor molecule and the substrate in the first precursor effluent.

[0034]

[0038] The first precursor may include any suitable precursor known to those skilled in the art. In one or more embodiments, the first deposition precursor is a compound of the general formula R 1 -(X) n (In the formula, n is an integer in the range of 1 to 6, R 1 X may have one or more aryl, aromatic, and cycloalkyl groups. n This includes one or more hydroxide groups, aldehyde groups, ketone groups, acid groups, amino groups, isocyanate groups, thiocyanate groups, and acyl chloride groups.

[0035]

[0039] Unless otherwise specified, the terms “lower alkyl,” “alkyl,” or “alk,” used herein alone or as part of another group, include both linear and branched hydrocarbons, typically having 1 to 20 carbon atoms in a chain, or 1 to 10 carbon atoms, such as methyl, ethyl, propyl, isopropyl, butyl, t-butyl, isobutyl, pentyl, hexyl, isohexyl, heptyl, 4,4-dimethylpentyl, octyl, 2,2,4-trimethylpentyl, nonyl, decyl, undecyl, dodecyl, and their various branched isomers. Such groups may optionally contain 1 to 4 substituents. Alkyls may be substituted or unsubstituted.

[0036]

[0040] Such alkyl groups may optionally contain 1 to 4 substituents, such as halo, e.g., F,Br,Cl, or I, or CF3, alkyl, alkoxy, aryl, aryloxy, aryl(aryl) or diaryl, arylalkyl, arylalkyloxy, alkenyl, cycloalkyl, cycloalkylalkyl, cycloalkylalkyloxy, amino, hydroxy, hydroxyalkyl, acyl, heteroaryl, heteroaryloxy, heteroarylalkyl, heteroarylalkoxy, aryloxyalkyl, alkylthio, arylalkylthio, aryloxyaryl, alkylamide, alkanoylamino, arylcarbonylamino, nitro, cyano, thiol, haloalkyl, trihaloalkyl, and / or alkylthio. In one or more embodiments, R is C 1~20 It is selected independently of alkyl. In other embodiments, R is C 1~12 Selected from alkyl groups.

[0037]

[0041] As used herein, the terms “alkene” or “alkenyl” or “lower alkenyl” mean vinyl, 2-propenyl, 3-butenyl, 2-butenyl, 4-pentenyl, 3-pentenyl, 2-hexenyl, 3-hexenyl, 2-heptenyl, 3-heptenyl, 4-heptenyl, 3-octenyl, 3-nonenyl, 4-decenyl, 3-undecenyl, 4-dodecenyl, 4,8,12-tetradecatreenyl, etc., which have 1 to 6 double bonds in a straight chain, and contain 2 to 20 carbon atoms or 2 to 12 carbon atoms in a straight chain. This refers to a linear or branched radical having carbon and 1 to 8 carbon atoms, which may be substituted with 1 to 4 substituents, namely halogens, haloalkyls, alkyls, alkoxys, alkenyls, alkynyls, aryls, arylalkyls, cycloalkyls, aminos, hydroxys, heteroaryls, cycloheteralkyls, alkanoylaminos, alkylamides, arylcarbonyl-aminos, nitros, cyanos, thiols, alkylthios, and / or any of the alkyl substituents described herein.

[0038]

[0042] As used herein, the terms “alkynyl” or “lower alkynyl” refer to linear compounds such as 2-propynyl, 3-butynyl, 2-butynyl, 4-pentynyl, 3-pentynyl, 2-hexynyl, 3-hexynyl, 2-heptynyl, 3-heptynyl, 4-heptynyl, 3-octinyl, 3-noninyl, 4-decinyl, 3-undecinyl, 4-dodecinyl, etc., which have one triple bond in their linear chain and have 2 to 20 carbon atoms, or 2 to 12 carbon atoms, or 2 to 8 carbon atoms in their linear chain. This refers to a chain or branched chain radical, which may be substituted with one to four substituents, namely halogens, haloalkyls, alkyls, alkoxys, alkenyls, alkynyls, aryls, arylalkyls, cycloalkyls, aminos, heteroaryls, cycloheteralkyls, hydroxys, alkanoylaminos, alkylamides, arylcarbonylaminos, nitros, cyanos, thiols, and / or alkylthios, and / or any of the alkyl substituents described herein.

[0039]

[0043] In this specification, the terms "halogen" or "halo," used alone or as part of another group, refer to chlorine, bromine, fluorine, and iodine, as well as CF3.

[0040]

[0044] As used herein, the term “aryl” refers to monocyclic and bicyclic aromatic groups (phenyl, biphenyl, or naphthyl including 1-naphthyl and 2-naphthyl) containing 6 to 10 carbon atoms in the ring portion, which may include 1 to 3 additional rings fused to a carbocyclic or heterocyclic ring (such as an aryl, cycloalkyl, heteroaryl, or cycloheteroalkyl ring). The aryl may be substituted with 1, 2, or 3 substituents through the available carbon atoms, such as hydrogen, halo, haloalkyl, alkyl, haloalkyl, alkoxy, haloalkoxy, alkenyl, trifluoromethyl, trifluoromethoxy, alkynyl, etc.

[0041]

[0045] Specific examples of the first precursor include, but are not limited to, one or more of the following: terephthalaldehyde, phenylenediamine, ethylenediamine, hexamethylenediamine, terephthaloyl chloride, 1,3,5-benzenetricarbonyl trichloride, and pyromellitic dianhydride.

[0042]

[0046] In one or more embodiments, the formation rate of the first portion 105a of the doped carbon-containing layer 106 may depend not only on the substrate temperature but also on the temperature of the deposition precursor flowing into the substrate processing area. Exemplary substrate temperatures during the formation operation may be 50°C or higher, 60°C or higher, 70°C or higher, 80°C or higher, 90°C or higher, 100°C or higher, 110°C or higher, 120°C or higher, 130°C or higher, 140°C or higher, 150°C or higher, or higher. In some embodiments, maintaining a substrate temperature high of about 100°C or higher can increase the number of available nucleation sites along the semiconductor surface 102 of the substrate, improve formation by increasing coverage at each location, and reduce void formation.

[0043]

[0047] The first precursor outflow remains within the substrate processing area for a certain period of time, allowing the first portion 105a of the doped carbon-containing layer 106 to form almost or completely. The precursor material can be supplied in alternating pulses to grow the material. In some embodiments, the pulse time for either or both of the first and second precursors may be 0.1 seconds or more, 1 second or more, 2 seconds or more, 3 seconds or more, 4 seconds or more, 5 seconds or more, 10 seconds or more, 20 seconds or more, 40 seconds or more, 60 seconds or more, 80 seconds or more, 100 seconds or more, or longer.

[0044]

[0048] Referring to Figure 1, in operation 18, after the formation of the first portion 105a of the doped carbon-containing layer 106, the first precursor is purged or removed from the substrate processing area. The effluent of the first precursor can be removed by pumping it out of the substrate deposition area over a period of time ranging from about 10 seconds to about 100 seconds. Additional exemplary time ranges may include, among other exemplary time ranges, about 20 seconds to about 50 seconds and 25 seconds to about 45 seconds. However, in some embodiments, longer purging times may cause the reaction sites to begin to be removed, reducing uniform formation. Therefore, in some embodiments, purging may be performed for 60 seconds or less, 50 seconds or less, 40 seconds or less, 30 seconds or less, or even less. In some embodiments, a purge gas may be introduced into the substrate processing area to aid in the removal of effluent. Exemplary purge gases may include, among other purge gases, argon (Ar), helium (He), and nitrogen (N2).

[0045]

[0049] Referring to Figures 1 and 3B, in operation 20, a second type of precursor reacts with the first precursor to form a second portion 105b of the doped carbon-containing layer 106. The second precursor favorably comprises one or more of phosphorus (P), boron (B), aluminum (Al), arsenic (As), gallium (Ga), indium (In), or zinc (Zn). Specific examples of the second precursor can be selected from tris(dimethylamino)phosphine, phosphorus trichloride, phosphorus oxychloride (V), tris(hydroxymethyl)phosphine, boron trichloride, trimethylaluminum, tris(dimethylamino)arsine, trimethylindium, diethylzinc, and the like.

[0046]

[0050] In one or more embodiments, the second precursor can form a bond with the unreacted reactive groups of the formed first precursor to the first portion 105a of the doped carbon-containing layer 106. The molecules of the second precursor react with the unreacted reactive groups of the first precursor to form a bond linking the second precursor molecules to the first precursor molecules. The reaction between the second precursor molecules and the first precursor molecules continues until most or all of the unreacted reactive groups on the first precursor molecules react with the second precursor molecules. The second portion 105b of the doped carbon-containing layer 106 of the deposited precursor is formed, blocking further reaction between the second precursor molecules in the second precursor effluent and the first portion 105a of the doped carbon-containing layer 106.

[0047]

[0051] Referring to Figure 1, in one or more embodiments, Method 10 also includes an operation 22 to purge or remove a second precursor discharge from the substrate processing area after the formation of the second portion of the doped carbon-containing layer 106. The discharge can be removed by discharge from the substrate deposition area over a time range of about 1 second to about 100 seconds. Additional exemplary time ranges may include about 20 seconds to about 50 seconds and 25 seconds to about 45 seconds, among other exemplary time ranges. In some embodiments, a purge gas may be introduced into the substrate processing area to aid in the removal of the discharge. Exemplary purge gases include argon, helium, and nitrogen, among other purge gases.

[0048]

[0052] In one or more embodiments, the formation rate of the second portion of the doped carbon-containing layer 106 may also depend on the pressure of the second precursor effluent in the substrate processing area. Exemplary effluent pressures in the substrate processing area may range from about 1 mTorr to about 20 Torr. Additional exemplary ranges include, among other exemplary ranges, 5 Torr to 15 Torr and 9 Torr to 12 Torr.

[0049]

[0053] Referring to Figure 1, in one or more embodiments of Method 10, after one or more cycles of forming the doped carbon-containing layer 106 (for example, after the formation of the first and second portions of the compound layer), there is a determination point 24 to determine whether the target thickness of the deposited doped carbon-containing layer 106 on the semiconductor surface 102 and on the dielectric surface of the substrate has been achieved. If the target thickness of the deposited doped carbon-containing layer 106 has not been achieved, another cycle is performed to form the first and second portions of the doped carbon-containing layer 106. If the target thickness of the deposited doped carbon-containing layer 106 has been achieved, another cycle to form another doped carbon-containing layer 106 is not initiated. The exemplary number of cycles for forming the carbon-containing layer may include 1 to 2000 cycles. Additional exemplary ranges of cycles may include 50 to 1000 cycles and 100 to 750 cycles, among other exemplary ranges.

[0050]

[0054] Accordingly, in one or more embodiments, method 10 further comprises depositing at least one additional doped carbon-containing layer on an initial doped carbon-containing layer, the initial doped carbon-containing layer and the at least one additional doped carbon-containing layer forming a doped carbon-containing layer 106 on the semiconductor surface and dielectric surface of the substrate.

[0051]

[0055] In one or more embodiments, the doped carbon-containing layer 106 may have any suitable thickness. In one or more embodiments, the thickness may be at least 1 nm, or at least 10 nm, or at least 100 nm, or at least 200 nm, or at least 500 nm, or at least 1000 nm. An exemplary range of target thickness for stopping further cycles of compound layer formation includes about 10 nm to about 500 nm. Additional exemplary thickness ranges may include about 50 nm to about 300 nm and 100 nm to about 200 nm, among other exemplary thickness ranges.

[0052]

[0056] In the embodiment shown in method 10 of Figure 1, the doped carbon-containing layer 106, which remains deposited on the semiconductor surface 102 and dielectric surface 104 of the substrate, can be etched from the non-target regions 102 and 104 in operation 26. In one or more embodiments, the target region is the target doping surface.

[0053]

[0057] In the embodiment shown in Method 10 of Figures 1 and 4, the doped carbon-containing layer 106 is thermally annealed in operation 28. In one or more embodiments, thermal annealing is used to introduce / diffuse a dopant (one or more of phosphorus (P), boron (B), aluminum (Al), arsenic (As), gallium (Ga), indium (In), or zinc (Zn)) into the substrate. In one or more embodiments, the annealing is a thermal annealing process at a temperature above 400°C. In some embodiments, the annealing is a thermal annealing process at a temperature in the range of 400°C to 1200°C, or in the range of 600°C to 800°C. In one or more embodiments, the thermal annealing is a one-step annealing process. In other embodiments, the thermal annealing is a two or more step process at different temperatures. The annealing environment in some embodiments includes an inert gas (e.g., molecular nitrogen (N2), argon (Ar)) or a reducing gas (e.g., molecular hydrogen (H2) or ammonia (NH3)), or one or more oxidizing agents such as oxygen (O2), ozone (O3), or peroxides, but is not limited to these. Annealing can be performed for any suitable time. In some embodiments, the carbon-containing layer is annealed for a predetermined time in the range of about 1 second to about 90 minutes, or in the range of about 1 minute to about 60 minutes.

[0054]

[0058] In the embodiment shown in Method 10 of Figures 1 and 5, the doped carbon-containing layer 106 is then subjected to a plasma treatment process in Operation 30 to remove the doped carbon-containing layer 106. The plasma may contain one or more of hydrogen (H2), argon (Ar), ammonia (NH3), or oxygen (O2).

[0055]

[0059] In some embodiments, the processing area is located within a modular system comprising a plurality of chambers that perform various functions, including detection and orientation of the substrate center, degassing, annealing, deposition, and / or etching. According to one or more embodiments, the modular system includes at least a first processing chamber and a central transfer chamber. The central transfer chamber may house a robot capable of reciprocating the substrate between the processing chamber and a load lock chamber. The transfer chamber is typically maintained under vacuum and provides an intermediate stage for reciprocating the substrate from one chamber to another and / or to a load lock chamber positioned at the front end of a cluster tool. Any suitable modular system known to those skilled in the art can be adapted to this disclosure. However, the exact arrangement and combination of chambers may be modified for the purpose of performing specific steps of the processing described herein. Other processing chambers that can be used include, but are not limited to, periodic layer deposition (CLD), atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etching, pre-cleaning, chemical cleaning, heat treatment such as RTP, plasma nitriding, annealing, orientation, hydroxide, and other substrate processing. By performing the process within a modular system's processing chamber, surface contamination of the substrate by atmospheric impurities can be avoided without oxidation before subsequent film deposition.

[0056]

[0060] According to one or more embodiments, the substrate is continuously under reduced pressure or “load-lock” conditions and is not exposed to ambient air when moving from one chamber to the next. Thus, the transport chamber is under reduced pressure and is “pumped down” under reduced pressure. An inert gas may be present in the processing chamber or transport chamber. In some embodiments, the inert gas is used to purge or remove some or all of the reactants (e.g., reactants). According to one or more embodiments, an inert gas is injected into the outlet of the processing chamber to prevent the reactants (e.g., reactants) from moving from the processing chamber to the transport chamber and / or additional processing chambers. Thus, the flow of the inert gas forms a curtain at the chamber outlet.

[0057]

[0061] The substrates can be processed within a single-substrate deposition chamber, where a single substrate is loaded, processed, and unloaded before another substrate is processed. The substrates can also be processed in a continuous manner, similar to a conveyor system, where multiple substrates are individually loaded into a first section of the chamber, move within the chamber, and unloaded from a second section. The shape of the chamber and the associated conveyor system can form a straight or curved path. Furthermore, the processing chamber may be a carousel where multiple substrates move around a central axis and are subjected to processes such as deposition, etching, annealing, and cleaning along the entire carousel path.

[0058]

[0062] During processing, the substrate may be heated or cooled. Such heating or cooling can be achieved by any suitable means, including, but not limited to, changing the temperature of the substrate support and flowing a heated or cooled gas over the substrate surface. In some embodiments, the substrate support includes a heater / cooler that can be controlled to electrically change the substrate temperature. In one or more embodiments, the gas used (either a reactive or inert gas) is heated or cooled to locally change the substrate temperature. In some embodiments, the heater / cooler is positioned in a chamber adjacent to the substrate surface to convectivally change the substrate temperature.

[0059]

[0063] The substrate can be kept stationary or rotated during processing. The rotating substrate can be rotated sequentially or in individual steps (around the substrate axis). For example, the substrate may be rotated throughout the entire process, or it may be rotated only slightly between exposures to different reactive or purging gases. Rotating the substrate (continuously or stepwise) during processing helps to minimize the effects of local variations in gas flow shape, for example, and to produce more uniform deposition or etching.

[0060]

[0064] In a spatial ALD process, reactive gases are introduced into different processing areas within a processing chamber. These processing areas are separated from adjacent processing areas to prevent mixing of the reactive gases. The substrate can be moved between processing areas to expose it to the reactive gases individually. During substrate movement, different parts of the substrate surface, or material on the substrate surface, are exposed to two or more reactive gases, such that no given point on the substrate is substantially exposed to two or more reactive gases simultaneously. As those skilled in the art will understand, diffusion of gases within the processing chamber may cause small portions of the substrate to be exposed to multiple reactive gases simultaneously, and simultaneous exposure is not intended unless otherwise specified.

[0061]

[0065] In another aspect of the spatial ALD process, the reactive gases are supplied to the reaction zone simultaneously but separated by an inert gas curtain and / or a vacuum curtain. The gas curtain can be a combination of the inflow of inert gas into the processing chamber and the outflow of a vacuum flow from the processing chamber. The substrate is moved relative to the gas supply device so that any point on the substrate is exposed to only one reactive gas.

[0062]

[0066] The terms "pulse" or "toze" used herein refer to the amount of source gas introduced intermittently or discontinuously into the processing chamber. The amount of a particular compound in each pulse may change over time depending on the duration of the pulse. A particular process gas may consist of a single compound or a mixture / combination of two or more compounds.

[0063]

[0067] In some embodiments of the time-domain ALD process, exposure to each reactive gas, including but not limited to the metals and dielectric materials used in the ALD film, is separated by a time delay to allow each compound to adhere to and / or react with the substrate surface and subsequently discharged from the processing chamber. Mixing of the reactive gases is prevented by purging the processing chamber between subsequent exposures.

[0064]

[0068] In some embodiments of the time-domain ALD process, a time delay exists between pulses of the reactive gas. At each time delay, a purge gas (e.g., argon) is introduced into the processing chamber to purge the reaction zone or to remove any residual reactive gas, reaction products, or by-products from the reaction zone. Alternatively, the purge gas may flow continuously throughout the entire deposition process so that only the purge gas flows during the time delays between pulses of the reactive gas. The reactive gas is pulsed multiple times, alternating with pulses of the purge gas. Purging can also be performed using a vacuum pump, with or without an inert gas.

[0065]

[0069] The duration of each pulse / dose is variable and can be adjusted, for example, to suit the spatial volume of the processing chamber and the capacity of the vacuum system connected to the processing chamber. Furthermore, the administration time of the reactive gas may vary depending on the flow rate of the process gas, the temperature of the reactive gas, the type of control valve, the type of processing chamber used, and the ability of the process gas components to adsorb onto the substrate surface. The dose time may also vary based on the type of layer to be formed and the shape dimensions of the device to be formed. The dose time must be long enough to provide a sufficient amount of compound to substantially adsorb / chemisorb onto the entire surface of the substrate and form a layer of process gas components on it.

[0066]

[0070] Once the carbon-containing layer is deposited, the method may optionally include further processing (e.g., bulk deposition of a dielectric film). In some embodiments, the further processing may be an ALD process.

[0067]

[0071] According to this disclosure, the process can generally be stored in memory as a software routine that, when executed by a processor, causes a process chamber to perform the process of this disclosure. The software routine can also be stored and / or executed by a second processor (not shown) located remotely from the hardware controlled by the processor. Some or all of the methods of this disclosure can also be implemented in hardware. Thus, the process can be implemented in software and executed in hardware using a computer system, for example, as an application-specific integrated circuit or other kind of hardware embodiment, or as a combination of software and hardware. When executed by a processor or controller, the software routine transforms a general-purpose computer into an application-specific computer (controller) that controls the operation of the chamber so that the process can be performed. When executed by a controller of a substrate processing chamber, the process can be stored in a non-temporary computer-readable medium containing instructions that cause the substrate processing chamber to perform the following operations: Specifically, in order to form a first portion of a carbon-containing film doped on a semiconductor surface and a dielectric surface, a first precursor containing a first reactive group is flowed onto a substrate including the semiconductor surface and the dielectric surface, the first precursor outflow containing the first precursor is removed from the substrate, and the first reactive group is reacted with the first precursor to form a second portion of a carbon-containing film doped on a semiconductor surface and a dielectric surface, a second precursor containing a second reactive group is flowed onto the substrate, the second precursor outflow containing the second precursor is removed from the substrate, and the doped carbon-containing film is annealed to form an annealed doped carbon-containing layer on the semiconductor surface and the dielectric surface.

[0068]

[0072] Throughout this specification, any reference to “one embodiment,” “a particular embodiment,” “one or more embodiments,” or “embodiment” means that a particular feature, structure, material, or property described in relation to an embodiment is included in at least one embodiment of this disclosure. Therefore, expressions such as “in one or more embodiments,” “in a particular embodiment,” “in one embodiment,” or “in an embodiment” in various parts of this specification do not necessarily refer to the same embodiment of this disclosure. Furthermore, particular features, structures, materials, or properties may be combined in any suitable manner in one or more embodiments.

[0069]

[0073] While the disclosures herein are described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and uses of the disclosure. It will be apparent to those skilled in the art that various modifications and alterations can be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Therefore, the disclosure is intended to include modifications and alterations that fall within the scope of the appended claims and their equivalents.

Claims

1. A method of semiconductor doping, To form a first portion of a carbon-containing layer doped on a semiconductor surface and a dielectric surface, a first precursor is flowed onto a substrate including the semiconductor surface and the dielectric surface, wherein the first precursor contains a first reactive group. To remove the first precursor outflow containing the first precursor from the substrate, In order to react with the first reactive group to form the doped carbon-containing layer on the semiconductor surface and the dielectric surface, a second precursor containing one or more of phosphorus (P), boron (B), aluminum (Al), arsenic (As), gallium (Ga), indium (In), or zinc (Zn) is flowed onto the substrate, To remove the second precursor outflow containing the second precursor from the substrate. Methods that include...

2. The first precursor is of general formula R １ - (X) ｎ [In the formula, R １ (X) comprises one or more alkyl groups, alkenyl groups, aryl groups, or aromatic groups, and cycloalkyl groups. ｎ [n] comprises one or more hydroxide groups, aldehyde groups, ketone groups, acid groups, amino groups, isocyanate groups, thiocyanate groups, and acyl chloride groups, and n is an integer in the range of 1 to 6. The method according to claim 1, comprising:

3. The method according to claim 1, wherein the first precursor is selected from one or more terephthalaldehyde, phenylenediamine, ethylenediamine, hexamethylenediamine, terephthaloyl chloride, 1,3,5-benzenetricarbonyltrichloride, and pyromellitic dianhydride.

4. The method according to claim 1, wherein the second precursor is selected from one or more of tris(dimethylamino)phosphine, phosphorus trichloride, phosphorus(V) oxychloride, tris(hydroxymethyl)phosphine, boron trichloride, trimethylaluminum, tris(dimethylamino)arsine, trimethylindium, and diethylzinc.

5. The method according to claim 1, further comprising pre-cleaning the semiconductor surface and the dielectric surface.

6. The method according to claim 1, further comprising depositing at least one additional doped carbon-containing layer on the doped carbon-containing layer.

7. Removing the first precursor is Flowing purge gas over the substrate, and The mixture of the first precursor effluent and the purge gas is removed from the substrate. The method according to claim 1, including the method described in claim 1.

8. The purge gas is argon (Ar), helium (He), and nitrogen (N ２ The method according to claim 7, selected from ).

9. The method according to claim 1, further comprising annealing the doped carbon-containing layer at a temperature in the range of 400°C to 1200°C.

10. The method according to claim 9, wherein the doped carbon-containing layer is annealed at a temperature in the range of 600°C to 800°C.

11. The method according to claim 1, further comprising subjecting the doped carbon-containing layer to plasma treatment in order to remove the doped carbon-containing layer from the semiconductor surface and the dielectric surface.

12. The method according to claim 1, further comprising etching the doped carbon-containing layer in a non-target region.

13. A method of semiconductor doping, The method involves flowing a first precursor onto a substrate including a semiconductor surface and a dielectric surface, wherein the first precursor is a general formula R １ - (X) ｎ [In the formula, R １ [Xn comprises one or more alkyl groups, alkenyl groups, aryl groups, or aromatic groups, and cycloalkyl groups, and Xn comprises one or more hydroxide groups, aldehyde groups, ketone groups, acid groups, amino groups, isocyanate groups, thiocyanate groups, and acyl chloride groups, and n is an integer in the range of 1 to 6] To form a first portion of a carbon-containing layer doped on one or more of the semiconductor surface and the dielectric surface, the first precursor is flowed to react with reactive groups on one or more of the semiconductor surface and the dielectric surface. To remove the first precursor outflow containing the first precursor from the substrate, The method involves flowing a second precursor onto the substrate, wherein the second precursor comprises one or more of phosphorus (P), boron (B), aluminum (Al), arsenic (As), gallium (Ga), indium (In), and zinc (Zn). The second precursor reacts with the first portion to form a doped carbon-containing layer, and the second precursor is flowed. To remove the second precursor outflow containing the second precursor from the substrate. A method that includes this.

14. The method according to claim 13, wherein the first precursor and the second precursor are independently selected from one or more of terephthalaldehyde, phenylenediamine, ethylenediamine, hexamethylenediamine, terephthaloyl chloride, 1,3,5-benzenetricarbonyl trichloride, pyromellitic dianhydride, tris(dimethylamino)phosphine, phosphorus trichloride, phosphorus(V) oxychloride, tris(hydroxymethyl)phosphine, boron trichloride, trimethylaluminum, tris(dimethylamino)arsine, trimethylindium, and diethylzinc.

15. The method according to claim 13, further comprising pre-cleaning one or more of the semiconductor surface and the dielectric surface.

16. The method according to claim 13, further comprising depositing at least one additional doped carbon-containing layer on the doped carbon-containing layer.

17. Removing the first precursor is Flowing purge gas over the substrate, and The mixture of the first precursor effluent and the purge gas is removed from the substrate. The method according to claim 13, including the method described in claim 13.

18. The purge gas is selected from argon (Ar), helium (He), and nitrogen (N ２ ), the method according to claim 17.

19. The method according to claim 13, further comprising annealing the doped carbon-containing layer at a temperature in the range of 400°C to 1200°C.

20. The method according to claim 13, further comprising subjecting the doped carbon-containing layer to plasma treatment in order to remove the doped carbon-containing layer from one or more of the semiconductor surface and the dielectric surface.

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