Ion implantation to reduce surface roughness of silicon nitride

Abstract

An exemplary method of semiconductor processing may include forming a silicon nitride layer on a semiconductor substrate. The silicon nitride layer may be characterized by a first roughness. The method may include performing a post-deposition treatment on the silicon nitride layer. The method may include reducing the roughness of the silicon nitride layer such that the silicon nitride layer is characterized by a second roughness less than the first roughness.

Description

[Technical Field]

[0001] Cross-reference with related applications

[0001] This application claims the benefits and priority of U.S. Patent Application No. 63 / 456,093, “ION IMPLANTATION FOR REDUCED ROUGHNESS OF SILICON NITRIDE,” filed on 31 March 2023, which is incorporated herein by reference in its entirety.

[0002] Technical field

[0002] This technology relates to a method and system for semiconductor processing. More specifically, this technology relates to a system and method for producing films having reduced roughness. [Background technology]

[0003] background

[0003] Integrated circuits are made possible by the process of creating material layers with complex patterns on the surface of a substrate. Manufacturing patterned materials on a substrate requires a controlled method for forming and removing the material. As devices become smaller, the properties of the film can have a greater impact on device performance. The material used to form the material layer can affect the operating characteristics of the manufactured device. As the thickness of the material continues to decrease, the properties of the film during deposition can have a greater impact on device performance.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used to manufacture high-quality devices and structures. These and other needs are addressed by this technology. [Overview of the project]

[0005] overview

[0005] An exemplary method of semiconductor processing may include forming a silicon nitride layer on a semiconductor substrate. The silicon nitride layer may be characterized by a first roughness. The method may include performing a post-deposition treatment on the silicon nitride layer. The method may include reducing the roughness of the silicon nitride layer such that the silicon nitride layer is characterized by a second roughness less than the first roughness.

[0006]

[0006] In some embodiments, the semiconductor substrate may be maintained at a temperature of about 550°C or less during the semiconductor processing method. Post-deposition processing may include an ion implantation process. The ion implantation process can be carried out at a temperature of about -100°C or higher. The ion implantation process can be carried out using ions of helium, neon, argon, silicon, boron, carbon, nitrogen, or germanium. Post-deposition processing may include a beamline ion implantation process or a plasma doping process. The first roughness may be about 0.50 nm or more. The second roughness may be about 0.30 nm or less.

[0007]

[0007] Some embodiments of the present technology encompass semiconductor processing methods. The method may include forming a silicon nitride layer on a semiconductor substrate. The silicon nitride layer may be characterized by a first roughness. The method may include transferring the semiconductor substrate to a beamline ion implantation chamber or a plasma doping chamber. The method may include performing a beamline ion implantation process or a plasma doping process on the silicon nitride layer. The method may include reducing the surface roughness of the silicon nitride layer to a second roughness which is less than the first roughness.

[0008]

[0008] In some embodiments, the silicon nitride layer can be formed on a polysilicon layer. The silicon nitride layer can be formed by plasma-enhanced chemical vapor deposition. The silicon nitride layer may be characterized by a thickness of about 100 nm or less. The silicon nitride layer can be formed at a temperature of about 500°C or less. The beamline ion implantation process or plasma doping process can be carried out at a temperature of about 550°C or less. The beamline ion implantation process or plasma doping process can be carried out at a temperature of about -100°C or higher. The beamline ion implantation process or plasma doping process can be carried out at a temperature of about 50°C or less. The beamline ion implantation process or plasma doping process can be carried out using helium, neon, argon, silicon, boron, nitrogen, or carbon ions. The second roughness may be about 0.40 nm or less.

[0009]

[0009] Some embodiments of the present technology encompass semiconductor processing methods. The method may include forming a silicon nitride layer on a semiconductor substrate in a first semiconductor processing chamber. The silicon nitride layer may be characterized by a first roughness. A silicon nitride layer is formed on a material layer. The method may include transferring the semiconductor substrate from the first semiconductor processing chamber to an ion implantation chamber. The method may include performing an ion implantation process on the silicon nitride layer. The ion implantation process may be a beamline ion implantation process or a plasma doping process, or may include both. The method may include reducing the surface roughness of the silicon nitride layer to a second roughness which is less than the first roughness.

[0010]

[0010] In some embodiments, the material layer is polysilicon or may contain polysilicon. The silicon nitride layer can be formed at a temperature of about 550°C or less. The ion implantation process can be carried out at a temperature of about -100°C or higher. The first roughness may be at least about 0.60 nm. The second roughness may be about 0.50 nm or less.

[0011]

[0011] Such technologies can offer many advantages over conventional systems and technologies. For example, embodiments of the technology can produce films characterized by reduced roughness. Furthermore, the technology can reduce the particle size of the film. The reduced roughness and / or reduced particle size of the film reduces the line width of any subsequently formed material present on the film characterized by reduced roughness / particle size. These numerous advantages and features, along with other embodiments, will be described in more detail below in conjunction with the accompanying drawings. [Brief explanation of the drawing]

[0012]

[0012] The nature and advantages of the disclosed technology will be further understood by referring to the remainder of the specification and the drawings.

[0013] [Figure 1]

[0013] This is a top view of an exemplary processing system according to some embodiments of the present technology. [Figure 2]

[0014] A schematic cross-sectional view of an exemplary plasma deposition system according to several embodiments of this technology is shown. [Figure 3]

[0015] The following describes the operating steps in a semiconductor processing method according to several embodiments of this technology.

[0014]

[0016] Some of the figures are included as circuit diagrams. Figures are for illustrative purposes only and should not be considered to scale unless explicitly stated otherwise. Furthermore, as schematic diagrams, they are provided to aid understanding and may not include all aspects or information compared to a realistic depiction, and may include exaggerated material for illustrative purposes.

[0015]

[0017] In the accompanying drawings, similar components and / or features may have the same reference labels. Further, various components of the same type can be distinguished according to the reference signs by letters that distinguish between similar components. If only the first reference sign is used in this specification, the description is applicable to any of the similar components having the same first reference sign, regardless of the letter.

Best Mode for Carrying Out the Invention

[0016] Detailed Description

[0018] As the size of semiconductor devices continues to shrink, the constituent films contained in the structure not only affect the performance of the device, but may also affect the manufacture of other materials contained in the device. Further, as demand increases, throughput and wait time are becoming more important. Therefore, high-quality materials and structures that can be formed quickly and efficiently are required. However, in the process of forming a silicon nitride material, a material with increased surface roughness may result from faster processes such as chemical vapor deposition or plasma-enhanced chemical vapor deposition. The rapid deposition of the material may cause the particle size of the film to increase. The particle size affects the properties of the film and may cause non-uniformity of the film surface that propagates to subsequent materials deposited on the silicon nitride.

[0017]

[0019] To reduce the particle size of the film, in the prior art, the deposition parameters can be changed and atomic layer deposition can be performed. For example, when depositing in atomic layer units, the particle size in the film may be maintained at a certain level, and the quality and properties of the film may be improved. These techniques may be effective, but atomic layer deposition reduces throughput.

[0018]

[0020] There may be a correlation between the particle size and surface roughness of a silicon nitride film. For example, in contrast to atomic layer deposition, increased particle size can be more easily induced during chemical vapor deposition and plasma-enhanced chemical vapor deposition, potentially leading to increased surface roughness. Furthermore, there may be a correlation between the surface roughness of the silicon nitride film and the linewidth roughness of subsequent materials deposited or formed on the silicon nitride film. For example, increased surface roughness may result in increased linewidth roughness in the material deposited on the silicon nitride film. Increased linewidth roughness can lead to non-uniformity in the final device. As a result, reducing the surface roughness of the silicon nitride film can improve the performance of the film and / or device compared to conventional structures.

[0019]

[0021] This technology overcomes these problems by performing an ion implantation process to rearrange the constituent bonds and reduce the particle size of the film. Implanting ions with sufficient energy reduces the particle size and therefore the surface roughness. Furthermore, by utilizing specific ion implantation techniques and adjusting the ion dosing, it is possible to limit the substrate temperature, sputtering, and the impact on the material during implantation.

[0020]

[0022] The remaining disclosures, as is customary, identify specific deposition processes that utilize the disclosed technology. However, it will be readily apparent that the system and method are equally applicable to other deposition and etching processes that may occur in the described chamber or any other chamber. Therefore, the technology should not be considered limited to use with these specific deposition processes or chambers alone. This disclosure describes a set of possible chambers that may be used to carry out the processes according to embodiments of the technology before describing additional modifications and adjustments of this system according to embodiments of the technology.

[0021]

[0023] Figure 1 shows a plan view of one embodiment of a deposition, etching, firing, and curing chamber processing system 100 according to an embodiment. In the figure, a pair of forward-opening unified pods 102 are received by a robotic arm 104 and supplied with substrates of various sizes to be placed in a low-pressure holding area 106 before being placed in one of the substrate processing chambers 108a-108f, which are positioned in tandem sections 109a-109c. A second robotic arm 110 may be used to transfer substrate wafers from the holding area 106 to and from the substrate processing chambers 108a-108f. Each substrate processing chamber 108a-108f may be equipped to perform a number of substrate processing operations, including the formation of laminates of semiconductor materials as described herein, in addition to other substrate processing operations, including plasma chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and annealing, ashing, etc.

[0022]

[0024] The substrate processing chambers 108a-108f may include one or more system components for depositing, annealing, curing, and / or etching dielectric or other films on a substrate. In one configuration, two pairs of processing chambers (e.g., 108c-108d and 108e-108f) may be used to deposit dielectric material on the substrate, and a third pair of processing chambers (e.g., 108a-108b) may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 108a-108f) may be configured to deposit alternating laminates of dielectric films on the substrate. One or more of the described processes may be performed in a chamber separated from the manufacturing system as shown in various embodiments. Additional configurations of deposition chambers, etching chambers, annealing chambers, and curing chambers for dielectric films will be understood as being intended by system 100.

[0023]

[0025] Figure 2 shows a schematic cross-sectional view of an exemplary plasma system 200 according to several embodiments of the present technology. The plasma system 200 may exemplify a pair of processing chambers 108 that are attached to one or more of the tandem sections 109 described above and may include faceplates or other components or assemblies according to embodiments of the present technology. The plasma system 200 may generally include a chamber body 202 having side walls 212, a bottom wall 216, and an internal side wall 201 that define a pair of processing regions 220A and 220B. Each of the processing regions 220A and 220B may be similarly configured and may include the same components.

[0024]

[0026] For example, the processing region 220B may have components included in the processing region 220A and may include a pedestal 228 positioned in the processing region through a passage 222 formed in the bottom wall 216 of the plasma system 200. The pedestal 228 may provide a heater adapted to support a substrate 229 on an exposed surface of the pedestal, such as a main body portion. The pedestal 228 may include a heating element 232, such as a resistive heating element, which can heat and control the substrate temperature at a desired processing temperature. The pedestal 228 may be heated by a remote heating element, such as a lamp assembly, or by other heating devices.

[0025]

[0027] The body of the pedestal 228 may be connected to the stem 226 by a flange 233. The stem 226 may electrically connect the pedestal 228 to a power output or power box 203. The power box 203 may include a drive system that controls the raising and moving of the pedestal 228 within the processing area 220B. The stem 226 may also include a power interface for supplying power to the pedestal 228. The power box 203 may also include interfaces for power and temperature indicators, such as thermocouple interfaces. The stem 226 may include a base assembly 238 adapted to be detachably connected to the power box 203. A circumferential ring 235 is shown above the power box 203. In some embodiments, the circumferential ring 235 may be a shoulder adapted as a mechanical stopper or land configured to provide a mechanical interface between the base assembly 238 and the top surface of the power box 203.

[0026]

[0028] The rod 230 may also be included in a passage 224 formed in the bottom wall 216 of the processing area 220B, and can be used to position the substrate lift pins 261 which are positioned through the body of the pedestal 228. The substrate lift pins 261 can selectively space the substrate 229 from the pedestal to facilitate the replacement of the substrate 229 using a robot used to transport the substrate 229 into and out of the processing area 220B through the substrate transfer port 260.

[0027]

[0029] A chamber lid 204 may be connected to the top of the chamber body 202. The lid 204 may house one or more precursor distribution systems 208 connected thereto. The precursor distribution system 208 may include a precursor injection passage 240, which can deliver reaction precursors and washing precursors into the processing area 220B through a gas delivery assembly 218. The gas delivery assembly 218 may include a gas box 248 having a shielding plate 244 positioned between it and a faceplate 246. A radio frequency ("RF") source 265 may be connected to the gas delivery assembly 218, which can supply power to the gas delivery assembly 218 to facilitate the generation of a plasma region between the faceplate 246 of the gas delivery assembly 218 and a pedestal 228, which may be the processing area of ​​the chamber. In some embodiments, the RF source may be connected to other parts of the chamber body 202, such as the pedestal 228, to facilitate plasma generation. A dielectric isolator 258 may be placed between the lid 204 and the gas delivery assembly 218 to prevent the conduction of RF power to the lid 204. A shadow ring 206 that engages with the pedestal 228 may be placed on the outer edge of the pedestal 228.

[0028]

[0030] To cool the gas box 248 during operation, an optional cooling channel 247 can be formed within the gas box 248 of the gas distribution system 208. A heat transfer fluid, such as water, ethylene glycol, gas, or similar, may be circulated through the cooling channel 247 so that the gas box 248 can be maintained at a predetermined temperature. To prevent the side walls 201, 212 from being exposed to the processing environment within the processing area 220B, a liner assembly 227 may be positioned within the processing area 220B, close to the side walls 201, 212 of the chamber body 202. The liner assembly 227 may include a circumferential pumping cavity 225 that can be connected to a pumping system 264 configured to exhaust gas and by-products from the processing area 220B and to control the pressure within the processing area 220B. Multiple exhaust ports 231 can be formed on the liner assembly 227. The exhaust port 231 may be configured to allow gas to flow from the processing area 220B to the circumferential pumping cavity 225 in a manner that facilitates processing within the system 200.

[0029]

[0031] Figure 3 shows exemplary operating steps in processing method 300 according to several embodiments of the present technology. The method may be performed in various processing chambers, including the processing chamber 200 described above. Method 300 may include one or more operations prior to the commencement of the described method operations, such as front-end processing, deposition, etching, polishing, cleaning, or other operations that may be performed before the described operating steps. The method may include a number of arbitrary operations, as shown in the figure, which may or may not be particularly relevant to the method according to the present technology. For example, many of the operations are described to provide a broader range of semiconductor processing but may not be important to the technology, or may be performed by alternative methodologies, as will be discussed further later.

[0030]

[0032] Method 300 may include any operations to develop a semiconductor structure into a specific manufacturing process. In some embodiments, Method 300 may be carried out on a base structure, while in some embodiments, the method may be carried out following the formation or removal of other materials. For example, any number of deposition, masking, and removal processes may be carried out to manufacture any transistor, memory, or other structural aspect on a substrate. The substrate may be placed on a substrate support, and the substrate support may be positioned within the processing area of ​​a semiconductor processing chamber. The processes may be carried out in the same chamber in which aspects of Method 300 may be carried out, and one or more processes may also be carried out in one or more chambers on a platform similar to the chamber in which the processes of Method 300 may be carried out, or on other platforms.

[0031]

[0033] In some embodiments, Method 300 may include forming a silicon nitride layer on a substrate in operation step 305. Formation or deposition can be carried out using any number of precursors, such as silane or other silicon-containing materials, and in some embodiments, the supplied silicon-containing precursors may also include hydrogen or nitrogen. The precursors may also include other precursors for forming silicon nitride materials, such as diatomic nitrogen, ammonia, or other nitrogen-containing materials, diatomic hydrogen, or other hydrogen-containing materials, or carrier gases and inert materials. As a result, the deposited or formed silicon nitride layer may be characterized by a first roughness. It should be understood that the technique is not limited to silicon films such as silicon nitride. The technique may also encompass the control of roughness in any number of films formed on a semiconductor substrate. Therefore, silicon nitride materials should be considered as just one example of films to which the technique can be applied.

[0032]

[0034] A silicon nitride layer can be part of any number of structures, and in some embodiments, this may include a thin-film transistor structure. For example, in some embodiments, a silicon nitride layer may be one of several layers in a stack of films formed on a substrate. In some embodiments, a silicon nitride layer may be included on or between other material layers, such as other silicon-containing materials or other material layers. In some structures, a silicon nitride material layer can be formed on a material layer such as a polysilicon material. In some structures, a silicon nitride layer can be formed between polysilicon material layers. Each layer in a stack containing a silicon nitride material layer may be characterized by a film thickness of about 500 nm or less, and can be characterized by film thicknesses of about 400 nm or less, about 350 nm or less, about 300 nm or less, about 250 nm or less, about 200 nm or less, about 150 nm or less, about 100 nm or less, about 50 nm or less, or less.

[0033]

[0035] As described above, some embodiments of this technology may include films formed on a material or structure. The underlying material or structure can be characterized by a thermal budget of about 550°C or less, about 500°C or less, about 450°C or less, about 400°C or less, about 350°C or less, about 300°C or less, or less. Accordingly, in some embodiments, a silicon nitride layer can be formed at or below any of these temperatures to adapt to the underlying material, and in some embodiments, one or more operating steps, including all operations of Method 300, can be performed at or below any of these temperatures, and the substrate during processing can be maintained at or near any of these temperatures throughout the entire process. The processing pressure during formation may be about 1 Torr or more in some embodiments, and may be between about 2 Torr and about 20 Torr, between about 2 Torr and about 10 Torr, or between about 2 Torr and about 5 Torr.

[0034]

[0036] In this embodiment, the silicon nitride layer can be formed by plasma-enhanced chemical vapor deposition. During deposition, the precursor plasma may be generated with a plasma power of about 250 W or more, about 400 W or more, about 500 W or more, or more. The plasma power may be about 2,500 W or less, about 2,000 W or less, about 1,750 W or less, about 1,500 W or less, or less. Compared to alternative deposition methods such as atomic layer deposition, the deposited material can be characterized by increased particle size and / or roughness. For example, the formed layer may be characterized by a first roughness. Since throughput may be reduced in alternative deposition methods such as atomic layer deposition, the first roughness may be 0.40 nm or more, 0.45 nm or more, 0.50 nm or more, 0.55 nm or more, 0.60 nm or more, or more. This surface roughness may lead to any of the aforementioned problems, such as line width roughness issues during subsequent etching processes.

[0035]

[0037] In subsequent film formation, in some embodiments, the substrate with the silicon nitride layer formed on it can be transferred from the first processing chamber to a second processing chamber in an optional operation step 310. For example, the formation or deposition of the silicon nitride layer can be performed in the first chamber, such as chamber 200, or in another deposition chamber capable of depositing silicon-containing material. In subsequent deposition, the substrate can be moved to a second chamber for an ion implantation process. The second chamber may be located on the same platform or tool as the first chamber, but in some embodiments, the substrate may be moved between tools for the ion implantation process. In embodiments, the second chamber for the ion implantation process may be from a Trident platform (e.g., Trident CRION, Trident Thermion, Trident, etc.) or from a plasma doping (PLAD) tool available from Applied Materials, Inc. (Santa Clara, California) (e.g., PLAD HVMS, PLAD HVM, etc.).

[0036]

[0038] In operation step 315, post-deposition treatments, including ion implantation processes such as beamline ion implantation, can be performed on one or more layers of the substrate containing the silicon nitride layer. Additionally, or alternatively, a plasma doping process may also be performed in operation step 315. This process is called ion implantation, but may involve ion modification, which involves ion implantation to reorganize the formed film and release material from the film, and this may also include the release of ions from the ion implantation process. This process may include beamline ion implantation, plasma doping implantation, or other implantation processes as described above. Ion implantation processes can be performed to modify the properties of the film. For example, in some embodiments, ion implantation may be performed to reorganize the bonding or structure, such as particle size, within the material, making the film more amorphous. A more amorphous film with reduced particle size can reduce the surface roughness of the material. Furthermore, in embodiments, post-deposition treatments can increase the density of the film and / or sp² within the film.3 The formation may increase.

[0037]

[0039] The ion implantation process can be performed at low pressures depending on the process being performed. For example, plasma-doped ion implantation can be performed at chamber pressures of approximately 100 mTorr or less, approximately 10 mTorr or less, approximately 1 mTorr or less, or less than 1 mTorr. Beamline ion implantation can be performed at much lower pressures, such as approximately 0.1 mTorr or less, approximately 0.05 mTorr or less, approximately 0.01 mTorr or less, or less. These low-pressure operations can facilitate the permeation of ions through the membrane structure. The ion implantation process can be performed at various substrate temperatures, such as approximately -150°C to a maximum of approximately 550°C. Examples of beamline ion implantation species may include inert substances such as helium, neon, and argon that do not bond with silicon nitride. Furthermore, silicon and / or carbon species can be used to bond with silicon nitride without doping the material, making the material n-type or p-type. The energy range of ion implantation may vary depending on the species used. For example, in the case of relatively lighter elements such as helium, the energy range may be lower than in the case of heavier elements such as silicon. From light to heavy elements, the injection energy range is approximately 200 eV to 300 keV, and the injection volume is approximately 1 eV. 14 ~1e 17 Ions / cm 2 This is within the range. For example, helium administered at an energy of approximately 300 keV can alter silicon nitride by up to 2 μm or more, but silicon species can be altered by less than 1 μm.

[0038]

[0040] The temperature at which post-deposition treatment is performed can affect the energy of the ions, and in some embodiments, high-temperature ion implantation can be performed. For example, in some embodiments, sufficient reorganization may occur at temperatures above about -100°C, and also at temperatures above about -50°C, above about 0°C, above about 50°C, above about 100°C, above about 150°C, above about 200°C, above about 250°C, above about 300°C, above about 350°C, above about 400°C, above about 450°C, or above, although in some embodiments, the ion implantation process may be performed at any of the aforementioned thermal budget temperatures or approximately those temperatures. In additional embodiments, low-temperature ion implantation may occur at temperatures below about 50°C, below about 25°C, below about 0°C, below about -25°C, below about -50°C, below about -75°C, below about -100°C, or below. When performing plasma doping, the doping bias voltage may be in the range of approximately 500V to 10kV or higher. Increasing the bias voltage allows for the modification of thicker films. As a non-limiting example, a bias voltage close to 10kV can be used to modify films with a thickness of 50nm to 200nm using lighter species such as helium. Plasma doping is 1e 15 ~1e 17 ions / cm³ 2 Plasma doping can be performed within the following temperature range: approximately 25°C to approximately 500°C.

[0039]

[0041] In ion implantation, ions produced from any number of precursors can be used. For example, in some embodiments, ion implantation is performed with helium, and because helium is a relatively light ion, it can easily penetrate structures greater than 100 nm, which may allow for rearrangement and amorphous formation at deeper levels within the membrane. Helium ion implantation can be performed at higher power, which may promote bond breakdown within the membrane and potentially reduce particle size. Since helium tends to be trapped within the membrane when ion implantation is performed, ion implantation can be performed at temperatures of approximately 250°C or higher, approximately 300°C or higher, or even higher, to promote helium release. In some embodiments, silicon ions from any number of silicon-containing precursors can be used in the ion implantation process. Silicon is characterized by its heavy mass, which may promote bond breakdown in some embodiments. As a result, silicon allows for processes at lower temperatures and higher implantation energies. Similarly, since the membrane being modified can be silicon nitride, silicon ions may not act as dopants to the membrane, and their capture or incorporation may not adversely affect the resulting membrane. Furthermore, the use of heavier ions facilitates control of the implantation depth, improving control over the depth of implantation and modification. For example, the treatment can be controlled to affect one or more layers of the thin-film transistor structure, but can be limited to minimal penetration into the underlying structure. Additional ions used during post-deposition treatment may include argon and neon ions, which act similarly to helium. In addition, boron, carbon, nitrogen, or germanium ions can also be used during post-deposition treatment. Unlike silicon, carbon, and germanium ions, boron ions can act as dopants to the film, and when captured or incorporated, they can be generated and alter the film.

[0040]

[0042] Based on the reorganization of particle size and the reformation of bonding through the film, the density of the film can be increased to a certain extent. Therefore, in some embodiments, the thickness of the film after post-deposition treatment may be about 99% or less of the thickness of the deposited layer or film. In some embodiments, the thickness may be about 98% or less of the thickness of the deposited film, or about 97% or less, or about 96% or less, or about 95% or less, or about 94% or less, or about 93% or less, or about 92% or less, or about 91% or less, or about 90% or less, or even less. However, the thickness of the layer after ion modification may be maintained at more than about 80%, more than about 85%, more than about 87%, more than about 90%, more than about 92%, more than about 95%, or more.

[0041]

[0043] In addition to the change in thickness due to densification, in some embodiments, the density of the film after post-deposition treatment may be about 99% or less of the density of the deposited layer or film. In some embodiments, the density may be about 98% or less of the density of the deposited film, or about 97% or less, or about 96% or less, or about 95% or less, or even less. However, the density of the layer after subsequent ion modification may be maintained at about 80% or more, about 85% or more, about 87% or more, about 90% or more, about 92% or more, about 95% or more, or more than that. In an embodiment, the density of the film may be about 2.80 g / cm 3 or less, or about 2.78 g / cm 3 or less, or about 2.76 g / cm 3 or less, or about 2.74 g / cm 3 or less, or about 2.72 g / cm 3 or less, or about 2.70 g / cm 3 or less, or even less.

[0042]

[0044] Since the dose amount of ion implantation can be controlled compared to other plasma-enhanced processes, the sputtering of the formed film can be limited. For example, in some embodiments, the dose amount of ions is 1e 15ions / cm³ 2 It may be the above, or 5e 15 ions / cm³ 2 It may be the above, or 1e 16 ions / cm³ 2 It may be the above, or 1e 17 ions / cm³ 2 It may be the above, or 1e 18 ions / cm³ 2 The amount may be greater than or equal to that amount. Plasma doping injection can be characterized by a higher dose than beamline injection, and the use of helium can facilitate the disruption of bonds and modification of the particle size of the film. Once post-deposition treatment is performed, method 300 may include reducing the roughness of the silicon nitride layer in operation step 320. The roughness of the silicon nitride layer can be reduced so that the silicon nitride layer can be characterized by a second roughness that is less than the first roughness. In embodiments, the second roughness may be about 0.55 nm or less, and may also be about 0.50 nm or less, about 0.45 nm or less, about 0.40 nm or less, about 0.35 nm or less, about 0.30 nm or less, or less.

[0043]

[0045] The above description includes many details for illustrative purposes in order to provide an understanding of the various embodiments of the Technology. However, it will be obvious to those skilled in the art that certain embodiments may be carried out without some of these details, or with additional details.

[0044]

[0046] While several embodiments have been disclosed, those skilled in the art will understand that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. In addition, some well-known processes and elements have not been described in order to avoid unnecessarily obscuring the Art. Therefore, the descriptions in the prior specification should not be considered to limit the scope of the Art.

[0045]

[0047] Where a range of values ​​is provided, unless explicitly stated otherwise in the context, each intermediary value between the upper and lower limits of that range is, of course, specifically disclosed down to the smallest unit of the lower limit. Narrower ranges between any listed values ​​within a given range or between unlisted intermediary values, and other listed or intermediary values ​​within such ranges, are included. The upper and lower limits of such narrower ranges may be included in or excluded from that range individually. Each range in which one, neither, or both of the limits are included is also included in this technology, although there may be limits that are specifically excluded within the given range. Where one or both of the limits are included in a given range, the range excluding one or both of the included limits is also included.

[0046]

[0048] As used herein and in the claims, the singular forms “a,” “an,” and “the” include multiple references unless the context clearly indicates otherwise. Thus, for example, “a precursor” includes multiple such precursors, and “the layer” includes one or more layers and their equivalents known to those skilled in the art, and so on.

[0047]

[0049] Furthermore, the terms “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including,” as used herein and in the claims, are intended to identify the presence of the described features, integers, components, or steps, but not to exclude the presence or addition of one or more other features, integers, components, processes, operations, or groups.

Claims

1. A semiconductor processing method, Forming a silicon nitride layer characterized by a first roughness on a semiconductor substrate, The silicon nitride layer is subjected to post-deposition treatment, The silicon nitride layer is characterized by a second roughness that is smaller than the first roughness, thereby reducing the roughness of the silicon nitride layer. A semiconductor processing method including [specific components].

2. The semiconductor processing method according to claim 1, wherein the semiconductor substrate is maintained at a temperature of approximately 550°C or less during the semiconductor processing method.

3. The post-deposition treatment includes an ion implantation process, The ion implantation process is performed at a temperature of approximately -100°C or higher. The semiconductor processing method according to claim 1.

4. The semiconductor processing method according to claim 3, wherein the ion implantation process is carried out using ions of helium, neon, argon, silicon, boron, carbon, nitrogen, or germanium.

5. The semiconductor processing method according to claim 1, wherein the post-deposition processing includes a beamline ion implantation process or a plasma doping process.

6. The semiconductor processing method according to claim 1, wherein the first roughness is about 0.50 nm or more.

7. The semiconductor processing method according to claim 1, wherein the second roughness is about 0.30 nm or less.

8. A semiconductor processing method, Forming a silicon nitride layer characterized by a first roughness on a semiconductor substrate, The semiconductor substrate is transferred to a beamline ion implantation chamber or a plasma doping chamber. Performing a beamline ion implantation process or a plasma doping process on the silicon nitride layer, The surface roughness of the silicon nitride layer is reduced to a second roughness which is less than the first roughness. A semiconductor processing method including [specific components].

9. The semiconductor processing method according to claim 8, wherein the silicon nitride layer is formed on the polysilicon layer.

10. The semiconductor processing method according to claim 8, wherein the silicon nitride layer is formed by plasma-enhanced chemical vapor deposition.

11. The semiconductor processing method according to claim 8, wherein the silicon nitride layer is characterized by a thickness of about 100 nm or less.

12. The semiconductor processing method according to claim 8, wherein the silicon nitride layer is formed at a temperature of about 500°C or less, and the beamline ion implantation process or the plasma doping process is performed at a temperature of about 550°C or less.

13. The semiconductor processing method according to claim 12, wherein the beamline ion implantation process or the plasma doping process is performed at a temperature of about -100°C or higher.

14. The semiconductor processing method according to claim 8, wherein the beamline ion implantation process or the plasma doping process is performed at a temperature of about 50°C or lower.

15. The semiconductor processing method according to claim 8, wherein the beamline ion implantation process or the plasma doping process is performed using ions of helium, neon, argon, silicon, boron, carbon, nitrogen, or germanium.

16. The semiconductor processing method according to claim 15, wherein the second roughness is about 0.40 nm or less.

17. A semiconductor processing method, The method involves forming a silicon nitride layer on a semiconductor substrate in a first semiconductor processing chamber, wherein the silicon nitride layer is characterized by a first roughness, and the silicon nitride layer is formed on a material layer, and the method involves forming the silicon nitride layer on the semiconductor substrate in the first semiconductor processing chamber. Transferring the semiconductor substrate from the first semiconductor processing chamber to the ion implantation chamber, Performing an ion implantation process on the silicon nitride layer, wherein the ion implantation process includes a beamline ion implantation process or a plasma doping process. The surface roughness of the silicon nitride layer is reduced to a second roughness which is less than the first roughness. A semiconductor processing method including [specific components].

18. The semiconductor processing method according to claim 17, wherein the material layer includes polysilicon.

19. The semiconductor processing method according to claim 17, wherein the silicon nitride layer is formed at a temperature of approximately 550°C or lower, and the ion implantation process is performed at a temperature of approximately -100°C or higher.

20. The semiconductor processing method according to claim 17, wherein the first roughness is at least about 0.60 nm and the second roughness is 0.50 nm or less.

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