4F2 Dual Work Function Word Line

Abstract

This technology generally relates to vertical cell array transistors (VCATs) and methods for forming such VCATs. A VCAT may include one or more bit lines arranged in a first horizontal direction, one or more word lines arranged in a second horizontal direction, and one or more channels, each extending vertically substantially orthogonal to the first and second horizontal directions such that one or more bit lines intersect the source / drain regions of one or more channels, and one or more word lines intersect the gate regions of one or more channels. The VCAT includes cases where at least one of the one or more word lines includes a first section adjacent to the source / drain region and a second section adjacent to the gate region. The second section includes a high work function material, and the first section includes a low work function material.

Description

[Technical Field]

[0001] Cross-reference of related applications

[0001] This application claims the benefit and priority of U.S. Patent Application No. 63 / 584,426, “DUAL WORK FUNCTION WORD LINE FOR 4F2,” filed on 21 September 2023, which is incorporated herein by reference in its entirety.

[0002]

[0002] This disclosure generally refers to 4F 2 This disclosure describes the design of a two-dimensional dynamic random access memory array. More specifically, this disclosure describes a 4F with reduced leakage current. 2 Let's discuss memory arrays. [Background technology]

[0003]

[0003] Advances in computing technology have made computing devices smaller and increased their processing power. Therefore, it is necessary to increase storage and memory to meet the programming and computing needs of the devices. By increasing the number of storage units with smaller form factors, miniaturization of devices with increased storage capacity can be achieved.

[0004]

[0004] Dynamic Random Access Memory (DRAM) architectures have been shrinking over time. For example, a one-transistor, one-capacitor (1T-1C) DRAM cell architecture is 8F 2 Sizes up to 6F 2 We successfully reduced the size to 6F (where F is the minimum feature size). 2 From 4th floor 2 Further design scheme modifications could help improve area density. 4F 2 In the DRAM architecture, the storage nodes (capacitors) and bit lines are located at the top and bottom of the vertical cell transistors, and the channels remain completely isolated from the main body. This configuration allows for the current 8F to be connected to the main body by the channels.2 or 6F 2 The floating body effect that is not a problem in the DRAM cell architecture of 4F or 6F becomes a major technical issue for the DRAM of 4F. Therefore, improvement in this technical field is necessary. 2 SUMMARY OF THE INVENTION

[0005]

[0005] The present technology generally relates to vertical cell array transistors (VCATs) and methods of forming such VCATs. A VCAT can include one or more bit lines arranged in a first horizontal direction, one or more word lines arranged in a second horizontal direction, and one or more channels extending in a vertical direction generally orthogonal to the first and second horizontal directions such that the one or more bit lines intersect source / drain regions of the one or more channels and the one or more word lines intersect gate regions of the one or more channels. The VCAT can include a case where at least one of the one or more word lines includes a first section adjacent to the source / drain region and a second section adjacent to the gate region. The second section includes a high work function material and the first section includes a low work function material.

[0006]

[0006] In embodiments, the low work function material has a lower work function than the high work function material. Additionally or alternatively, in embodiments, at least one word line includes a third section adjacent to the second source / drain region. In further embodiments, the third section includes the second low work function material. Furthermore, in embodiments, the second low work function material is the same material as the low work function material or a different material. In embodiments, the high work function material exhibits a work function at least about 2% greater than the work function of the low work function material. In many further embodiments, the low work function material has a work function of about 4.2 eV or less. Furthermore, in embodiments, the high work function material has a work function greater than 4.2 eV. In embodiments, the source / drain region includes a Schottky contact or an ohmic contact. Furthermore, in embodiments, the VCAT further includes a second horizontally extending gate formed around at least a portion of one or more channels.

[0007]

[0007] The technology also generally relates to a plurality of bit lines arranged in a first horizontal direction, a plurality of word lines extending in a second horizontal direction, and a plurality of channels, wherein the plurality of bit lines intersect the source / drain regions of one or more channels, and the plurality of word lines intersect the gate regions of one or more channels, and the plurality of channels extend in a vertical direction that is substantially orthogonal to the first and second horizontal directions. VCAT includes cases where at least one of the plurality of word lines includes a first section adjacent to the source / drain region, a second section adjacent to the gate region, and a third section adjacent to the second source / drain region. VCAT includes cases where the second section includes high work function material, and the first and third sections include low work function material.

[0008]

[0008] In some embodiments, the first section extends from the bottom of the word line to a height above a plane that is substantially coplanar with the upper surface of the adjacent source / drain region. In more embodiments, the second section extends from the upper surface of the first section to a height below a plane that is substantially coplanar with the lower surface of the second source / drain region. Furthermore, in some embodiments, the third section extends from the upper surface of the second section to a height below the upper surface of the adjacent channel. In yet another embodiment, the second section contains molybdenum, and the first and third sections contain polysilicon.

[0009]

[0009] The technology also generally covers methods for forming VCATs. The method includes etching a substrate to form one or more shallow trench isolations and a plurality of vertically extending channels. The method includes forming gate dielectric material around one or more shallow trench isolations extending in the word line direction. The method includes depositing low work function material within one or more shallow trench isolations extending in the word line direction. The method includes etching the low word function material to a height below the deposited height. The method also includes depositing high work function material within one or more shallow trench isolations extending in the word line direction and etching the high work function material to a height below the deposited height. The method includes filling the shallow trench isolations with dielectric material before etching the low work function material.

[0010]

[0010] In the embodiment, filling of the dielectric material in the shallow trench isolation is performed before depositing the gate dielectric material and the low work function material. In a further embodiment, the method includes depositing sacrificial material around one or more shallow trench isolations, filling the shallow trench isolation with dielectric material, and etching the sacrificial material to a height below the deposited height. Furthermore, in the embodiment, the method includes filling the shallow trench isolation with dielectric material after depositing the low work function material. Additionally or alternatively, the method includes forming one or more source / drain regions, which are formed by ion implantation, siliconization, or a combination thereof.

[0011]

[0011] Such technologies can offer numerous advantages over conventional systems and techniques. For example, the processes and systems can reduce leakage current without affecting the overall function of the word line. In addition, the processes and systems can significantly improve gate-induced drain leakage. These embodiments and other embodiments, along with their many advantages and features, are described in detail in the following description and accompanying drawings.

[0012]

[0012] The nature and advantages of the disclosed technology can be further understood by referring to the remainder of this specification and the drawings. [Brief explanation of the drawing]

[0013] [Figure 1A] This shows a top view of an exemplary processing chamber according to an embodiment of this technology. [Figure 1B] This shows a top view of a conventional 4F2 memory array. [Figure 1C] A perspective view of a conventional 4F2 memory array is shown. [Figure 2] The selected steps in the formation method according to the embodiment of this technology are shown. [Figure 3A]A perspective view of a semiconductor structure according to an embodiment of the present technology having dielectric material filling after shallow trench isolation formation is shown. [Figure 3B] A perspective view of a semiconductor structure according to an embodiment of the present technology patterned for second shallow trench isolation formation is shown. [Figure 3C] A perspective view of a semiconductor structure according to an embodiment of the present technology having gate oxide and low work function material deposited word line insulation is shown. [Figure 3D] A perspective view of a semiconductor structure according to an embodiment of the present technology with word line insulation filled is shown. [Figure 3E] A perspective view of a semiconductor structure according to an embodiment of the present technology with the low work function material etched back is shown. [Figure 3F] A perspective view of a semiconductor structure according to an embodiment of the present technology having a high work function material deposited within a word line isolation portion is shown. [Figure 3G] A perspective view of a semiconductor structure according to an embodiment of the present technology with the high work function material etched back is shown. [Figure 3H] A perspective view of a semiconductor structure according to an embodiment of the present technology having a low work function material deposited on a word line isolation portion over a high work function material is shown. [Figure 3I] A perspective view of a semiconductor structure according to an embodiment of the present technology with the low work function material etched back is shown. [Figure 3J] A perspective view of a semiconductor structure according to an embodiment of the present technology having doped source / drain regions is shown. [Figure 4A] A perspective view of a semiconductor structure according to an embodiment of the present technology having spacers formed before the low work function material is deposited is shown. [Figure 4B] A perspective view of a semiconductor structure according to an embodiment of the present technology having etched spacers formed before the low work function material is deposited is shown. [Figure 5A] A perspective view of a semiconductor structure according to an embodiment of the present technology in which source / drain formation is performed after depositing a low work function material over a high work function material is shown. [Figure 5B]A perspective view of a semiconductor structure according to an embodiment of this technology in which a second source / drain region is formed is shown. [Modes for carrying out the invention]

[0014]

[0031] Some drawings are included as schematic diagrams. These diagrams are for illustrative purposes only and should not be considered to scale unless explicitly stated otherwise. Furthermore, as schematic diagrams, they are provided to aid understanding and may not include all aspects or information compared to realistic depictions, and may include exaggerated material for illustrative purposes.

[0015]

[0032] In the attached drawings, similar components and / or features may have the same reference numeral. Furthermore, various components of the same type may be distinguished according to their reference numerals by letters that distinguish between similar components. Where only a first reference numeral is used in this specification, its description is applicable to any of the similar components having the same first reference numeral, regardless of the letters used.

[0016]

[0033] Traditionally, DRAM chip bit density increased by approximately 25% per node. However, the increase in bit density between nodes has decreased to nearly 20% in more recent generations, mainly due to challenges associated with scaling the cell area. The cell design architecture for the latest DRAM technology is 6F 2 Based on shape dimensions, "F" is the minimum feature size of a given technology node. 6F 2 From 4th floor 2 Switching to a cell architecture could result in a 33% increase in bit density at the same technology node. Furthermore, the difficulty of patterning 4F2DRAM is a factor for 6F 2 This is significantly reduced compared to the previous method. This is because, at least in part, in the 4F2DRAM method, the capacitor and bit lines are 6F 2This is due to the fact that they are located at the two ends of the vertical cell transistors, rather than being tightly packed on the same side as the DRAM.

[0017]

[0034] However, 4F 2 DRAM design has its own challenges. For example, 4F 2 In memory cells, transistor channels are placed between the bit lines and the capacitor layer, and there is no common substrate remaining to connect the channels, resulting in a floating body effect in these transistors. For example, in conventional 4F 2 DRAM devices are thought to exhibit off-leak current problems. Off-leak current is caused by the floating body effect (e.g., 4F due to isolated channels). 2 This is due to the accumulation of holes in the body of the DRAM device. Electron-hole pairs can be formed within the semiconductor channel by interband tunneling. Electrons can flow into the n-type source or drain region of the transistor, but holes cannot. 4F without substrate connection 2 In DRAM devices, holes have no path to leave the channel and continue to accumulate. Therefore, the floating body effect leads to channel activation without gate activation, ultimately converting into leakage current from the capacitor or the data storage side of the device. Attempts have been made to provide body connections using embedded body contact schemes. However, such attempts can result in gate overlap at the source / drain junction edge, potentially leading to undesirable gate-induced drain leakage or limiting scalability to smaller dimensions. Furthermore, such design schemes also allow for the fabrication of high aspect ratio structures that challenge existing doping techniques.

[0018]

[0035] Due to the stray body effect, at least partially, vertical channel array transistors (VCATs) are susceptible to increased leakage current values, such as gate-induced drain leakage. Furthermore, gate-induced drain leakage can further increase hole generation. Efforts have been made to reduce the work function of the word line material to reduce hole accumulation, but there are limitations on how low the work function can go because the threshold voltage of the VCAT is determined by the word line. Moreover, at low work functions, resistivity and off-leak current increase, preventing hole mobility outside the source / drain region.

[0019]

[0036] This technology overcomes these and other problems by providing a multi-zone word line containing low-work-function and high-work-function materials. The low-work-function material can be formed adjacent to and overlapping the source / drain region of the word line, while the high-work-function material can be formed adjacent to the channel region. In this way, a high threshold voltage is maintained within the channel region, resulting in excellent reduction of off-current leakage. Furthermore, the low-work-function material can reduce the electric field near the source / drain region, thereby reducing gate-induced drain leakage. Thus, unlike conventional attempts, this technology can provide a word line that maintains the threshold voltage required for low off-current leakage while reducing gate-induced drain leakage and even the stray body effect of vertical channel array transistors (VCATs). Furthermore, this technology can provide a method for forming VCATs with multi-material word lines.

[0020]

[0037] In the remaining disclosures, 4F 2While this disclosure routinely identifies specific deposition and etching processes used to form vertical cell array transistors (VCATs) such as DRAM devices, it will be readily apparent that the systems and methods are equally applicable to gate-all-around and Schottky barrier VCATs, other devices suffering from the floating-body effect, and the processes for forming such devices. Therefore, this technology should not be considered limited to use in these specific devices or systems alone. Before describing additional modifications and adjustments to this device according to embodiments of this technology, this disclosure describes a possible semiconductor device, which may include one or more components, using one or more word lines according to embodiments of this technology.

[0021]

[0038] Figure 1A shows a top view of a multi-chamber processing system 100, which may be specifically configured to implement aspects or operations according to several embodiments of the present technology. The multi-chamber processing system 100 may be configured to perform one or more manufacturing processes on individual substrates, such as any number of semiconductor substrates, in order to form semiconductor devices. The multi-chamber processing system 100 may include some or all of a transfer chamber 106, a buffer chamber 108, single wafer load locks 110 and 112 (dual load locks may also be included), processing chambers 114, 116, 118, 120, 122, and 124, preheating chambers 123 and 125, and robots 126 and 128. The single wafer load locks 110 and 112 may include a heating element 113 and may be mounted on the buffer chamber 108. The processing chambers 114, 116, 118, and 120 may be mounted on the transfer chamber 106. The processing chambers 122 and 124 may be mounted on the buffer chamber 108. Two substrate transfer platforms 102 and 104 may be positioned between the transfer chamber 106 and the buffer chamber 108 to facilitate transfer between robots 126 and 128. Platforms 102 and 104 may be open to the transfer chamber and the buffer chamber, or they may be selectively isolated or sealed from the chambers so that varying operating pressures are maintained between the transfer chamber 106 and the buffer chamber 108. Transfer platforms 102 and 104 may each include one or more tools 105 for orientation or measurement operations, etc.

[0022]

[0039] The operation of the multi-chamber processing system 100 may be controlled by a computer system 130. The computer system 130 may include any device or combination of devices configured to implement the operations described below. Thus, the computer system 130 may be a general-purpose computer comprising a controller or an array of controllers and / or software stored on a non-temporary computer-readable medium that, when executed, can perform the steps described in relation to the methods according to embodiments of this art. Each of the processing chambers 114, 116, 118, 120, 122, and 124 may be configured to perform one or more processing steps in the manufacture of a semiconductor structure. More specifically, the processing chambers 114, 116, 118, 120, 122, and 124 may be equipped to perform a number of substrate processing steps, including, among any number of other substrate processes, dry etching, periodic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, degassing, and orientation.

[0023]

[0040] Figures 1B and 1C show the conventional 4F 2 A top view and a perspective view of the memory array 150 are shown. The memory array 150 may include a plurality of word lines 152 arranged in a first layer on a substrate. The word lines 152 may be conductive traces used to select the word lines of memory cells in the memory array 150. The memory array 150 may further include a plurality of bit lines 154 arranged in a second layer on a substrate. The plurality of bit lines may be conductive traces used to select the bit lines of memory cells in the memory array 150. Individual cells in the memory array 150 can be selected by activating one of the plurality of bit lines 154 and one of the plurality of word lines 152. The first and second layers may include different metal layers formed at different times during the manufacturing process. For example, the first layer having the word lines 152 may be formed on top of the second layer having the bit lines 154 such that the two layers do not intersect.

[0024]

[0041] Multiple vertical memory cells may be arranged on the intersections between multiple word lines 152 and multiple bit lines 154. Each of the multiple vertical memory cells may include a vertical transistor, which may be called a vertical pillar transistor or vertical column transistor. The channel material for the transistor may be formed from a single-crystal silicon pillar or any other substrate, which will be described in more detail below. This silicon channel may be formed by etching the substrate. Each of the multiple vertical memory cells may also include a vertical capacitor 156. The vertical memory cell may operate by storing charge in the vertical capacitor 156 to indicate a stored memory state. However, although Figures 1B and 1C show the arrangement of vertical transistors and capacitors in a rectangular, roughly orthogonal grid pattern (where "roughly orthogonal" is within about 10° of orthogonal, e.g., about 7.5° or less from orthogonal, e.g., about 5° or less, e.g., about 2.5° or less, e.g., 1° or less, or any range or value in between, and "roughly" may be used to similarly vary "vertical," "horizontal," etc.), it should be understood that other directions are also usable in this technology. For example, in one embodiment, capacitors and vertical transistors may be spaced apart in alternating rows offset by half the distance between vertical transistors. That is, in one embodiment, the first row of memory cells may be regularly spaced in a row in a first direction, and the second row of memory cells may also be regularly spaced in a row in a first direction, but the second row of memory cells may be offset from the first row of memory cells, for example, aligned approximately midway between the vertical transistors and capacitors of the first row. Such a pattern is sometimes referred to as a "honeycomb" or "hexagonal pattern" in comparison to the square pattern shown in Figures 1B and 1C. Therefore, it should be understood that any suitable orientation can be used in this technology.

[0025]

[0042] This conventional 4F 2It is useful to characterize the dimensions of the unit cell region 166 of the memory array for comparison with a simple memory array described later. For example, the capacitor footprint 158 ​​can be defined as the circular region around each vertical capacitor 156. The capacitor footprint 158 ​​may include the horizontal cross-sectional area of ​​the capacitor, which expands until its cross-sectional area contacts the capacitor region from an adjacent memory cell. Assume that the word line pitch 162 for multiple word lines 152 and the bit line pitch 164 for multiple bit lines 154 can be defined as 2F. This gives the overall cross-sectional area of ​​the unit cell region 166 to be 4F. 2 It will become.

[0026]

[0043] Figure 2 shows exemplary operation of Method 200 according to several embodiments of the present technology. This method can be carried out in various processing chambers, including the processing chamber 100 described above. Method 200 may include a number of arbitrary operations, some of which may or may not be particularly relevant to certain embodiments of the method relating to the present technology. For example, many operations are described to provide a wider range of structural forms, but may not be important to the present technology or may be carried out by alternative methods that are easily understood. In addition, while the method can be described in a perpendicular manner, it should be understood that other orientations from the bit line to the word line side may also be utilized.

[0027]

[0044] Method 200 may include additional steps before commencing the enumerated steps. For example, additional processing operations may include forming a structure on a semiconductor substrate, which may include both forming and removing material. The pre-processing steps may be performed in the chamber in which Method 200 may be performed, or the processing may be performed in one or more other processing chambers before the substrate is brought into the semiconductor processing chamber in which Method 200 may be performed. In any case, Method 200 may optionally include delivering the semiconductor substrate to a processing area of ​​a semiconductor processing chamber, such as the processing chamber 100 described above, or to a processing area of ​​another chamber, which may include the components described above. The substrate may be a pedestal, such as a substrate support 104, and may be deposited on a substrate support / transfer platform that may be present in a processing area of ​​a chamber, such as the processing area of ​​the processing chamber 120 described above. Method 200 describes the steps schematically shown in Figures 3A to 3J, which are described in conjunction with the steps of Method 200. Figures 3A to 3J show only partial schematic diagrams, and it should be understood that the semiconductor substrate may include further components shown in the figures, as well as alternative components of any size or configuration from which the embodiments of this technology can still be beneficial.

[0028]

[0045] Method 200 may or may not include optional operations to evolve the semiconductor structure to a specific manufacturing operation. It should be understood that Method 200 can be performed on any number of semiconductor structures 300 or substrates 302, as shown in Figures 3A to 3J, including exemplary structures on which selectively deposited material can be formed. As shown in Figure 3A, the substrate 302 may be any number of materials, for example, a base wafer or substrate made from silicon or a silicon-containing material, germanium, other substrate materials, and one or more materials that can be formed on the substrate during semiconductor processing.

[0029]

[0046] In embodiments, the structure 300 may be a semiconductor substrate containing silicon on a bulk substrate, an epitaxially grown substrate, and / or an insulating wafer. As used herein, the term “semiconductor substrate” refers to a substrate whose entirety is made of semiconductor material. The semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> The semiconductor material may include one or more materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In one embodiment, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 300 includes a semiconductor material, for example, silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 302 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). While some examples of materials that can form substrates are described herein, any material that can serve as a basis for constructing passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) is included in the spirit and scope of this disclosure.

[0030]

[0047] In embodiments, the semiconductor material may be a doped material such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. As used herein, the term “n-type” refers to a semiconductor produced by doping an intrinsic semiconductor with an electron donor element during manufacturing. The term n-type derives from the negative charge of electrons. In n-type semiconductors, electrons are majority carriers and holes are minority carriers. As used herein, the term “p-type” refers to the positive charge of wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a hole concentration greater than the electron concentration. In p-type semiconductors, holes are majority carriers and electrons are minority carriers.

[0031]

[0048] As shown in Figure 3A, a structure 300 is provided which includes a substrate 302 in which a source / drain 304 has been formed, a shallow trench isolation 308 has been formed, and a first dielectric material 306 has been filled into the shallow trench isolation 308. However, as will be described in more detail with respect to Figure 4, it is clear that the first source / drain region 304 may instead be formed after the front treatment is completed. In addition, two or more walls 305 are formed between each of the first shallow trench isolation 308, and the illustrated walls 305 are spaced apart in a row extending horizontally and generally perpendicular to the word line direction in this embodiment. However, as will be understood by those skilled in the art, in the embodiment the shallow trench isolation may first be cut in a direction generally parallel to the word line direction. In the embodiment, when the formation of the source / drain 304 is performed as part of the front treatment, the formation may include one or more ion implantations and subsequent annealing. The implantation process may be a single implantation or may include a series of multiple implantations. When multiple implantations are used, each implantation may utilize the same or different ions. However, it should be understood that the source / drain region 304 can be formed from any suitable process. The method may include providing a semiconductor structure having a first source / drain region 304 for multiple vertical channels and forming multiple word lines in contact with the first source / drain region. Overall, this process may gradually form each stage of the transistor on top of the previously completed stage.

[0032]

[0049] Furthermore, although various deposition and filling processes are described, in embodiments, the semiconductor structure may be transferred to and between one or more processing chambers 114, 116, 118, 120, 122, and 124 configured for deposition and / or filling processes, including chambers for chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal chemical vapor deposition (CVD), plasma chemical vapor deposition (PECVD), plasma atomic layer deposition (PEALD), etc. Thus, it should be understood that any one or more of the above methods known in the art can be used unless otherwise specified. Similarly, the semiconductor structure may be transferred to and between one or more processing chambers 114, 116, 118, 120, 122, and 124 configured for etching, such as inductively coupled plasma (ICP) etching, reactive ion etching (RIE), capacitively coupled plasma (CCP) etching, etc., and other etching processes known in the art.

[0033]

[0050] Nevertheless, in step 201, method 200 may include forming both a first shallow trench isolation and a second shallow trench isolation 346, as shown in Figure 3A. For example, in an embodiment, the substrate 302 may be loaded into load locks 110, 112 and transported via robots 126, 128 to a processing chamber (such as processing chamber 114), and the semiconductor structure 300 may undergo the formation of a mask 340 and the formation of a second shallow trench isolation 346 in step 201 (the second shallow trench isolation 346 may extend in a generally horizontal direction that is generally parallel to the word line direction, and is therefore also referred to herein as word line trench formation). For example, Figure 3B shows the formation of a mask 340, which may be any patterning mask known in the art, and in an embodiment, etching a wall 305 into a channel 348 by using the mask 340 to etch in a direction extending in a second horizontal direction that is generally perpendicular to the first horizontal direction. That is, as described above, to form shallow trench isolations 308 between walls 305, the pattern or mask 340 defining the second shallow trench isolation 346 may be used in this embodiment to form isolations between channels 348 that are formed by an etching process, in rows parallel to the word lines or extending in a plane with respect to the word lines. The resulting channels 348 may have uniform or non-uniform widths and / or widths generally equal to the walls 305. The second shallow trench isolation 346 may serve to isolate adjacent channels 348. Thus, a semiconductor structure 300 including first and second shallow trench isolations may be provided, as shown in Figures 3A and 3B, where the first shallow trench isolation may include a dielectric material deposited or filled as described above. It should be understood that the substrate may be transferred between each process step, or only a portion of the process steps, because some process steps may be completed within the same processing chamber.

[0034]

[0051] As shown in Figure 3C, after step 201, in step 203, the gate dielectric material 350 may be formed along the adjacent side walls 305 of each word line trench 346 of the second horizontally extending row (for example, so that the gate dielectric material 350 is substantially parallel to the word line direction) 350. The gate dielectric material 350 may be formed from an oxide containing SiO or other similar material, as is known in the art. For example, in embodiments where the channel material is silicon, the gate dielectric material may be SiO that can be oxidized from the wall 305 used as the gate dielectric material 350. However, in embodiments, the dielectric material (e.g., gate oxide) 350 may be any material and may be deposited as is known in the art. Regardless of this method, the gate dielectric material 350 generally extends along the outer circumference of each shallow trench separation 346. The thickness of the gate dielectric material may be between approximately 1 nm and approximately 10 nm, for example between approximately 2 nm and approximately 9 nm, for example between approximately 3 nm and approximately 8 nm, for example between approximately 3 nm and approximately 6 nm, or any range or value in between these.

[0035]

[0052] Step 203 may further include depositing the first word line material of the multilayer word line. Thus, in embodiments, a low work function material 352 can be deposited on the gate dielectric material 350. In Figure 3C, the low work function material 352 is generally shown deposited along the outer circumference of each shallow trench isolation 346 on the gate dielectric 350. The low work function material 352 can be deposited between about 1 nm and about 10 nm, for example between about 2 nm and about 9 nm, for example between about 3 nm and about 8 nm, for example between about 3 nm and about 6 nm, or in any range or value in between these. In this way, a suitable word line for low resistance can be formed without adversely affecting the pitch of the device.

[0036]

[0053] In embodiments, the low work function material 352 may have a work function of less than 4.5 eV, e.g., about 4.2 eV or less, e.g., about 4 eV or less, e.g., about 3.5 eV or less, e.g., about 3 eV or less, e.g., about 2.5 eV or less, e.g., about 2 eV or less, e.g., about 1.5 eV or less, or any range or value in between these. For example, in embodiments, the low work function material 352 may be a metal, an oxide thereof, polysilicon, or other material known in the art, having a work function of less than 4.5 eV (e.g., about 4.2 eV or less). For example, in embodiments, the low work function material 352 may be a metal or oxide thereof containing aluminum (Al), niobium (Nb), tantalum (Ta), a metallic substance having a Fermi level lower than the Fermi level of hafnium (Hf), polysilicon, or a combination thereof, or may include these.

[0037]

[0054] However, in embodiments, the low work function material 352 may be additionally or alternatively selected to have a work function smaller than that of the high work function material 354. This will be explained in more detail below. Thus, in embodiments, the low work function material 352 may be a metal, its oxide, or polysilicon, etc., having a work function at least 1% lower than that of the high work function material 354, for example, about 1.5% or less, about 2% or less, about 2.5% or less, about 3.5% or less, about 4% or less, about 4.5% or less, about 5% or less, or any range or value in between thereof. In other words, in the embodiment, the low work function material 352 may have a work function at least about 50 mV lower than the work function of the high work function material 354, for example about 75 mV or less, for example about 100 mV or less, for example about 150 mV or less, for example about 175 mV or less, for example about 225 mV or less, for example about 250 mV or less, for example about 275 mV or less, for example about 300 mV or less, or any range or value in between these.

[0038]

[0055] In embodiments, it may be desirable to provide further stability to the semiconductor structure. Examples include high aspect ratio structures, gate-all-around structures, and other structures known in the art. Therefore, in some embodiments, optional step 202 may be performed, which may be more clearly shown in Figures 4A and 4B. In such embodiments, a sacrificial material layer 420 may be deposited in the word line isolation section 446 before forming the gate dielectric material 450 and the low work function material 452. Various materials are conceivable, but the sacrificial material 420 should exhibit etching selectivity for the low work function material. Therefore, in embodiments, the sacrificial material layer 420 may be or include SiO2, SiON, or other materials known in the art, depending on the material selected for the low work function material. The word line isolation section 446 backed with the sacrificial material layer 420 may then undergo a filling step to form a second dielectric material 432 in the word line isolation section 446 backed with the sacrificial material layer 420. Furthermore, as shown in Figure 4B, the sacrificial material layer 420 may become concave after the filling process. In this way, the second dielectric material 432 can provide further stability to the structure during processing.

[0039]

[0056] After the recesses of the sacrificial material layer 420 are formed, the gate dielectric material 350 may be deposited along the outer circumference of the separation portion 346, for example, along the side walls 405 of each shallow trench separation portion 346, and the remaining space between the dielectric 350 and the second dielectric material 432, left by the formation of the recesses of the sacrificial material 320, may be filled with a low work function material 352, as more clearly shown in Figure 3D and described in more detail below.

[0040]

[0057] For example, if the optional step 202 is not performed, after the gate dielectric material and low work function material are deposited in step 203, the remaining portion of the shallow trench separation 346 may be filled in step 204. Figure 3D shows the filling being carried out with a first dielectric material 306, a gate dielectric material 350, or a second dielectric material 332 which may be the same dielectric material as a different dielectric material, relating to any one or more of the materials described above or known in the art. In embodiments, the first dielectric material 306, the gate dielectric material 350, and / or the second dielectric material 332 may be any one or more dielectric materials (silicon oxide, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, combinations thereof, or known in the art and formed using any of the filling methods described above). In the following description, silicon oxide or silicon nitride as dielectric material and / or spacer material will be discussed periodically, but any number of dielectric materials may be used in embodiments of the art, and it should be understood that the art should not be limited to any specific dielectric material on which features can be formed. Nevertheless, please understand that other materials may also be used in process 204, as will be explained in more detail below.

[0041]

[0058] Following the filling step 204 or 202, the low work function material 352 may be recessed in step 205, as shown in Figure 3E. In embodiments, the recess formation step may be any recess formation step known in the art for forming a recess in the word line material. In embodiments, the recess formation step may be selected to hold the gate dielectric 350, the first dielectric material 306, and / or the second dielectric material 350. Nevertheless, in embodiments, the low work function material 352 may be recessed to a depth between the midpoint of a shallow trench isolation and the trench height which is substantially coplanar with one or more source / drain regions 304 or a planned source / drain region, as described in more detail with respect to Figures 5A and 5B, forming the first word line region. In embodiments, the trench height t may be defined from the first edge 312 adjacent to the substrate 302 to the top surface 314 of the semiconductor structure 300.

[0042]

[0059] Nevertheless, in embodiments, the low work function material 352 may be recessed to a depth between the midpoint of the shallow trench separation and the trench height which is substantially coplanar with the upper surface 316 of one or more source / drain regions 304 or the planned source / drain region. In this way, the low work function material 352 may extend from the base or bottom of the word line and form a first word line section that prevents overlap between the high work function material 354 and one or more source / drain regions 304. In addition, such size and shape also make it possible to fill part of the trench with the high work function material, enabling a higher threshold voltage in the central portion of the shallow trench separation 346 and the adjacent channel 348. In embodiments, the low work function material 352 may be recessed to a depth above the plane of the upper surface 316 of one or more source / drain regions in order to overlap with the source / drain region adjacent to the upper surface 316 and the channel region 318 of the adjacent channel 348. By extending to the height above the upper surface 316 of the adjacent source / drain region 304, contact between the high work function material 354 and the source / drain region 304 can be further reduced.

[0043]

[0060] Therefore, in the embodiment, the low work function material 352 can be reduced to a height at least about 1% higher than the height h of the adjacent source / drain region (which may extend from the substrate 302 to the top surface 316 as shown in Figure 3E), for example, about 2% or more, for example about 3% or more, for example about 5% or more, for example about 6% or more, for example about 7% or more, for example about 8% or more, for example about 9% or more, for example about 10% or more, for example about 12.5% ​​or more, for example about 15% or more, for example about 17.5% or more, for example about 20% or more, or any range or value in between these heights.

[0044]

[0061] In addition, in order to retain a high work function material sufficient to provide good off-current prevention, the low work function material 352 may be reduced to a height of at least about 1% less than the midpoint of each shallow trench separation 346, for example, about 2% or less, for example, about 3% or less, for example, about 4% or less, for example, about 5% or less, for example, about 6% or less, for example, about 7% or less, for example, about 8% or less, for example, about 9% or less, for example, about 10% or less, for example, about 12.5% ​​or less, for example, about 15% or less, for example, about 17.5% or less, for example, about 20% or less, for example, about 22.5% or less, for example, about 25% or less, for example, about 27.5% or less, for example, about 30% or less, for example, about 32.5% or less, for example, about 37.5% or less, for example, about 40% or less, for example, about 42.5% or less, for example, about 45% or less, for example, about 47.5% or less, for example, about 50% or less, or any range or value in between.

[0045]

[0062] Regardless of the depth to which the low work function material 352 is recessed corresponding to the section height, step 206 may include filling the upper surface of the low work function material 352 in the recess 322 formed between the gate dielectric 350 and the second dielectric material 332 with the high work function material 354 by removing the low work function material 352, as shown in Figure 3F. Thus, in embodiments, the high work function material 354 can be deposited on top of the low work function material 352 and between the gate dielectric material 350 and the second dielectric material 332. The high work function material 354 can be deposited in thicknesses between about 1 nm and about 10 nm, for example between about 2 nm and about 9 nm, for example between about 3 nm and about 8 nm, for example between about 3 nm and about 6 nm, or any range or value in between these (for example, in the direction between the dielectric material 332 and the gate dielectric 350). In this way, a suitable word line for low resistance can be formed without adversely affecting the pitch of the device.

[0046]

[0063] In embodiments, the high work function material 354 may have a work function in the range of about 2 eV or more, for example, about 2.5 eV or more, for example, about 3 eV or more, for example, about 3.5 eV or more, for example, about 4 eV or more, for example, about 4.2 eV or more, for example, about 4.5 eV or more, for example, about 4.75 eV or more, for example, about 5 eV or more, or any range in between these. For example, in embodiments, the high work function material 354 may be a metal, an oxide thereof, or other material known in the art, having a work function of about 4.2 eV or more (for example, about 4.5 eV or more). For example, in the embodiment, the high work function material 354 may be or may include metals or oxides thereof containing molybdenum (Mo), ruthenium (Ru), platinum (Pt), iridium (Ir), tantalum (Ta), rhodium (Rh), palladium (Pd), metallic substances having a Fermi level lower than that of hafnium (Hf), other metals, nitrides, or oxides known in the art, or combinations thereof. Furthermore, in the embodiment, if the low work function material is polysilicon, the high work function material may also include titanium nitride.

[0047]

[0064] However, in embodiments, the high work function material 354 may be additionally or alternatively selected to have a work function greater than that of a low work function material, such as the low work function material 352 and / or a second low work function material 356, which will be described in more detail below. Thus, in embodiments, the high work function material 354 may be a metal, an oxide thereof, etc., having a work function that is at least 1% greater than that of a low work function material, for example, about 1.5% or more, for example, about 2% or more, for example, about 2.5% or more, for example, about 3.5% or more, for example, about 4% or more, for example, about 4.5% or more, for example, about 5% or more, or any range or value in between. In other words, in the embodiment, the high work function material 354 may have a work function that is at least 50 mV higher than the work function of one or more low work function materials, for example, about 75 mV or more, for example about 100 mV or more, for example about 125 mV or more, for example about 150 mV or more, for example about 175 mV or more, for example about 200 mV or more, for example about 225 mV or more, for example about 250 mV or more, for example about 275 mV or more, for example about 300 mV or more, or any range or value in between these.

[0048]

[0065] Regardless of the material selected for the high work function material 354, the high work function material 354 may be recessed to a depth between the midpoint of the shallow trench separation and the bottom surface 326 of the second source / drain region 324 (shown in Figures 3J and 5A), or, as shown in Figure 3G, the trench height which is approximately coplanar with the planned source / drain region. In this way, the high work function material 354 can form a second word line section that overlaps with the channel region 318 of the adjacent channel 348 to a high extent without having significant overlap with the source / drain (or planned source / drain region) 304, 324. Thus, it is possible to achieve an improved threshold voltage in the channel region 318 while also obtaining a reduction in leakage current in the source / drain region. In embodiments, the high work function material 354 may be recessed to a depth below the plane of the bottom surface 326 of one or more second source / drain regions 324 in order to avoid overlap with the second source / drain region 324 of the adjacent channel 348. Contact between the high work function material 354 and the source / drain region 324 can be further reduced by recessing the height of one or more second source / drain regions 324 to the height below the bottom surface 326.

[0049]

[0066] Therefore, in the embodiment, the high work function material 354 can be reduced to a height at least about 1% lower than the height of the bottom surface 326 of the adjacent second source / drain region 324, for example, about 2% or less, for example, about 3% or less, for example, about 4% or less, for example, about 5% or less, for example, about 6% or less, for example, about 7% or less, for example, about 8% or less, for example, about 9% or less, for example, about 10% or less, for example, about 12.5% ​​or less, for example, about 15% or less, for example, about 17.5% or less, for example, about 20% or less, for example, about 25% or less, for example, about 30% or less, or any range or value in between.

[0050]

[0067] Regardless of the depth to which the high work function material 354 is recessed, step 207 may include filling the upper surface of the high work function material 354 in the recess 334 formed between the gate dielectric 350 and the second dielectric material 332 with the second low work function material 356 by removing the high work function material 354, as shown in Figure 3H. Thus, in embodiments, the second low work function material 356 can be deposited on top of the high work function material 354 and between the gate dielectric material 350 and the second dielectric material 332. The second low work function material 356 may be deposited with a thickness between about 1 nm and about 10 nm, for example between about 2 nm and about 9 nm, for example between about 3 nm and about 8 nm, for example between about 3 nm and about 6 nm, or any range or value in between (for example, in the direction between the dielectric material 332 and the gate dielectric 350). In this way, a suitable word line for low resistance can be formed without adversely affecting the pitch of the device. Furthermore, the second low work function material 356 may be any one or more of the low work function materials described above with respect to the low work function material 352, including the electrical properties described above. In embodiments, the second low work function material 356 may be the same as or different from the low work function material 352.

[0051]

[0068] Furthermore, in step 207, the second low work function material 356 may be recessed from the upper surface 314 of each shallow trench separation portion 346 so that the word wire material can be separated by one or more dielectric materials (such as the second dielectric material 332). Thus, in the embodiment, the second low work function material 356 may be recessed such that the upper surface 358 of the second low work function material 356 is separated from the upper surface 314 of the adjacent channel 348 by a height of at least about 1% of the total trench height of each shallow trench separation portion, for example, about 2%, about 3%, about 4%, about 5%, about 6%, about 7%, about 8%, about 9%, about 10%, about 12.5%, about 15%, about 17.5%, or 20%, or any range or value in between.

[0052]

[0069] After the above, following step 207, a dielectric material which may be the same as or different from any one or more of the dielectric materials described above may be filled into the recess 328 formed by the recess formation of the second low work function material 356. Thus, in step 208, a second source / drain region 324 may be formed. The second source / drain region 324 can be formed by any one or more of the methods described above for forming 304. In embodiments, the second source / drain region 324 may be the same as, or formed in the same way as, or different from, the source / drain region 304.

[0053]

[0070] Although not shown, in embodiments, if a low work function word line material is introduced prior to the filling of the dielectric material 332, it may be beneficial to remove connections between adjacent word lines. In such embodiments, the semiconductor structure may be inverted or otherwise oriented, for example by polishing, to remove the substrate 302. Furthermore, parts of the source / drain 304, channel 348, and shallow trench isolation 346 may be removed, for example by polishing. In this way, parts of the low work function material 352 may be removed, separating adjacent word lines from each other and reducing the possibility of short circuits.

[0054]

[0071] However, it should be understood that in embodiments, one or both of the first source / drain region 304 and the second source / drain region 324 may instead be formed as Schottky contacts instead of the ohmic contacts described above. That is, in embodiments, contacts such as one or more source / drain regions can eliminate PN junctions, reduce the floating body effect, and thus further reduce leakage current. For example, referring to Figures 5A and 5B, in step 207, a metal silicide contact 330 may be formed as the second source / drain region 524. In such embodiments, the second source / drain region 324 may undergo a metallization process such as siliconization to form a metallized interface. For example, a metal layer may be applied over the second source / drain region 324 and then exposed to the siliconization process. In embodiments, the metal layer may be tungsten, molybdenum, titanium, zirconium, nickel, hafnium, cobalt, tin, tantalum, platinum, iron, niobium, palladium, their metal-containing species, their alloys, or combinations thereof. Therefore, the resulting interface may be any one or more metallized layers of the above-mentioned metals and channel materials (such as silicon). Only in such examples may the interface layer be titanium silicide, molybdenum silicide, hafnium silicide, or combinations thereof. The contact may also include one or more ion implantations, such as phosphorus, arsenic, or some other material, to generate a barrier height of about 0.60 V or higher, or about 0.65 V or higher, about 0.70 V or higher, about 0.75 V or higher, about 0.80 V or higher, about 0.85 V or higher, or higher. Nevertheless, such silicification procedures may be carried out at low temperatures.

[0055]

[0072] In such embodiments, the source / drain region 504 may be formed as part of a "backside treatment." Thus, as shown in Figure 5B, the semiconductor structure can be inverted so that the end adjacent to the substrate 502 is positioned above the formed channel and shallow trench isolation. Furthermore, the substrate 502 may be removed via polishing to expose the source / drain region 504. Thus, the source / drain region 504 may be formed by an injection or siliconization process, as described above. However, it should be understood that other methods for forming contacts or other source / drain regions may be utilized. In embodiments, such backside treatment may also allow for the combination of capacitors on the channel described herein using hybrid coupling. Such a process can avoid the low-temperature limitations commonly associated with Schottky-type contacts.

[0056]

[0073] Regardless of the method and timing of the formation of the source / drain regions 304 and 324, the semiconductor structure 300 / 400 / 500 is 4F 2 The semiconductor structure may re-enter the normal processing flow of a vertical cell DRAM array, such as a DRAM array, and undergo one or more further processing steps. For example, the semiconductor structure may undergo contact redistribution, coupling pad formation, and / or copper contact formation. Nevertheless, the semiconductor structure may still have significantly reduced gate-induced leakage current, off-current leakage, and / or stray body effects.

[0057]

[0074] The specific step shown in the figure is 4F according to various embodiments. 2 It should be understood that this provides a specific method for forming a DRAM array. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments may perform the steps described above in a different order. Furthermore, the individual steps shown in the figures may include multiple substeps that may be performed in various sequences depending on the individual step. Furthermore, additional steps may be added or removed depending on the particular application. Many variations, modifications, and alternatives are also included in the scope of this disclosure.

[0058]

[0075] As used herein, the terms “about,” “approximately,” and “substantially” should be interpreted as being within the range expected by a person skilled in the art in light of this specification.

[0059]

[0076] In the above description, for the sake of clarity and to provide a complete understanding of various embodiments, numerous specific details have been included. However, it will be apparent that some embodiments can be carried out without some of these specific details. In other examples, well-known structures and devices are shown in the form of block diagrams.

[0060]

[0077] The above description provides only illustrative embodiments and does not limit the scope, applicability, or configuration of this disclosure. Rather, the above description of various embodiments provides a feasible disclosure for implementing at least one embodiment. It should be understood that various modifications may be made to the function and arrangement of the elements without departing from the spirit and scope of some embodiments, as described in the appended claims.

[0061]

[0078] Specific details are given in the above description to provide a complete understanding of the embodiments. However, it will be understood that embodiments can be carried out even without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in the form of block diagrams to avoid obscuring the embodiments with unnecessary details. In other examples, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary details to avoid obscuring the embodiments.

[0062]

[0079] Furthermore, note that individual embodiments have been described as processes, shown as flowcharts, flow diagrams, data flow diagrams, structural diagrams, or block diagrams. While flowcharts may sometimes describe operations as sequential processes, many operations can be executed in parallel or simultaneously. Moreover, the order of operations may be rearranged. A process terminates when its operations are complete, but there may be additional steps not shown in the diagram. A process can correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, its termination may correspond to the function's return to the calling function or main function.

[0063]

[0080] The term “computer-readable medium” includes, but is not limited to, portable or fixed-storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying one or more instructions and / or data. A code segment or machine-executable instruction may represent a procedure, function, subprogram, program, routine, subroutine, module, software package, class, or any combination of instructions, data structures, or program statements. A code segment may be connected to another code segment or hardware circuit by passing information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc., may be passed, transferred, or transmitted via any suitable means, including memory sharing, message passing, token passing, network transmission, etc.

[0064]

[0081] Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, a hardware description language, or any combination thereof. If implemented by software, firmware, middleware, or microcode, program code or code segments for performing the required tasks may be stored in a machine-readable medium. One or more processors may perform the required tasks.

[0065]

[0082] While the features are described in the above specification with reference to specific embodiments, it should be noted that not all embodiments are limited thereto. Various features and aspects of several embodiments may be used individually or collectively. Furthermore, embodiments may be used in any number of environments and applications other than those described herein without departing from the broader spirit and scope of this specification. Accordingly, this specification and the drawings should be considered illustrative, not limiting.

[0066]

[0083] Furthermore, for illustrative purposes, the method has been described in a specific order. It should be understood that in alternative embodiments, the method may be performed in an order different from that described. Furthermore, it should be understood that the method described above may be performed by hardware components or embodied by a sequence of machine-executable instructions, which can be used to cause a machine (e.g., a general-purpose or special-purpose processor, or a logic circuit programmed with instructions) to perform the method. These machine-executable instructions may be stored in one or more machine-readable media (e.g., CD-ROM or other types of optical disks, floppy diskettes, ROM, RAM, EPROM, EEPROM, magnetic or optical cards, flash memory, or other types of machine-readable media suitable for storing electronic instructions). Alternatively, the method may be implemented by a combination of hardware and software.

Claims

1. A vertical cell array transistor (VCAT), A first horizontally arranged bit line or one or more bit lines, A second horizontally arranged word line, One or more channels, wherein one or more bit lines intersect the source / drain regions of the one or more channels, and one or more word lines intersect the gate regions of the one or more channels, extending in a vertical direction substantially perpendicular to the first horizontal and second horizontal directions, and Includes, At least one of the one or more word lines includes a first section adjacent to the source / drain region and a second section adjacent to the gate region, wherein the second section includes a high work function material and the first section includes a low work function material. Vertical cell array transistor (VCAT).

2. The vertical cell array transistor (VCAT) according to claim 1, wherein the low work function material has a lower work function than the high work function material.

3. The vertical cell array transistor (VCAT) according to claim 1, wherein the at least one word line includes a third section adjacent to a second source / drain region.

4. The vertical cell array transistor (VCAT) according to claim 3, wherein the third section comprises a second low work function material.

5. The vertical cell array transistor (VCAT) according to claim 4, wherein the second low work function material is the same material as the low work function material, or a different material from the low work function material.

6. The vertical cell array transistor (VCAT) according to claim 1, wherein the high work function material exhibits a work function at least about 2% greater than the work function of the low work function material.

7. The vertical cell array transistor (VCAT) according to claim 1, wherein the low work function material includes a work function of about 4.2 eV or less.

8. The vertical cell array transistor (VCAT) according to claim 7, wherein the high work function material includes a work function greater than 4.2 eV.

9. The vertical cell array transistor (VCAT) according to claim 1, wherein the source / drain region includes a Schottky contact or an ohmic contact.

10. The vertical cell array transistor (VCAT) according to claim 1, further comprising a second horizontally extending gate formed around at least a portion of the one or more channels.

11. A vertical cell array transistor (VCAT), A first set of horizontally arranged bit lines, A second set of horizontally arranged word lines, A plurality of channels, wherein the plurality of bit lines intersect the source / drain regions of the plurality of channels, and the plurality of word lines intersect the gate regions of the plurality of channels, and the plurality of channels extend in a vertical direction that is substantially perpendicular to the first horizontal direction and the second horizontal direction, Includes, At least one of the plurality of word lines includes a first section adjacent to the source / drain region, a second section adjacent to the gate region, and a third section adjacent to the second source / drain region, wherein the second section includes a high work function material, and the first and third sections include a low work function material. Vertical cell array transistor (VCAT).

12. The vertical cell array transistor (VCAT) according to claim 11, wherein the first section extends from the bottom of at least one word line to a height above a plane that is substantially flush with the upper surface of the adjacent source / drain region.

13. The vertical cell array transistor (VCAT) according to claim 12, wherein the second section extends from the upper surface of the first section to a height below a plane that is substantially flush with the lower surface of the second source / drain region.

14. The vertical cell array transistor (VCAT) according to claim 13, wherein the third section extends from the upper surface of the second section to a height below the upper surface of the adjacent channel.

15. The vertical cell array transistor (VCAT) according to claim 11, wherein the second section comprises molybdenum and the first and third sections comprise polysilicon.

16. A method for forming a vertical cell array transistor (VCAT), Etching the substrate to form one or more shallow trench isolation sections and multiple vertically extending channels, Forming a gate dielectric material around one or more shallow trench isolation portions extending in the direction of the word line, Depositing a low work function material in one or more shallow trench separations extending in the direction of the word line, Etching the aforementioned low work function material to a height lower than the deposited height, Depositing a high work function material in one or more shallow trench separation sections extending in the direction of the word line, Etching the aforementioned high work function material to a height lower than the deposited height, Includes, Before etching the low work function material, a dielectric material is filled into the shallow trench separation area. method.

17. The method according to claim 16, comprising filling the one or more shallow trench isolation portions with the dielectric material before depositing the gate dielectric material and the low work function material.

18. The method according to claim 17, further comprising depositing sacrificial material around one or more shallow trench isolation portions, filling the shallow trench isolation portions with the dielectric material, and etching the sacrificial material to a height below the deposited height.

19. The method according to claim 16, comprising filling the shallow trench separation portion with the dielectric material after depositing the low work function material.

20. The method according to claim 16, further comprising forming one or more source / drain regions, wherein the one or more source / drain regions are formed by ion implantation, silicification, or a combination thereof.

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