Memory, flash memory data writing circuit and method

Abstract

The present invention provides a data writing circuit and method for memory and flash memory. The data writing circuit includes an analog voltage generation module that supplies the necessary voltage to each module, a source voltage selection module for supplying a source voltage, a well voltage selection module for supplying a negative voltage to the well electrode of the memory cell to be written to, a word line gating module for supplying a first positive voltage to the word line of the memory cell to be written to, and a bit line gating module for supplying a second positive voltage to the bit line of the memory cell to be written to. The data writing circuit and method for memory and flash memory in the present invention achieves the writing operation by applying a negative voltage to the well electrode, multiplying secondary electrons, and injecting them into the floating gate. This makes it possible to effectively reduce cost and memory area and improve integration density.

Description

Technical Field

[0001] The present invention relates to the field of memory, and in particular, to a data writing circuit and method for memory and flash memory.

Background Art

[0002] Small memory cell size, high performance, and low power consumption have always been the goals that the memory industry has been pursuing. The smaller the size, the more dies can be produced from each wafer, and only with high performance can the needs of high-speed computing be met. Also, without low power consumption, it is impossible to improve the battery charging frequency of portable devices and the heat dissipation problem in data center systems. For embedded systems, the cost and size of memory are important factors that require consideration. Therefore, how to reduce the size of memory has always been an urgent issue that needs to be solved in the memory industry.

[0003] In conventional NOR FLASH, the write operation is performed by the hot carrier injection method. However, in the case of the hot carrier injection method, the effective channel length is extremely limited, so the area of the NOR type flash memory has always been impossible to reduce. Also, when performing the write operation, a high voltage needs to be applied to the NOR FLASH. The high voltage needs to be generated by a multi-stage charge pump or a large-capacity output capacitor is required, but both of these lead to an increase in the area of the memory peripheral circuit, making it impossible to reduce the area of the NOR type flash memory. Therefore, in order to further reduce the area of the memory, it is necessary to explore a new data writing method.

[0004] It should be noted that the above explanation of the technical background is provided merely for the convenience of clearly and concisely describing the technical means of this application, and for the convenience of understanding of those skilled in the art. The mere fact that these technical means are described in detail in the background art section of this application does not mean that they are publicly known to those skilled in the art. [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a memory, a flash memory data writing circuit, and a method in order to solve the problem of the prior art that further reduction of memory area is impossible. [Means for solving the problem]

[0006] To achieve the above-mentioned objectives and other related objectives, the present invention provides a data writing circuit for flash memory. The flash memory data writing circuit includes at least a memory array, an analog voltage generation module, a source voltage selection module, a well voltage selection module, a word line gating module, and a bit line gating module.

[0007] The analog voltage generation module is connected to the input terminals of the source voltage selection module, the well voltage selection module, the word line gating module, and the bit line gating module, and supplies the necessary voltage to each module.

[0008] The source voltage selection module is connected to the source line of the memory array and is used to supply a source voltage to the source of the memory cell to be written to.

[0009] The well voltage selection module is connected to the well electrodes of the memory array and is used to supply a negative voltage to the well electrodes of the memory cells to be written.

[0010] The word line gating module is connected to each word line of the memory array and is used to supply a first positive voltage to the word line of the memory cell to be written.

[0011] The bit line gating module is connected to each bit line of the memory array and is used to supply a second positive voltage to the bit line of the memory cell to which data is to be written.

[0012] The negative voltage is selectively set to -0.5 to -3V.

[0013] Selectively, the first positive voltage is set to 5 to 10V.

[0014] Selectively, the second positive voltage is set to 2.5 to 4V.

[0015] More selectively, the memory array is a NOR-type flash memory array.

[0016] To achieve the above-mentioned objectives and other related objectives, the present invention further provides a memory, the memory comprising at least a data writing circuit for the flash memory.

[0017] To achieve the above-mentioned objectives and other related objectives, the present invention further provides a method for writing data to a flash memory. The method for writing data to a flash memory includes, at a minimum, connecting the source of the memory cell to be written to ground, and applying a voltage for a predetermined duration to the well electrode, bit line, and word line of the memory cell to be written to, thereby gating the memory cell and writing the data.

[0018] A negative voltage is applied to the well electrodes of the memory cell to be written, a first positive voltage is applied to the word line, and a second positive voltage is applied to the bit line. The first positive voltage is greater than the second positive voltage.

[0019] Optionally, the predetermined time length is set to 0.5 us or more.

[0020] Optionally, the negative voltage is set to -0.5 to -3V.

[0021] Optionally, the first positive voltage is set to 5 to 10V.

[0022] Optionally, the second positive voltage is set to 2.5 to 4V.

[0023] More preferably, the memory cell to be written with data is a NOR type flash memory cell.

Advantages of the Invention

[0024] As described above, the memory, the data writing circuit and method of the flash memory in the present invention have the following beneficial effects.

[0025] 1. The memory, the data writing circuit and method of the flash memory in the present invention reduce the word line voltage and bit line voltage of the memory cell by applying a negative voltage to the well electrode. Thereby, the complexity and area of the analog voltage generation module are reduced, and the objectives of cost reduction and integration improvement are achieved.

[0026] 2. The memory, the data writing circuit and method of the flash memory in the present invention realize the writing operation by multiplying secondary electrons and injecting them into the floating gate. Thereby, it becomes possible to improve the effective programming efficiency, reduce the power consumption, and reduce the effective channel length, and further cost reduction and integration improvement are achieved.

Brief Description of the Drawings

[0027] [Figure 1] FIG. 1 shows a schematic structural diagram of a data writing circuit of a flash memory in the present invention. [Figure 2]Figure 2 shows a schematic flowchart of the data writing method for flash memory according to the present invention. [Modes for carrying out the invention]

[0028] Embodiments of the present invention will be described below with reference to specific examples. Those skilled in the art will readily understand the other advantages and effects of the present invention from the information disclosed herein. Furthermore, the present invention may be implemented or applied by other different specific embodiments. Also, various additions or modifications may be made to each detail herein, based on different perspectives and applications, provided that the spirit of the invention is not departed.

[0029] Refer to Figures 1 and 2. It should be noted that the drawings provided in this embodiment only provide a general overview of the basic concept of the present invention. The drawings only show assemblies related to the present invention and do not represent the number, shape, and size of assemblies that would actually be used in implementation. The form, number, and proportions of each assembly may be arbitrarily changed in actual implementation, and the layout and form of the assemblies may become more complex.

[0030] As shown in Figure 1, the present invention provides a flash memory data writing circuit 1. The flash memory data writing circuit 1 includes a memory array 10, an analog voltage generation module 11, a source voltage selection module 12, a well voltage selection module 13, a word line gating module 14, and a bit line gating module 15.

[0031] As shown in Figure 1, the memory array 10 consists of m+1 rows and n+1 columns of memory cells, where m and n are natural numbers greater than or equal to 0.

[0032] Specifically, in this example, the memory array 10 is a NOR-type flash memory array and includes (m+1)*(n+1) NOR-type flash memory cells. In actual use, any memory cell applicable to the present invention can be used, and the invention is not limited to this embodiment.

[0033] Specifically, in this embodiment, the gates of each memory cell in the same row are connected to the same word line. Each word line is, from top to bottom, WL <0> WL <1> ···WL <m-1>、WL <m>This is defined as follows. Also, the drains of each memory cell in the same row are connected to the same bit line. Each bit line is, from left to right, BL <0> BL <1> ...BL <n-1>、BL <n>This is defined as follows. Furthermore, the sources of two adjacent rows of memory cells are connected to the same source line, and each source line is connected to the same source voltage CS. In actual use, the source lines of each row of memory cells may be provided individually, and this embodiment is not limited to this example.

[0034] As shown in Figure 1, the analog voltage generation module 11 is connected to the input terminals of the source voltage selection module 12, the well voltage selection module 13, the word line gating module 14, and the bit line gating module 15, supplying the necessary voltage to each module.

[0035] Specifically, as an example, the analog voltage generation module 11 includes an input voltage source and a charge pump. The charge pump generates a corresponding voltage signal as needed for programming the memory cell. When the voltage value supplied as needed for programming is large, the charge pump needs to raise the output voltage to a higher potential using a multi-stage cascade method, and accordingly, the circuit configuration of the analog voltage generation module 11 becomes complex and the occupied area increases. Conversely, when the voltage value supplied as needed for programming is small, the circuit configuration of the analog voltage generation module 11 becomes simpler and the occupied area decreases. As another example, the analog voltage generation module 11 is a DC voltage conversion unit. When the voltage value supplied as needed for programming is large, the capacity of the output capacitor of the DC voltage conversion unit also needs to be large (and accordingly, the volume of the capacitor increases). Conversely, in the opposite case, the volume of the analog voltage generation module 11 decreases.

[0036] As shown in Figure 1, the source voltage selection module 12 is connected to the source line of the memory array 10 and is used to supply a source voltage CS to the source of the memory cell to be written to.

[0037] Specifically, the source voltage selection module 12 acquires the source voltage CS from the analog voltage generation module 11 and supplies it to the memory array 10. In this embodiment, the source voltage of each memory cell is 0V. Alternatively, the source voltage of each memory cell in each column may be set individually. In that case, the source of the memory cell to be written to may be floating. In actual use, the source voltage of each memory cell may be set to any value as needed, as long as data writing can be achieved.

[0038] As shown in Figure 1, the well voltage selection module 13 is connected to the well electrodes of the memory array 10 and is used to supply a negative voltage to the well electrodes of the memory cells to be written to.

[0039] Specifically, the well voltage selection module 13 obtains the well voltage from the analog voltage generation module 11 and supplies it to the memory array 10. The voltage at the well electrode of the memory cell to be written is a negative voltage. The negative voltage includes, but is not limited to, -0.1V, -0.3V, -1V, -1.5V, -2V, -2.5V, -3.5V, -4V, and -5V. In this example, the negative voltage is set to -0.5 to -3V. Similarly, in order to avoid a situation where the structure of the analog voltage generation module 11 becomes complicated and the size increases due to the absolute value of the negative voltage being too large, in this embodiment the minimum value of the negative voltage is set to -6V, but in actual use it may be set as needed.

[0040] As shown in Figure 1, the word line gating module 14 is connected to each word line of the memory array 10 and is used to supply a first positive voltage V1 to the word line of the memory cell to be written to.

[0041] Specifically, the word line gating module 14 obtains the word line voltage of each word line from the analog voltage generation module 11. The word line voltage supplied to the memory cell to be written to is a first positive voltage V1. In the present invention, since the voltage at the well electrode of the memory cell to be written to is a negative voltage, the first positive voltage V1 can be reduced, thereby reducing the size of the analog voltage generation module 11. The first positive voltage V1 includes, but is not limited to, 4.5V, 5V, 5.5V, 5.7V, 6V, 6.3V, 6.5V, 6.8V, 7V, 7.5V, 8V, 8.5V, 9V, 9.5V, 10V, 10.5V, 11V, 11.5V, and 12V. In this embodiment, the first positive voltage V1 is set to 5 to 10V.

[0042] One point to explain is that while the well electrodes of a memory cell to be written to are generally set to 0V, in this invention, the voltage at the well electrodes of the memory cell to be written to is set to a negative voltage. Therefore, in a memory structure with the same parameters, if the voltage difference between the gate and the well electrodes is the same, the first positive voltage V1 in this invention will be smaller than the corresponding gate voltage when the well voltage is 0V. Therefore, the value of the first positive voltage V1 is not limited; it only needs to be smaller than the corresponding gate voltage when the well voltage is 0V, and is not limited to this embodiment.

[0043] As shown in Figure 1, the bit line gating module 15 is connected to each bit line of the memory array 10 and is used to supply a second positive voltage V2 to the bit line of the memory cell to be written.

[0044] Specifically, the bit line gating module 15 obtains the bit line voltage from the analog voltage generation module 11. The bit line voltage in the memory cell to be written to is the second positive voltage V2. Similarly, in this case as well, since the voltage at the well electrode of the memory cell to be written to is a negative voltage, the second positive voltage V2 can be made smaller, thereby reducing the size of the analog voltage generation module 11. The second positive voltage V2 includes 2V, 2.5V, 2.7V, 3V, 3.2V, 3.5V, 4V, and 4.5V. In this embodiment, the second positive voltage V2 is set to 2.5 to 4V. In actual use, the second positive voltage V2 is smaller than the first positive voltage V1 and can be set as needed. Similarly, in this case as well, in a memory structure with the same parameters, if the voltage difference between the gate and the well electrode is the same, the second positive voltage V2 in the present invention will be smaller than the corresponding drain voltage when the well voltage is 0V. Therefore, the value of the second positive voltage V2 only needs to be smaller than the corresponding drain voltage when the well voltage is 0V, and this is not limited to this embodiment.

[0045] The present invention further provides a memory, which includes at least one data writing circuit 1 for the flash memory. This allows for an effective reduction in the chip area of ​​the memory, thereby achieving the desirable effect of reducing production costs.

[0046] As shown in Figure 2, the present invention further provides a method for writing data to a flash memory. In this embodiment, the method for writing data to a flash memory is implemented by the flash memory data writing circuit 1, but in actual use, any structure capable of implementing this method can be applied. The method for writing data to a flash memory includes connecting the source of the memory cell to be written to ground, and applying a voltage for a predetermined time length to the well electrode, bit line, and word line of the memory cell to be written to, thereby gating the memory cell to be written and writing the data.

[0047] Furthermore, a negative voltage is applied to the well electrodes of the memory cell to be written, a first positive voltage V1 is applied to the word line, and a second positive voltage V2 is applied to the bit line. The first positive voltage V1 is greater than the second positive voltage V2.

[0048] Specifically, a data writing method based on the flash memory data writing circuit 1 will be described. This method includes the following steps.

[0049] Step S1) The analog voltage generation module 11 generates a negative voltage, a first positive voltage V1, and a second positive voltage V2 necessary for programming. In this example, the negative voltage is set to -0.5 to -3V, the first positive voltage V1 is set to 5 to 10V, and the second positive voltage V2 is set to 2.5 to 4V. In actual use, the setting ranges for the negative voltage, the first positive voltage V1, and the second positive voltage V2 can be determined by referring to the above, and are not limited to this embodiment.

[0050] Step S2) The first positive voltage V1 is transmitted to the selected word line through the word line gating module 14, and the second positive voltage V2 is transmitted to the selected bit line through the bit line gating module 15.

[0051] Step S3) The source line of the memory array 10 is connected to ground through the source voltage selection module 12.

[0052] Step S4) The P well of the memory array 10 is connected to the negative voltage through the well voltage selection module 13.

[0053] Step S5) The first positive voltage V1, the second positive voltage V2, and the negative voltage are applied simultaneously. The duration is at least 0.5us, and includes, but is not limited to, 1us, 1.5us, 2us, 2.5us, and 3us, as long as the data writing can be completed.

[0054] Step S6) By providing the corresponding voltage value and voltage duration as described above, the memory cell becomes capable of a "write" operation. Then, by gating the next memory cell and repeating the above steps, data is written to each memory cell sequentially.

[0055] It should be noted that there is no absolute order in which steps S2) to S4) are performed; the order can be adjusted, or they can be performed simultaneously, and this is not limited to this embodiment.

[0056] This invention achieves a "write" operation by multiplying secondary electrons and injecting them into a floating gate. By generating a lateral electric field between the source and drain within the memory cell to be written, electron-hole pairs are generated, forming the movement of primary electrons to the drain. When primary electrons collide with the side wall of the drain region, the holes accelerate downward and impact the substrate of the memory cell to be written, generating secondary electrons. The secondary electrons further collide with electron-hole pairs due to the action of a longitudinal electric field between the gate and the substrate, generating even more secondary electrons. After the secondary electrons generated by the two collisions are superimposed, they are injected into the floating gate of the memory cell to be written, completing the data writing process.

[0057] The present invention provides effective and easy-to-use operating conditions for data writing operations in flash memory, supporting the memory, flash memory, and data writing operations. According to the present invention, the word line voltage and bit line voltage of the memory cell can be effectively reduced, thereby reducing the complexity and area of ​​the analog voltage generation module that supplies the word line voltage and bit line voltage, enabling effective cost reduction and improved integration density. Furthermore, the data writing method in the present invention is realized by multiplying secondary electrons and injecting them into the floating gate. As a result, the electrons ultimately enter the floating gate vertically in a vertical electric field, enabling effective improvement of programming efficiency, reduction of power consumption, and reduction of effective channel length, leading to further cost reduction and improved integration density.

[0058] In summary, the present invention provides a memory, a flash memory data writing circuit, and a method. The data writing circuit includes a memory array, an analog voltage generation module, a source voltage selection module, a well voltage selection module, a word line gating module, and a bit line gating module. The analog voltage generation module is connected to the input terminals of the source voltage selection module, the well voltage selection module, the word line gating module, and the bit line gating module to supply the required voltage to each module. The source voltage selection module is connected to the source lines of the memory array and used to supply the source voltage. The well voltage selection module is connected to the well electrodes of the memory array and used to supply a negative voltage to the well electrodes of the memory cells to be written. The word line gating module is connected to each word line of the memory array and used to supply a first positive voltage to the word lines of the memory cells to be written. The bit line gating module is connected to each bit line of the memory array and used to supply a second positive voltage to the bit lines of the memory cells to be written. The memory, flash memory data writing circuit, and method of the present invention achieve the writing operation by applying a negative voltage to the well electrode, thereby multiplying secondary electrons and injecting them into the floating gate. This makes it possible to effectively reduce cost and memory area while improving integration density. Therefore, the present invention effectively overcomes various drawbacks of the prior art and has high industrial value.

[0059] The above embodiments are merely illustrative examples illustrating the principles and effects of the present invention and do not limit it. Those familiar with the art may supplement or modify the above embodiments without departing from the spirit and scope of the invention. Therefore, any equivalent supplement or modification that a person skilled in the art could complete without departing from the spirit and technical concept disclosed herein remains within the scope of the claims of the present invention. [Explanation of Symbols]

[0060] 1. Flash memory data writing circuit 10 memory arrays 11 Analog voltage generation module 12. Source Voltage Selection Module 13-well voltage selection module 14 Word Line Gating Module 15-bit line gating module S1-S6 Steps< / n> < / m>

Claims

1. A data writing circuit for flash memory, It includes at least a memory array, an analog voltage generation module, a source voltage selection module, a well voltage selection module, a word line gating module, and a bit line gating module. The analog voltage generation module is connected to the input terminals of the source voltage selection module, the well voltage selection module, the word line gating module, and the bit line gating module, and supplies the necessary voltage to each module. The source voltage selection module is connected to the source line of the memory array and is used to supply a source voltage to the source of the memory cell to be written to. The well voltage selection module is connected to the well electrodes of the memory array and used to supply a negative voltage to the well electrodes of the memory cells to be written to. The word line gating module is connected to each word line of the memory array and used to supply a first positive voltage to the word line of the memory cell to be written. A flash memory data writing circuit characterized in that the bit line gating module is connected to each bit line of the memory array and used to supply a second positive voltage to the bit line of the memory cell to be written.

2. The flash memory data writing circuit according to claim 1, characterized in that the negative voltage is set to -0.5 to -3V.

3. The flash memory data writing circuit according to claim 1, characterized in that the first positive voltage is set to 5 to 10V.

4. The flash memory data writing circuit according to claim 1, characterized in that the second positive voltage is set to 2.5 to 4V.

5. The flash memory data writing circuit according to any one of claims 1 to 4, characterized in that the memory array is a NOR type flash memory array.

6. A memory characterized by including at least a data writing circuit for a flash memory according to any one of claims 1 to 5.

7. A method for writing data to flash memory, wherein at least, This includes connecting the source of the memory cell to be written to ground, and applying a voltage for a predetermined duration to the well electrode, bit line, and word line of the memory cell to be written to, thereby gatering the memory cell and writing the data. A method for writing data to a flash memory, characterized in that a negative voltage is applied to the well electrodes of the memory cell to be data written, a first positive voltage is applied to the word line, and a second positive voltage is applied to the bit line, wherein the first positive voltage is greater than the second positive voltage.

8. The flash memory data writing method according to claim 7, characterized in that the predetermined time length is set to 0.5 us or more.

9. The method for writing data to a flash memory according to claim 7, characterized in that the negative voltage is set to -0.5 to -3V.

10. The flash memory data writing method according to claim 7, characterized in that the first positive voltage is set to 5 to 10V.

11. The flash memory data writing method according to claim 7, characterized in that the second positive voltage is set to 2.5 to 4V.

12. The method for writing data to a flash memory according to any one of claims 7 to 11, characterized in that the memory cell to be used for data writing is a NOR type flash memory cell.

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