Device having a memory cell calibration mechanism and method for operating said device

Abstract

Methods, apparatuses, and systems for tracking charge loss are described. An apparatus may include a tracking mechanism configured to perform direct measurements for tracking charge loss in a first type of cell. An apparatus may be configured to specify a set of first type cells as a surrogate for modeling charge loss in a second type of cell having a different storage density than the first type of cell. The apparatus may perform measurements on the surrogate set of first type cells and use the tracking mechanism to translate the measurement results to respond to charge loss in the second type of cell.

Description

Technical Field

[0001] The disclosed embodiments relate to an apparatus, and in particular, to a semiconductor memory device having a memory cell calibration mechanism and a method for operating the apparatus.

Background Art

[0002] A memory system may employ a memory device for storing information and accessing the information. The memory device may include a volatile memory device, a non-volatile memory device (e.g., flash memory using "NAND" technology or logic gates, flash memory using "NOR" technology or logic gates, or a combination thereof), or a combined device. The memory device utilizes electrical energy at corresponding threshold levels or processing / read voltage levels to store and access data. However, the performance or characteristics of the memory device change or degrade over time, use, and environmental conditions. This change in performance or characteristics becomes inconsistent with the threshold or processing voltage levels over time, leading to errors and other performance problems. The changed performance further degrades as the density of the memory device increases (e.g., by storing more bits per cell).

Brief Description of the Drawings

[0003] The above and other objects, features, and advantages of the present disclosure will become apparent from the following description of embodiments as illustrated in the accompanying drawings, and like reference numerals refer to like parts throughout the various figures. The figures are not necessarily to scale, and instead emphasis is placed on explaining the principles of the present disclosure. [Figure 1] A block diagram of a calculation system according to an embodiment of the present technology. [Figure 2A] An illustration of charge loss. [Figure 2B] An illustration of charge loss. [Figure 3] An example of a conversion mechanism according to an embodiment of the present technology. [Figure 4]This is an illustration of memory state measurement according to an embodiment of this technology. [Figure 5] This flowchart illustrates an exemplary method for manufacturing and operating an apparatus according to an embodiment of this technology. [Figure 6] This is a schematic diagram of a system including the apparatus according to an embodiment of this technology. [Modes for carrying out the invention]

[0004] As detailed below, the technology disclosed herein relates to an apparatus for calibrating memory cells in apparatuses comprising multiple types of cells, such as memory systems, systems having memory devices, associated methods, and others. The apparatus is capable of tracking or measuring the amount of charge loss for a first type of memory cell (e.g., higher density memory cells such as quad-level cells (QLCs)), and the resulting charge loss can be used to estimate the charge loss for a second type of memory cell (e.g., lower density memory cells such as triple-level cells (TLCs), multi-level cells (MLCs), and / or single-level cells (SLCs)).

[0005] Technological advancements have made it possible for memory cells (e.g., NAND flash memory cells) to store an increasing number of bits. The storage capacity of a memory cell can be expressed as bits per cell (BPC). For example, SLC may have a capacity of 1 BPC, MLC 2 BPC, TLC 3 BPC, and QLC 4 BPC. Increasing the BPC allows more bits to be stored on a single wafer, thus reducing the cost per bit for a given die size. Furthermore, including multiple cells of different types or densities within a group of cells / each group or within a single device can provide additional features and operational flexibility. For example, during higher demand loads or relatively frequent memory accesses, a device can utilize lower-density cells for temporary storage similar to cache memory. In such write surges, the device can leverage the faster write speeds of lower-density cells to initially receive the data. Next, the device can move the initially received data to higher-density cells (for example, 12 bits stored in 12 SLCs to 4 TLCs or 3 QLCs).

[0006] However, different types of memory cells can also behave differently. For example, QLC and TLC may have different charge loss patterns. That is, different types of memory cells may be exposed to different rates of charge loss. Conventional methods for measuring charge loss required separate measurement circuits. Other conventional methods for tracking and calculating charge loss require relatively large tables used to track write time and / or storage duration for each cell or each group of cells. Thus, such conventional methods require additional resources, such as a dedicated measurement circuit or designated storage space, for each type of memory to track the tables.

[0007] Embodiments of the technology described herein may utilize resources for one type of memory cell (e.g., QLC) to calculate / track estimated charge loss for another type of memory cell (e.g., faster, lower-density cells such as TLC). For example, the apparatus may include circuitry and / or routines for measuring the charge loss characteristics of one or more QLC blocks. The apparatus may include or select one or more dummy word lines (WLs) of QLC as surrogates to represent and track the charge loss behavior of one or more TLC blocks. When estimating the charge loss of TLC blocks, the apparatus may use existing circuitry / routines for measuring the charge loss characteristics of corresponding dummy WLs without directly measuring or tracking the TLC blocks. The apparatus may use a conversion mechanism to translate the measured charge loss characteristics of the dummy WLs into an estimate of the charge loss of the TLC blocks. The apparatus may use the same type of resources to estimate and track the charge loss behavior for multiple types of memory cells, rather than relying on separate and dedicated resources for each type of cell.

[0008] Figure 1 is a block diagram of a calculation system 100 according to an embodiment of the present technology. The calculation system 100 may include personal computer devices / systems, enterprise systems, mobile devices, server systems, database systems, distributed computing systems, and others. The calculation system 100 may include a memory system 102 connected to a host device 104. The host device 104 may include one or more processors that write data to and / or read data from the memory system 102. For example, the host device 104 may include an upstream central processing unit (CPU).

[0009] The memory system 102 may include circuitry configured to store data (e.g., by write operations) and provide access to the stored data (e.g., by read operations). For example, the memory system 102 may include persistent, or non-volatile, data storage systems such as NAND flash drive systems, solid-state drive (SSD) systems, SD cards, and others. In some embodiments, the memory system 102 may include a host interface 112 (e.g., a buffer, transmitter, receiver, and / or others) configured to facilitate communication with the host device 104. For example, the host interface 112 may be configured to support one or more host-to-host connectivity schemes such as Universal Serial Bus (USB), Peripheral Component Interconnect (PCI), Serial AT Attachment (SATA), and others. The host interface 112 may receive commands, addresses, data (e.g., write data), and / or other information from the host device 104. The host interface 112 may also send data (e.g., read data), and / or other information to the host device 104.

[0010] The memory system 102 may further include a memory controller 114 and a memory array 116. The memory array 116 may include memory cells configured to store units of information. The memory controller 114 may be configured to control the overall operation of the memory system 102, including the operation of the memory array 116.

[0011] In some embodiments, the memory array 116 may include a collection of NAND flash devices / packages. Each package may include a collection of memory cells, each storing data in a charge-storage structure. Memory cells may include, for example, floating gates, charge traps, phase-change devices, ferroelectrics, magnetoresistives, and / or other suitable memory elements configured to store data permanently or semi-permanently. A memory cell may be a one-transistor memory cell that can be programmed into a target state to represent information. For example, charge may be placed in or removed from a charge-storage structure (e.g., a charge trap or floating gate) of the memory cell to program the cell into a specific data state. The stored charge in the charge-storage structure of the memory cell may represent the cell's Vt. For example, an SLC may be programmed into one of two distinct data states that can be represented by binary units of 1 or 0. Also, some flash memory cells may be programmed into one of more than two data states that can be targeted. An MLC may be programmed into any one of four data states (e.g., binary 00, 01, 10, 11) to store two bits of data. Similarly, TLC uses 8 (i.e., l) to store 3 bits of data. 3 It can be programmed to one of ) data states, and QLC stores 16 (i.e., l) bits of data to store 4 bits. 4 It can be programmed into one of the )

[0012] Such memory cells may be arranged in rows (for example, each corresponding to a word line 130) and columns (for example, each corresponding to a bit line). The array may further correspond to other groups of memory cells. For example, each word line 130 may correspond to one or more memory pages. The memory array 116 may also contain memory blocks, each containing a set of memory pages. In operation, data may be written to or otherwise programmed (e.g., erased) to various memory areas of the memory array 116, such as by writing to groups of pages and / or memory blocks. In NAND memory, a write operation often involves programming a memory cell in a selected memory page with a specific data value (e.g., a string of data bits with logical values ​​of 0 or 1). An erase operation is similar to a write operation, except that it reprograms an entire memory block or all of multiple memory blocks to the same data state (e.g., logical 0).

[0013] For illustrative purposes, the device 100 and its memory array 116 are described as having a group of first type cells 132 (e.g., QLC) with a higher density and a group of second type cells 134 (e.g., TLC) with a lower density. In some embodiments, the second type cells 134 may be permanently configured to have a lower density (e.g., by one or more physical or structural traits). In other embodiments, the second type cells 134 may be physically or structurally configured to have the maximum capacity to match the first type cells 132, but may have a configuration that is dynamically specified to store fewer bits than that maximum capacity. The memory array 116 may contain the first type cells 132 and the second type cells 134 together in a single package. In one or more packages, the first type cells 132 and the second type cells 134 may be grouped into separate blocks. For example, a package in memory array 116 may contain one or more QLC blocks and one or more TLC blocks. Also, memory array 116 may contain more first-type cells 132 than second-type cells 134.

[0014] In some embodiments, the device 100 may use a first type of cell 132 for first storage and / or long-term storage, and a second type of cell 134 or a subset thereof as dynamic transition memory 136. As an example for illustrative purposes, when the device 100 is subjected to higher utilization (e.g., when rapidly received write commands exceed a threshold amount within a given period), the device 100 may write incoming data to the dynamic transition memory 136. Thus, the device 100 can utilize lower densities and higher operating speeds due to lower densities to accommodate relatively fast influxes of data. Subsequently, for example, when the load decreases, the device 100 can move the data stored in the dynamic transition memory 136 to the higher-density first type of cell 132, thereby effectively compressing the received data into fewer cells. The dynamic transition memory 136 may be selectively made available based on one or more real-time measurements characterizing the load, such as valid data detected for garbage collection, one or more recognizable command patterns, remaining unused instances of the second type of cell 134, and so on. The dynamic transition memory 136 (e.g., memory designated to provide temporary storage or caching functionality at any time) may be separate from and appended to the fixed cache 138.

[0015] While the memory array 116 is described in relation to memory cells, it is understood that the memory array 116 may include other elements (not shown). For example, the memory array 116 may also include other circuit elements such as multiplexers, decoders, buffers, read / write drivers, address registers, data output / data input registers, etc., for accessing and / or programming (e.g., writing) data and other functions.

[0016] As described above, the memory controller 114 may be configured to control the operation of the memory array 116. The memory controller 114 may include a processor 122, such as a microcontroller, a logic circuit for a specific purpose (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor. The processor 122 may execute instructions encoded in hardware, firmware, and / or software (e.g., instructions stored in the controller-embedded memory 124 to perform various processes, logic flows, and routines for controlling the operation of the memory system 102 and / or the memory array 116).

[0017] Furthermore, the memory controller 114 may further include an array controller 128 that controls or monitors detailed or targeted modes of operation of the memory array 116. For example, the array controller 128 may provide a communication interface between the processor 122 and the memory array 116 (e.g., its components). The array controller 128 may function as a multiplexer / demultiplexer, such as to handle the transfer of data over a serial connection of the memory array 116 to the flash device.

[0018] The memory controller 114, the logic circuits within the memory array 116, the corresponding firmware, or a combination thereof, may implement a calibration mechanism 150 that adjusts one or more modes of data access depending on the state of the stored charge. To provide background to the calibration mechanism 150, Figures 2A and 2B illustrate charge loss. Figure 2A illustrates the charge distribution within a single cell (left) for a given bit value following the initial programming operation, and the distribution of Vt across multiple cells (right, e.g., with respect to the program verify level). When a memory cell is programmed, at least a target amount of charge is stored in the charge trap layer (CTL) to represent the corresponding bit value. During the write / programming operation, some charge may be unintentionally generated or placed in the tunnel layer (TNL) and / or the semiconductor substrate (poly) layer.

[0019] At the end of a write / programming operation, the memory system 102 may read or verify the result to ensure accuracy. In fact, the memory system 102 may perform a verification to ensure that the stored charge exceeds the access level (e.g., program verify (PV) level) corresponding to the target bit value. Different cells hold different amounts of charge in the CTL, which results in a curve with a dip shape for the Vt distribution with respect to the cell storing a given bit value.

[0020] FIG. 2B illustrates the charge loss for both individual cells and the Vt distribution. The charge loss may correspond to the movement of charge within the memory cell to other locations such as the TNL and / or poly from the CTL. Such displacement of the stored charge can realistically reduce the Vt. Since memory cells may suffer from or be exposed to charge loss at various rates, the Vt for a cell to store a given bit value may vary at various rates. Thus, the Vt distribution for a given bit value may shrink (e.g., shift to the left) and / or expand. Some of the cells with a lower Vt at the time of the first programming and / or cells that are exposed to earlier / greater charge loss may shift below the PV level. In fact, a memory cell with a Vt value that shifts below the PV level may be exposed to data corruption and reflect a bit value different from the originally stored bit value.

[0021] Such behavior of charge loss may vary for different types of cells (e.g., by BPC density). For example, QLC and TLC may have different charge loss characteristics or patterns. Thus, dedicated tracking and / or estimation of charge loss is necessary for different cells or associated memory blocks.

[0022] Referring back to FIG. 1, the calibration mechanism 150 (e.g., implemented via the processor 122, logic inside the memory array 116, software routines / instructions, firmware, or a combination thereof) may be configured to estimate and / or track the charge loss for the memory cells and accordingly control adjustments to data processing (e.g., read level voltage adjustment). For a memory array 116 having multiple types of cells (e.g., memory blocks with different BPCs such as the first and second types of cells 132 and 134), the calibration mechanism 150 may have different tracking mechanisms. For example, the calibration mechanism 150 may include a first tracking mechanism 152 and a second tracking mechanism 160.

[0023] The first tracking mechanism 152 may include a circuit, software instructions / routines, firmware, or a combination thereof configured to track a first type of cell 132 (e.g., a block of memory having a higher density BPC configuration). The first tracking mechanism 152 may directly track or estimate the data storage behavior (e.g., charge loss) of the first type of cell 132. In some embodiments, the first tracking mechanism 152 may maintain a first tracking list 154 that identifies blocks of the first type of cell 132 according to, among other things, the amount of charge loss, the corresponding offset amount for the read level voltage, etc. For example, the first tracking mechanism 152 may group or bin QLC blocks according to a predetermined range of the amount of charge loss or the corresponding offset amount.

[0024] In some embodiments, the first tracking mechanism 152 may include a first measurement mechanism 156 (e.g., a dedicated circuit and / or operation instructions) configured to directly measure one or more aspects of charge loss in a target first type of cell 132. The apparatus 100 may be configured to trigger the first measurement mechanism 156 to obtain resulting measurements for blocks of the first type of cell 132. The resulting measurements may be used to identify bins and corresponding access adjustments 158 for each of the measured blocks (e.g., QLC blocks). Details regarding the first tracking mechanism 152 are described below.

[0025] The second tracking mechanism 160 may include a circuit, software instructions / routines, firmware, or a combination thereof configured to track a second type of cell 134 (e.g., a block of memory with a lower density BPC configuration). The second tracking mechanism 160 may indirectly track or estimate the data storage behavior (charge loss) of the second type of cell 134 based on the use of the first measurement mechanism 156. For example, the second tracking mechanism 160 may have a proxy access group 162 for a given set of second type of cell 134 (e.g., one or more blocks). The proxy access group 162 may include one or more examples (e.g., one or more word lines) of the access group 140 of the first type of cell 132 that act as proxys for the target block of the second type of cell 134. The second tracking mechanism 160 may use the first measurement mechanism 156 to measure storage characteristics (e.g., charge loss) and generate a proxy measurement 164 that represents the storage state of the target memory block.

[0026] As an example for illustrative purposes, the device 100 may simultaneously operate (e.g., write) a surrogate access group 162 in a QLC block whenever a data operation (e.g., write) is being performed on one or more word lines in a corresponding TLC block (e.g., via the logic and circuitry in the processor 122, the memory array 116, the second tracking mechanism 160, or a combination thereof). After the operation, the second tracking mechanism 160 may generate a surrogate measurement 164 by utilizing the first measurement mechanism 156 to directly measure the memory characteristics (e.g., charge loss) of the surrogate access group 162. The second tracking mechanism 160 further calculates a converted measurement result 166 based on processing the surrogate measurement 164 according to the conversion mechanism 168. The converted measurement result 166 may be a mapping or estimation that reflects the state of data in a target second type cell 134 (e.g., TLC) using the measured characteristics of the corresponding first type cell 132 (e.g., QLC). The conversion mechanism 168 may include processes, equations, lookup tables, and the like that reflect predetermined relationships or connections between charge loss patterns across different types of cells. That is, the conversion mechanism 168 may be configured to provide a charge loss estimate for a cell with a second BPC under the same conditions (e.g., retention time) in relation to a measurable charge loss in a cell with a first BPC.

[0027] In some embodiments, the device 100 may use a conversion mechanism 168 to extract and use access adjustments 158 whenever a readout is requested in a second type of cell 134. For example, the device 100 may (1) perform measurements of a proxy access group 162 using a first measurement mechanism 156, (2) convert the measurement results into converted measurement results 166 with respect to a target set of TLCs, (3) extract access adjustments 158 (e.g., readout level voltage offset) based on the converted measurement results 166, and (4) apply the access adjustments 158 in response to all readout commands targeting the TLC cells.

[0028] In other embodiments, the device 100 may track a second tracking list 170 according to an update trigger 172 (e.g., a predetermined timing or condition). The second tracking list 170 may include converted measurement results 166 for a set of blocks of a second type. The measurement results in the second tracking list 170 may be updated according to the update trigger 172. With respect to updates, the device may measure and convert the corresponding proxy access group 162 and store the resulting converted measurement results 166 and / or access adjustments 158, similar to the case of the first tracking list 154. In response to a read command targeting a cell of a second type 134, the device 100 may access the second tracking list 170 to extract or calculate access adjustments 158 for the target cell and use the resulting access adjustments 158 to perform the read operation.

[0029] Figure 3 shows a conversion mechanism 168 as an example according to an embodiment of the present technology. The conversion mechanism 168 may identify a target path voltage (VPASS) 302 used to group the various values ​​of the surrogate measurement 164 in Figure 1 or the corresponding levels of charge loss. For each bin or VPASS value, the conversion mechanism 168 may identify various access adjustments 158 according to a predetermined voltage range or corresponding bit value. Thus, the apparatus 100 may use the conversion mechanism 168 (e.g., a lookup table) to determine whether the converted measurement result 166 or the access adjustment 158 ​​or both in Figure 1 are appropriate for the measurement output 403.

[0030] In some embodiments, the conversion mechanism 168 may include internal adjustments that reflect the converted measurement result 166 or access adjustment 158 ​​in Figure 1, or both. Thus, the conversion mechanism 168 may be used to directly calculate or output the adjusted access level based on the measurement output 403.

[0031] Figure 4 illustrates a memory state measurement according to an embodiment of the present technology (e.g., the first measurement mechanism 156 in Figure 1). Figure 4 may illustrate the steps or details taken to carry out the first measurement mechanism 156. That is, the first measurement mechanism 156 includes details or steps relating to directly measuring one or more aspects of charge loss in a target cell (e.g., the first type cell 132 in Figure 1).

[0032] In directly measuring one or more aspects, the first measurement mechanism 156 may be configured to vary with respect to the access group 140 in question in Figure 1, such as by gradually increasing the access group voltage 402 (e.g., word line voltage, read level voltage, etc.). The apparatus 100 in Figure 1 (e.g., via the processor 122 in Figure 1, logic circuits in the memory array 116 in Figure 1, software instructions or routines, firmware, or a combination thereof) may determine the measurement output 403 as a voltage level of the access group voltage 402 that satisfies predetermined conditions. For example, when the calibration enable 404 is active, the apparatus 100 may change the string current 408 (e.g., the current flowing through the access group 140 in Figure 1) when the calibration register value 406 changes when the stored data is first read or disturbed; string The access group voltage 402 can be detected and recorded when it reaches a predetermined threshold, when a predetermined period of time has elapsed, or at other times. The measurement output 403 may correspond to the result of the first measurement mechanism 156 and the VPASS 302 in Figure 3 recorded in the first tracking list 154 in Figure 1. The measurement output 403 may also correspond to the proxy measurement 164 in Figure 1, since it directly measures the proxy access group 162 in Figure 1.

[0033] In some embodiments, the first measuring mechanism 156 may include a sequence of phases or parts. For example, the first measuring mechanism 156 may start after establishing an initial state 412, such that the bit lines are set to a predetermined level (e.g., analog source voltage level) and the word lines are set to a voltage source level (e.g., VCC) or a combination thereof. Thereafter, the first measuring mechanism 156 may perform an initial slope portion 414 that gradually increases the access group voltage 402 to a minimum measurement level 422 according to an initial step size 415 (e.g., a predetermined increase amount and / or duration). During the initial slope portion 414, one or more bit lines may be precharged.

[0034] When the access group voltage 402 reaches the minimum measurement level 422, the first measurement mechanism 156 may perform the measurement portion 416. The measurement portion 416 may occur simultaneously with the activation of the calibration enable 404.

[0035] During the measurement section 416, the apparatus 100 may gradually increase the access group voltage 402 with a step size 417 (e.g., a predetermined increase and / or duration) that differs from the initial step size 415 in voltage and / or duration. For example, the initial step size 415 may have a relatively large voltage increase and a short duration to shorten the time in establishing the minimum measurement 422 at the access group voltage 402. By comparison, step size 417 may have a smaller voltage increase and / or a longer duration than the initial step size 415 to provide finer granularity and / or a sufficient measurement duration, resulting in improved measurement accuracy.

[0036] While iteratively / incrementally increasing the access group voltage 402, the device 100 may monitor the measurement conditions. The measurement conditions may correspond to readout conditions or similar changes in the electrical balance of the access group 140 and the corresponding cell. The measurement conditions may be expressed by transitions in the calibration register value 406 and / or by the string current 408 reaching a threshold level. The device 100 may detect the level of the access group voltage 402 when the measurement conditions are met. The device 100 may store the detected level as a measurement output 403.

[0037] In some embodiments, the device 100 may continue to increase the access group voltage 402 after a measurement condition has been met. For example, the device 100 may continue the measurement portion 416 until the access group voltage 402 reaches the adjusted access level 424. While continuing to increase the measurement portion 416, the device 100 may access a predetermined lookup table to determine an offset value corresponding to the measurement output 403. Thus, the device 100 may dynamically calculate the adjusted access level 424 as a combination of the determined offset value and the measurement output 403 (for example, while gradually increasing the measurement portion 416). When the voltage reaches or exceeds the adjusted access level 424, the device 100 may stop the measurement portion 416 and the increase at the access group voltage 402. Alternatively, the device 100 may issue an interruption to reset the access group voltage 402, such as in response to an error condition or other reset condition.

[0038] The device 100 may perform a full-surface sensing section 418 after the measuring section 416. During the full-surface sensing section 418, the device 100 may prepare for sensing to detect the amount of charge stored in the corresponding memory cell, for example, by operating a sense amplifier. After the full-surface sensing section 418, the device 100 may return to the reset state (e.g., before T0) by resetting the access group voltage 402 and other related conditions.

[0039] In other embodiments, the device 100 may perform the first measurement mechanism 156 by applying a voltage pulse to measure the response in the memory cell. For example, the device 100 may determine a certain amount of bits / memory cell with a Vt higher than the applied voltage pulse. Thus, the device 100 may determine the highest Vt that can be used to calculate the measurement output 403.

[0040] As will be further detailed here, the apparatus 100 may use the first measurement mechanism 156 for a second tracking mechanism 160. The apparatus 100 may identify a surrogate access group 162 associated with one or more target TLC blocks. For example, the apparatus 100 selects a dummy word line in QLC mode on a target TLC block. The apparatus 100 may update the read offset bin adjustment (e.g., access adjustment 158 ​​in Figure 1) for the target TLC block by determining the measurement output 403 of the dummy word line (e.g., a surrogate measurement 164 representing charge loss) and converting the measurement output 403 to the converted measurement result 166 in Figure 1 according to the conversion mechanism 168. In some embodiments, the apparatus 100 may update the read offset bin without evaluating a timer (e.g., a timer used to track the elapsed time since the last write / refresh), temperature, or both.

[0041] In some embodiments, the device 100 may use an update trigger 172 shown in Figure 1, which is initiated as needed. For example, the update trigger 172 may initiate the first measuring mechanism 156 during read error handling, media scanning, periodic scanning, or other operations.

[0042] Figure 5 is a flowchart illustrating an exemplary method 500 for operating an apparatus according to an embodiment of the present technology (e.g., apparatus 100, memory system 102, memory controller 114, memory array 116 and / or other circuits shown in Figure 1). Method 500 may be for performing the calibration mechanism 150 of Figure 1, including the second tracking mechanism 160 of Figure 1 (e.g., via the processor 122 of Figure 1, the logic in the memory array 116, other logic circuits or a combination thereof). That is, Method 500 may be for calculating and / or tracking converted measurement results 166 that reflect the charge loss and the corresponding memory state of a target cell (e.g., the first type of cell 132 of Figure 1, including QLC), such as the charge loss and the second type of cell 134 of Figure 1 (e.g., TLC).

[0043] In block 502, the device 100 may determine a proxy group of the first type of cell 132 in Figure 1. As an example for illustrative purposes, a memory array 116 (e.g., a flash memory array) may include the first type of cell 132 and the second type of cell 134. In some embodiments, the first type of cell 132 and the second type of cell 134 may be contained within a single block. A memory block may include the second type of cell 134 configured to store a reduced number of BPCs, fewer than its maximum BPC. For example, a memory block may include the second type of cell 134 of QLC that is dynamically configured (e.g., "on the fly" or during the deployment of the memory array 116) to store three or fewer bits and operate as TLC, MLC, or SLC. The device 100 may operate the block at a reduced storage density to reduce operating time (e.g., write and read time) compared to a configuration with a larger or maximum bit density. For example, device 100 may utilize a second type of cell 134 to store data transiently, similar to cache memory.

[0044] Considering a default configuration with a larger capacity, device 100 may include a first tracking mechanism 152 in Figure 1, configured to track charge loss with respect to a cell operating at one BPC (e.g., maximum capacity). Device 100 may retain the first type of cell 132 as a surrogate access group 162 in Figure 1 to model charge loss with respect to a second type of cell 134 in the same block. For example, within a block, device 100 may determine (e.g., via one or more logic circuits or combinations thereof in the processor 122, memory array 116) a set of cells (e.g., along one dummy or surrogate word line) to operate as the higher / maximum storage capacity and continue to function as the surrogate access group 162. For comparison, the remaining cells (e.g., the second type of cell 134) may store content i.e., payload data and / or be connected to other / separate word lines. For the determined proxy grouping, the first tracking mechanism 152 can track or estimate the charge loss over time (e.g., degradation of accessible data or content data within the block) for the second type of cell 134 in the same block.

[0045] In other embodiments, the memory block may include a reserved word line. The device 100 may utilize the reserved word line as a first type of cell 132 and a substitute access group 162. For example, the device 100 may implement the substitute access group 162 by programming the memory cells connected to the reserved word line into QLC mode. Thus, the device 100 may use the reserved word line to track charge loss using a first tracking mechanism 152.

[0046] In block 504, the device 100 may pad a proxy group (e.g., a first type of cell 132 or a proxy access group 162). For example, the device 100 may pad a proxy access group 162 by storing predetermined data values ​​to establish an initial state in order to track and monitor charge loss over time. In some embodiments, the device 100 may pad a proxy access group 162 when a corresponding memory block (e.g., its first word line) is written to or refreshed.

[0047] In block 506, the device 100 may identify a trigger event for estimating charge loss. For example, the device 100 may identify the conditional completion of the update trigger 172 in Figure 1. Once the trigger event is identified, the device 100 may implement the first tracking mechanism 152 to finally calculate and generate the estimated charge loss for a memory block (e.g., its second type of cell 134) and an appropriate amount of adjustment required to access the stored data in the degraded state of the memory block. In some embodiments, the device 100 may initiate charge loss estimation during handling read errors, scanning the medium, periodic scanning, or a combination thereof.

[0048] In block 508, the apparatus 100 may acquire a surrogate measurement 164 (e.g., measurement output 403 in Figure 4) that models the charge loss in the second type of cell 134. That is, the apparatus 100 may generate the measurement output 403 by implementing the first tracking mechanism 152 to operate directly on the first type of cell 132 (e.g., surrogate access group 162 in block 508). The acquired surrogate measurement 164 may include or represent the charge loss over time in the first type of cell 132 (e.g., a change or degradation from the initial state).

[0049] The apparatus 100 may acquire a surrogate measurement 164 based on gradually increasing the access group voltage 402 in Figure 4. In some embodiments, the apparatus 100 may gradually increase the access group voltage 402 on a surrogate word line along other (e.g., all) word lines within the memory block. The apparatus 100 may use the first step size 415 in Figure 4 to bring the word line voltage up to the minimum measurement 422 in Figure 4. The apparatus 100 may then use the step size 417 in Figure 4 to increase the word line voltage beyond the minimum measurement 422. During the iterative / gradual increase, the apparatus 100 may monitor one or more circuits of the memory array 116 to detect a predetermined response with respect to a first type of cell 132. In response to detecting a predetermined response, the apparatus 100 determines the corresponding voltage of the access group voltage 402 as a measurement output 403. The apparatus 100 may use the measurement output 403 as a surrogate measurement 164 to model or represent the charge loss in a second type of cell 134 of the memory block. The device 100 may continue to gradually increase the access group voltage 402 during and after the determination of the measurement output 403, and in parallel with the other steps described below.

[0050] In block 510, the apparatus 100 may calculate a converted measurement result 166 based on a surrogate measurement 164 (e.g., measurement output 403). For example, the apparatus 100 may calculate the converted measurement result 166 using the measurement output 403 as input to the conversion mechanism 168 in Figure 1, which represents the relationship between the charge losses in the first type of cell 132 and the second type of cell 134. The converted measurement result 166 may include an estimate of the charge loss in the second type of cell 134.

[0051] In block 512, the device 100 may extract an access adjustment 158 ​​based on the converted measurement result 166. The device 100 may extract an access adjustment 158 ​​to adjust the read-level voltage for the second type of cell 134 to account for charge loss. Thus, the device 100 may extract an access adjustment 158 ​​using the existing first tracking mechanism 152 and without specifically tracking / estimating charge loss for the second type of cell 134. For example, the device 100 may extract an access adjustment 158 ​​without or instead tracking additional storage periods specific to or for the second type of cell 134, such as without adjusting the temperature during storage in the second type of cell 134 and / or without directly measuring charge loss in the second type of cell 134.

[0052] In some embodiments, method 500 may combine the steps described in blocks 510 and 512 into a single step. For example, the conversion mechanism 168 may directly output an appropriate access adjustment 158 ​​to the measurement output 403, which may internally include the converted measurement result 166.

[0053] In block 514, the device 100 may access data stored in the second type of cell 134 using the access adjustment 158. The device 100 may calculate an adjusted access level 424 based on a combination of the access adjustment 158 ​​and the converted measurement result 166. In some embodiments, the conversion mechanism 168 may internally incorporate the converted measurement result 166 and the access adjustment 158, thereby directly outputting the adjusted access level 424 according to the measurement output 403.

[0054] The device 100 may use a tuned access level 424 to read from the second type of cell 134. In some embodiments, the word line voltage scaling may continue even after the determination of the measurement output 403. During or in parallel with such scaling, the device 100 may perform the necessary calculations regarding the tuned access level 424. In fact, the device 100 may raise the word line voltage for the second type of cell 134 to the tuned access level 424. The device 100 may use the tuned access level 424 to operate the sense amplifier to read from the second type of cell 134.

[0055] Figure 6 is a schematic diagram of a system including a device according to an embodiment of the present technology. Any of the devices described above with reference to Figures 1 to 5 (e.g., memory devices) can be incorporated into any of the countless larger and / or more complex systems, the most representative of which is system 680 schematically shown in Figure 6. System 680 consists of a memory device 600, a power supply 682, a driver 684, a processor 686, and / or other subsystems or components 688. The memory device 600 may include features generally similar to those of the devices described above with reference to one or more of the figures, and therefore may include various features for performing direct read requests from a host device. As a result, system 680 can perform any of a wide range of functions, such as storage in memory, data processing, and / or other appropriate functions. Thus, a typical system 680 may, without limitation, include handheld devices (e.g., mobile phones, tablets, e-readers, digital audio players), computers, vehicles, consumer electronics, and other products. The components of System 680 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communication network). The components of System 680 may also include any of the following: remote devices and a wide range of computer-readable media.

[0056] As described above, specific embodiments of the present technology have been described herein for illustrative purposes, but it is understood that various improvements can be made without departing from this disclosure. In addition, certain aspects of the novel technology described in the context of specific embodiments may also be combined or omitted in other embodiments. Furthermore, while advantages associated with certain embodiments of the novel technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments necessarily exhibit such advantages in order to be included in the scope of the present technology. Thus, this disclosure and related technologies may include other embodiments not expressly shown or described herein.

[0057] In the illustrated embodiments described above, the apparatus has been described in the context of a NAND flash device. However, apparatus configured according to other embodiments of the Art may include, in addition to or instead of a NAND flash device, other types of suitable storage media, such as NOR-based non-volatile storage media (e.g., NAND flash), magnetic storage media, phase-change storage media, ferroelectric storage media, dynamic random-access memory (DRAM) devices, and others.

[0058] As used herein, the term “processing” includes the manipulation of signals and data, such as writing, programming, reading, erasing, refreshing, adjusting or changing numerical values, calculating results, executing instructions, assembling data structures, transferring, and / or manipulating them. The term “data structure” includes information arranged as bits, words or codewords, blocks, files, input data, data generated by the system, calculated or generated data, and program data. Furthermore, as used herein, the term “dynamic” refers to processing, functions, operations or executions that occur during the operation, use or deployment of the corresponding device, system, or embodiment, and after or during the execution of manufacturer or third-party firmware. Dynamically occurring processing, functions, operations or executions may occur after design, manufacture, and initial testing, installation, or configuration.

[0059] The embodiments described above are described in sufficient detail so that a person skilled in the art can implement and use them. However, a person skilled in the art will understand that the art may have additional embodiments and that the art may be implemented without some of the details of the embodiments described above, with reference to one or more of the figures above.

Claims

1. A memory device, A memory array comprising non-temporary, rewritable memory cells grouped into blocks and configured to store charges representing stored data, The memory block is configured to include a second type of cell which is specified to store a second number of bits per cell and is configured to store accessible data, and The memory block includes a word line configured as a first type of cell, which is specified to store a first number of bits per cell greater than the second number of bits and is configured as a surrogate for modeling charge loss in the second type of cell. The memory array, and A logic circuit coupled to the memory array, Padding the first type of cell with a predetermined data value for monitoring charge loss over time, wherein the first type of memory cell is padded to represent the storage state of the second type of cell, Since it operates in the first type of cell described above, the measurement output is obtained directly, The process involves calculating a converted measurement result for the second type of cell using the measurement output and the conversion mechanism, The converted measurement results include an estimate of the charge loss in the second type of cell, and also, The conversion mechanism represents the relationship between the charge losses in the first type of cell and the second type of cell. The above calculation and, Extracting an access adjustment based on the converted measurement result, wherein the access adjustment is for adjusting the read level voltage to respond to the charge loss in the second type of cell in the read from the second type of cell, The logic circuit configured to do the following, The memory device, including the memory device.

2. A memory device according to claim 1, The memory device wherein the second type of cell is a triple-level cell (TLC) and the first type of cell is a quad-level cell (QLC).

3. A memory device according to claim 1, The memory device wherein the second type of cell has (1) a maximum storage capacity greater than the first number of bits, and (2) is dynamically configured to store less than the maximum capacity in order to reduce the write time compared to the first type of cell.

4. A memory device according to claim 1, The memory device is configured such that the logic circuit acquires the measurement output and calculates the converted measurement result during read error handling, media scanning, periodic scanning, or a combination thereof.

5. A memory device according to claim 1, The memory device wherein the logic circuit is configured to extract the access adjustment without (1) tracking the storage period in the second type of cell, (2) directly measuring the charge loss in the second type of cell, and (3) adjusting with respect to temperature, or a combination thereof.

6. A method for operating a memory device including a rewritable memory cell configured to store an electric charge representing stored data, Determining a first type of memory cell configured to have a first storage density, wherein the first type of memory cell is configured as a substitute for a second type of memory cell having a second storage density. Pad the first type of memory cell with a predetermined data value for monitoring charge loss over time, The method involves obtaining a measurement output directly from operating in the first type of cell, wherein the measurement output reflects the charge loss in the first type of cell, and the method of obtaining the measurement output is described above. The process involves calculating a converted measurement result based on the measurement output and the conversion mechanism, which maps the measured charge loss in the first type of cell to the estimated charge loss in the second type of cell, and Extracting an access adjustment based on the converted measurement result, wherein the access adjustment is for adjusting the read level voltage for the second type of cell, The method comprising the above.

7. The method according to claim 6, wherein the measurement output is obtained Gradually increasing the access group voltage in the first type of cell, The measurement output is determined as the access group voltage that produces a predetermined reaction with respect to the first type of cell, The adjusted access level is calculated based on combining the aforementioned access adjustment with the converted measurement results, and The method comprising reading the second type of cell using the adjusted access level.

8. The method according to claim 7, The first type of cell and the second type of cell include a memory block. The first type of cell is connected to a proxy word line, The first memory density is the maximum memory density for the memory block, The second type of cell is (1) connected to a separate memory word line, and (2) dynamically configured to store the second memory density less than the maximum memory density, Gradually increasing the access group voltage includes continuing to gradually increase the access group voltage during and after determining the measurement output and while calculating the converted measurement result, extracting the access adjustment, and calculating the adjusted access level. Reading the second type of cell described above is: Simultaneously with the access group voltage, the voltage to the memory word line is gradually increased, and The method comprising raising the voltage on the memory word line to at least the adjusted access level.

9. The method according to claim 8, The maximum storage density for the memory block is 4 bits per cell. The method wherein the second type of cell is a QLC dynamically configured to operate as a TLC to reduce read and write times.

10. The method according to claim 7, Gradually increasing the access group voltage means The access group voltage is increased to the minimum measurable value according to the initial step size, and The method comprises increasing the access group voltage beyond the minimum measurement value using a measurement step size having a smaller scale, a longer duration, or both, compared to the first step size.

11. A memory device, A rewritable memory cell comprising a first type of cell and a second type of cell, each designated to store a different number of bits, and configured to store charges representing stored data, grouped into blocks, and A logic circuit coupled to the rewritable memory cell, Determine a proxy access group which includes a set of the first type of cells configured to model the charge loss for the second type of cell, The surrogate access group is padded to establish an initial state for tracking the charge level in the second type of cell, The measurement output representing the charge loss over time from the initial state is obtained directly from the proxy access group, and Using the measurement output, access adjustments for reading the second type of cell are extracted based on transforming the measurement output to represent the estimated charge loss in the second type of cell. The logic circuit configured as described above, A memory device including the following.

12. A memory device according to claim 11, The aforementioned rewritable memory cell is a flash memory cell. The second type of cell is a triple-level cell (TLC), and also, The memory device wherein the first type of cell is a quad-level cell (QLC).

13. A memory device according to claim 11, The memory device wherein the second type of cell has (1) a maximum storage capacity greater than the first number of bits, and (2) is configured to store less than the maximum capacity in order to reduce the write time.

14. A memory device according to claim 13, The second type of cell includes a memory block and is dynamically configured to store less than the maximum capacity, The memory device wherein the proxy access group is a word line in the memory block configured to operate as a cell of the first type.

15. A memory device according to claim 11, The memory device wherein the logic circuit is configured to extract the access adjustment instead of (1) tracking the storage period in the second type of cell, (2) directly measuring the charge loss in the second type of cell, or (3) making adjustments with respect to temperature, or a combination thereof.

16. A memory device according to claim 11, The memory device is configured such that the logic circuit acquires the measurement output and calculates the converted measurement result during readout error handling, media scanning, periodic scanning, or a combination thereof.

17. A memory device according to claim 11, The aforementioned logic circuit is The access group voltage for the aforementioned proxy access group is gradually increased. The measurement output is determined as the access group voltage that produces a predetermined reaction with respect to the first type of cell. The converted measurement result is calculated based on the measurement output and the conversion mechanism, and the measured charge loss in the first type of cell is mapped to the estimated charge loss in the second type of cell. Based on the converted measurement results, the access adjustment is extracted, The adjusted access level is calculated based on the combination of the aforementioned access adjustment with the converted measurement results, and Read the second type of cell using the adjusted access level. The memory device configured as described above.

18. A memory device according to claim 17, The first type of cell and the second type of cell include a memory block. The proxy access group includes the first type of cell connected to the proxy word line, The first memory density is the maximum memory density for the memory block, The second type of cell is (1) connected to a separate memory word line, and (2) dynamically configured to store the second memory density less than the maximum memory density, The aforementioned logic circuit further, During and after determining the measurement output, in parallel with (1) calculating the converted measurement result, (2) extracting the access adjustment, and calculating the adjusted access level, the access group voltage is continuously increased. The voltage is gradually increased on the memory word line that matches the access group voltage, Based on raising the voltage on the memory word line to at least the adjusted access level, The memory device configured to read out the second type of cell.

19. A memory device according to claim 18, The maximum storage density for the memory block is 4 bits per cell. The memory device wherein the second type of cell is a QLC dynamically configured to store three bits or less per cell in order to reduce read and write times.

20. A memory device according to claim 17, The aforementioned logic further, The access group voltage is increased to the minimum measurable value according to the initial step size, and Using a measurement step size having a smaller scale, a longer duration, or both compared to the first step size, to increase the access group voltage beyond the minimum measurement value, The memory device is configured to gradually increase the access group voltage based on the following.

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