Interconnection capping by integrated processing step

Abstract

A cluster tool for forming an interconnect structure includes a pre-cleaning chamber, a selective chemical vapor deposition (CVD) chamber, a plasma-enhanced CVD (PECVD) chamber, one or more transfer chambers connected to the pre-cleaning chamber, the selective CVD chamber, and the PECVD chamber, configured to transfer the interconnect structure between the pre-cleaning chamber, the selective CVD chamber, and the PECVD chamber without disrupting the vacuum environment, a controller configured to pre-clean the exposed surface of a metal layer formed in a first dielectric layer of the interconnect structure in the pre-cleaning chamber, and selectively depositing a cap layer on the pre-cleaned surface of the metal layer in the selective CVD chamber, and depositing a second dielectric layer on the exposed surface of the cap layer and the first dielectric layer in the PECVD chamber.

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure generally relate to a method of forming an interconnect structure for semiconductor applications.

Background Art

[0002]

[0002] For example, as the dimensions of integrated circuit (IC) components in three-dimensional (3D) NAND peripheral complementary metal-oxide semiconductor (CMOS) devices shrink (e.g., to sub-micron dimensions), copper (Cu) wires have been used to fabricate such components due to their low sheet resistance and high electromigration (EM) resistance, instead of aluminum (Al). A typical back-end-of-line (BEOL) interconnect wire includes a copper (Cu) wire encapsulated by a metal cap layer to improve EM performance, and a dielectric layer as a diffusion barrier layer.

[0003]

[0003] Conventionally, a dielectric layer (e.g., silicon carbon nitride (SiCN)) has been deposited in a cluster tool different from the cluster tool in which a metal cap layer (e.g., cobalt (Co)) is deposited for Cu interconnects. To reduce oxidation of the metal cap layer, the wafer can be transferred through a nitrogen (N2)-purged front-opening unified pod (FOUP) between cluster tools. However, oxidation of the metal cap layer cannot be eliminated, and thus a pre-cleaning process of the metal cap layer before deposition of the dielectric layer may be required, which damages the underlying layer. Further, it is necessary to control the queue time of the cluster tool.

[0004]

[0004] Therefore, there is a need for a method and system for forming a metal interconnect having a metal cap layer and a dielectric layer in a simplified step without being exposed to the surrounding environment.

Summary of the Invention

[0005]

[0005] Embodiments of the present disclosure provide a cluster tool for forming an interconnection structure. The cluster tool is an apparatus comprising: a pre-cleaning chamber configured to pre-clean the exposed surface of a metal layer formed in a first dielectric layer of the interconnect structure; a selective chemical vapor deposition (CVD) chamber configured to selectively deposit a cap layer on the pre-cleaned surface of the metal layer; a plasma CVD (PECVD) chamber configured to deposit a second dielectric layer on the exposed surface of the cap layer and the first dielectric layer; one or more transfer chambers connected to the pre-cleaning chamber, the selective CVD chamber, and the PECVD chamber, configured to transfer the interconnect structure between the pre-cleaning chamber, the selective CVD chamber, and the PECVD chamber without disrupting the vacuum environment; and a controller configured to cause the pre-cleaning of the metal layer in the pre-cleaning chamber, the selective deposition of the cap layer in the selective CVD chamber, and the deposition of the second dielectric layer in the PECVD chamber.

[0006]

[0006] Embodiments of the present disclosure provide a method for forming an interconnect structure. The method includes: performing a pre-cleaning process in a pre-cleaning chamber to remove oxides formed on the exposed surface of a metal layer formed in a first dielectric layer of the interconnect structure; performing a selective deposition process in a selective chemical vapor deposition (CVD) chamber to deposit a cap layer on the pre-cleaned surface of the metal layer; and performing a blanket deposition process in a plasma CVD (PECVD) chamber to deposit a second dielectric layer on the exposed surface of the cap layer and the first dielectric layer, wherein the pre-cleaning process, the selective deposition process, and the blanket deposition process are performed in the cluster tool with respect to the external environment of the cluster tool, without being exposed to the external environment of the cluster tool.

[0007]

[0007] Embodiments of the present disclosure provide a method for forming an interconnect structure. The method includes performing a selective deposition process to deposit a cap layer on the exposed surface of a metal layer formed in a first dielectric layer of the interconnect structure in a selective chemical vapor deposition (CVD) chamber, and performing a blanket deposition process to deposit a second dielectric layer on the exposed surface of the cap layer and the first dielectric layer in a plasma CVD (PECVD) chamber, wherein the selective deposition process and the blanket deposition process are performed within the cluster tool without exposure to the ambient environment outside the cluster tool.

[0008]

[0008] To enable a more detailed understanding of the above-mentioned features of the Disclosure, a more specific description of the Disclosure, which has been briefly summarized above, can be given by reference to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings only show exemplary embodiments and should not be considered to limit the scope of the Disclosure, and the Disclosure may permit other equally effective embodiments. [Brief explanation of the drawing]

[0009] [Figure 1] This is a schematic top view of a multi-chamber cluster tool according to one or more embodiments of the present disclosure. [Figure 2] A flowchart illustrating a method for manufacturing an interconnection structure according to one embodiment of the present disclosure is shown. [Figure 3A-3D] Figure 2 shows a partial cross-sectional view of the semiconductor structure corresponding to various states of the method. [Modes for carrying out the invention]

[0010]

[0012] To facilitate understanding of the embodiments, the same reference numerals were used, where possible, to indicate identical elements common to multiple figures. It is assumed that elements and features of one embodiment may be advantageously incorporated into other embodiments without further explanation.

[0011]

[0013] A system and method are provided for capping back-end obline (BEOL) interconnect wires (e.g., copper (Cu)) with a metal cap layer (e.g., cobalt (Co)) and a dielectric layer (e.g., silicon carbonitride (SiCN)) incorporated into a single cluster tool, without exposure to the ambient environment outside the cluster tool. By eliminating exposure to the ambient environment, contamination of the metal cap layer before deposition of the dielectric layer can be avoided, which leads to improved adhesion of the dielectric layer on the metal cap layer and, consequently, improved time-dependent dielectric breakdown (TDDB) lifetime of the low dielectric layer surrounding the interconnect wires. Furthermore, the use of a metal cap layer (e.g., cobalt (Co)) between the metal layer (e.g., copper (Cu)) and the dielectric layer improves the electromigration (EM) performance of the metal layer.

[0012]

[0014] Figure 1 is a schematic top view of a multi-chamber cluster tool 100 according to one or more embodiments of the present disclosure. The cluster tool 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chamber 108, a transfer robot 110 having one or more transfer blades 112 (two shown), and one or more twin-chamber processing systems 114, 116, 118 (three shown), each of which includes two processing chambers 120 and 122, 124 and 126, 128 and 130. Each of the twin-chamber processing systems 114, 116, 118 includes an independent processing space that may be separated from each other and may share resources (e.g., processing gas supply, vacuum pump) between the two processing chambers. As detailed herein, the substrate W within the cluster tool 100 can be processed in various chambers and transferred between various chambers without exposing the substrate W to the ambient environment outside the cluster tool 100 (e.g., the ambient air environment that may exist in a factory). For example, the substrate W can be processed and transferred in various chambers maintained at low pressure (e.g., about 300 Torr or less) or in a vacuum environment without breaking the low-pressure or vacuum environment during the various processes performed on the substrate W within the cluster tool 100. Thus, the cluster tool 100 can provide an integrated solution for several processes of the substrate W.

[0013]

[0015] Examples of processing systems that can be appropriately modified in accordance with the teachings provided herein include the Centura® or Producer® integrated processing systems, or other suitable processing systems, commercially available from Applied Materials, Inc., located in Santa Clara, California. Other processing systems (including those from other manufacturers) may be adapted to benefit from the embodiments described herein.

[0014]

[0016] In the example shown in Figure 1, the factory interface 102 includes a docking station 132 and a factory interface robot 134 to facilitate the transfer of substrates W. The docking station 132 is adapted to receive one or more forward-opening unified pods (FOUPs) 136. In some embodiments, each factory interface robot 134 generally includes a blade 138 located at one end of the respective factory interface robot 134, adapted to transfer substrates W from the factory interface 102 to the load lock chambers 104, 106.

[0015]

[0017] The load lock chambers 104 and 106 have ports 140 and 142, respectively, connected to the factory interface 102, and ports 144 and 146, respectively, connected to the transfer chamber 108. The transfer chamber 108 further has ports 148, 150, 152, 154, 156, and 158, connected to the processing chambers 120, 122, 124, 126, 128, and 130. Ports 144, 146, 148, 150, 152, 154, 156, and 158 can be slit valve openings having slit valves to provide a seal for passing substrates W by, for example, a transfer robot 110 and preventing gas from passing between the respective chambers. Generally, any port is open for transferring substrates. Otherwise, the port is closed.

[0016]

[0018] The load lock chambers 104, 106, transfer chamber 108, and processing chambers 120, 122, 124, 126, 128, 130 may be fluid-coupled to a gas and pressure control system (not shown). The gas and pressure control system may include one or more gas pumps (e.g., turbopumps, cryopumps, roughing pumps), a gas source, various valves, and conduits fluid-coupled to the various chambers. During operation, the factory interface robot 134 transfers the substrate from the FOUP 136 to the load lock chamber 104 or 106 via port 140 or 142. The gas and pressure control system then pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chamber 108 in an internal low-pressure or vacuum environment (which may include an inert gas). Therefore, pumping down the load lock chamber 104 or 106 facilitates the passage of the substrate between, for example, the atmospheric environment of the factory interface 102 and the low-pressure or vacuum environment of the transfer chamber 108.

[0017]

[0019] With the substrate in load lock chamber 104 or 106 pumped down, the transfer robot 110 transfers the substrate from load lock chamber 104 or 106 through port 144 or 146 into transfer chamber 108. The transfer robot 110 can then transfer the substrate to any of the processing chambers 120, 122, 124, 126, 128, and 130 for processing through their respective ports 148, 150, 152, 154, 156, and / or transfer the substrate between any of the processing chambers 120, 122, 128, and 130. Transfer of the substrate within and between the various chambers may be in a low-pressure or vacuum environment provided by a gas and pressure control system.

[0018]

[0020] Processing chambers 120, 122, 124, 126, 128, and 130 can be any suitable chamber for processing the substrate. In some embodiments, processing chamber 120 can perform an etching process, processing chamber 122 can perform a cleaning process, and processing chambers 124, 126, 128, and 130 can perform a deposition process. Processing chamber 120 may be a Selectra® etching chamber available from Applied Materials in Santa Clara, California. Processing chamber 122 may be an Aktiv® Preclean (APC) chamber available from Applied Materials in Santa Clara, California. Processing chambers 124 and 126 may be Volta® Cobalt CVD chambers available from Applied Materials in Santa Clara, California. Processing chamber 128 may be a Blok® PECVD chamber available from Applied Materials in Santa Clara, California.

[0019]

[0021] The system controller 160 is connected to the cluster tool 100 to control the cluster tool 100 or its components. For example, the system controller 160 can control the operation of the cluster tool 1110 by using direct control of the chambers 104, 106, 108, 120, 122, 124, 126, 128, and 130 of the cluster tool 100, or by controlling the controllers associated with the chambers 104, 106, 108, 120, 122, 124, and 126. During operation, the system controller 160 enables data acquisition and feedback from each chamber to adjust the performance of the cluster tool 100.

[0020]

[0022] The system controller 160 generally includes a central processing unit (CPU) 162, memory 164, and support circuitry 166. The CPU 162 may be one of any form of general-purpose processor available for use in an industrial environment. The memory 164 or non-temporary computer-readable medium is accessible by the CPU 162 and may be one or more of the following: random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of local or remote digital storage. The support circuitry 166 is connected to the CPU 162 and may include a cache, clock circuitry, input / output subsystems, power supply, etc. The various methods disclosed herein can generally be implemented by the CPU 162 executing, for example, computer instruction code stored in memory 164 (or the memory of a particular processing chamber) as a software routine under the control of the CPU 162. Once the computer instruction code is executed by the CPU 162, the CPU 192 controls each chamber to perform processing according to various schemes.

[0021]

[0023] Other processing systems can also be configured in other ways. For example, more or fewer processing chambers can be connected to the transfer device. In the illustrated embodiment, the transfer device includes a transfer chamber 108. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as transfer devices within the processing system.

[0022]

[0024] FIG. 2 shows a process flow diagram of a method 200 for forming a semiconductor structure 300 that may include a dual damascene interconnect structure utilized in a back-end-of-line (BEOL) according to one or more embodiments of the present disclosure. FIGS. 3A, 3A’, 3B’, 3C’, 3C’, 3D, and 3D’ are cross-sectional views of a portion of the semiconductor structure 300 corresponding to various states of the method 200. FIGS. 3A, 3A’, 3B’, 3C’, 3C’, 3D, and 3D’ show only partial schematic views of the semiconductor structure 300, and it should be understood that the semiconductor structure 300 may include any number of transistor sections and additional materials having aspects as shown in the figures. Also, while the method shown in FIG. 2 is described sequentially, other processing sequences including one or more steps that are omitted and / or added and / or rearranged in another desired order are within the scope of the embodiments of the disclosure described herein.

[0023]

[0025] As shown in FIG. 3A, the semiconductor structure 300 includes a metal layer 302 encapsulated within a metal seed layer 304 and within a barrier layer, and a liner (shown combined in the figure) 306, within a dielectric layer 308 formed on a substrate (not shown). In some embodiments, as shown in FIG. 3A’, the metal layer 302 is recessed from the upper surface 308S of the dielectric layer 308.

[0024]

[0026] The dielectric layer 308 may be formed of a low-k dielectric material such as silicon oxide (SiO2) or carbon-containing silicon oxide (SiOC), e.g., a Black Diamond (registered trademark) dielectric film available from Applied Materials, or another low-k polymer such as polyamide, by a suitable lithography method, and may be patterned by an aperture 310.

[0025]

[0027] The barrier layer can be formed of a transition metal such as tantalum (Ta) or titanium (Ti), and a nitride such as tantalum nitride (TaN) or titanium nitride (TiN). The liner can be formed of cobalt (Co) or ruthenium (Ru). The barrier layer and the liner 306 are deposited on the patterned dielectric layer 308 by a suitable deposition process such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0026]

[0028] The metal layer 302 and the metal seed layer 304 can be formed of a metal, such as copper (Cu), a copper-aluminum (CuAl) alloy (Al at a ratio of 0.1 to 5 atomic %), or a copper-manganese (CuMn) alloy (Mn at a ratio of 0.1 to 5 atomic %). Since the conductivity of the metal (e.g., copper (Cu)) on the barrier layer 306 (e.g., Ta / TaN) is low and nucleation is insufficient, the metal seed layer 304 can be deposited by CVD, PVD, atomic layer deposition (ALD), electrophoretic deposition (ED) process, or other suitable deposition processes to ensure defect-free filling of the openings 3111100 with the metal in the metallization process.

[0027]

[0029] The semiconductor structure 300 can be planarized by a chemical mechanical polishing (CMP) process to remove the overfilled metal (e.g., copper (Cu)).

[0028]

[0030] The substrate can be a material such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, and patterned or unpatterned wafer silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, etc. The substrate can have various dimensions, such as wafers with a diameter of 200 mm, 300 mm, or 450 mm, and rectangular or square panels. Unless otherwise specified, the embodiments and examples described herein are implemented on substrates having a diameter of 300 mm or 450 mm.

[0029]

[0031] Method 200 begins in block 210. In block 210, an oxide 312 (e.g., copper oxide CuO) is formed on the exposed surface 302S of the metal layer 302, as shown in Figures 3B and 3B'. x A pre-cleaning process is performed to remove ). The pre-cleaning process may be performed in a pre-cleaning chamber such as the processing chamber 122 in Figure 1 or the Aktiv® Preclean (APC) chamber available from Applied Materials, Santa Clara, California, which can be appropriately adapted in a cluster tool such as the cluster tool 100 shown in Figure 1 or the Producer® cluster tool available from Applied Materials, Santa Clara, California.

[0030]

[0032] The pre-cleaning process involves the generation of reactive hydrogen radicals (H) by a remote plasma source within the pre-cleaning chamber. * This includes supplying hydrogen radicals H * Cleaning with hydrogen ions (H + Compared to cleaning by (), damage to the underlying dielectric layer 308 was reduced. In some embodiments, an inert gas such as argon (Ar) or helium (He) is also supplied into the pre-cleaning chamber.

[0031]

[0033] Reducing the oxide 312 on the surface 302S of the metal layer 302 may increase the metallic surface area of ​​the metal layer 302, improving the adhesion of the metal cap layer during the selective deposition process of block 220.

[0032]

[0034] In block 220, a selective deposition process is performed to deposit a capping layer 314 onto the pre-cleaned surface of the metal layer 302, as shown in Figures 3C and 3C'. The selective deposition process may include a selective CVD deposition process performed in a selective CVD chamber such as processing chamber 124 or 126, or a Volta® Cobalt CVD chamber available from Applied Materials, Santa Clara, California. This can be appropriately adapted to the cluster tool. The selective deposition process for block 220 is performed within the cluster tool after the pre-cleaning process for block 210, without exposing the semiconductor structure 300 to the ambient environment outside the cluster tool.

[0033]

[0035] The capping layer 314 is deposited upon completion of the metal level at the back-end of line (BEOL) to improve the reliability of the wiring, such as its electromigration (EM) performance. EM in thin metal interconnects (i.e., mass metal transport under stress due to high current density) occurs through diffusion at the interface between the metal and dielectric layers, potentially creating atomic vacancies and voids or hillocks at the interconnect. Void formation can result in open circuits and increased line resistance. Hillock formation can cause short circuits between adjacent interconnects. The capping layer 314 between the metal layer 302 and the dielectric layer can reduce EM between the metal layer 302 and the dielectric layer, thereby improving EM resistance.

[0034]

[0036] The cap layer 314 may be formed from a metal cap layer selectively deposited directly onto the pre-cleaned surface of the metal layer 302. The metal cap layer may include cobalt (Co), titanium (Ti), manganese (Mn), ruthenium (Ru), cobalt tungsten phosphide (CoWP), tungsten (W), nickel (Ni), platinum (Pt), copper (Cu), or alloys thereof, such as a titanium-copper (TiCu) alloy, and may have a thickness between about 1 nm and about 10 nm, for example, about 2 nm. In some embodiments, the cap layer 314 further includes a dielectric cap layer selectively deposited on the metal cap layer. The dielectric cap layer may include dielectric materials such as silicon nitride (SiN), nitrogen-doped carbon-containing silicon (e.g., silicon carbonitride (SiCN)), or carbon-containing silicon (e.g., silicon carbide (SiC)).

[0035]

[0037] In some other embodiments, the cap layer 314 is formed from a dielectric cap layer selectively deposited directly onto the pre-cleaned surface of the metal layer 302. The dielectric cap layer may include dielectric materials such as silicon nitride (SiN), nitrogen-doped carbon-containing silicon (e.g., silicon carbonitride (SiCN)), or carbon-containing silicon (e.g., silicon carbide (SiC)).

[0036]

[0038] In block 230, as shown in Figures 3D and 3D', a blanket deposition process is performed to deposit a dielectric layer 316 onto the exposed surfaces of the cap layer 314 and dielectric layer 308. The blanket deposition process may include a plasma-enhanced CVD (PECVD) process performed in a PECVD chamber available from Applied Materials, Santa Clara, California (e.g., the BLOk® PECVD chamber available from Applied Materials, Santa Clara, California). This process can be appropriately adapted and integrated within a pre-cleaning chamber such as the Aktiv® Preclean (APC) chamber available from Applied Materials, Santa Clara, California, and a selective CVD chamber such as the Volta® CVD chamber. The blanket deposition process for block 230 is performed within the cluster tool after the selective deposition process for block 220, without exposing the semiconductor structure 300 to the ambient environment outside the cluster tool.

[0037]

[0039] Conventional cluster tools do not integrate processing chambers adapted for depositing low dielectric materials with pre-cleaning chambers such as the Aktiv® Preclean (APC) chamber available from Applied Materials, Santa Clara, California, or selective CVD chambers such as the Volta® Cobalt CVD chamber available from Applied Materials, Santa Clara, California. Therefore, after the selective deposition process of block 220, the semiconductor structure 300 needs to be transferred from one cluster tool to another via a nitrogen-purged FOUP to minimize oxidation or any other influence from exposure to the ambient environment outside the cluster tool. Furthermore, since the cap layer 314 (e.g., cobalt (Co)) is readily oxidized even in a nitrogen-purged FOUP, another pre-cleaning process may be performed after transfer via the nitrogen-purged FOUP to remove oxides and contaminants from the exposed surface of the cap layer 314. This pre-cleaning process may use capacitively coupled plasma (CCP) ammonia (NH3) plasma, which damages the underlying dielectric layer 308 and / or increases the dielectric constant of the low dielectric material within the dielectric layer 308. Destruction of the underlying dielectric layer 308 can lead to short circuits between adjacent interconnects, increasing the resistance-capacitance (RC) delay.

[0038]

[0040] In the cluster tool according to the embodiments described herein, Plasma-enhanced CVD (PECVD) chambers (for example, BLOk® CVD chambers available from Applied Materials in Santa Clara, California) A pre-cleaning chamber (e.g., an Aktiv® Preclean (APC) chamber available from Applied Materials, Santa Clara, California) and a selective CVD chamber (e.g., a Volta® Cobalt CVD chamber available from Applied Materials, Santa Clara, California) are integrated to allow the semiconductor structure 300 to be transferred from the pre-cleaning chamber to the selective CVD chamber, and from the selective CVD chamber to the PECVD chamber, without exposure to the ambient environment outside the cluster tool. Thus, oxidation of the capping layer 314 can be avoided, and there is no pre-cleaning process (with CCP ammonia (NH3) plasma) to remove oxides from the capping layer 314. Furthermore, a FOUP with nitrogen flow capability is not required, nor is it necessary to control the waiting time during which the semiconductor structure 300 is outside the processing chamber or controlled environment.

[0039]

[0041] By eliminating exposure to the surrounding environment, the reliability of the device, such as time-dependent dielectric breakdown (TDDB) (i.e., dielectric degradation due to electric fields), and the lifespan of the dielectric layer 308 can be improved. This is because the adhesion of the dielectric layer 316 to the cap layer is improved due to the absence of contamination (e.g., moisture or carbon) on the cap layer due to exposure to the surrounding environment.

[0040]

[0042] The dielectric layer 316 can be formed from a low dielectric material (e.g., a dielectric constant of about 5.5 or less), such as BLOk® low dielectric film available from Applied Materials, Inc.

[0041]

[0043] The dielectric layer 316 acts as a diffusion barrier layer, preventing the diffusion of metallic elements (e.g., copper (Cu)) from the metal layer 302, which could lead to short circuits and other device defects. The dielectric layer 316 can also function as an etching stop layer in subsequent patterning processes. The dielectric layer 316 can have a thickness between approximately 1 nm and approximately 100 nm.

[0042]

[0044] In some embodiments, the dielectric layer 316 includes a reinforced nitrogen interface (ENI) to further improve reliability.

[0043]

[0045] Following the blanket deposition process of block 230, other layers, such as an ILD (interlayer dielectric) layer (not shown), may be deposited on the dielectric layer 316 within the same cluster tool or a different cluster tool. During transfer to another tool, the cap layer 314 is protected from oxidation by the dielectric layer 316.

[0044]

[0046] Embodiments provided herein offer a system and method for capping back-end ob-line (BEOL) interconnect wires (e.g., copper (Cu)) having a metal cap layer (e.g., cobalt (Co)) and a dielectric layer (e.g., silicon carbonitride (SiCN)) within a single cluster tool without exposure to the ambient environment outside the cluster tool. The use of a metal cap layer can improve the electromigration (EM) performance of the interconnect wires. Because exposure to the ambient environment is eliminated, the time-dependent breakdown-of-dielectric-duration (TDDB) lifetime of the low-dielectric-constant dielectric layer surrounding the metal layer can be improved. The processing steps for capping the interconnect wires are integrated into a single cluster tool so that latency control is not required.

[0045]

[0047] While the above description applies to embodiments of the present disclosure, other embodiments and further embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure, and the scope of the present disclosure is determined by the following claims.

Claims

1. A cluster tool for forming interconnection structures, A pre-cleaning chamber configured to pre-clean the exposed surface of a metal layer formed within the first dielectric layer of the interconnection structure, A selective chemical vapor deposition (CVD) chamber is configured to selectively deposit a cap layer onto the pre-cleaned surface of the metal layer, A plasma CVD (PECVD) chamber configured to deposit a second dielectric layer on the exposed surfaces of the cap layer and the first dielectric layer, One or more transfer chambers connected to the pre-cleaning chamber, the selective CVD chamber, and the PECVD chamber, wherein one or more transfer chambers are configured to transfer the interconnection structure between the pre-cleaning chamber, the selective CVD chamber, and the PECVD chamber without disrupting the vacuum environment, A controller configured to cause pre-cleaning of the metal layer in the pre-cleaning chamber, selective deposition of the cap layer in the selective CVD chamber, and deposition of the second dielectric layer in the PECVD chamber, A cluster tool equipped with these features.

2. Pre-cleaning the exposed surface of the metal layer is performed by generating reactive hydrogen radicals H by a remote plasma source in the pre-cleaning chamber. ＊ The cluster tool according to claim 1, comprising supplying the following.

3. The metal layer comprises at least one of copper (Cu), copper-aluminum (CuAl) alloy, and copper-manganese (CuMn) alloy. The first dielectric layer is silicon oxide (SiO ２ ) or includes a low dielectric constant dielectric material, The second dielectric layer includes a low dielectric constant dielectric material. The cluster tool according to claim 1.

4. The cluster tool according to claim 1, wherein the cap layer comprises a metal cap layer selectively deposited on the pre-cleaned surface of the metal layer, and the metal cap layer comprises at least one of cobalt (Co), titanium (Ti), manganese (Mn), ruthenium (Ru), cobalt tungsten phosphide (CoWP), tungsten (W), nickel (Ni), platinum (Pt), copper (Cu), and alloys thereof.

5. The cluster tool according to claim 4, wherein the cap layer further comprises a first dielectric cap layer selectively deposited on the metal cap layer, the first dielectric cap layer comprising at least one of silicon nitride, nitrogen-doped carbon-containing silicon, and carbon-containing silicon.

6. The cluster tool according to claim 1, wherein the cap layer comprises a second dielectric cap layer selectively deposited on the pre-cleaned surface of the metal layer, and the second dielectric cap layer comprises at least one of silicon nitride, nitrogen-doped carbon-containing silicon, and carbon-containing silicon.

7. A method for forming an interconnection structure, In the pre-cleaning chamber, a pre-cleaning process is performed to remove oxides formed on the exposed surface of the metal layer formed in the first dielectric layer of the interconnection structure. To deposit a cap layer on the pre-cleaned surface of the metal layer in a selective chemical vapor deposition (CVD) chamber, a selective deposition process is performed. A blanket deposition process is performed to deposit a second dielectric layer on the exposed surfaces of the cap layer and the first dielectric layer within a plasma CVD (PECVD) chamber. Includes, A method in which a pre-washing process, a selective deposition process, and a blanket deposition process are performed within the cluster tool without being exposed to the ambient environment outside the cluster tool.

8. The metal layer comprises at least one of copper (Cu), copper-aluminum (CuAl) alloy, and copper-manganese (CuMn) alloy. The first dielectric layer is silicon oxide (SiO ２ ) or includes a low dielectric constant dielectric material, The second dielectric layer includes a low dielectric constant dielectric material. The method according to claim 7.

9. The method according to claim 7, wherein the cap layer comprises a metal cap layer selectively deposited on the pre-cleaned surface of the metal layer, and the metal layer comprises at least one of cobalt (Co), titanium (Ti), manganese (Mn), ruthenium (Ru), cobalt tungsten phosphide (CoWP), tungsten (W), nickel (Ni), platinum (Pt), copper (Cu), and alloys thereof.

10. The method according to claim 9, wherein the cap layer further comprises a first dielectric cap layer selectively deposited on the metal cap layer, and the first dielectric cap layer comprises at least one of silicon nitride, nitrogen-doped carbon-containing silicon, and carbon-containing silicon.

11. The method according to claim 7, wherein the cap layer comprises a second dielectric cap layer selectively deposited on the pre-cleaned surface of the metal layer, and the second dielectric cap layer comprises at least one of silicon nitride, nitrogen-doped carbon-containing silicon, and carbon-containing silicon.

12. The pre-cleaning process generates reactive hydrogen radicals H by a remote plasma source in the pre-cleaning chamber. ＊ The method according to claim 7, which includes supplying.

13. The method according to claim 7, wherein the selective deposition treatment includes selective CVD treatment.

14. The method according to claim 7, wherein the blanket deposition process includes a PECVD process.

15. A method for forming an interconnection structure, In order to deposit a cap layer on the exposed surface of the metal layer formed in the first dielectric layer of the interconnection structure within a selective chemical vapor deposition (CVD) chamber, a selective deposition process is performed. A blanket deposition process is performed to deposit a second dielectric layer on the exposed surfaces of the cap layer and the first dielectric layer within a plasma CVD (PECVD) chamber. Includes, A method in which selective deposition and blanket deposition processes are performed within a cluster tool without exposure to the surrounding environment outside the cluster tool.

16. The metal layer comprises at least one of copper (Cu), copper-aluminum (CuAl) alloy, and copper-manganese (CuMn) alloy. The first dielectric layer is silicon oxide (SiO ２ ) or includes a low dielectric constant dielectric material, The second dielectric layer includes a low dielectric constant dielectric material. The method according to claim 15.

17. The method according to claim 15, wherein the cap layer comprises a metal cap layer selectively deposited on a pre-cleaned surface of the metal layer, and the metal cap layer comprises at least one of cobalt (Co), titanium (Ti), manganese (Mn), ruthenium (Ru), cobalt tungsten phosphide (CoWP), tungsten (W), nickel (Ni), platinum (Pt), copper (Cu), and alloys thereof.

18. The method according to claim 17, wherein the cap layer further comprises a first dielectric cap layer selectively deposited on the metal cap layer, and the first dielectric cap layer comprises at least one of silicon nitride, nitrogen-doped carbon-containing silicon, and carbon-containing silicon.

19. The method according to claim 15, wherein the cap layer comprises a second dielectric cap layer selectively deposited on a pre-cleaned surface of the metal layer, and the second dielectric cap layer comprises at least one of silicon nitride, nitrogen-doped carbon-containing silicon, and carbon-containing silicon.

20. The method according to claim 15, wherein the selective deposition treatment includes selective CVD treatment and the blanket deposition treatment includes PECVD treatment.

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