Package substrate having electronic components mounted within the core cavity of the package substrate using resin.

Abstract

In one embodiment, an electronic device is disclosed, comprising a substrate, a core having an upper plane and a lower plane, the core including a cavity extending through the core; an electronic component at least partially disposed within the cavity, the electronic component having an upper plane with one or more electronic component terminals; a first cured resin layer, the first cured resin layer in which the upper plane of the electronic component is at least partially embedded in the first cured resin layer in at least the upper portion of the cavity; and an upper metallization structure disposed on the upper plane of the core, the upper metallization structure configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

Description

Technical Field

[0001]

[0001] This disclosure generally relates to package substrates, and more particularly to package substrates having embedded electronic components implemented within the cores of package substrates.

Background Art

[0002]

[0002] Integrated circuit (IC) technology has achieved great progress in improving computing power by miniaturizing electrical components. An IC can be realized in the form of an IC chip having a set of circuits integrated thereon. In some mounting forms, one or more IC chips can be physically carried and protected by an IC package, and various power and signal nodes of the one or more IC chips can be electrically coupled to respective conductive terminals of the IC package via electrical paths formed within the package substrate of the IC package. Various packaging technologies can be found in many electronic devices, including processors, servers, radio frequency (RF) integrated circuits, and the like. Advanced packaging and processing techniques can be used to realize composite devices, such as multi-electronic component devices and system-on-a-chip (SOC) devices, which can include multiple functional blocks designed to perform specific functions, such as, for example, microprocessor functions, graphics processing unit (GPU) functions, communication functions (e.g., WiFi, Bluetooth, and other communications), and the like.

[0003]

[0003] In some implementations, embedded passive devices, such as deep trench capacitors, are incorporated into the IC packaging for improved performance and reduced package size. One factor driving the use of such embedded passive devices is the demand for small form factor products that have electrical performance equivalent to or better than their larger passive device counterparts. Depending on the size and / or thickness of the package substrate, and the size and / or process node of the IC chip supported thereon, a process for embedding a passive device in the package substrate in one packaging task may not be suitable for another packaging task.

[0004]

[0004] Therefore, there is a need for an improved method for embedding electrical components in a substrate such as a package substrate, which can be used for a wider variety of packaging tasks. [Overview of the project]

[0005]

[0005] The following provides a simplified overview of one or more embodiments disclosed herein. Therefore, the following overview should not be considered a broad overview of all intended embodiments, nor should it be considered to identify the main or important elements of all intended embodiments, or to define the scope associated with any particular embodiment. Accordingly, the sole purpose of the following overview is to provide, in a simplified form, certain concepts relating to one or more embodiments of the mechanisms disclosed herein, prior to the detailed descriptions presented below.

[0006]

[0006] In one embodiment, the electronic device includes a substrate comprising: a core having an upper plane and a lower plane, the core including a cavity extending between the upper plane and the lower plane of the core; an electronic component at least partially disposed within the cavity, the electronic component having an upper plane with one or more electronic component terminals; a first cured resin layer, the first cured resin layer in which the upper plane of the electronic component is at least partially embedded in the first cured resin layer in at least the upper portion of the cavity; and an upper metallization structure disposed on the upper plane of the core, the upper metallization structure configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

[0007]

[0007] In one embodiment, the substrate includes a core having an upper plane and a lower plane, the core including a cavity extending between the upper plane and the lower plane of the core; an electronic component at least partially disposed within the cavity, the electronic component having an upper plane with one or more electronic component terminals; a first cured resin layer, the first cured resin layer in which the upper plane of the electronic component is at least partially embedded in the first cured resin layer in at least the upper portion of the cavity; and an upper metallization structure disposed on the upper plane of the core, the upper metallization structure configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

[0008]

[0008] In one embodiment, a method for manufacturing a substrate includes forming a cavity in a core, the cavity extending between a first plane of the core and a second plane of the core; mounting an electronic component at least partially in the cavity, the electronic component including a first plane having one or more electronic component terminals, the first plane of the electronic component being at least partially embedded in a first cured resin layer at a first end of the cavity; and forming a first metallization structure on a first plane of the core, the first metallization structure configured to provide one or more conductive paths from one or more electronic component terminals to one or more metal terminals of the first metallization structure.

[0009]

[0009] Other purposes and advantages associated with the embodiments disclosed herein will become apparent to those skilled in the art based on the accompanying drawings and detailed description. [Brief explanation of the drawing]

[0010]

[0010] A more complete understanding of many aspects of this disclosure and their associated advantages will be easier to obtain if they are examined together with the accompanying drawings, which are presented not to limit this disclosure but merely to illustrate it, by referring to the following detailed description. [Figure 1]

[0011] Figure 1 is a cross-sectional view of an exemplary substrate having embedded electronic components according to an aspect of the present disclosure. [Figure 2]

[0012] Figure 2 is an exemplary cross-sectional view of a substrate showing void propagation and resulting defects in a dielectric material according to an aspect of this disclosure. [Figure 3]

[0013] This is a cross-sectional view of an exemplary trench capacitor (DTC) according to an aspect of the present disclosure. [Figure 4]

[0014] Figures 4A and 4B are exemplary cross-sectional views of a substrate according to an aspect of the present disclosure. [Figure 5]

[0015] Figures 5A to 5D illustrate exemplary operations that may be performed during the manufacturing of an exemplary substrate according to embodiments of this disclosure. [Figure 6]

[0016] Figures 6A and 6B are exemplary cross-sectional views of a substrate according to an aspect of the present disclosure. [Figure 7ABC]

[0017] Figures 7A to 7C illustrate exemplary operations that may be performed during the manufacturing of an exemplary substrate according to an aspect of this disclosure. [Figure 7DE] Figures 7D and 7E illustrate exemplary operations that may be performed during the manufacturing of an exemplary substrate according to an aspect of this disclosure. [Figure 8]

[0018] This flowchart shows an exemplary method for manufacturing a substrate according to an aspect of the present disclosure. [Figure 9]

[0019] A side view of a package including a surface mount substrate, an integrated device, and an integrated passive device according to an aspect of this disclosure is shown. [Figure 10]

[0020] This disclosure illustrates exemplary methods for providing or manufacturing a package including an integrated device comprising a package substrate. [Figure 11]

[0021] This document illustrates various electronic devices that may be integrated with any of the package substrates of this disclosure.

[0011]

[0022] By convention, features depicted in the drawings may not be drawn to scale. Therefore, the dimensions of depicted features may be enlarged or reduced as appropriate for clarity. By convention, some of the drawings are simplified for clarity. Therefore, the drawings may not depict all parts of a particular apparatus or method. Furthermore, similar reference numerals indicate similar features throughout this specification and the drawings. [Modes for carrying out the invention]

[0012]

[0023] In the following description and the related drawings directed to specific embodiments, aspects of the present disclosure are shown. Alternative aspects or embodiments may be devised without departing from the scope of the teachings herein. Additionally, well-known elements of the exemplary embodiments herein may not be described in detail or may be omitted so as not to obscure the relevant details of the teachings in the present disclosure.

[0013]

[0024] In some of the described exemplary implementations, cases are identified where some of the structure and operation of various components can be incorporated from known conventional techniques and then configured according to one or more exemplary embodiments. In such cases, to help avoid the possibility of obscuring the concepts illustrated in the exemplary embodiments disclosed herein, details inside of some of the structure and / or operation of the known conventional components may be omitted.

[0014]

[0025] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. The singular forms "a", "an", and "the" used herein shall include the plural forms as well, unless the context clearly dictates otherwise. The terms "comprises", "comprising", "includes", and / or "including" when used herein specify the presence of the stated feature, integer, step, operation, element, and / or component, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0015]

[0026] FIG. 1 is a cross-sectional view of an exemplary substrate 100 having an embedded electronic component according to an aspect of the present disclosure. In this example, substrate 100 includes a core 102 having a cavity 104 that extends completely through the core 102. An electronic component 106 is disposed within the cavity 104. The electronic component 106 has an upper plane 108 with one or more electronic component terminals 110. According to various aspects of the present disclosure, the electronic component 106 can be one or more of an active electronic component, a passive electronic component (e.g., a deep trench capacitor (DTC)), a die, etc.

[0016]

[0027] According to various aspects of the present disclosure, the substrates described herein that include a core and an embedded electronic component (e.g., substrate 100) are targeted at package substrates. A package substrate is a part of an integrated circuit package that gives the board its mechanical strength and enables it to connect to external devices. Such a package substrate should be distinguished from other substrates, such as a substrate contained within the embedded electronic component itself, a die including a substrate (e.g., a silicon substrate or other similar electronic device).

[0017]

[0028] Substrate 100 further includes a plurality of dielectric layers 112 and a patterned metallization layer 114 lying on the upper plane 116 of core 102 (only one such dielectric layer and the corresponding patterned metal layer lying on the upper plane 116 are shown in FIG. 1). A patterned metallization layer 118 including via structures 120 is disposed on the upper plane 116 of core 102 to provide an electrical connection between one or more electronic component terminals 110 and the patterned metallization layer 114.

[0018]

[0029] In this example, one or more vias 122 extend through the core 102, connecting a patterned metallization layer 118 on the upper plane 116 of the core 102 to a further patterned metallization layer 124 on the lower surface 126 of the core 102. Further dielectric layers 128 and patterned metallization layers 130 are formed on the lower surface 126 of the core 102 (Figure 1 shows only one such dielectric layer and corresponding patterned metal layer formed on the lower surface 126).

[0019]

[0030] In one embodiment, the same dielectric material used to form the dielectric layer 128 may be used to fill the cavity 104. Commonly used dielectric materials include Ajinomoto Build-Up Film (ABF), PPG (registered trademark) liquid resin, and similar materials. During the fabrication of the substrate 100, the electronic component 106 is inserted into the cavity 104 before the dielectric resin is injected to fill the region 132 between the cavity 104 and the electronic component 106. During insertion, the electronic component 106 is carefully aligned within the cavity 104 to ensure that one or more electronic component terminals 110 make proper contact with the corresponding portions of the patterned metallization layer 118 and electrically couple. In addition, the injection of the dielectric resin into the region 132 must be carried out carefully so as not to disturb the initial alignment of the electronic component 106 within the cavity 104. In one embodiment, once the dielectric resin is cured, it fixes the electronic component 106 in its appropriate location within the cavity 104.

[0020]

[0031] Current trends in package substrate design are directed towards applications that present unique design and manufacturing challenges (e.g., the need to reduce substrate warpage, the need for cavities to accommodate large electronic components, the need for larger keep-out zones, etc.). These challenges can be addressed, at least in part, by employing thicker cores in the design and manufacturing of such substrates. For example, warpage control is more easily achieved with thicker cores than with thinner cores. In addition, the need for larger cavity sizes and keep-out zones can be met by employing such thicker cores. In some scenarios, cores (e.g., both thick and thin cores) may be required to accommodate large embedded electronic components that occupy a considerable volume of the cavity in which they are embedded.

[0021]

[0032] However, substrates employing thick cores or requiring large embedded electronic components may be difficult to fabricate using the same packaging techniques used in the production of substrates with thin cores and / or smaller embedded electronic components. When using thick cores, a large gap exists between the electronic component and the cavity resulting from the increased cavity depth compared to the height of the electronic component (for example, a thick core has a thickness greater than the die height). In such thick core scenarios, it may be difficult or impossible to fill the cavity (e.g., particularly the area between the outside of the electronic component and the inner wall of the cavity) with commonly used dielectric resins (e.g., Ajinomoto Build-Up Film® (ABF), PPG® liquid resin, etc.) without creating voids in the resulting dielectric material into which the electronic component is finally embedded. Similarly, when the electronic component occupies a considerable volume of the cavity, it may be difficult to adequately fill the small area between the electronic component and the cavity with commonly used dielectric resins without creating voids in the resulting dielectric material into which the electronic component is finally embedded.

[0022]

[0033] Figure 1 shows a void 134 in the dielectric material filling the cavity 104, which occurs when the region between the inner surface of the cavity 104 and the outer surface of the electronic component 106 is not properly filled with the dielectric material. In Figure 1, the void 134 in the dielectric material does not present an immediate problem regarding the connection between one or more electronic component terminals 110 and the patterned metallization layer 118. However, the void 134 may propagate through the dielectric material as a result of thermal and / or mechanical stresses that occur during the use of the substrate for its intended purpose.

[0023]

[0034] Figure 2 is a cross-sectional view of an exemplary substrate 100 showing the propagation of voids 134 in a dielectric material and the resulting defects according to an aspect of this disclosure. For simplicity, the reference numerals used in Figure 1 are also used to indicate similar elements in Figure 2.

[0024]

[0035] In Figure 2, the propagation of the void 134 allows the electronic component 106 to move within the cavity 104, resulting in the electronic component 106 detaching from the core 102. Such detachment can lead to performance degradation and / or complete failure of the electronic device on which the substrate 100 is incorporated.

[0025]

[0036] According to certain aspects of this disclosure, the electronic component may be a DTC. Figure 3 is a cross-sectional view of an exemplary DTC 300 according to an aspect of this disclosure. In Figure 3, a capacitor 310 is deposited in trenches 320 of an insulator 304 on a substrate 302. The capacitor 310 may include a metal layer 312, a dielectric layer 314, and a metal layer 316. The dielectric layer 314 separates the metal layer 312 from the metal layer 316. The metal layers 312, 316 form the electrodes of the capacitor 310 and may be connected to terminals on a surface, for example (see, for example, the upper plane 108 having the electronic component terminals 110 of the electronic component 106 shown in Figure 1). In some scenarios, the capacitor is formed from an array of deep trenches in the substrate and filled with an electrical insulator (e.g., a dielectric) between the electrode layers. In some scenarios, the capacitor is mounted on the land side under the shadow of the integrated circuit die (land-side capacitor, LSC), or mounted on the die side adjacent to the die (die-side capacitor, DSC).

[0026]

[0037] Some aspects of this disclosure are implemented with recognition of the problems associated with using existing processing techniques and materials to fabricate substrates having thick cores and / or cavities that house large embedded electronic components. According to some aspects of this disclosure, electronic components may be embedded in a cavity using a liquid resin that is dispensed into the cavity and then cured to fix the electronic components within the cavity. Some aspects of this disclosure are implemented with recognition of the fluid and other material properties (e.g., low viscosity, which is useful for filling large cavities) that allow the liquid resin to substantially fill the area between the inner surface of the cavity and the outer surface of the electronic component without creating voids, thereby resulting in a more rigid embedding of the electronic component into the core of the substrate. From a process point of view, liquid resin filling may be preferable to dielectric layer lamination for large cavities because dielectric layer lamination may require high pressure and temperature conditions that can cause movement of electronic components within the cavity. According to certain aspects of this disclosure, a liquid resin dispensed into a cavity during the manufacturing of a substrate can at least partially cure the electronic components once they are embedded in the liquid resin, thereby holding the electronic components in place while the rest of the cavity is filled with filler material (e.g., dielectric material, further liquid resin material, etc.). According to certain aspects of this disclosure, and not limited thereto, liquid resins such as the THP-100DX1 series liquid resin available from Taiyo America, Inc. and the PHP900 series liquid resin available from Yamaei Chemical Co., Ltd. are suitable for fixing electronic components within a cavity.

[0027]

[0038] Figures 4A and 4B are cross-sectional views of an exemplary substrate 400 according to an aspect of the present disclosure. As shown in Figure 4A, the substrate 400 includes an array of electronic components 402 embedded within a core 404. Figure 4B is an exploded view of a region 406 of the substrate 400 shown in Figure 4A.

[0028]

[0039] As shown in Figure 4B, the substrate 400 includes an electronic component 402 having a lower plane 408 and an upper plane 410. The lower plane nor 410 of the electronic component 402 includes one or more electronic component terminals 412 that provide electrical connections to the electronic component 402.

[0029]

[0040] The core 404 includes a lower plane 414 and an upper plane 416. A cavity 418 extends through the core 404 between the upper plane 416 and the lower plane 414. In this example, the thickness H1 of the core 404 is substantially the same as the height H2 of the electronic component 402. According to various aspects of this disclosure, the core 404 may be a thin core having a thickness H1 of 760 micrometers (μm) or less. Alternatively, the core may be a thick core having a thickness H1 greater than 760 μm (e.g., 820 μm or more, 1240 μm or more, etc.).

[0030]

[0041] According to various embodiments of this disclosure, the electronic component 402 is mounted in the upper portion of the cavity 418 within the cured resin layer 420. In the example shown in Figure 4B, the cured resin layer 420 fills the region of the cavity 418 between the upper plane 410 of the electronic component 402 and the bottom dielectric layer 422 of the upper metallization structure 424 disposed on the upper plane 416 of the core 404. In one embodiment, the cured resin layer 420 also at least partially fills the region of the cavity 418 between the inner sidewall of the core 404 and the outer sidewall of the electronic component 402.

[0031]

[0042] In the example shown in Figure 4B, the upper metallization structure 424 is configured to provide one or more conductive paths between one or more electronic component terminals 412 and one or more upper metal terminals 426 of the upper metallization structure 424. The conductive paths are provided by vias (e.g., vias 428) extending between one or more dielectric layers (e.g., dielectric layer 430) connecting one or more patterned metal layers (e.g., patterned metal layer 432). In one embodiment, the upper metal terminals 426 may be configured for connection to a surface mount electronic package (not shown in Figure 4B). In addition, or in alternative examples, the upper metal terminals 426 may be configured to connect the substrate 400 to other electronic components (e.g., active components, passive components, integrated circuits, etc.).

[0032]

[0043] Core vias (e.g., via 434) connect one or more patterned metal layers (e.g., patterned metal layer 436) of the upper metallization structure 424 to one or more patterned layers (e.g., patterned metal layer 438) of the lower metallization structure 440 in order to electrically connect the upper metallization structure 424 to the lower metallization structure 440. The lower metallization structure 440 provides one or more conductive paths between the patterned metal layer 438 and one or more terminals 442 of the lower metallization structure 440. The metal terminals 442 may be configured to connect the substrate 400 to other electronic components (e.g., active components, passive components, integrated circuits, etc.), including surface mount electronic packages (not shown in Figure 4B).

[0033]

[0044] The cured resin layer 420 maintains the electronic component 402 fixed within the cavity 418 and provides a substantially void-free solid material (e.g., void-free or having fewer and / or smaller voids than those typically found in conventional dielectric fillings used to embed electronic components under similar geometric filling constraints), thereby resulting in a robust mounting of the electronic component 402 within the cavity 418. Thus, the electronic component 402 is fixed within the cavity 418 in a manner that minimizes the opportunity for the electronic component 402 to detach from the core 404.

[0034]

[0045] In one embodiment, the cured resin layer 420 may be initially deposited as a liquid resin in the cavity 418. The electronic component 402 may be at least partially embedded in the liquid resin before the liquid resin is cured to form the cured resin layer 420. In this way, the electronic component 402 may be held in place in the cavity 418 as the remaining portion of the cavity 418 that is not initially filled with resin is filled with the filler material 444. In the example shown in Figure 4B, the filler material 444 is a dielectric material. In one embodiment, the dielectric material used as the filler material 444 may be the same dielectric material used to form one or more dielectric layers (e.g., dielectric layer 446) of the lower metallization structure 440.

[0035]

[0046] Although the dielectric layers of the upper metallization structure 424 are shown as separate layers in Figure 4B, it will be understood that multiple dielectric layers may be fused during the fabrication process so that they appear and function as a single dielectric structure. Furthermore, it will be understood that different layers of the dielectric layers of the upper metallization structure 424 may be formed from different dielectric materials during the fabrication process. In one embodiment, different dielectric materials may be used for different dielectric layers when one or more of the dielectric layers are to have a different dielectric constant than other dielectric layers.

[0036]

[0047] Similarly, the dielectric layers of the lower metallization structure 440 are shown as separate layers in Figure 4B. However, it will be understood that multiple dielectric layers may be fused during the manufacturing process so that they appear and function as a single dielectric structure. Furthermore, it will be understood that different layers of the dielectric layers of the upper metallization structure 424 may be formed from different dielectric materials during the manufacturing process. In one embodiment, different dielectric materials may be used for different dielectric layers when one or more of the dielectric layers are to have a different dielectric constant than other dielectric layers.

[0037]

[0048] Figures 5A to 5D illustrate exemplary operations that may be performed during the manufacturing of an exemplary substrate according to embodiments of the present disclosure. Figure 5A shows a first intermediate state 500 of the substrate during an exemplary manufacturing process according to embodiments of the present disclosure. In this example, the first intermediate state 500 of the substrate includes a core 502 having a first plane 504 and a second plane 506. In one embodiment, the core 502 undergoes a drilling operation to form a cavity 508 extending between the first plane 504 and the second plane 506 of the core 502. A layer of polyimide (PI) tape 510 is fixed onto the second plane 506 of the core 502, covering the opening of the cavity 508.

[0038]

[0049] Figure 5B shows a second intermediate state 512 of a substrate during an exemplary manufacturing process according to an aspect of the present disclosure. In this example, via holes are drilled through the core 502. The via holes undergo metallization and tenting operations to form core vias (e.g., core vias 514). Here, the core vias (e.g., core vias 514) connect patterned metallization layers (e.g., patterned metallization layers 516, 518) in the first plane 504 and the second plane 506 of the core 502. A quantity of liquid resin 520 is placed on the plane of the PI tape 510 at the central location within each cavity 508.

[0039]

[0050] Figure 5C shows a third intermediate state 522 of a substrate during an exemplary manufacturing process according to an aspect of the present disclosure. Here, each cavity 508 has an electronic component 524 inserted. In this example, each electronic component 524 has a height H2 which is the same dimension as the thickness H1 of the core H1. According to various aspects of the present disclosure, the electronic component 524 may be one or more of active electronic components, passive electronic components (e.g., deep trench capacitors (DTCs)), dies, etc.

[0040]

[0051] As shown in the figure, each electronic component 524 is inserted into the cavity 508 such that the plane 526 of the electronic component 524 and its corresponding electronic component terminals 528 are at least partially embedded in the liquid resin 520 of the cavity 508. In this example, the electronic component 524 pushes the liquid resin 520 so that it fills the area between the PI tape 510 and the plane 526 of the electronic component 524. In addition, depending on the amount of liquid resin 520 dispensed into the cavity 508, the electronic component 524 may push the liquid resin 520 to the extent that it fills a portion of the side wall of the cavity 508 adjacent to the electronic component 524 (for example, filling the area between the outer side wall 532 of the electronic component 524 and the inner side wall 534 of the cavity 508). Once each electronic component 524 is positioned within its respective cavity 508, the liquid resin 520 is cured (for example, by heat curing on a hot plate). The liquid resin 520 then forms a cured resin layer 520 within each cavity 508, which holds the electronic components 524 in place during subsequent substrate manufacturing operations (for example, filling the portions of the cavity 508 that are not yet filled with a cured resin layer (still identified using reference numeral 520)).

[0041]

[0052] Figure 5D shows the formation of a finished substrate 538 according to an embodiment of the present disclosure, where the PI tape 510 layer is removed. A first metallization structure 540 is formed on a first plane 504 of the core 502, and a second metallization structure 542 is formed on a second plane 506 of the core 502. In this example, portions of the cavity 508 not filled with the cured resin layer 520 are filled with dielectric material 544. In one embodiment, the dielectric material 544 may be the same dielectric material used to form one or more dielectric layers (e.g., dielectric layer 546) of the first metallization structure 540.

[0042]

[0053] According to certain aspects of this disclosure, the formation of metallization layers 540 and 542 may include an initial dielectric stacking operation on each of the planes 504 and 506 of the core 502. Following the initial dielectric stacking operation, one or more layer build-up operations may be performed. In one embodiment, each layer build-up operation may be carried out using a semi-additive process (SAP). According to such SAP, each dielectric layer is deposited and then laser-drilled to form via holes, which are subjected to an electroless plating process to deposit metal onto the walls of the via holes. If the via structures remain hollow after the electroless plating process, they may be filled with filler ink. During the build-up operation, patterned metallization layers may be formed on the dielectric layers using pattern plating and seed etching processes. The formation of metallization layers 540 and 542 may also employ surface roughness (SR) processing, surface treatment, and solder-on-pad (SOP) operations.

[0043]

[0054] Figures 6A and 6B are cross-sectional views of an exemplary substrate 600 according to an aspect of the present disclosure. As shown in Figure 6A, the substrate 600 includes an array of electronic components 602 embedded within a core 604. Figure 6B is an exploded view of a region 606 of the substrate 600 shown in Figure 6A.

[0044]

[0055] As shown in Figure 6B, the substrate 600 includes an electronic component 602 having a lower plane 608 and an upper plane 610. The lower plane 608 of the electronic component 602 includes one or more electronic component terminals 612 that provide electrical connections to the electronic component 602.

[0045]

[0056] The core 604 includes a lower plane 614 and an upper plane 616. A cavity 618 extends through the core 604 between the upper plane 616 and the lower plane 614. In this example, the thickness H1 of the core 604 is considerably greater than the height H2 of the electronic component 602. According to various aspects of this disclosure, the core 604 may be a thin core having a thickness H1 of 760 micrometers (μm) or less. Alternatively, the core may be a thick core having a thickness H1 greater than 760 μm (e.g., 820 μm or more, 1240 μm or more, etc.).

[0046]

[0057] According to various embodiments of this disclosure, the electronic component 602 is mounted within a cavity 618 in a cured resin layer 620. In the example shown in Figure 6B, the cured resin layer 620 fills the cavity 618 region between the upper plane 610 of the electronic component 602 and the bottom dielectric layer 622 of the upper metallization structure 624 disposed on the upper plane 616 of the core 604. In one embodiment, the cured resin layer 620 also at least partially fills the cavity 618 region between the inner sidewall of the core 604 and the outer sidewall of the electronic component 602.

[0047]

[0058] As described above, the thickness H1 of the core 604 (and therefore the depth of the cavity 618) is considerably greater than the height H2 of the electronic component 602. Therefore, a considerable portion of the cavity 618 remains unfilled by the cured resin layer 620. For very thick core options (e.g., core thickness >= 820 μm), even with the resin layer 620 present, it may be difficult to adequately fill the remaining portion of the cavity 618 with filler material 628 (e.g., dielectric material). In one embodiment, a second resin layer 626 may be used to reduce the volume of the cavity 618 before filling the remaining open portion of the cavity 618 with filler material 628. Thus, an additional cured resin layer 626 is formed on top of the cured resin layer 620. In this example, the additional cured resin layer 626 fills the region between the outer sidewall of the electronic component 602 and the inner sidewall of the core 604 that is not filled by the cured resin layer 620. In addition, the further cured resin layer 620 fills the portion of the cavity 618 below the lower plane 608 of the electronic component 602. In one embodiment, the cured resin layer 620 and the further cured resin layer 626 may be formed from the same resin material. Alternatively, the cured resin layer 620 and the further cured resin layer 626 may be formed from different resin materials. In one embodiment, any remaining portion of the cavity 618 not filled by either the cured resin layer 620 or the further cured resin layer 626 may be filled with a filler material 628 (e.g., a dielectric material).

[0048]

[0059] In the example shown in Figure 6B, the upper metallization structure 624 is configured to provide one or more conductive paths between one or more electronic component terminals 612 and one or more upper metal terminals 630 of the upper metallization structure 624. Here, the conductive paths are formed by vias (e.g., vias 632) extending between one or more dielectric layers (e.g., dielectric layer 634) connecting one or more patterned metal layers (e.g., patterned metal layer 636). In one embodiment, the upper metal terminals 630 may be configured for connection to a surface mount electronic package (not shown in Figure 6B). In addition, or in alternative examples, the upper metal terminals 630 may be configured to connect the substrate 600 to other electronic components (e.g., active components, passive components, integrated circuits, etc.).

[0049]

[0060] Core vias (e.g., via 638) connect one or more patterned metal layers (e.g., patterned metal layer 640) of the upper metallization structure 624 to one or more patterned layers (e.g., patterned metal layer 642) of the lower metallization structure 644 in order to electrically connect the upper metallization structure 624 to the lower metallization structure 644. The lower metallization structure 644 provides one or more conductive paths between the patterned metal layer 642 and one or more metal terminals 646 of the lower metallization structure 644. The metal terminals 646 may be configured to connect the substrate 600 to other electronic components (e.g., active components, passive components, integrated circuits, etc.), including surface mount electronic packages (not shown in Figure 6B).

[0050]

[0061] The cured resin layer 620 and the further cured resin layer 626 maintain the electronic component 602 fixed within the cavity 618 and provide a substantially void-free solid material (e.g., void-free or having fewer and / or smaller voids than those typically found in conventional dielectric fillings used to embed electronic components under similar geometric filling constraints), thereby resulting in a robust mounting of the electronic component 602 within the cavity 618. Thus, the electronic component 602 is fixed within the cavity 618 in a manner that minimizes the opportunity for the electronic component 602 to detach from the core 604.

[0051]

[0062] In one embodiment, the cured resin layer 620 may be initially deposited as a liquid resin in the cavity 618. The electronic component 602 may be at least partially embedded in the liquid resin before the liquid resin is cured to form the cured resin layer 620. In this way, the electronic component 602 may be held in place in the cavity 618 as the remaining portion of the cavity 618 that is not initially filled with the cured resin layer 620 is filled to form a further cured resin layer 626 and filler material 628. In the example shown in Figure 6B, the filler material 628 may be a dielectric material. In one embodiment, the dielectric material used as the filler material 628 may be the same dielectric material used to form one or more dielectric layers (e.g., dielectric layer 650) of the lower metallization structure 644.

[0052]

[0063] Figures 7A to 7E illustrate exemplary operations that may be performed during the manufacturing of an exemplary substrate according to embodiments of the present disclosure. Figure 7A shows a first intermediate state 700 of a substrate during an exemplary manufacturing process according to embodiments of the present disclosure. In this example, the first intermediate state 700 of the substrate includes a core 702 having a first plane 704 and a second plane 706. In one embodiment, the core 702 undergoes a drilling operation to form a cavity 708 extending between the first plane 704 and the second plane 706 of the core 702. A layer of polyimide (PI) tape 710 is fixed onto the second plane 706 of the core 702, covering the opening of the cavity 708.

[0053]

[0064] Figure 7B shows a second intermediate state 712 of a substrate during an exemplary manufacturing process according to an aspect of the present disclosure. In this example, via holes are drilled through the core 702. The via holes undergo metallization and tenting operations to form core vias (e.g., core vias 714). Here, the core vias (e.g., core vias 714) connect patterned metallization layers (e.g., patterned metallization layers 716, 718) in the first plane 704 and the second plane 706 of the core 702. A quantity of liquid resin 720 is placed on the plane of the PI tape 710 at the central location within each cavity 708.

[0054]

[0065] Figure 7C shows a third intermediate state 722 of a substrate during an exemplary manufacturing process according to an aspect of the present disclosure, where each cavity 708 has an electronic component 724 inserted. In this example, each electronic component 724 has a height H2 that is considerably smaller than the thickness H1 of the core 702. According to various aspects of the present disclosure, the electronic component 724 may be one or more of active electronic components, passive electronic components (e.g., deep trench capacitors (DTCs)), dies, etc.

[0055]

[0066] As shown in the figure, each electronic component 724 is inserted into the cavity 708 such that the plane 726 of the electronic component 724 and its corresponding electronic component terminals 728 are at least partially embedded in the liquid resin 720 of the cavity 708. In this example, the electronic component 724 pushes the liquid resin 720 so that it fills the area between the PI tape 710 and the plane 726 of the electronic component 724. In addition, depending on the amount of liquid resin 720 dispensed into the cavity 708, the electronic component 724 may push the liquid resin 720 to the extent that it surrounds a portion of the side wall of the cavity 708 (for example, filling the area between the outer side wall 732 of the electronic component 724 and the inner side wall 734 of the cavity 708). Once each electronic component 724 is positioned within its respective cavity 708, the liquid resin 720 is cured (for example, by heat curing on a hot plate). The liquid resin 720 then forms a cured resin layer 720 within each cavity 708, which holds the electronic components 724 in place during subsequent substrate manufacturing operations (for example, filling the portions of the cavity 708 that are not yet filled with a cured resin layer (still identified using reference numeral 720)).

[0056]

[0067] Figure 7D shows a fourth intermediate state 735 of the substrate during an exemplary manufacturing process according to an aspect of the present disclosure. Here, a further amount of liquid resin is dispensed into each cavity 708. The further amount of liquid resin is cured to form a further cured resin layer 736. In this example, the further cured resin layer 736 fills the portion of the cavity 708 that is not filled with the cured resin layer 720, including the portion of the cavity 708 that lies above the upper plane 737 of the electronic component 724.

[0057]

[0068] Figure 7E shows the formation of a finished substrate 738 according to an embodiment of the present disclosure, where the PI tape 710 layer is removed. A first metallization structure 740 is formed on a first plane 704 of the core 702, and a second metallization structure 742 is formed on a second plane 706 of the core 702. In this example, portions of the cavity 708 not filled with a cured resin layer 720 or a further cured resin layer 736 are filled with dielectric material 744. In one embodiment, the dielectric material 744 may be the same dielectric material used to form one or more dielectric layers (e.g., dielectric layer 746) of the first metallization structure 740.

[0058]

[0069] According to certain aspects of this disclosure, the formation of metallization structures 740 and 742 may include an initial dielectric stacking operation on each of the planes 704 and 706 of the core 702. Following the initial dielectric stacking operation, one or more layer build-up operations may be performed. In one embodiment, each layer build-up operation may be carried out using a semi-additive process (SAP). According to such SAP, each dielectric layer is deposited and then laser-drilled to form via holes, which are subjected to an electroless plating process to deposit metal onto the walls of the via holes. If the via structures remain hollow after the electroless plating process, they may be filled with filler ink. During the build-up operation, patterned metallization layers may be formed on the dielectric layers using pattern plating and seed etching processes. The formation of metallization structures 740 and 742 may also employ surface roughening (SR) processing, surface treatment, and solder-on-pad (SOP) operations.

[0059]

[0070] Figure 8 is a flowchart illustrating 800 exemplary methods for manufacturing a substrate according to aspects of the present disclosure. In operation 802, a cavity is formed in a core, the cavity extending between a first plane of the core and a second plane of the core. In operation 804, an electronic component is mounted at least partially in the cavity, the electronic component including a first plane having one or more electronic component terminals, the first plane being at least partially embedded in a first cured resin layer at a first end of the cavity. In operation 806, a first metallization structure is formed on the first plane of the core, the first metallization structure being configured to provide one or more conductive paths from one or more electronic component terminals to one or more metal terminals of the first metallization structure.

[0060]

[0071] In some embodiments, the mounting of an electronic component includes arranging a polyimide (PI) tape to cover an opening at a first end of the cavity, dispensing a liquid resin into the cavity onto the PI tape, inserting the electronic component into the cavity such that a first plane of the electronic component is at least partially embedded in the liquid resin, and curing the liquid resin to form a first cured resin layer.

[0061]

[0072] In some embodiments, the method includes filling one or more areas of a cavity not filled by the first cured resin layer with a filler, the filler comprising a dielectric filler having the same dielectric material as at least one dielectric layer of the first metallization structure, a further amount of liquid resin to be cured to form a second cured resin layer adjacent to the first cured resin layer, a further amount of liquid resin to be cured to form a second cured resin layer adjacent to the first cured resin layer, or a combination thereof.

[0062]

[0073] In some embodiments, the electronic component includes a deep trench capacitor.

[0063]

[0074] The technical advantage of Method 800 is that it can be used to form a substrate having embedded electronic components (e.g., deep trench capacitors) in which the embedded electronic components are rigidly mounted within the cavity of the substrate. The rigidity of the mounting is less dependent on the size or core thickness of the electronic components than conventional electronic component embedding processes using cavity filling.

[0064]

[0075] Figure 9 shows a side view of a package 900 according to an aspect of the present disclosure, including a surface mount substrate 902, an integrated device 903, and an integrated passive device 905 (e.g., a substrate having embedded electronic components in a core). The package 900 may be coupled to a printed circuit board (PCB) 906 via a plurality of solder interconnects 910. The PCB 906 may include at least one board dielectric layer 960 and a plurality of board interconnects 962.

[0065]

[0076] The surface mount substrate 902 includes at least one dielectric layer 920 (e.g., a substrate dielectric layer), a plurality of interconnection parts 922 (e.g., substrate interconnection parts), a solder resist layer 940, and a solder resist layer 942. The integrated device 903 may be coupled to the surface mount substrate 902 via a plurality of solder interconnection parts 930. The integrated device 903 may be coupled to the surface mount substrate 902 via a plurality of pillar interconnection parts 932 and a plurality of solder interconnection parts 930. The integrated passive device 905 may be coupled to the surface mount substrate 902 via a plurality of solder interconnection parts 950. The integrated passive device 905 may be coupled to the surface mount substrate 902 via a plurality of pillar interconnection parts 952 and a plurality of solder interconnection parts 950.

[0066]

[0077] The package (e.g., 900) may be implemented within a radio frequency (RF) package. The RF package may be a radio frequency front end (RFFE) package. The package (e.g., 900) may be configured to provide Wireless Fidelity (WiFi) communications and / or cellular communications (e.g., 2G, 3G, 6G, 5G). The package (e.g., 900) may be configured to support Global System for Mobile (GSM) communications, Universal Mobile Telecommunications System (UMTS), and / or Long-Term Evolution (LTE). The package (e.g., 900) may be configured to transmit and receive signals with different frequencies and / or different communication protocols.

[0067]

[0078] Figure 10 shows an exemplary method 1000 for providing or manufacturing a package including an integrated device comprising a package substrate (e.g., a substrate having embedded electronic components in a core) according to an aspect of the present disclosure. In some packaging configurations, the method 1000 of Figure 10 can be used to provide or manufacture the package 900 of Figure 9 described in the present disclosure. However, the method 1000 can also be used to provide or manufacture any of the packages described in the present disclosure.

[0068]

[0079] It should be noted that the method in Figure 10 may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a package including an integrated device and / or an integrated passive device including a magnetic layer. In some implementations, the order of the processes may be changed or modified.

[0069]

[0080] The method provides a substrate (e.g., 902) (in 1005). The substrate 902 may be provided by a supplier or manufactured by the supplier. The substrate 902 includes at least one dielectric layer 920 and a plurality of interconnection portions 922. The substrate 902 may include an embedded trace substrate (ETS). In some mounting configurations, at least one dielectric layer 920 may include a prepreg layer.

[0070]

[0081] This method (in 1010) bonds at least one integrated device (e.g., 903) to a first surface of a substrate (e.g., 902). For example, the integrated device 903 may be bonded to the substrate 902 via a plurality of pillar interconnects 932 and a plurality of solder interconnects 930. The plurality of pillar interconnects 932 can be optional. The plurality of solder interconnects 930 are bonded to a plurality of interconnects 922. A solder reflow process may be used to bond the integrated device 903 to the plurality of interconnects via the plurality of solder interconnects 930.

[0071]

[0082] The method also involves bonding at least one integrated passive device (e.g., 905) to a first surface of a substrate (e.g., 902) (in 1010). For example, the integrated passive device 905 may be bonded to the substrate 902 via a plurality of pillar interconnects 952 and a plurality of solder interconnects 950. The plurality of pillar interconnects 952 can be optional. The plurality of solder interconnects 950 are bonded to a plurality of interconnects 922. A solder reflow process may be used to bond the integrated passive device 905 to the plurality of interconnects via the plurality of solder interconnects 950.

[0072]

[0083] This method involves bonding a plurality of solder interconnects (e.g., 910) (in 1015) to a second surface of a substrate (e.g., 902). A solder reflow process may be used to bond the plurality of solder interconnects 910 to the substrate.

[0073]

[0084] Figure 11 shows various electronic devices that can be integrated with any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, electronic components, interposer packages, package-on-package (PoP), system-in-package (SiP), or system-on-chip (SoC). For example, a mobile phone device 1102, a laptop computer device 1104, a stationary terminal device 1106, a wearable device 1108, or a motor vehicle 1110 may include a device 1100 as described herein. Device 1100 can be, for example, any of the devices and / or integrated circuit (IC) packages described herein. Devices 1102, 1104, 1106, and 1108, and vehicle 1110 shown in Figure 11 are merely examples. Device 1100 may also feature a group of devices (e.g., electronic devices) including, but not limited to, mobile devices, handheld personal communication systems (PCS) units, portable data units such as personal information terminals, global positioning system (GPS) devices, navigation devices, set-top boxes, music players, video players, entertainment units, stationary data units such as meter reading devices, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in automobiles (e.g., autonomous vehicles), or any other devices that store or take in data or computer instructions, or any combination thereof.

[0074]

[0085] Implementation examples will be described in the following numbered embodiments.

[0075]

[0086] Embodiment 1. An electronic device comprising a substrate, the substrate comprising: a core having an upper plane and a lower plane, the core including a cavity extending between the upper plane and the lower plane of the core; an electronic component at least partially disposed within the cavity, the electronic component having an upper plane with one or more electronic component terminals; a first cured resin layer, the first cured resin layer in which the upper plane of the electronic component is at least partially embedded in the first cured resin layer in at least the upper portion of the cavity; and an upper metallization structure disposed on the upper plane of the core, the upper metallization structure configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

[0076]

[0087] Embodiment 2. The electronic device according to Embodiment 1, wherein the first cured resin layer fills the region between the upper plane of the electronic component and the lower dielectric layer of the upper metallization structure.

[0077]

[0088] Embodiment 3. An electronic device according to Embodiment 1 or 2, wherein the core includes a plurality of inner side walls, the electronic component includes a plurality of outer side walls facing the plurality of inner side walls of the core, and the first cured resin layer fills the region between the plurality of outer side walls of the electronic component and the plurality of inner side walls of the core.

[0078]

[0089] Embodiment 4. The electronic device according to Embodiment 3, further comprising a dielectric filler disposed in at least a portion of the cavity below the first cured resin layer.

[0079]

[0090] Embodiment 5. The electronic device according to Embodiment 4, wherein the electronic component has a height greater than or equal to the depth of the core.

[0080]

[0091] Embodiment 6. The electronic device according to Embodiment 5, wherein the core has a thickness of 760 micrometers or less.

[0081]

[0092] Embodiment 7. An electronic device according to any one of Embodiments 4 to 6, further comprising a lower metallization structure disposed below the lower plane of a core, wherein the lower metallization structure is configured to provide one or more conductive paths from a patterned metallization layer disposed above the lower plane of the core to one or more lower metal terminals of the lower metallization structure.

[0082]

[0093] Embodiment 8. The electronic device according to Embodiment 7, wherein the dielectric filler comprises the same dielectric material as at least one dielectric layer of the lower metallization structure.

[0083]

[0094] Embodiment 9. An electronic device according to any one of Embodiments 1 to 8, further comprising a second cured resin layer that fills at least a portion of the cavity below the first cured resin layer and below the lower plane of the electronic component.

[0084]

[0095] Embodiment 10. The electronic device according to Embodiment 9, further comprising a lower metallization structure disposed below the lower plane of the core and below the second cured resin layer, wherein the second cured resin layer fills the cavity between the first cured resin layer and the upper surface of the lower metallization structure.

[0085]

[0096] Embodiment 11. The electronic device according to Embodiment 9 or 10, wherein the first cured resin layer and the second cured resin layer are formed from the same resin material.

[0086]

[0097] Embodiment 12. An electronic device according to any one of Embodiments 9 to 11, wherein the electronic component has a height less than the depth of the core.

[0087]

[0098] Embodiment 13. The electronic device according to Embodiment 12, wherein the core has a thickness greater than 760 micrometers.

[0088]

[0099] Embodiment 14. An electronic device according to any one of embodiments 1 to 13, further comprising one or more metal vias extending between the upper plane of the core and the lower plane of the core.

[0089]

[0100] Embodiment 15. An electronic device according to any one of Embodiments 1 to 14, further comprising an electronic circuit package mounted on one or more upper metal terminals of an upper metallization structure.

[0090]

[0101] Embodiment 16. An electronic device according to any one of Embodiments 1 to 15, wherein the electronic component includes a deep trench capacitor.

[0091]

[0102] Embodiment 17. An electronic device according to any one of Embodiments 1 to 16, wherein the electronic device includes at least one of the following: a music player, video player, entertainment unit, navigation device, communication device, mobile device, mobile phone, smartphone, personal digital assistant, stationary terminal, tablet computer, computer, wearable device, laptop computer, server, Internet of Things (IoT) device, or device in a motor vehicle.

[0092]

[0103] Embodiment 18. A substrate comprising: a core having an upper plane and a lower plane, the core including a cavity extending between the upper plane and the lower plane of the core; an electronic component at least partially disposed within the cavity, the electronic component having an upper plane with one or more electronic component terminals; a first cured resin layer, the first cured resin layer in which the upper plane of the electronic component is at least partially embedded within the first cured resin layer in at least the upper portion of the cavity; and an upper metallization structure disposed on the upper plane of the core, the upper metallization structure configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure.

[0093]

[0104] Embodiment 19. The substrate according to Embodiment 18, wherein the first cured resin layer fills the region between the upper plane of the electronic component and the lower dielectric layer of the upper metallization structure.

[0094]

[0105] Embodiment 20. The substrate according to Embodiment 18 or 19, wherein the core includes a plurality of inner side walls, the electronic component includes a plurality of outer side walls facing the plurality of inner side walls of the cavity, and the first cured resin layer fills the region between the plurality of outer side walls of the electronic component and the plurality of inner side walls of the core.

[0095]

[0106] Embodiment 21. The substrate according to Embodiment 20, further comprising a dielectric filler that fills at least a portion of the cavity below the first cured resin layer.

[0096]

[0107] Embodiment 22. The substrate according to Embodiment 21, wherein the electronic components have a height greater than or equal to the depth of the core.

[0097]

[0108] Embodiment 23. A substrate according to any one of embodiments 18 to 22, further comprising a second cured resin layer that fills at least a portion of the cavity below the first cured resin layer and below the lower plane of the electronic component.

[0098]

[0109] Embodiment 24. The substrate according to Embodiment 23, wherein the first cured resin layer and the second cured resin layer are formed from the same resin material.

[0099]

[0110] Embodiment 25. The substrate according to Embodiment 23 or 24, wherein the electronic components have a height less than the depth of the core.

[0100]

[0111] Embodiment 26. A substrate according to any one of Embodiments 18 to 25, wherein the electronic component includes a deep trench capacitor.

[0101]

[0112] Embodiment 27. A method for manufacturing a substrate, comprising: forming a cavity in a core, the cavity extending between a first plane of the core and a second plane of the core; mounting an electronic component at least partially within the cavity, the electronic component including a first plane having one or more electronic component terminals, the first plane of the electronic component being at least partially embedded in a first cured resin layer at a first end of the cavity; and forming a first metallization structure on a first plane of a core, the first metallization structure configured to provide one or more conductive paths from one or more electronic component terminals to one or more metal terminals of the first metallization structure.

[0102]

[0113] Embodiment 28. The method according to Embodiment 27, wherein the mounting of an electronic component includes arranging a polyimide (PI) tape to cover an opening at a first end of the cavity, dispensing a liquid resin into the cavity onto the PI tape, inserting the electronic component into the cavity such that a first plane of the electronic component is at least partially embedded in the liquid resin, and curing the liquid resin to form a first cured resin layer.

[0103]

[0114] Embodiment 29. The method according to Embodiment 28, further comprising filling one or more areas of a cavity not filled by the first cured resin layer with a filler, the filler comprising a dielectric filler having the same dielectric material as at least one dielectric layer of the first metallization structure, a further amount of liquid resin to be cured to form a second cured resin layer adjacent to the first cured resin layer, or a combination thereof.

[0104]

[0115] Embodiment 30. The method according to Embodiment 28 or 29, wherein the electronic component includes a deep trench capacitor.

[0105]

[0116] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, electric current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0106]

[0117] It should be noted that the figures in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures may not be to exact scale. In some cases, not all components and / or parts may be shown for clarity. In some cases, the position, location, size, and / or shape of various parts and / or components in the figures may be illustrative. In some implementations, various components and / or parts in the figures may be optional.

[0107]

[0118] The term “exemplary” is used herein to mean “serving as an example, case, or illustration.” Any implementation or aspect described herein as “exemplary” should not necessarily be construed as being preferable or advantageous to other aspects of the Disclosure. Similarly, the term “aspect” does not require that all aspects of the Disclosure include the features, advantages, or modes of operation discussed. The term “coupled” is used herein to mean a direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A is in physical contact with object B, and object B is in contact with object C, then objects A and C can still be considered coupled to each other, even though they are not in direct physical contact with each other. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together so that an electric current (e.g., signal, power, ground) can propagate between them. Two electrically coupled objects may or may not propagate an electric current between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or any number above fourth) is arbitrary. Any of the components described may be the first, second, third, or fourth component. For example, a component referred to as the second component may also be the first, second, third, or fourth component. The term “encapsulating” means that an object can partially or completely encapsulate another object. The terms “top” and “bottom” are arbitrary. A component located at the top may be located on top of a component located at the bottom. A top component may be considered a bottom component, and vice versa.As described in this disclosure, a first component positioned "over" a second component may mean that the first component is positioned above or below the second component, depending on how the bottom or top is arbitrarily defined. In another example, the first component may be positioned on (e.g., above) a first surface of the second component, and the third component may be positioned on (e.g., below) a second surface of the second component, in which case the second surface is on the opposite side of the first surface. It should be further noted that, in the context of one component being positioned on another, the term “on” as used in this application may be used to mean a component that is on and / or inside another component (e.g., on the surface of the component or embedded within the component). Therefore, for example, a first component on a second component may mean (1) the first component is on the second component but does not directly contact the second component, (2) the first component is on the second component (e.g., on the surface of the second component), and / or (3) the first component is inside the second component (e.g., embedded within the second component). A first component located "in" a second component may be partially located within the second component or completely located within the second component. As used in this disclosure, the terms "about 'value X'" or "approximately value X" mean a range of 10 percent of "value X". For example, a value of "about 1" or "approximately 1" means a value in the range of 0.9 to 1.1.

[0108]

[0119] In some implementations, an interconnect is an element or component of a device or package that enables or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or underbump metallization (UBM) layers / interconnects. In some implementations, an interconnect may include conductive material that can be configured to provide electrical paths for signals (e.g., data signals), ground, and / or power. An interconnect may include two or more elements or components. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form an interconnect. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spray coating, and / or plating processes can be used to form interconnects.

[0109]

[0120] Furthermore, note that various disclosures contained herein may be described as processes shown as flowcharts, flow diagrams, structural diagrams, or block diagrams. While flowcharts can describe operations as sequential processes, many of these operations can also be performed in parallel or simultaneously. Moreover, the order of operations can be rearranged. A process terminates when its operations are completed.

[0110]

[0121] In the detailed description above, it will be seen that in the examples, different features are grouped together. This manner of disclosure should not be understood as an intention that exemplary embodiments have more features than are explicitly stated within each embodiment. Rather, the various embodiments of this disclosure may contain fewer features than all the features of the individual exemplary embodiments disclosed. Accordingly, the following embodiments should be considered incorporated into the description, and each embodiment may be valid on its own as a distinct example. Each dependent embodiment may refer within the embodiment to a specific combination with one of the other embodiments, but the embodiments (singular or plural) of that dependent embodiment are not limited to that specific combination. It will be understood that other exemplary embodiments may also include combinations of dependent embodiments (singular or plural) with the subject matter of any other dependent embodiment or independent embodiment, or any combination of features with other dependent embodiments and independent embodiments. The various embodiments disclosed herein explicitly include certain combinations (e.g., contradictory embodiments such as defining an element as both an electrical insulator and an electrical conductor) unless it is explicitly stated or easily inferred that such combinations are not intended. Furthermore, even if an aspect is not directly dependent on an independent aspect, it is intended that aspects of that aspect may be included in any other independent aspect.

[0111]

[0122] While the above disclosures represent exemplary aspects of the Disclosure, it should be noted that various changes and modifications can be made to this Specified without departing from the scope of the Disclosure as defined by the appended claims. The functions, steps, and / or actions of the method claims in the aspects of the Disclosure described herein do not need to be performed in any particular order. Furthermore, elements of the Disclosure may be described or claimed in the singular, but the plural is intended unless a limitation to the singular is explicitly stated.

Claims

1. It is an electronic device, It is a substrate, A core having an upper plane and a lower plane, wherein the core includes a cavity extending between the upper plane and the lower plane of the core, An electronic component at least partially disposed within the cavity, wherein the electronic component has an upper plane having one or more electronic component terminals, A first cured resin layer, wherein the upper plane of the electronic component is at least partially embedded in the first cured resin layer in at least the upper portion of the cavity, An upper metallization structure disposed on the upper plane of the core, wherein the upper metallization structure is configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure, An electronic device comprising a substrate.

2. The electronic device according to claim 1, wherein the first cured resin layer fills the region between the upper plane of the electronic component and the lower dielectric layer of the upper metallization structure.

3. The core includes a plurality of inner side walls, The electronic component includes a plurality of outer side walls facing the plurality of inner side walls of the core, The electronic device according to claim 1, wherein the first cured resin layer fills the region between the plurality of outer side walls of the electronic component and the plurality of inner side walls of the core.

4. The electronic device according to claim 3, further comprising a dielectric filler disposed in at least a portion of the cavity below the first cured resin layer.

5. The electronic device according to claim 4, wherein the electronic component has a height greater than or equal to the depth of the core.

6. The electronic device according to claim 5, wherein the core has a thickness of 760 micrometers or less.

7. The electronic device according to claim 4, further comprising a lower metallization structure disposed below the lower plane of the core, wherein the lower metallization structure is configured to provide one or more conductive paths from a patterned metallization layer disposed on the lower plane of the core to one or more lower metal terminals of the lower metallization structure.

8. The electronic device according to claim 7, wherein the dielectric filler comprises the same dielectric material as at least one dielectric layer of the lower metallization structure.

9. The electronic device according to claim 1, further comprising a second cured resin layer that fills at least a portion of the cavity below the first cured resin layer and below the lower plane of the electronic component.

10. The electronic device according to claim 9, further comprising a lower metallization structure disposed below the lower plane of the core and below the second cured resin layer, wherein the second cured resin layer fills the cavity between the first cured resin layer and the upper surface of the lower metallization structure.

11. The electronic device according to claim 9, wherein the first cured resin layer and the second cured resin layer are formed from the same resin material.

12. The electronic device according to claim 9, wherein the electronic component has a height smaller than the depth of the core.

13. The electronic device according to claim 12, wherein the core has a thickness greater than 760 micrometers.

14. The electronic device according to claim 1, further comprising one or more metal vias extending between the upper plane of the core and the lower plane of the core.

15. The electronic device according to claim 1, further comprising an electronic circuit package mounted on one or more upper metal terminals of the upper metallization structure.

16. The electronic device according to claim 1, wherein the electronic component includes a deep trench capacitor.

17. The aforementioned electronic device The electronic device according to claim 1, comprising at least one of the following: a music player, video player, entertainment unit, navigation device, communication device, mobile device, mobile phone, smartphone, personal digital assistant, stationary terminal, tablet computer, computer, wearable device, laptop computer, server, Internet of Things (IoT) device, or device in an automobile vehicle.

18. It is a substrate, A core having an upper plane and a lower plane, wherein the core includes a cavity extending between the upper plane and the lower plane of the core, An electronic component at least partially disposed within the cavity, wherein the electronic component has an upper plane having one or more electronic component terminals, A first cured resin layer, wherein the upper plane of the electronic component is at least partially embedded in the first cured resin layer in at least the upper portion of the cavity, An upper metallization structure disposed on the upper plane of the core, wherein the upper metallization structure is configured to provide one or more conductive paths from one or more electronic component terminals to one or more upper metal terminals of the upper metallization structure, A substrate comprising the above.

19. The substrate according to claim 18, wherein the first cured resin layer fills the region between the upper plane of the electronic component and the lower dielectric layer of the upper metallization structure.

20. The core includes a plurality of inner side walls, The electronic component includes a plurality of outer side walls facing the plurality of inner side walls of the cavity, The substrate according to claim 18, wherein the first cured resin layer fills the region between the plurality of outer side walls of the electronic component and the plurality of inner side walls of the core.

21. The substrate according to claim 20, further comprising a dielectric filler that fills at least a portion of the cavity below the first cured resin layer.

22. The substrate according to claim 21, wherein the electronic component has a height greater than or equal to the depth of the core.

23. The substrate according to claim 18, further comprising a second cured resin layer that fills at least a portion of the cavity below the first cured resin layer and below the lower plane of the electronic component.

24. The substrate according to claim 23, wherein the first cured resin layer and the second cured resin layer are formed from the same resin material.

25. The substrate according to claim 23, wherein the electronic component has a height smaller than the depth of the core.

26. The substrate according to claim 18, wherein the electronic component includes a deep trench capacitor.

27. A method for manufacturing a circuit board, A cavity within the core, wherein the cavity extends between a first plane of the core and a second plane of the core, forming a cavity. An electronic component, wherein the electronic component includes a first plane having one or more electronic component terminals, and the first plane of the electronic component is at least partially embedded in a first cured resin layer at a first end of the cavity, and the electronic component is at least partially mounted in the cavity. A first metallization structure is formed on the first plane of the core, wherein the first metallization structure is configured to provide one or more conductive paths from one or more electronic component terminals to one or more metal terminals of the first metallization structure. Methods that include...

28. The mounting of the aforementioned electronic component is A polyimide (PI) tape is placed to cover the opening at the first end of the cavity. Dispense the liquid resin into the cavity onto the PI tape. Inserting the electronic component into the cavity such that the first plane of the electronic component is at least partially embedded in the liquid resin, and The liquid resin is cured in order to form the first cured resin layer. The method according to claim 27, including the method described in claim 27.

29. One or more regions of the cavity not filled by the first cured resin layer are filled with a filling material, wherein the filling material is A dielectric filler having the same dielectric material as at least one dielectric layer of the first metallization structure, A further amount of liquid resin to be cured in order to form a second cured resin layer adjacent to the first cured resin layer, or These combinations, The method according to claim 28, further comprising filling with a filler material.

30. The method according to claim 28, wherein the electronic component includes a deep trench capacitor.

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