Plating-compatible single-layer capacitors

Abstract

A single-layer capacitor and a circuit board are provided. The circuit board may include a circuit board substrate having a mounting surface and a single-layer capacitor at least partially embedded within the circuit board substrate. The single-layer capacitor may include a first passivation layer formed on at least a portion of a first surface of the substrate, a first conductive layer formed on at least a portion of the first passivation layer, and a second conductive layer formed on at least a portion of a second surface of the substrate. A method for forming a single-layer capacitor may include the steps of depositing a passivation layer on at least a portion of a first surface of the substrate, depositing a first conductive layer on at least a portion of the passivation layer, and depositing a second conductive layer on at least a portion of a second surface of the substrate opposite to the first surface.

Description

[Technical Field]

[0001] Related applications This application claims priority to U.S. Provisional Patent Application No. 63 / 501,161, filed on 10 May 2023, which is incorporated herein by reference. [Background technology]

[0002] Single-layer capacitors (SLCs) offer various advantages, including temperature stability, generally high breakdown voltage, and low leakage current. However, SLCs are generally relatively thin, and this thinness can hinder their usefulness in embedded applications, as embedded capacitors may require a thicker metal layer to allow the formation of one or more vias for connection without impacting or damaging the capacitor's substrate layer. Therefore, improved SLCs for embedded applications are needed. [Overview of the project]

[0003] According to one embodiment of the present disclosure, a circuit board may include a circuit board substrate having a mounting surface and a single-layer capacitor at least partially embedded within the circuit board substrate. The single-layer capacitor may include a substrate having a first surface opposite to a second surface, a first passivation layer formed on at least a portion of the first surface of the substrate, a first conductive layer formed on at least a portion of the first passivation layer, and a second conductive layer formed on at least a portion of the second surface of the substrate.

[0004] According to another embodiment of the present disclosure, a single-layer capacitor may include a substrate having a first surface and a second surface opposite to the first surface; a first passivation layer formed on at least a portion of the first surface of the substrate; a first conductive layer formed on at least a portion of the first passivation layer; and a second conductive layer formed on at least a portion of the second surface of the substrate.

[0005] According to yet another embodiment of the present disclosure, a method for forming a single-layer capacitor can include depositing a first passivation layer on at least a portion of a first surface of a substrate, depositing a first conductive layer on at least a portion of the first passivation layer, and depositing a second conductive layer on at least a portion of a second surface of the substrate, wherein the second surface is on the opposite side of the first surface.

[0006] A complete and implementable disclosure of the invention, including the best mode thereof, directed to those of ordinary skill in the art, will be described in more detail in the remaining part of this specification, with reference to the accompanying drawings.

Brief Description of the Drawings

[0007] [Figure 1] A side view of a capacitor according to an aspect of the present disclosure. [Figure 2A] A circuit board including a fully embedded capacitor according to an aspect of the present disclosure is shown. [Figure 2B] Another circuit board including a fully embedded capacitor according to an aspect of the present disclosure is shown. [Figure 2C] A circuit board including a partially embedded capacitor according to an aspect of the present disclosure is shown. [Figure 3A] A perspective view of a capacitor according to an aspect of the present disclosure. [Figure 3B] A side view of the capacitor of FIG. 3A. [Figure 4] A circuit board including a fully embedded capacitor according to an aspect of the present disclosure is shown. [Figure 5] A flowchart of a method for forming a capacitor according to an aspect of the present disclosure. [Figure 6] A flowchart of another method for forming a capacitor according to an aspect of the present disclosure.

Modes for Carrying Out the Invention

[0008] The repeated use of reference numerals in this specification and drawings is intended to represent the same or similar features or elements of the present invention.

[0009] Those skilled in the art will understand that this description is merely an illustrative embodiment and is not intended to limit the broader embodiments of the present invention that are embodied in the illustrative structures.

[0010] Generally speaking, the present invention relates to a single-layer capacitor having a passivation layer. For example, a single-layer capacitor (SLC or “capacitor” as used herein) may include a substrate, a passivation layer formed on at least a portion of a first surface of the substrate, a first conductive layer (or first electrode) formed on at least a portion of the passivation layer, and a second conductive layer (or second electrode) formed on at least a portion of a second surface of the substrate opposite to the first surface of the substrate. The second passivation layer may be formed on a second surface of the substrate, and the second conductive layer may be formed on the second passivation layer such that the second passivation layer is positioned between the second conductive layer and the substrate.

[0011] A passivation layer between the substrate and the conductive layer can enable the plating of the conductive layer. More specifically, many embedded capacitor applications require a relatively thick conductive layer to allow via drilling for connections without impacting or damaging the substrate. A dielectric protective layer (i.e., a passivation layer) allows the wafer to be plated to obtain the necessary thickness of conductive layer to protect the substrate. A passivation layer may be formed on each of a pair of opposing surfaces of the substrate or wafer to enable the plating of a conductive layer on each of the pair of opposing surfaces.

[0012] Additionally or alternatively, plated conductive layers or electrodes can also enable single-layer capacitors to be solderable components. A typical single-layer capacitor without plated conductive layers or electrodes is only wire-bondable or epoxy-connectable. Single-layer capacitors with plated conductive layers or electrodes may be soldered to, for example, a circuit board, which can expand the possible applications of single-layer capacitors.

[0013] In some embodiments, the substrate may be formed from a material having a dielectric constant (K) less than about 30, less than about 25 in some embodiments, less than about 20 in some embodiments, and less than about 15 in some embodiments, when determined according to ASTM D2520-13 at an operating temperature of 25°C and a frequency of 500 MHz. However, in other embodiments, a material having a dielectric constant greater than 30 may be used to achieve higher frequencies and / or smaller components. For example, in such embodiments, the dielectric constant may be in the range of about 30 to about 120 or greater, when determined according to ASTM D2520-13 at an operating temperature of 25°C and a frequency of 500 MHz, and in some embodiments, it may be about 50 to about 100, and in some embodiments, about 70 to about 90.

[0014] In further embodiments, the substrate may be formed from a material having a relatively high dielectric constant (K), such as about 10 to 40,000, about 50 to 30,000 in some embodiments, and about 100 to 20,000 in some embodiments.

[0015] The substrate may generally have a low thermal conductivity, such as less than about 10 W / (m·K), less than about 5 W / (m·K) in some embodiments, less than about 3 W / (m·K) in some embodiments, less than about 2 W / (m·K) in some embodiments, less than about 1 W / (m·K) in some embodiments, and greater than about 0.1 W / (m·K) in some embodiments. However, in other embodiments, the substrate may have a thermal conductivity greater than 10 W / (m·K).

[0016] The substrate may comprise one or more suitable ceramic materials. Suitable materials are generally electrically insulating and thermally conductive. For example, in some embodiments, the substrate may comprise sapphire, ruby, alumina (Al2O3), aluminum nitride (AlN), beryllium oxide (BeO), aluminum oxide (Al2O3), boron nitride (BN), silicon (Si), silicon carbide (SiC), silica (SiO2), silicon nitride (Si3N4), gallium arsenide (GaAs), gallium nitride (GaN), zirconium dioxide (ZrO2), mixtures thereof, oxides and / or nitrides of such materials, or any other suitable ceramic material. Further examples of ceramic materials include barium titanate (BaTiO3), calcium titanate (CaTiO3), zinc oxide (ZnO), ceramics containing low-fired glass, or other glass-bonding materials. Dielectric materials such as diamond and cubic boron arsenide may also be used.

[0017] Specific examples of high dielectric constant materials include, for example, NPO(COG) (up to about 100), X7R (from about 3,000 to about 7,000), X7S, Z5U, and / or Y5V materials. It should be understood that the aforementioned materials are described by their definitions accepted in the industry, some of which are standard classifications established by the Electronic Industries Association (EIA) and therefore should be recognized by those skilled in the art. For example, such materials may include ceramics. Such materials may include barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconate, barium strontium zirconate, barium calcium zirconate, etc.), lead titanate and related solid solutions (e.g., lead zirconate, lead zirconate lanthanum), and perovskites such as bismuth sodium titanate. In a particular embodiment, for example, formula Ba x Sr 1-xBarium strontium titanate of TiO3 ( "BSTO" ) may be used, where x is 0 to 1, in some embodiments from about 0.15 to about 0.65, and in some embodiments from about 0.25 to about 0.6. Other suitable perovskites are, for example, Ba x Ca 1-x TiO3, where x is from about 0.2 to about 0.8, in some embodiments from about 0.4 to about 0.6, Pb x Zr 1-x TiO3 ( "PZT" ), where x ranges from about 0.05 to about 0.4, lead lanthanum zirconate titanate ( "PLZT" ), lead titanate (PbTiO3), barium calcium zirconium titanate (BaCaZrTiO3), sodium nitrate (NaNO3), KNbO3, LiNbO3, LiTaO3, PbNb2O6, PbTa2O6, KSr (NbO3) and NaBa2 (NbO3) 5KHb2PO4 may be included. Further additional complex perovskites may include A[B1 1 / 3 B2 2 / 3 O3 materials, where A is Ba x Sr 1-x (x can be a value from 0 to 1), B1 is Mg y Zn 1-y (y can be a value from 0 to 1), B2 is Ta z Nb 1-z (z can be a value from 0 to 1). In a particular embodiment, the dielectric material may include a titanate.

[0018] As used herein, "formed on top" may refer to a layer in direct contact with another layer. However, an intermediate layer may be formed between them. Further, when used with respect to the bottom surface, "formed on top" may be used with respect to the outer surface of the component. Thus, a layer "formed on top" of the bottom surface may be closer to the outside of the component than the layer on which it is formed.

[0019] The passivation layer of the capacitor can be formed on at least a portion of the surface of the substrate. The passivation layer can cover and protect the substrate from deposition processes (e.g., electroplating) used to form a conductive layer on the substrate surface. The passivation layer can be formed from a variety of suitable materials, including polymer materials. For example, in some embodiments, the passivation layer may be or contain polyimide. In some embodiments, the (one or more) passivation layers may include at least one of silicon oxynitride, Al2O3, SiO2, Si3N4, benzocyclobutene, or glass. The substrate and / or passivation layer can be formed from a variety of inorganic materials, such as glass, ceramic, or glass-ceramic mixtures. As described above, the substrate may include silicon oxynitride, silicon oxide, silicon, alumina, sapphire, and / or other suitable materials.

[0020] In some embodiments, the passivation layer may be formed by depositing a paste (e.g., glass paste, glass ceramic paste, etc.) followed by a firing step. However, any suitable process may be used to form the passivation layer.

[0021] The first conductive layer of the capacitor can be formed on at least a portion of the passivation layer. The first conductive layer does not have to include direct contact with the substrate and / or direct electrical connection. In exemplary configurations, the conductive material on which the first conductive layer is formed may be electroplated on the passivation layer. Other methods for depositing the conductive material may also be used, as will be recognized by those skilled in the art.

[0022] The capacitor may also include an additional or second conductive layer. In some embodiments, the second conductive layer may be formed on the second surface of the substrate opposite the first surface of the substrate (on which the passivation layer and the first conductive layer are formed). Furthermore, in some embodiments, the second passivation layer may be formed on at least a portion of the second surface of the substrate, and the second conductive layer may be formed on the second passivation layer such that the second passivation layer is positioned between the second conductive layer and the substrate. As described above with respect to the passivation layer formed between the first conductive layer and the substrate, the second passivation layer may be formed by depositing a paste (e.g., glass paste, glass ceramic paste, etc.) followed by a firing step, but any suitable process may be used to form the second passivation layer. Furthermore, the second passivation layer may be formed from a variety of suitable materials, including polymer materials. For example, in some embodiments, the second passivation layer may be polyimide, or may contain polyimide, and / or may contain at least one of silicon oxynitride, Al2O3, SiO2, Si3N4, benzocyclobutene, glass, ceramic, or glass-ceramic mixture.

[0023] The conductive layer may be formed from any of several different metals, as is known in the art. The conductive layer or electrode layer may be made from a metal such as a conductive metal. Conductive materials may include noble metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and various combinations thereof. The conductive layer or electrode may also be made from low-resistance materials such as silver, copper, gold, aluminum, and palladium. In a particular embodiment, the conductive layer may include nickel or an alloy thereof.

[0024] One or more protective layers can be formed on the substrate and / or one or more passivation layers. For example, one or more protective layers can be formed on a first surface and / or a second surface of the substrate. As another example, one or more protective layers can be formed on a first passivation layer (formed on the first surface of the substrate) such that a first conductive layer is formed on one or more protective layers. In some embodiments, one or more protective layers may similarly be formed on a second passivation layer, such as between a second passivation layer and a second conductive layer. Examples of materials for the one or more protective layers include benzocyclobutene (BCB), polyimide, silicon oxynitride, alumina (Al2O3), silica (SiO2), silicon nitride (Si3N4), epoxy, glass, or other suitable materials.

[0025] Various thin-film techniques can be used to form the thin-film layers of a capacitor. For example, one or more of the first conductive layer, the second conductive layer, the first passivation layer, and the second passivation layer may be the thin-film layers of the capacitor. Examples of such techniques that may be used include chemical deposition (e.g., chemical vapor deposition), PECVD (plasma chemical vapor deposition), physical deposition (e.g., sputtering), or any other suitable deposition technique for forming thin-film elements. Further examples include any suitable patterning technique for forming thin-film elements (e.g., photolithography), etching, and any other suitable subtractive technique.

[0026] The thin film layer can have a thickness within a range. For example, the thin film layer may have a thickness ranging from about 0.001 micrometers (microns) to about 100 microns in some embodiments, from about 0.0375 microns to about 40 microns in some embodiments, from about 0.1 microns to about 30 microns in some embodiments, from about 0.2 microns to about 20 microns in some embodiments, and from about 0.4 microns to about 10 microns in some embodiments. For example, in some embodiments, the resistive layer may have a thickness of less than about 10 microns, less than about 8 microns in some embodiments, less than about 6 microns in some embodiments, and less than 4 microns in some embodiments.

[0027] The conductive layer can be plated on each passivation layer. For example, if the first passivation layer is formed on the first surface of the substrate, the first conductive layer can be plated on the first passivation layer. In embodiments that also include a second passivation layer formed on the second surface of the substrate, the second conductive layer can be plated on the second passivation layer.

[0028] The conductive layers may be formed such that each conductive layer is a thin film plating of a metal. Such thin film plating can be formed by depositing a conductive material, such as a conductive metal, onto a passivation layer. The plated conductive layers or electrodes may be formed by techniques known in the art, such as electroless plating, electroplating, or a combination thereof. When multiple layers are used to form an electrode, the electrode may include an electroplated layer and an electroless plating layer. For example, electroless plating may be used first to deposit an initial layer of material. The plating technique may then be switched to an electrochemical plating system, which can allow for a faster build-up of the material. When (one or more) plated conductive layers or (one or more) electrodes are formed by any of the plating methods, at least a portion of the capacitor is exposed to the plating solution. By exposure, in one embodiment, the capacitor may be immersed in the plating solution.

[0029] The plating solution used in the plating process may contain conductive materials such as conductive metals. For example, the plating solution may be a nickel sulfamate bath solution or other nickel solution, such that the plating layer and external terminals contain nickel. Alternatively, the plating solution may be a copper acid bath or other suitable copper solution, such that the plating layer and external terminals contain copper. Furthermore, it should be understood that the plating solution may contain other additives commonly known in the art. For example, the additives may include other organic additives and media that can assist the plating process. Furthermore, additives may be used to use the plating solution at a desired pH level. In one embodiment, resistance-reducing additives may be used in the solution to help achieve a complete plating coating and bond the plating material to the capacitor. The capacitor may be exposed, immersed, or immersed in the plating solution for a predetermined time. The exposure time is not necessarily limited and may be sufficient to deposit enough plating material to form a plating layer. In this regard, the time should be sufficient to allow the formation of a continuous layer on each surface of the substrate.

[0030] The difference between electroplating and electroless plating is that electroplating uses an electrical bias, such as by using an external power supply. Electroplating solutions typically operate in a high current density range, e.g., 10-15 amp / ft. 2 It may be exposed to (rated 9.4 volts). The connection may be formed by a negative connection to a capacitor requiring the formation of a plated terminal and a positive connection to a solid material in the same plating solution (e.g., Cu in a Cu plating solution). That is, the capacitor is biased to the opposite polarity to the plating solution. Using such a method, the conductive material of the plating solution is adsorbed onto a metal already placed on the substrate. For example, as mentioned above, an initial amount of metal may be deposited on the substrate using an electroless process, and the remaining amount of metal for the conductive layer may be deposited using electroplating.

[0031] Various pretreatment steps may be used before immersing or exposing the capacitor to the plating solution. Such steps may be performed for a variety of purposes, including catalyzing, accelerating, and / or improving the adhesion of the plating material to the initial deposited metal. Furthermore, an initial cleaning step may be used before the plating step or any other pretreatment step. This step may be used to remove any oxide buildup formed on the substrate and / or the initial deposited metal. Component cleaning may be affected by complete immersion in a pre-cleaning bath, such as one containing an acidic cleaning agent. In one embodiment, the exposure may last for a predetermined time, such as about 10 minutes. Alternatively, cleaning may be affected by a chemical polishing or harparizing step.

[0032] Furthermore, a step to activate the metal may be performed to facilitate the deposition of conductive materials. Activation can be achieved by palladium salt immersion, photopatterned palladium organometallic precursors (via mask or laser), screen printing or inkjet-deposited palladium compounds, or electrophoretic palladium deposition. It should be understood that palladium-based activation is disclosed here only as an example of an activation solution that often works well in activating exposed areas formed of nickel or its alloys. However, it should be understood that other activation solutions may be used and are therefore not necessarily limited. Also, an activation dopant may be introduced into the conductive material instead of, or in addition to, the aforementioned activation step. For example, if the conductive layer contains nickel and the activation dopant contains palladium, the palladium dopant may be introduced into the nickel ink or composition forming the (one or more) conductive layers. In doing so, the palladium activation step can be eliminated. It should be further understood that some of the above activation methods, such as organometallic precursors, are also useful for co-deposition of glass-forming agents to enhance adhesion to the capacitor body, mainly ceramic. When the activation step is performed as described above, traces of the activating material often remain on the exposed conductive areas before and after plating.

[0033] Furthermore, post-plating treatment steps may be used as desired or as needed. Such steps may be performed for a variety of purposes, including strengthening and / or improving the adhesion of the material. For example, a heating (or annealing) step may be used after the plating step. Such heating may be performed by firing, laser irradiation, UV irradiation, microwave irradiation, arc welding, etc.

[0034] Therefore, as described above, the conductive layer used in a capacitor may include at least one plating layer. In one embodiment, the conductive layer may include only one plating layer. However, it should be understood that the conductive layer may include multiple plating layers. For example, the conductive layer or electrode may include a first plating layer and a second plating layer. Furthermore, the conductive layer or electrode may include a third plating layer. Furthermore, the materials of these plating layers may be any of those mentioned above that are commonly known in the art. For example, one plating layer, such as the first plating layer, may contain copper or an alloy thereof. Another plating layer, such as the second plating layer, may contain nickel or an alloy thereof. Alternatively, another plating layer, such as the second plating layer, may contain copper or an alloy thereof. Another plating layer, such as the third plating layer, may contain a combination of tin, lead, gold, or an alloy. Alternatively, the initial plating layer may contain nickel, followed by a tin or gold plating layer. In another embodiment, an initial copper plating layer may be formed, followed by a nickel layer.

[0035] In one embodiment, the initial or first plating layer may be a conductive metal (e.g., copper). This region may then be covered with a second layer containing a resistive polymer material for sealing. This region may then be polished to selectively remove the resistive polymer material and then re-plated with a third layer containing a conductive metal material (e.g., copper). The aforementioned second layer above the initial plating layer may correspond to a solder barrier layer, e.g., a nickel solder barrier layer. In some embodiments, the aforementioned layer may be formed by electroplating an additional metal layer (e.g., nickel or copper) on top of an initial electroless or electroplated layer (e.g., plated copper). Other exemplary materials for laminating the aforementioned solder barrier layer include nickel-phosphorus, gold, and silver. The aforementioned third layer on the solder barrier layer may, in some embodiments, correspond to a conductive layer such as plated Ni, Ni / Cr, Ag, Pd, Sn, Pb / Sn, or other suitable plated solder. Furthermore, a layer of metal plating may be formed, followed by an electroplating step to provide a resistance alloy or a higher resistance metal alloy coating, such as an electroless Ni-P alloy, on top of such metal plating. However, it should be understood that any metal coating is possible, as will be understood by those skilled in the art from the full disclosure herein. Any of the aforementioned steps can be carried out as bulk steps, such as barrel plating, fluidized bed plating, and / or fluidized bed terminating steps, all of which are generally known in the art. Such bulk steps allow multiple components to be processed at once, providing an efficient and rapid electrode deposition process. This is particularly advantageous compared to conventional electrode deposition methods, such as printing of thick conductive or electrode layers, which require individual component processing.

[0036] In some embodiments, the conductive layer may be formed to be relatively thick. For example, such a conductive layer may be formed by attaching a thick strip of metal to a substrate. Such metal may be in a glass matrix and may include silver or copper. For example, such a strip may be printed and fired onto the capacitor, or deposited by immersing the capacitor in a liquid conductive material. Such attachment of a thick conductive layer may include any method commonly known in the art (e.g., by a printing wheel for transferring a metal-supported paste onto a substrate). In some embodiments, an additional layer may be plated on one or more thick conductive layers using any suitable plating method described herein.

[0037] The thick conductive layer may have an average thickness of at least about 5 μm or microns, for example, about 10 microns or more, about 20 microns or more, about 25 microns or more, about 35 microns or more, about 50 microns or more, or about 75 microns or more. The thick conductive layer may have an average thickness of about 500 microns or less, for example, about 300 microns or less, for example, about 200 microns or less, for example, about 150 microns or less, for example, about 100 microns or less, for example, about 80 microns or less. For example, the thick conductive layer may have an average thickness in the range of about 5 microns to about 150 microns, for example, in the range of about 10 microns to about 100 microns, for example, in the range of about 25 microns to about 75 microns. In one embodiment, the aforementioned thickness refers to the average thickness of the entire conductive portion or electrode of the capacitor attached or deposited on one surface of the capacitor, which may include, for example, the attachment of two or more layers of conductive material to achieve a first conductive layer or electrode on a first surface of the substrate and / or a second conductive layer or electrode on a second surface of the substrate. In another embodiment, the aforementioned thickness refers to the average thickness of a single layer of the conductive layer or electrode of the capacitor.

[0038] In some embodiments, the capacitor can be at least partially embedded in a circuit board, such as a printed circuit board (PCB). For example, the capacitor may be placed in an opening or cavity of the circuit board such that at least a portion of the capacitor is enclosed by the circuit board. A portion of the capacitor may protrude from or extend above the mounting surface of the circuit board, or at most the outermost surface of the capacitor may be coplanar with the mounting surface of the circuit board, with the rest of the capacitor located in an opening or cavity and enclosed by the circuit board. In at least some embodiments, the capacitor may be electrically connected to the circuit board, for example, via vias or other conductive paths extending from the capacitor to a conductive area of ​​the circuit board (e.g., a conductive layer, termination, or port) on the circuit board.

[0039] Figure 1 is a side view of a single-layer capacitor 100 according to an embodiment of the present disclosure. The single-layer capacitor 100 may also be referred to herein as SLC 100 or capacitor 100. As shown in Figure 1, the capacitor 100 may include a substrate 102 having a first surface 104 and a second surface 106 opposite the first surface 104 along the height or thickness direction Z. The substrate 102 may be formed from a dielectric material. In some embodiments, the dielectric material may have a relatively low dielectric constant (K), while in other embodiments, the dielectric material may have a relatively high dielectric constant.

[0040] The capacitor 100 may include a first conductive layer 108 formed on at least a portion of a first surface 104 of the substrate 102, and a second conductive layer 110 formed on at least a portion of a second surface 106 of the substrate 102. In some embodiments, the first conductive layer 108 is a thick conductive layer and has a first thickness t1 of at least about 5 microns. For example, the first conductive layer 108 may have a first thickness t1 of at least about 10 microns, a first thickness t1 of at least about 12 microns, a first thickness t1 of at least about 20 microns, a first thickness t1 of at least about 40 microns, a first thickness t1 of at least about 80 microns, a first thickness t1 of at least about 100 microns, a first thickness t1 of at least about 250 microns, or a first thickness t1 of at least about 500 microns. In some embodiments, the first thickness t1 may be in the range of about 5 microns to about 150 microns, about 10 microns to about 100 microns, or about 25 microns to about 75 microns. The first conductive layer 108 may also have other thicknesses.

[0041] Similarly, in at least some embodiments, the second conductive layer 110 is a thick conductive layer having a second thickness t2 of at least about 5 microns. For example, the second conductive layer 110 may have a second thickness t2 of at least about 10 microns, at least about 12 microns, at least about 20 microns, at least about 40 microns, at least about 80 microns, at least about 100 microns, at least about 250 microns, or at least about 500 microns. In some embodiments, the second thickness t2 may be in the range of about 5 to about 150 microns, about 10 to about 100 microns, or about 25 to about 75 microns. The second conductive layer 110 may also have other thicknesses.

[0042] Furthermore, in at least some embodiments, the substrate thickness t subThis can be at least about 50 microns. For example, substrate thickness t sub This may be at least about 75 microns, at least about 100 microns, at least about 150 microns, at least about 250 microns, at least about 500 microns, or at least about 1000 microns. In some embodiments, the Thickness t of the substrate relative to the first Thickness t1 sub The ratio can be at least 2, for example, at least 2, at least 2.5, at least 3, or at least 4. Similarly, in some embodiments, the thickness t of the substrate relative to the second thickness t2. sub The ratio can be at least 2, for example, at least 2, at least 2.5, at least 3, or at least 4.

[0043] Continuing to refer to Figure 1, the substrate has a substrate thickness t along the height or thickness direction Z. sub It can have a substrate thickness t. In some embodiments, the substrate thickness t sub The substrate thickness t can be greater than the thickness t1, t2 of at least one of the first conductive layer 108 or the second conductive layer 110. In other embodiments, the substrate thickness t sub The substrate thickness t can be greater than the sum of the thicknesses t1 and t2 of the first conductive layer 108 and the second conductive layer 110. In yet another embodiment, the substrate thickness t sub The thickness of at least one of the first conductive layer 108 or the second conductive layer 110 can be less than t1, t2.

[0044] It will be understood that the first conductive layer 108 and the second conductive layer 110 can be formed from any suitable conductive material as described elsewhere in this specification, and the substrate 102 can be formed from any suitable dielectric material as described elsewhere in this specification.

[0045] In some embodiments, the first conductive layer 108 and / or the second conductive layer 110 can extend across the entire respective surfaces 104, 106 on which each layer 108, 110 is formed. For example, the first conductive layer 108 can extend to each edge defining the first surface 104 of the substrate 102, and / or the second conductive layer 110 can extend to each edge defining the second surface 106 of the substrate 102. Alternatively, the first conductive layer 108 and / or the second conductive layer 110 can be offset from one or more edges of the respective surfaces 104, 106, as shown, for example, in Figure 1.

[0046] Referring now to Figures 2A to 2C, side views of a circuit board 250 having at least partially embedded single-layer capacitor 100 according to an embodiment of the present disclosure are shown. The circuit board 250 may include a circuit board substrate 252 having a mounting surface 254. In the embodiments shown in Figures 2A and 2B, the capacitor 100 is fully embedded in the circuit board substrate 252. More specifically, in the embodiment of Figure 2A, the capacitor 100 is fully embedded in the circuit board substrate 252 such that the substrate 102, the first conductive layer 108, and the second conductive layer 110 of the capacitor 100 are respectively positioned below the mounting surface 254 of the circuit board 250 along the height or thickness direction Z. In the embodiment of Figure 2B, the capacitor 100 is fully embedded in the circuit board substrate 252 such that the first conductive layer 108 of the capacitor 100 is coplanar with the mounting surface 254 of the circuit board 250. For example, the outermost surface of the first conductive layer 108 (i.e., the surface of the first conductive layer 108 opposite the first surface 104 of the substrate 102) can be coplanar with the mounting surface 254 of the circuit board 250, and since no part of the capacitor 100 extends above the circuit board 250, beyond the circuit board 250, or outside the circuit board, the capacitor 100 is still considered to be fully embedded in the circuit board. In other embodiments, the capacitor 100 can be partially embedded in the circuit board substrate 252 such that a portion of the capacitor 100 is located within the circuit board 250, and the remaining portion of the capacitor 100, such as the first conductive layer 108 and / or at least a portion of the substrate 102 of the capacitor 100, protrudes from the circuit board 250 or is outside the circuit board 250, for example, along the height or thickness direction Z. For example, in the embodiment shown in Figure 2C, the capacitor 100 is partially embedded in the circuit board substrate 252 such that the first conductive layer 108 extends above the mounting surface 254 of the circuit board 250.

[0047] As further shown in Figures 2A to 2C, the capacitor 100 can be electrically connected to the conductive layer 256 of the circuit board 250. For example, as shown in Figure 2A, the via 258 extends from the first conductive layer 108 of the capacitor 100 toward the mounting surface 254 of the circuit board 250 and can be connected to the conductive layer 256 formed on the mounting surface 254. Thus, the via 258 of the circuit board 250 can electrically connect the capacitor 100 to the conductive layer 256 of the circuit board 250.

[0048] Referring to Figures 2B and 2C, in another embodiment, the conductive path 260 can electrically connect the capacitor 100 to the conductive layer 256 of the circuit board 250. As shown in Figures 2B and 2C, the conductive path 260 extends from the first conductive layer 108 of the capacitor 100 to the conductive layer 256 of the circuit board 250. Thus, the conductive path 260 of the circuit board 250 can electrically connect the capacitor 100 to the conductive layer 256 of the circuit board 250.

[0049] Next, other embodiments of an embeddable single-layer capacitor will be described with reference to Figures 3A, 3B, and 4. Figures 3A and 3B show perspective and side views of the single-layer capacitor 300, respectively. Similar to the capacitor 100 described above, the capacitor 300 includes a substrate 302 having a first surface 304 along the height or thickness direction Z and a second surface 306 opposite the first surface 304. The capacitor 300 also includes a first conductive layer 108 formed on at least a portion of the first surface 304 of the substrate 302 and a second conductive layer 310 formed on at least a portion of the second surface 306 of the substrate 302.

[0050] However, unlike capacitor 100, capacitor 300 shown in Figures 3A and 3B also includes a first passivation layer 312 and a second passivation layer 314. The first passivation layer 312 is formed on at least a portion of the first surface 304 of the substrate 302 such that the first passivation layer 312 is positioned between the substrate 302 and the first conductive layer 308. The second passivation layer 314 is formed on at least a portion of the second surface 306 of the substrate 302 such that the second passivation layer 314 is positioned between the substrate 302 and the second conductive layer 310. The passivation layers 312 and 314 can facilitate the formation of the conductive layers 308 and 310 using plating methods (such as electroless plating and electrolytic plating), which can enhance the usefulness or functionality of the single-layer capacitor.

[0051] In some embodiments, the first passivation layer 312 and / or the second passivation layer 314 can extend over the entire respective surfaces 304, 306 on which the respective passivation layers 312, 314 are formed. For example, the first passivation layer 312 can extend to each edge defining the first surface 304 of the substrate 302, and / or the second passivation layer 314 can extend to each edge defining the second surface 306 of the substrate 302. Alternatively, the first passivation layer 312 and / or the second passivation layer 314 can be offset from one or more edges of the respective surfaces 304, 306, as shown, for example, in Figures 3A and 3B.

[0052] Similarly, the first conductive layer 308 may extend over the entire first passivation layer 312, for example, to each edge of the first passivation layer 312, and / or the second conductive layer 310 may extend over the entire second passivation layer 314, for example, to each edge of the second passivation layer 314. In other embodiments, the first conductive layer 308 and / or the second conductive layer 310 may be offset from one or more edges of the respective passivation layers 312, 314 on which the respective conductive layers 308, 310 are formed.

[0053] As shown in Figure 3B, the first conductive layer 308 may have a first thickness t1 along the height or thickness direction Z, and the second conductive layer 310 may have a second thickness t2 along the height or thickness direction Z. The first passivation layer 312 may have a first passivation thickness t along the height or thickness direction Z. p1 The second passivation layer 314 may have a second passivation thickness t along the height or thickness direction Z. p2 It may have a similar shape. Similarly, the substrate 302 has a substrate thickness t along the height or thickness direction Z. sub It may have.

[0054] In some embodiments, the first conductive layer 308 and the second conductive layer 310 may have approximately equal thicknesses t1 and t2, while in other embodiments, the first thickness t1 of the first conductive layer 308 or the second thickness t2 of the second conductive layer 310 may be greater than the other thickness t1 and t2. Similarly, in various embodiments, the first passivation layer 312 and the second passivation layer 314 may have approximately equal passivation thickness t p1 t p2 It may have, or different passivation thickness t p1 t p2 It may have a first thickness t1 of the first conductive layer 308 and / or a second thickness t2 of the second conductive layer 310, the first passivation thickness tp1 and the second passivation thickness t p2 It may be larger. In other embodiments, the first passivation thickness t p1 or second passivation thickness t p2 At least one of the two thicknesses may be greater than at least one of the first thickness t1 or the second thickness t2.

[0055] Furthermore, substrate thickness t sub The substrate thickness t may be greater than the thickness of each individual layer 308, 310, 312, and 314, and in some embodiments, the substrate thickness t sub This may be greater than or equal to the sum of the thicknesses of each individual layer 308, 310, 312, and 314. However, in other embodiments, at least one of the first conductive layer 308, the second conductive layer 310, the first passivation layer 312, or the second passivation layer 314 is the substrate thickness t sub It may have a thickness greater than or, in yet another embodiment, the substrate thickness t sub The substrate thickness t may be less than the sum of the thicknesses of each individual layer 308, 310, 312, and 314. For example, in some embodiments, the substrate thickness t may be less than the sum of the thicknesses of each individual layer 308, 310, 312, and 314. sub The ratio may be at least about 1, for example, at least about 1.5, at least about 2, at least about 2.5, at least about 3, or at least about 4. However, in other embodiments, the substrate thickness t is relative to the sum of the respective thicknesses of each individual layer 308, 310, 312, 314. sub The ratio may be approximately 1 or less, for example, approximately 0.9 or less, approximately 0.8 or less, approximately 0.75 or less, or approximately 0.7 or less.

[0056] In some embodiments, the first passivation thickness t p1 and / or second passivation thickness t p2 This may be at least about 50 angstroms, for example, at least about 75 angstroms, at least about 100 angstroms, or at least about 150 angstroms. Furthermore, the substrate thickness tsub This may be at least about 50 microns, for example, at least about 75 microns, at least about 100 microns, at least about 150 microns, at least about 250 microns, at least about 500 microns, or at least about 1000 microns.

[0057] Referring here to Figure 4, a side view is provided of a circuit board 450 having at least partially embedded single-layer capacitor 300 according to an aspect of the present disclosure. The circuit board 450 may include a circuit board substrate 452 having a mounting surface 454. In the embodiment shown in Figure 4, the capacitor 300 is fully embedded in the circuit board substrate 452. More specifically, in the embodiment of Figure 4, the capacitor 300 is fully embedded in the circuit board substrate 452 such that the substrate 302 of the capacitor 300, the first conductive layer 308, the first passivation layer 312, the second passivation layer 314, and the second conductive layer 310 are respectively positioned below the mounting surface 454 of the circuit board 450 along the height or thickness direction Z. Although not shown herein, in other embodiments, it will be understood that the capacitor 300 may be fully embedded within the circuit board substrate 452 in a manner similar to that shown with respect to the capacitor 100 in Figure 2B, such that the first conductive layer 308 of the capacitor 300 is coplanar with the mounting surface 454 of the circuit board 450. In yet another embodiment, the capacitor 300 may be partially embedded within the circuit board substrate 452 such that the first conductive layer 308 of the capacitor 300, the first passivation layer 312, at least a portion of the substrate 302, the second passivation layer 314, and / or a portion of the second conductive layer 310 extend above the mounting surface 454 of the circuit board 450 along the height or thickness direction Z.

[0058] As further shown in Figure 4, the capacitor 300 can be electrically connected to the conductive layer 456 of the circuit board 450. For example, as shown in Figure 4, a via 458 can extend from the first conductive layer 308 of the capacitor 300 toward the mounting surface 454 of the circuit board 450 and connect to the conductive layer 456 formed on the mounting surface 454. Thus, the via 458 of the circuit board 450 can electrically connect the capacitor 300 to the conductive layer 456 of the circuit board 450. In other embodiments, a conductive path, such as the conductive path 260 of the circuit board 250 shown in Figures 2B and 2C, or a conductive path formed on the mounting surface 454, can electrically connect the capacitor 300 to the conductive layer 456 of the circuit board 450.

[0059] Referring here to Figure 5, aspects of this subject matter relate to a method 500 for forming a single-layer capacitor as described herein. Generally, the method 500 is described herein with reference to the capacitor 100 in Figures 1, 2A, 2B, and 2C. However, it should be understood that the method 500 disclosed may be carried out using any suitable capacitor. Furthermore, although Figure 5 shows the steps performed in a particular order for illustrative and explanatory purposes, the method described herein is not limited to any particular order or arrangement. Those skilled in the art will understand that, using the disclosure provided herein, various steps of the method disclosed herein can be omitted, rearranged, combined, and / or adapted in various ways without departing from the scope of this subject matter.

[0060] Method 500 may include the step (502) of depositing a first conductive layer 108 on at least a portion of the first surface 104 of the substrate 102 of the capacitor 100. The first conductive layer 108 may have a thickness of at least about 10 microns, for example, at least about 20 microns, at least about 40 microns, or at least about 80 microns. The first conductive layer 108 may cover the entire first surface 104 of the substrate 102, or it may be offset from one or more edges defining the periphery of the first surface 104. The first conductive layer 108 may be formed from any suitable conductive material as described herein.

[0061] Method 500 may also include the step (504) of depositing a second conductive layer 110 on at least a portion of the second surface 106 of the substrate 102 of the capacitor 100. The second conductive layer 110 may have a thickness of at least about 10 microns, for example, at least about 20 microns, at least about 40 microns, or at least about 80 microns. The second conductive layer 110 may cover the entire second surface 106 of the substrate 102, or it may be offset from one or more edges defining the periphery of the second surface 106. The second conductive layer 110 may be formed from any suitable conductive material as described herein.

[0062] It will be understood that the steps of depositing the first conductive layer 108 (502) and depositing the second conductive layer 110 (504) may include finishing the capacitor 100 (the substrate 102 having the first conductive layer 108 and the second conductive layer 110 on opposing surfaces) using any suitable method such as firing to ensure that the components of the capacitor 100 adhere to each other and to prepare the capacitor 100 for use on the circuit board 250 described herein.

[0063] In some embodiments, depositing the first conductive layer 108 may include printing the first conductive layer 108 onto at least a portion of the first surface 104 of the substrate 102, for example, by screen printing. Similarly, in some embodiments, depositing the second conductive layer 110 may include printing the second conductive layer 110 onto at least a portion of the second surface 106 of the substrate 102, for example, by screen printing. It will be understood that screen printing the first conductive layer 108 and / or the second conductive layer 110 may include utilizing screen printing techniques known in the art. However, the (one or more) conductive layers 108, 110 may be applied to the substrate 102 by any known process such as spin coating, impregnation, casting, drop coating, spray coating, vapor deposition, sputtering, sublimation, knife coating, painting, or printing (e.g., inkjet, screen, or pad printing).

[0064] In some embodiments, one or more additional layers of conductive material can be plated on an initial printed layer of conductive material to form a first conductive layer 108 and / or a second conductive layer 110 having a thickness of at least about 5 microns, for example, about 10 microns or more. For example, depositing the first conductive layer 108 may include printing a first layer of conductive material on a first surface 104 of the substrate 102, and then plating at least one additional layer of conductive material on the first layer of conductive material. Similarly, depositing the second conductive layer 110 may include printing a second layer of conductive material on a second surface 106 of the substrate 102, and then plating at least one additional layer of conductive material on the second layer of conductive material.

[0065] Referring here to Figure 6, aspects of this subject matter relate to a method 600 for forming a single-layer capacitor as described herein. Generally, method 600 is described herein with reference to the capacitor 300 in Figures 3A, 3B, and 4. However, it should be understood that method 600 of disclosure can be carried out using any suitable capacitor. Furthermore, although Figure 6 shows the steps performed in a particular order for illustrative and explanatory purposes, the method described herein is not limited to any particular order or arrangement. Those skilled in the art will understand that using the disclosure provided herein, various steps of the method disclosed herein can be omitted, rearranged, combined, and / or adapted in various ways without departing from the scope of this subject matter.

[0066] Method 600 may include the step (602) of depositing a first passivation layer 312 on at least a portion of the first surface 304 of the substrate 302 of the single-layer capacitor 300. The passivation layer 312 may be formed from a variety of suitable materials, including polymer materials and / or inorganic materials such as glass or ceramic. For example, in some embodiments, the first passivation layer 312 may be or contain polyimide. In some embodiments, the (one or more) passivation layers may contain at least one of silicon oxynitride, Al2O3, SiO2, Si3N4, benzocyclobutene, or glass.

[0067] Method 600 may include the step (604) of depositing the first conductive layer 308 on at least a portion of the first passivation layer 312 such that the first passivation layer 312 is positioned between the first surface 304 of the substrate 302 and the first conductive layer 308. The first conductive layer 308 may be included within the periphery of the first passivation layer 312, for example, extending to the edge of the first passivation layer 312 and / or offset from one or more edges of the first passivation layer 312. The first conductive layer 308 does not have to include direct contact and / or direct electrical connection with the substrate 302.

[0068] Furthermore, the method 600 may include the step (606) of depositing a second passivation layer 314 on at least a portion of a second surface 306 of a substrate 302, wherein the second surface 306 is on the opposite side of the first surface 304 on which the first passivation layer 312 is formed. Similar to the first passivation layer 312, the second passivation layer 314 may be formed from a variety of suitable materials, including polymer materials and / or inorganic materials such as at least one of glass, ceramic, polyimide, silicon oxynitride, Al2O3, SiO2, Si3N4, or benzocyclobutene.

[0069] Furthermore, method 600 may include the step (608) of depositing the second conductive layer 310 on at least a portion of the second passivation layer 314 such that the second passivation layer 314 is positioned between the second surface 306 of the substrate 302 and the second conductive layer 310. The second conductive layer 310 may be included within the periphery of the second passivation layer 314, for example, extending to the edge of the second passivation layer 314 and / or offset from one or more edges of the second passivation layer 314. The second conductive layer 310 does not have to include direct contact and / or direct electrical connection with the substrate 302.

[0070] As described elsewhere in this specification, depositing the first and / or second passivation layers 312, 314 may include depositing a paste (e.g., glass paste, glass ceramic paste, etc.) onto the substrate 302, and then firing the substrate and paste to form (one or more) passivation layers on the substrate 302. However, any suitable process may be used to form (one or more) passivation layers. It will be understood that (one or more) passivation layers are deposited on the substrate 302 by depositing a paste as described above and firing the paste and substrate 302 before depositing the respective conductive layers 308, 310 on each of the passivation layers 312, 314.

[0071] Furthermore, depositing the first and / or second conductive layers 308, 310 may include plating the first conductive layer 308 onto the first passivation layer 312 and / or plating the second conductive layer 310 onto the second passivation layer 314. The first and / or second conductive layers 308, 310 may be plated using electroplating and / or electroless plating methods as described above.

[0072] In any case, it will be understood that the steps of depositing the first passivation layer 312 (602), depositing the first conductive layer 308 (604), depositing the second passivation layer 314 (606), and depositing the second conductive layer 310 (608) may include finishing the capacitor 300 (the substrate 302 having the first conductive layer 308 and the first passivation layer 312 on opposite surfaces of the second conductive layer 310 and the second passivation layer 314) using any suitable method such as firing to ensure that the components of the capacitor 300 adhere to each other and to prepare the capacitor 300 for use on the circuit board 450 described herein. [Industrial applicability]

[0073] The capacitors described herein are useful for a variety of applications, including filtering of hybrid package components and internally packaged semiconductors. Furthermore, because the capacitors exhibit excellent performance at high frequencies, such as above 20 GHz, they may be useful in devices that process broadband radio frequency signals. Examples of such devices include mobile devices (e.g., cell phones, tablets), cell phone base stations, receiver optical subassemblies (ROSAs), transmit optical subassemblies (TOSAs), and other RF communication devices. Such RF devices may be particularly useful for military and space applications.

[0074] These and other modifications and variations of the present invention can be carried out by those skilled in the art without departing from the spirit and scope of the invention. Furthermore, it should be understood that the aspects of the various embodiments may be interchangeable in whole or in part. Furthermore, those skilled in the art will understand that the foregoing description is merely illustrative and is not intended to limit the invention as further described in the appended claims. [Explanation of Symbols]

[0075] 100 Capacitors 102 circuit boards 104 First surface 106 Second surface 108 First conductive layer 110 Second conductive layer 250 circuit boards 252 Circuit board base material 254 Implementation aspects 256 Conductive layer 258 Beer 260 Conductive Path 300 Single-layer capacitor 302 circuit board 304 First surface 306 Second surface 308 First conductive layer 310 Second conductive layer 312 First Passivation Layer 314 Second Passivation Layer 450 Circuit Boards 452 Circuit board base material 454 Implementation aspects 456 Conductive layer 458 Beer 500 ways 600 ways t1 First thickness t2 Second thickness t sub substrate thickness t p1 First passivation thickness t p2 Second passivation thickness Z (height or thickness direction)

Claims

1. A circuit board substrate having a mounting surface, A single-layer capacitor, at least partially embedded within the circuit board substrate, A substrate having a first surface opposite to the second surface, A first passivation layer formed on at least a portion of the first surface of the substrate, A first conductive layer formed on at least a portion of the first passivation layer, A second conductive layer formed on at least a portion of the second surface of the substrate and Includes single-layer capacitors and A circuit board equipped with the following features.

2. The aforementioned single-layer capacitor is A second passivation layer formed on at least a portion of the second surface of the substrate. It further includes, The circuit board according to claim 1, wherein the second conductive layer is formed on the second passivation layer such that the second passivation layer is disposed between the substrate and the second conductive layer.

3. The aforementioned single-layer capacitor is At least one via connected to the first conductive layer, the at least one via extending toward the mounting surface of the circuit board substrate. The circuit board according to claim 1, further comprising:

4. The circuit board according to claim 3, wherein a conductive layer of the circuit board is formed on the mounting surface, and at least one via electrically connects the conductive layer of the circuit board and the first conductive layer of the single-layer capacitor.

5. The circuit board according to claim 1, wherein the single-layer capacitor is completely embedded in the circuit board substrate such that the substrate, the first passivation layer, the first conductive layer, and the second conductive layer are each positioned below the mounting surface along the height direction.

6. The circuit board according to claim 1, wherein the single-layer capacitor is completely embedded in the circuit board substrate such that the first conductive layer is coplanar with the mounting surface.

7. The circuit board according to claim 1, wherein the single-layer capacitor is partially embedded in the circuit board substrate such that one or more of the substrate, the first passivation layer, the first conductive layer, and the second conductive layer extend upward along the height direction toward the mounting surface.

8. A substrate having a first surface and a second surface opposite to the first surface, A first passivation layer formed on at least a portion of the first surface of the substrate, A first conductive layer formed on at least a portion of the first passivation layer, A second conductive layer formed on at least a portion of the second surface of the substrate and A single-layer capacitor, including one.

9. A second passivation layer formed on at least a portion of the second surface of the substrate. It further includes, The single-layer capacitor according to claim 8, wherein the second conductive layer is formed on the second passivation layer such that the second passivation layer is disposed between the substrate and the second conductive layer.

10. A method for forming a single-layer capacitor, wherein the method is The steps include depositing a first passivation layer on at least a portion of the first surface of a substrate, The steps include depositing a first conductive layer on at least a portion of the first passivation layer, A step of depositing a second conductive layer on at least a portion of the second surface of the substrate, wherein the second surface is on the opposite side of the first surface. Methods that include...

11. The step of depositing the second passivation layer on at least a portion of the second surface of the substrate such that the second passivation layer is positioned between the second surface of the substrate and the second conductive layer. The method according to claim 10, further comprising:

12. The method according to claim 11, wherein the first passivation layer and the second passivation layer are deposited before depositing either the first conductive layer or the second conductive layer, and the steps of depositing the first passivation layer and depositing the second passivation layer include the steps of depositing a paste and firing the substrate together with the paste deposited on the substrate.

13. The method according to claim 12, wherein the step of depositing the second conductive layer includes the step of plating the second conductive layer onto the second passivation layer.

14. The method according to claim 10, wherein the step of depositing the first passivation layer includes the step of depositing a paste, and the step of firing the substrate together with the paste deposited on the substrate.

15. The method according to claim 14, wherein the step of depositing the first conductive layer includes the step of plating the first conductive layer onto the first passivation layer.

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