MOSFET having an injected charge compensation region

Abstract

A semiconductor device includes a semiconductor layer having a first conductivity type, a well region within the semiconductor layer having a second conductivity type opposite to the first conductivity type, a source region having the first conductivity type within the well region, and a charge compensation region formed by injection below the well region within the semiconductor layer. The source region is adjacent to a channel region within the well region. A method for forming a semiconductor device includes forming a well region having a second conductivity type within a semiconductor layer having a first conductivity type opposite to the second conductivity type, forming a source region having the first conductivity type within the well region, and injecting ions into the semiconductor layer to form a charge compensation region below the well region within the semiconductor layer. The source region is adjacent to a channel region within the well region.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, and more particularly to power semiconductor switching devices.

Background Art

[0002] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a well-known type of semiconductor transistor that can be used as a switching device. A MOSFET is a three-terminal device that includes a source region and a drain region separated by a channel region, and a gate electrode disposed adjacent to the channel region. A MOSFET can be turned on or off by applying a gate bias voltage to the gate electrode. When the MOSFET is turned on (i.e., in its "on state"), current is conducted through the channel region of the MOSFET between the source region and the drain region. When the bias voltage is removed from the gate electrode (or drops below the threshold level), current ceases to conduct through the channel region. As an example, an n-type MOSFET has an n-type source region and drain region and a p-type channel. Thus, an n-type MOSFET has an "n-p-n" design. An n-type MOSFET turns on when a gate bias voltage sufficient to create a conductive n-type inversion layer in the p-type channel region that electrically connects the n-type source region and drain region is applied to the gate electrode, thereby enabling conduction of majority carriers between the source region and the drain region.

[0003] The gate electrode of a power MOSFET is typically isolated from the channel region by a thin gate isolation pattern, such as a silicon oxide pattern. Because the MOSFET's gate electrode is isolated from the channel region by this pattern, a minimal gate current is required to maintain the MOSFET in its on state or to switch it between its on and off states. Since the gate forms a capacitor with the channel region, the gate current remains low during switching. Therefore, only a minimal charge / discharge current is required during switching, enabling a simpler gate drive circuit.

[0004] Another well-known type of semiconductor switching device is the insulated-gate bipolar transistor (IGBT), which combines the high impedance gate of a power MOSFET with the low on-state conduction loss of a power bipolar junction transistor (BJT). IGBTs can be implemented, for example, as a Darlington pair with a high-voltage n-channel MOSFET at the input and a BJT at the output. The base current of the BJT is supplied through the channel of the MOSFET, enabling a simplified external drive circuit.

[0005] There is a growing demand for high-power semiconductor switching devices that can carry large currents in the "on" state and block large voltages (e.g., hundreds or even thousands of volts) in the reverse-blocked state. To support high current densities and block such high voltages, power MOSFETs and IGBTs typically have a vertical structure with sources and drains on either side of a thick semiconductor layer structure to block higher voltage levels. In very high power applications, semiconductor switching devices are typically formed from wide-bandgap semiconductor material systems such as silicon carbide ("SiC"), which have several advantageous properties, including, for example, high field breakdown strength, high thermal conductivity, high electron mobility, high melting point, and high saturated electron drift rate (in this specification, the term "wide-bandgap semiconductor" encompasses any semiconductor having a bandgap of at least 1.4 eV). Compared to devices formed using other semiconductor materials such as silicon, electronic devices formed using silicon carbide can have the ability to operate at higher temperatures, higher power densities, higher speeds, higher power levels, and / or under higher radiation densities. [Overview of the Initiative] [Means for solving the problem]

[0006] A semiconductor device according to some embodiments includes a semiconductor layer having a first conductivity type, a well region within the semiconductor layer having a second conductivity type opposite to the first conductivity type, a source region having the first conductivity type within the well region, and an injection-formed charge compensation region below the well region within the semiconductor layer. The source region is adjacent to a channel region within the well region.

[0007] In some embodiments, the charge compensation region enhances the voltage blocking capability of the semiconductor device.

[0008] The semiconductor device may further include a gate insulating layer on top of the channel region in the semiconductor layer, a gate contact on the gate insulating layer, and a first contact on the source region.

[0009] The semiconductor device is a substrate having a first conductivity type, wherein a semiconductor layer is located on the substrate, and a second contact is located on the substrate, and the substrate may further include this substrate.

[0010] In some embodiments, the charge compensation region includes unactivated implanted dopant ions.

[0011] In some embodiments, the semiconductor layer comprises silicon carbide, and the charge compensation region comprises hydrogen dopant ions, aluminum dopant ions, or nitrogen dopant ions.

[0012] In some embodiments, the semiconductor layer comprises silicon carbide, and the charge compensation region comprises inert ions. The inert ions may include He ions, Ne ions, and / or Ar ions.

[0013] In some embodiments, the semiconductor layer comprises silicon carbide, and the charge compensation region comprises dopant ions that form deep-level traps within the semiconductor layer. The dopant ions may comprise carbon and / or iron.

[0014] The charge compensation region can reduce the electric field strength in the area around the charge compensation region within the semiconductor layer during the voltage blocking operation of the device.

[0015] The semiconductor device may further include a doped well-contact region within the semiconductor layer adjacent to the source region, the well-contact region having a second conductivity type and in contact with the well region, and a charge compensation region provided at least partially beneath the well-contact region.

[0016] The semiconductor device may further include a doped well-contact region within the semiconductor layer adjacent to the source region, the well-contact region having a second conductivity type and in contact with the well region, and the charge compensation region is not located directly beneath the well-contact region.

[0017] In some embodiments, the charge compensation region is spaced vertically away from the well region.

[0018] The semiconductor device may further include a vertical conductive region adjacent to the well region, and the charge compensation region may be formed below the lower corner of the well region, near the vertical conductive region.

[0019] In some embodiments, the charge compensation region extends beyond the lower corner of the well region into the vertical conductive region.

[0020] Methods for forming a semiconductor device according to some embodiments include forming a well region within a semiconductor layer, wherein the semiconductor layer has a first conductivity type and the well region has a second conductivity type opposite to the first conductivity type; forming a source region within the well region, wherein the source region has a first conductivity type and the source region is adjacent to a channel region within the well region; and implanting ions into the semiconductor layer to form a charge compensation region below the well region within the semiconductor layer.

[0021] The charge compensation region can enhance the voltage blocking capability of semiconductor devices.

[0022] In some embodiments, the semiconductor layer comprises silicon carbide, and forming a charge compensation region involves implanting aluminum dopant ions or nitrogen dopant ions into the semiconductor layer.

[0023] In some embodiments, the semiconductor layer comprises silicon carbide, and the charge compensation region comprises dopant ions that form deep-level traps within the semiconductor layer. The dopant ions may comprise carbon and / or iron.

[0024] In some embodiments, the semiconductor layer includes silicon carbide, and ion implantation includes implanting inert ions. The inert ions may include He ions, Ne ions, and / or Ar ions.

[0025] In some embodiments, the charge compensation region reduces the electric field strength in the area around the charge compensation region within the semiconductor layer during the voltage blocking operation of the device.

[0026] The method can further include forming a doped well contact region adjacent to the source region within the semiconductor layer, the well contact region having a second conductivity type and contacting the well region, and the charge compensation region being at least partially formed under the well contact region.

[0027] The method can further include forming a doped well contact region adjacent to the source region within the semiconductor layer, the well contact region having a second conductivity type and contacting the well region, and the charge compensation region not being provided directly under the well contact region.

[0028] In some embodiments, the charge compensation region is vertically spaced from the well region.

[0029] The method can further include forming a vertical conductive region adjacent to the well region, and the charge compensation region is formed under the lower corner of the well region near the vertical conductive region.

[0030] In some embodiments, the charge compensation region extends into the vertical conductive region beyond the lower corner of the well region.

[0031] The method can further include forming a gate insulating layer over the channel region in the semiconductor layer, a gate contact over the gate insulating layer, and a first contact over the source region.

[0032] The method further includes providing a substrate having a first conductivity type, wherein the semiconductor layer is formed on the substrate, and forming a second contact on the substrate. [Brief explanation of the drawing]

[0033] [Figure 1] This is a cross-sectional view of a conventional MOSFET structure. [Figure 2A] This is a cross-sectional view of a MOSFET structure including a charge compensation structure / charge trapping structure according to several embodiments. [Figure 2B] This is a cross-sectional view of a MOSFET structure including a charge compensation structure / charge trapping structure according to several embodiments. [Figure 2C] This is a graph of dopant concentrations in MOSFET structures, including charge compensation / charge trapping structures, for several examples. [Figure 3] This is a cross-sectional view of a MOSFET structure including a charge compensation structure / charge trapping structure according to several embodiments. [Figure 4] This is a cross-sectional view of a MOSFET structure including a charge compensation structure / charge trapping structure according to several embodiments. [Figure 5] This is a cross-sectional view of a MOSFET structure including a charge compensation structure / charge trapping structure according to several embodiments. [Figure 6] This is a cross-sectional view of a MOSFET structure including a charge compensation structure / charge trapping structure according to several embodiments. [Figure 7] This is a cross-sectional view of a MOSFET structure including a charge compensation structure / charge trapping structure according to several embodiments. [Figure 8] This block diagram shows the operation for forming a MOSFET structure including a charge compensation structure / charge trapping structure according to several embodiments. [Modes for carrying out the invention]

[0034] Power silicon carbide MOSFETs are currently used for applications requiring high voltage blocking, such as blocking voltages of 5,000 volts or more. For example, silicon carbide MOSFETs rated to current densities of 10 A / cm² or higher, blocking voltages of at least 10 kV, are commercially available. To form such a device, typically multiple "unit cells" are formed, each containing a MOSFET transistor. In higher power applications, typically a large number (e.g., hundreds or thousands) of these unit cells are mounted on a single semiconductor substrate, with a gate electrode pattern forming on the upper side of the semiconductor substrate, acting as the gate electrode for all the unit cells. The opposite (bottom) side of the semiconductor substrate acts as a common drain for all the unit cells of the device. Multiple source contacts are formed on the source region within the semiconductor layer structure, exposed within the opening in the gate electrode pattern. These source contacts are also electrically connected to each other and function as a common source. The resulting device has three terminals: a common source terminal, a common drain terminal, and a common gate electrode, which act as terminals for hundreds or thousands of individual unit cell transistors. The above explanation pertains to an n-type MOSFET, and it should be understood that the drain and source locations are reversed for a p-type MOSFET.

[0035] One potential problem with conventional MOSFET structures, such as power MOSFETs using SiC, is the presence of a high electric field in the gate oxide at the center of the junction field-effect transistor (JFET) region of the device. The JFET region is generally the active portion of the N-type drift layer, which may contain an N-type dopant and is located between two P-type wells. The JFET region refers to the region within the drift layer that contacts the channel region, which approaches the surface of the P-type well in response to the application of a gate voltage. In a vertical device, the JFET region forms a vertical conductive path for the electrodes in the device, including the N+ source region, the channel region, the N-type drift layer, the substrate, and the drain electrode.

[0036] Figure 1 is a schematic cross-sectional view of a unit cell of a conventional semiconductor device 100, where the region of interest is identified according to some embodiments described herein.

[0037] As shown in Figure 1, the device 100 may be a transistor (e.g., a MOSFET) formed using an n-type silicon carbide semiconductor substrate 110, or may include such a transistor. The substrate 110 may include, for example, a single-crystal 4H silicon carbide semiconductor substrate (i.e., an n+ silicon carbide substrate) highly doped with n-type impurities. A low-doped n-type (n-) silicon carbide drift layer 120 is provided on the substrate 110. The upper part of the n-type silicon carbide drift layer 120 may be p-type doped by ion implantation to form p-wells 130. Each p-well 130 may be formed by ion implantation, but the embodiments described herein are not limited thereto.

[0038] As is well known to those skilled in the art, ions such as n-type or p-type dopants can be implanted into a semiconductor layer or region by ionizing a desired ion species and accelerating these ions to a predetermined kinetic energy as an ion beam toward the surface of the semiconductor layer in an ion implantation target chamber. Based on the desired kinetic energy, the desired ion species can penetrate into the semiconductor layer. The ions will be implanted into the semiconductor layer at various depths, and therefore the desired kinetic energy will provide an implantation "profile" in which the ion concentration changes with depth.

[0039] A highly doped (n+)n-type silicon carbide source region 140 can be formed on top of the p-well 130. The n-type source region 140 can be formed by ion implantation. The highly doped (n+)n-type silicon carbide region 140 acts as a source region for the device 100. A P+ well contact region 145 can be formed extending from the surface of the drift layer 120 into the p-well 130.

[0040] The drift layer 120 and the substrate 110 both act as a common drain region for the device 100. The n-type silicon carbide substrate 110, the n-type silicon carbide drift layer 120, the p-well 130, and the n-type source region 140 formed in the p-well 130 can together constitute the semiconductor layer structure 150 of the device 100.

[0041] A gate insulation pattern 170 may be formed on the upper surface of the semiconductor layer structure 150. The gate insulation pattern 170 may include, for example, a silicon dioxide (SiO2) layer, but other insulating materials such as SiOxNy, SiOxNy, Al2O3, and / or high dielectric constant dielectrics such as hafnium oxide may be used. A gate electrode 172 may be formed on the gate insulation pattern 170 facing the semiconductor layer structure 150.

[0042] A source contact 162 may be formed on a highly doped n-type source region 140, and a drain contact 164 may be formed on the underside of the substrate 110. It will be understood that the above description pertains to an n-type MOSFET. In a p-type device, the locations of the source and drain contacts may be reversed, and the conductivity types of the other n-type and p-type regions may be swapped. Thus, the source region 140 can be called a "source / drain region" 140.

[0043] The voltage blocking characteristics of vertical power FET devices, such as MOSFETs or IGBTs, are a critical performance factor of the device. The embodiments described herein provide structures and methods for improving the voltage blocking characteristics of vertical power FET devices including p-well regions. In particular, some embodiments provide methods for suppressing / mitigating electric field concentration below or near the bottom of a p-well by providing a charge compensation region / charge trapping region below or near the bottom of the p-well. The charge compensation region / charge trapping region can be formed, for example, by implanting ions near the bottom of the p-well. The ions may include dopant ions that are not later activated, or inactive ions such as He, Ne, or Ar. The dopant ions may include, for example, shallow-level dopant ions such as Al, P, or N, or deep-level dopant ions such as Fe, C, or H.

[0044] While we do not wish to be bound by a specific theory of operation, it is believed that implantation damage caused by ion implantation forms charge compensation / charge trapping regions at specific locations within the device structure. These charge compensation / charge trapping regions are thought to play a role in suppressing / mitigating electric field concentration within the device. The blocking characteristics of the device can be enhanced by positioning these compensation / trapping regions near the bottom of the p-well region, particularly near the corners of the p-well region adjacent to the JFET region 125 of the device, where failure typically occurs.

[0045] When dopant ions are implanted into a semiconductor crystal, the charged ions are accelerated by an electric field with a predetermined energy (typically expressed as keV or MeV), guided toward the semiconductor crystal, and physically implanted into the crystal. The implantation action causes damage to the crystal lattice of the semiconductor crystal (sometimes called "lattice damage"). Typically, dopant ions are implanted into a semiconductor crystal to change its electrical properties depending on the nature of the implanted ions, for example, to an n-type or p-type material. For example, nitrogen ions or phosphorus ions can be implanted into a silicon carbide crystal to form n-type SiC, while aluminum ions can be implanted into a silicon carbide crystal to form p-type SiC. After dopant ion implantation, the lattice damage is repaired by annealing or heat-treating the semiconductor crystal at high temperatures, which can create chemical bonds in the semiconductor crystal being repaired and / or move the dopant ions to positions within the crystal lattice, where they can become electrically active. Where lattice damage is not repaired, electrical "traps" can form that can capture or compensate for mobile charge carriers (e.g., electrons or holes) within the semiconductor crystal.

[0046] According to some embodiments, implantation damage caused by ion implantation may remain unrepaired, thus leaving electrical traps within the semiconductor crystal. Currently, it is believed that by positioning these electrical traps at specific locations within the device structure, they may help mitigate electric field concentration within the device at those locations. Therefore, in some embodiments, the activation / repair annealing process may be omitted after ion implantation to form charge compensation / charge trapping regions within the device. The charge compensation / charge trapping regions formed by ion implantation may be more concisely referred to herein as "charge compensation regions."

[0047] Figure 2A shows some vertical power FET devices 200 according to several embodiments. In particular, the vertical power FET device 200 includes an n-drift layer 120 on a 4H-SiC substrate 110. A p-type p-well region 130 is formed within the drift layer 120, and an n-type source region 140 is formed within the p-well region. A p-well contact region 145 is provided adjacent to the source region 140. A channel region 135 is defined between the source region 140 and the JFET region 125 of the drift layer 120.

[0048] A source contact 162 is formed on the surface of the semiconductor layer structure 150 and is in contact with the source region 140 and the p-well contact region 145. A gate dielectric 170 is located on the drift layer 120, and the gate contact 172 is located on the gate dielectric 170.

[0049] A charge compensation region 210 is formed below the p-well region 130. As described above, the charge compensation region 210 can be formed by implanting dopant ions that are not later activated (e.g., by implantation-activated annealing), or by implanting inactive / inert ions such as He, Ne, or Ar, so that lattice damage caused by implantation is not later repaired by annealing. Dopant ions may include, for example, shallow-level dopant ions such as Al, P, or N, or deep-level dopant ions such as Fe, C, or H.

[0050] The charge compensation region 210 may be located directly below the p-well region 130, as shown in Figure 2A, or it may be spaced vertically from the p-well region 130 by a distance d1, as shown in Figure 2B. The distance d1 can be, for example, about 0 microns to about 1 micron. As described above, we do not wish to be bound by a specific theory of operation, but it is thought that the injection damage caused by dopant ion injection forms a charge compensation region 210 that can help suppress / mitigate electric field concentration within the device when the device is operating under reverse bias conditions. This can improve the blocking characteristics of the device.

[0051] Figure 2C schematically shows the doping concentrations in the p-well region 130, p+ contact region 145, and charge compensation region 210 of device 200, with the depth in the drift layer 120 shown along the x-axis and the doping concentration along the y-axis. As shown in Figure 2C, the p-well region 130 and p+ contact region 145 are 1E19cm -3 It can have doping concentrations exceeding this and can extend to a depth of approximately 1.2 microns into the drift layer 120 (in this example, depths of 0.4 to 4 microns may be used). The charge compensation region 210 is approximately 1E16 to 1E18 cm². -3 The peak doping concentration is significantly lower than the doping concentrations in the p-well region 130 and the p+ contact region 145. The injection conditions for forming the charge compensation region 210 (e.g., injection angle, injection energy, injection temperature) can be selected such that the peak doping concentration of the charge compensation region 210 is at or near the interface between the p-well region 130 and the p+ contact region 145 in the drift layer 120. However, as described above, in some embodiments, the injection conditions for forming the charge compensation region 210 can be selected such that the peak doping concentration of the charge compensation region 210 is spaced away from the interface between the p-well region 130 and the p+ contact region 145 in the drift layer 120 (i.e., the peak concentration of the charge compensation region 210 is deeper than that of the p-well region 130 and the p+ contact region 145 in the drift layer 120).

[0052] The charge compensation region 210 can be located in various places within the device 200 according to several embodiments. For example, as shown in Figure 3, in some embodiments, the charge compensation region 210 may be located primarily below the p+ contact region 140 and not located below most of the p well region 130.

[0053] Referring to Figure 4, in some embodiments, the charge compensation region 210 can be located directly below the p-well region 130, near the corner 130C of the p-well region 130, adjacent to the JFET region 125 of the device 200.

[0054] Referring to Figure 5, in some embodiments, the charge compensation region 210 can be located below the p-well region 130 rather than directly below the p+ contact region 140.

[0055] Referring to Figure 6, in some embodiments, the charge compensation region 210 can be located below the p-well region 130, near the corner 130C of the p-well region 130, adjacent to the JFET region 125 of the device 200, and can extend into the JFET region 125 beyond the side wall 130A of the p-well region 130 by a distance d2 of approximately 0 to 1 micron. In the examples shown in Figures 3 to 6, the charge compensation region may be in contact with the edge of the p-well region 130 (as shown in Figures 2A and 2B) or slightly below its edge.

[0056] Figure 7 shows a schematic mask layout of a MOSFET having an injected charge compensation region 210. The device shall have He injection below the p-well region 130 and / or p+ contact region 145 inside the active area of ​​the device. In particular, Figure 7(a) shows a layout scheme for a stripe cell design, and Figure 7(b) shows a layout scheme for a hexagonal cell design. Thus, the charge compensation region pattern can be adjusted for various MOSFET layouts as described.

[0057] Figure 8 shows the operation of forming the structure of a semiconductor device 200 according to several embodiments. Referring to Figures 2A to 6 and Figure 8, the operation includes forming a p-well region 130 within the semiconductor layer 120 (block 802). The semiconductor layer 120 has a first conductivity type (e.g., n-type), and the p-well region 130 has a second conductivity type (e.g., p-type) opposite to the first conductivity type.

[0058] A source region 140 is formed within the well region (block 804). The source region 140 has a first conductivity type and is adjacent to the channel region 135 within the well region. Ions are injected into the semiconductor layer 120 to form a charge compensation region 210 within the semiconductor layer 120 below the p-well region 130 (block 806). The charge compensation region 210 can enhance the voltage blocking capability of the semiconductor device 200. In particular, the charge compensation region 210 can reduce the electric field strength in the area around the charge compensation region 210 within the semiconductor layer 120 during the voltage blocking operation of the device 200.

[0059] The semiconductor layer 120 may contain silicon carbide, and forming the charge compensation region 210 may include implanting aluminum dopant ions or nitrogen dopant ions into the semiconductor layer 120.

[0060] In some embodiments, the charge compensation region 210 includes dopant ions that form deep level traps within the semiconductor layer 120. For example, the dopant ions may include carbon and / or iron.

[0061] In some embodiments, ion implantation includes implanting inert ions. For example, the inert ions may include He ions, Ne ions, and / or Ar ions.

[0062] The method may further include forming a doped well contact region 145 within the semiconductor layer 120 adjacent to the source region 140. The well contact region 145 has a second conductivity type and contacts the p-well region 130. A charge compensation region 210 may be formed at least partially beneath the well contact region 145 in some embodiments.

[0063] In some embodiments, the charge compensation region 210 is not located directly below the well contact region 145.

[0064] In some embodiments, the charge compensation region 210 is spaced vertically away from the p-well region 130.

[0065] The method may further include forming a vertical conductive region 125 adjacent to the p-well region 130. In some embodiments, the charge compensation region 210 may be formed near the vertical conductive region 125, below the lower corner 130C of the p-well region 130. In some embodiments, the charge compensation region 210 may extend beyond the lower corner 130C of the p-well region 130 into the vertical conductive region 125.

[0066] The method further includes forming a gate insulating layer 170 on the channel region 135, a gate contact 172 on the gate insulating layer 170, and a source contact 162 on the source region in the semiconductor layer 120.

[0067] The method may further include providing a substrate 110 having a first conductivity type, on which a semiconductor layer 120 is formed, and forming a drain contact 164 (Figure 1) on the substrate 110.

[0068] Examples of the concept of the present invention have been described above with reference to the accompanying drawings illustrating embodiments of the concept of the present invention. However, the concept of the present invention disclosed herein may be embodied in many different forms and should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided to make this disclosure thorough and complete and to fully convey the scope of the concept of the present invention to those skilled in the art. In the drawings, the sizes and relative sizes of layers and areas may be exaggerated for clarity. When an element or layer is referred to as “on top of,” “connected to,” or “joined to” another element or layer, it will be understood that it may be directly on top of, connected to, or joined to that other element or layer, or there may be an intervening element or layer. Conversely, when an element is referred to as “directly on top of,” “directly connected to,” or “directly joined to” another element or layer, there is no intervening element or layer. Where used herein, the term “and / or” includes all combinations of one or more of the relatedly enumerated items. Similar numbers refer to similar elements throughout.

[0069] In this specification, the terms "first" and "second" are used to describe various regions, layers, and / or elements, but it will be understood that these regions, layers, and / or elements should not be limited by these terms. These terms are used solely to distinguish one region, layer, or element from another. Thus, without departing from the scope of the concept of the present invention, the first region, layer, or element discussed below may also be referred to as the second region, layer, or element, and similarly, the second region, layer, or element may also be referred to as the first region, layer, or element.

[0070] In this specification, relative terms such as “below” or “bottom” and “up” or “top” may be used to describe the relationship of one element to another, as shown in the drawings. It will be understood that relative terms are intended to encompass various orientations of the device, in addition to the orientations shown in the drawings. For example, if the device in the drawing is inverted, an element described as being “below” another element will be oriented “up” the other element. Thus, the exemplary term “below” encompasses both “below” and “up” orientations, depending on the particular orientation of the drawing. Similarly, if the device in one of the drawings is inverted, an element described as being “below” another element will be oriented “up” the other element. Thus, the exemplary terms “below” or “bottom” can encompass both up and down orientations.

[0071] The terminology used herein is for the sole purpose of describing specific embodiments and is not intended to limit the concepts of the present invention. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless the context clearly indicates otherwise. Where used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the described features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or groups thereof.

[0072] Examples are described herein with reference to schematic cross-sectional views. Therefore, modifications from the exemplary shapes, for example, as a result of manufacturing techniques and / or tolerances, are also expected. Accordingly, embodiments of the concept of the present invention should not be construed as being limited to specific shapes of the regions shown herein, and should include, for example, deviations of shape due to manufacturing. For example, an injection region shown as a rectangle will typically have rounded or curved features and / or a gradient of injection concentration at its edges, rather than a binary transition from the injection region to the non-injection region. Therefore, the regions shown in the figures are essentially schematic, and their shapes are not intended to represent the actual shapes of the regions of the device and are not intended to limit the scope of the concept of the present invention.

[0073] It will be understood that the embodiments disclosed herein can be combined. Therefore, features described and / or explained for the first embodiment can similarly be included for the second embodiment, and vice versa.

[0074] While the above embodiments are described with reference to specific figures, it should be understood that some embodiments of the concept of the present invention may include additional and / or intervening layers, structures, or elements, and / or certain layers, structures, or elements may be omitted. Although several exemplary embodiments have been described, those skilled in the art will readily understand that many modifications are possible in the exemplary embodiments without substantially departing from the novel teachings and merits of the concept of the present invention. Accordingly, all such modifications are intended to fall within the scope of the concept of the present invention as defined in the claims. Therefore, it should be understood that the foregoing description is illustrative of the concept of the present invention and should not be construed as limiting to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to fall within the scope of the concept of the present invention.

Claims

1. A semiconductor layer having a first conductivity type, A well region within the semiconductor layer having a second conductivity type opposite to the first conductivity type, A source region within the well region, wherein the source region has the first conductivity type and is adjacent to a source region within the well region, A charge compensation region injected below the well region within the semiconductor layer and A semiconductor device equipped with the following features.

2. The semiconductor device according to claim 1, wherein the charge compensation region enhances the voltage blocking capability of the semiconductor device.

3. The semiconductor device according to claim 1, further comprising a gate insulating layer on the channel region, a gate contact on the gate insulating layer, and a first contact on the source region on the semiconductor layer.

4. The semiconductor device according to claim 3, further comprising a substrate having the first conductivity type, wherein the semiconductor layer is on the substrate and the second contact is on the substrate.

5. The semiconductor device according to claim 1, wherein the charge compensation region includes unactivated implanted dopant ions.

6. The semiconductor device according to claim 1, wherein the semiconductor layer comprises silicon carbide, and the charge compensation region comprises a hydrogen dopant ion, an aluminum dopant ion, or a nitrogen dopant ion.

7. The semiconductor device according to claim 1, wherein the semiconductor layer contains silicon carbide and the charge compensation region contains inert ions.

8. The semiconductor device according to claim 7, wherein the inert ions include He ions, Ne ions, and / or Ar ions.

9. The semiconductor device according to claim 1, wherein the semiconductor layer comprises silicon carbide, and the charge compensation region comprises dopant ions that form deep-level traps within the semiconductor layer.

10. The semiconductor device according to claim 5, wherein the dopant ion comprises carbon and / or iron.

11. The semiconductor device according to claim 1, wherein the charge compensation region reduces the electric field strength in the area around the charge compensation region within the semiconductor layer during the voltage blocking operation of the device.

12. The semiconductor device according to claim 1, further comprising a well contact region doped adjacent to the source region within the semiconductor layer, wherein the well contact region has the second conductivity type and is in contact with the well region, and the charge compensation region is at least partially provided below the well contact region.

13. The semiconductor device according to claim 1, further comprising a well contact region doped adjacent to the source region within the semiconductor layer, wherein the well contact region has the second conductivity type, is in contact with the well region, and the charge compensation region is not provided directly beneath the well contact region.

14. The semiconductor device according to claim 1, wherein the charge compensation region is spaced vertically away from the well region.

15. The semiconductor device according to claim 1, further comprising a vertical conductive region adjacent to the well region, wherein the charge compensation region is formed near the vertical conductive region and below the lower corner of the well region.

16. The semiconductor device according to claim 15, wherein the charge compensation region extends beyond the lower corner of the well region into the vertical conductive region.

17. A method for forming a semiconductor device, A step of forming a well region within a semiconductor layer, wherein the semiconductor layer has a first conductivity type, and the well region has a second conductivity type opposite to the first conductivity type. A step of forming a source region within the well region, wherein the source region has the first conductivity type, and the source region is adjacent to a channel region within the well region. The steps include: implanting ions into the semiconductor layer in order to form a charge compensation region below the well region within the semiconductor layer; Methods that include...

18. The method according to claim 17, wherein the charge compensation region enhances the voltage blocking capability of the semiconductor device.

19. The method according to claim 17, wherein the semiconductor layer comprises silicon carbide, and the step of forming the charge compensation region comprises the step of implanting aluminum dopant ions or nitrogen dopant ions into the semiconductor layer.

20. The method according to claim 17, wherein the semiconductor layer comprises silicon carbide, and the charge compensation region comprises dopant ions that form deep level traps within the semiconductor layer.

21. The method according to claim 20, wherein the dopant ion comprises carbon and / or iron.

22. The method according to claim 17, wherein the semiconductor layer contains silicon carbide, and the step of implanting ions includes the step of implanting inert ions.

23. The method according to claim 22, wherein the inert ion includes He ions, Ne ions, and / or Ar ions.

24. The method according to claim 17, wherein the charge compensation region reduces the electric field strength in the area around the charge compensation region within the semiconductor layer during the voltage blocking operation of the device.

25. The method according to claim 17, further comprising the step of forming a doped well contact region adjacent to the source region within the semiconductor layer, wherein the well contact region has the second conductivity type and is in contact with the well region, and the charge compensation region is at least partially formed below the well contact region.

26. The method according to claim 17, further comprising the step of forming a doped well contact region adjacent to the source region within the semiconductor layer, wherein the well contact region has the second conductivity type, is in contact with the well region, and the charge compensation region is not located directly beneath the well contact region.

27. The method according to claim 17, wherein the charge compensation region is spaced vertically away from the well region.

28. The method according to claim 17, further comprising the step of forming a vertical conductive region adjacent to the well region, wherein the charge compensation region is formed near the vertical conductive region and below the lower corner of the well region.

29. The method according to claim 28, wherein the charge compensation region extends beyond the lower corner of the well region into the vertical conductive region.

30. The method according to claim 17, further comprising the step of forming a gate insulating layer on the channel region, a gate contact on the gate insulating layer, and a first contact on the source region on the semiconductor layer.

31. A step of providing a substrate having the first conductivity type, wherein the semiconductor layer is formed on the substrate, The steps include forming a second contact on the substrate and The method according to claim 30, further comprising:

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