Semiconductor void spacer and manufacturing method

Abstract

Embodiments of the present disclosure advantageously provide semiconductor devices, in particular Finn field-effect transistors (FinFETs), and methods for manufacturing such devices having improved effective capacitance (Ceff). The FinFET includes a gate structure in which a void is provided by recessing a high dielectric constant material layer placed between the gate structure and a spacer layer, thereby reducing the effective dielectric constant in the high dielectric constant dielectric layer and improving the effective capacitance (Ceff) of the device.

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure generally relate to semiconductor devices and manufacturing methods. More specifically, embodiments of the present disclosure are directed to field effect transistors (FETs) in which voids are provided by recessing a high-k dielectric material within a gate structure, thereby improving the effective capacitance (Ceff) of the device.

Background Art

[0002]

[0002] Transistors are important components in most integrated circuits. Since the drive current, and thus the speed, of a transistor is proportional to the gate width of the transistor, generally a larger gate width is required for a faster transistor. Therefore, there is a trade-off between the size and speed of a transistor, and "fin" field effect transistors (FinFETs) have been developed to address the conflicting goals of maximum drive current and minimum size. FinFETs are characterized by a fin-shaped channel region that can significantly increase the transistor size without significantly increasing the transistor's mounting area, and are currently applied to many integrated circuits.

[0003]

[0003] However, as the feature size of transistor devices continues to shrink to increase circuit density and performance, parasitic capacitance and off-state leakage become problems. Therefore, it is necessary to improve the design and manufacture of transistor devices to enable further reduction of device size while reducing these adverse effects.

Summary of the Invention

[0004]

[0004] One aspect of the present disclosure is directed to a semiconductor device, the semiconductor device comprising: a semiconductor stack disposed on a substrate; a metal gate structure disposed on the upper surface of the semiconductor stack, having a bottom surface, an upper surface, and side surfaces; A high dielectric constant layer is placed at the bottom of the side surface of the metal gate structure, between the bottom surface of the metal gate structure and the top surface of the semiconductor stack; A spacer layer extending along the side surface of a metal gate structure, (a) A high dielectric constant dielectric layer disposed between the spacer layer at the bottom of the side of the metal gate structure and the metal gate structure, and (b) A gap between the spacer layer on the bottom of the side of the metal gate structure and the metal gate structure, The spacer layer is separated from the side of the metal gate structure by this; A gate cap material is placed on the upper surface of the metal gate structure and does not extend into the void, This void provides a reduction in the effective dielectric constant between the side surface of the metal gate structure and the spacer layer.

[0005]

[0005] Another aspect of the present disclosure relates to a substitution metal gate structure for a semiconductor device, the substitution metal gate structure is Gate metal filling and; A gate metal filling with at least one work function metal layer surrounding the bottom and sides; A high dielectric constant layer surrounding the bottom and sides of the gate metal filling; A spacer layer extending along the side of the gate metal filling; A gap is placed between the spacer layer and at least one work function layer on the high dielectric constant layer; A gate cap material is positioned between the spacer layers and extends above the gap along the upper surface of the gate metal filling. Equipped with, At least one work function layer is located between the high dielectric constant layer and the gate metal filling. The high dielectric constant layer is located between the spacer layer and at least one work function layer at the bottom of the side surface of the gate metal filling. The void reduces the effective dielectric constant within the high-dielectric-constant dielectric layer, improving the effective capacitance of the semiconductor structure.

[0006]

[0006] Another aspect of the present disclosure relates to a method for forming a semiconductor structure, which is To provide a semiconductor stack on a substrate surface, the semiconductor stack comprising a gate structure on the upper surface of the semiconductor stack, a spacer structure extending along the outer side surface of the gate structure, and a high dielectric constant dielectric layer disposed between the spacer structure and the gate structure; To create an opening between the spacer structure and the gate structure, at least a portion of the high dielectric constant layer is selectively removed; The gate cap material is deposited on the upper surface of the gate structure to seal the opening, and a gap is formed between the spacer structure and the gate structure; Includes.

[0007]

[0007] Another aspect of the present disclosure relates to a method for forming voids within a semiconductor structure, the method being To provide a gate structure on the upper surface of a semiconductor stack, the gate structure having a bottom surface, an upper surface and a side surface, a spacer structure extending along the outer side surface of the gate structure, and a high dielectric constant dielectric layer disposed between the spacer structure and the gate structure along the outside of the gate structure; To create an opening between the spacer structure and the gate structure, at least a portion of the high dielectric constant dielectric layer is selectively removed from the top surface of the gate structure to a depth along the outer side surface of the gate structure; Along the upper surface of the gate structure, a gate cap material extending over the opening is deposited to close the opening, forming a gap between the spacer structure and the gate structure; Includes, A method in which air gaps reduce the effective dielectric constant within a high-dielectric-constant dielectric layer, thereby improving the effective capacitance of a semiconductor structure.

[0008]

[0008] To enable a more detailed understanding of the above-described features of the Disclosure, a more detailed description of the Disclosure, which is briefly summarized above, can be obtained by referring to embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings show only typical embodiments of the Disclosure, and therefore should not be considered to limit the scope of the Disclosure, as other equally valid embodiments may be permitted. Embodiments described herein are shown in the figures of the accompanying drawings as examples, not as limitations, and similar reference numerals indicate similar elements. [Brief explanation of the drawing]

[0009] [Figure 1A] The diagram shows a double cross-sectional view of a FinFET device having a dummy gate stack formed across the entire semiconductor stack, according to one or more embodiments. [Figure 1B] Figure 1A shows a side cross-sectional view of the dummy gate stack. [Figure 1C] Figure 1A shows a dual cross-sectional view of a FinFET device having a replacement metal gate (RMG) stack formed according to one or more embodiments. [Figure 1D] Figure 1C shows a side cross-sectional view of the replacement metal gate (RMG) stack. [Figure 1E] Figure 1C shows a double cross-sectional view of a FinFET device after the replacement metal gate (RMG) stack has been recessed, according to one or more embodiments. [Figure 1F] Figure 1E shows a side cross-sectional view of the replacement metal gate (RMG) stack. [Figure 1G] Figure 1E shows a double cross-sectional view of a FinFET device after the high dielectric constant gate dielectric layer has been recessed to expose the spacer and form a gap between the spacer and the outer side surface of the replacement metal gate (RMG) stack, according to one or more embodiments. [Figure 1H] Figure 1G shows a side cross-sectional view of the replacement metal gate (RMG) stack. [Figure 1I]A double cross-sectional view of a FinFET device of FIG. 1G after a capping layer is disposed over a replacement metal gate (RMG) stack, according to one or more embodiments, is shown. [Figure 1J] A side cross-sectional view of a replacement metal gate (RMG) stack of FIG. 1I is shown. [Figure 2] A schematic view of a capacitive component of a fin / gate structure is shown. [Figure 3] A graph and schematic diagram showing the impact on the effective capacitance (Ceff) when a replacement metal gate (RMG) stack, according to one or more embodiments, is recessed to different levels.

Best Mode for Carrying Out the Invention

[0010]

[0021] Before describing some exemplary embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of the configurations or process steps described in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0011]

[0022] As used herein, the term “about” means approximately or nearly and, in the context of a stated numerical value or range, means a variation of less than or equal to ±15% of that numerical value. For example, values that differ by only ±14%, ±13%, ±12%, ±11%, ±10%, ±9%, ±8%, ±7%, ±6%, ±5%, ±4%, ±3%, ±2%, or ±1% from the stated value satisfy the definition of about.

[0012]

[0023] As used herein and in the appended claims, the terms “substrate” or “wafer” refer to a surface or portion of a surface on which a process is performed. Furthermore, when a substrate is referred to, it will be understood by those skilled in the art that unless otherwise explicitly stated in the context, it may refer only to a portion of the substrate. In addition, when a deposition on a substrate is referred to, it may mean both a bare substrate and a substrate on which one or more films or features are deposited or formed. In this specification, “substrate” means any substrate on which a film treatment is performed during a manufacturing process, or any material surface formed on a substrate. For example, substrate surfaces on which treatment may be performed include, depending on the application, silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. A substrate includes, but is not limited to, a semiconductor wafer. The substrate can be subjected to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to direct film treatment on the surface of the substrate itself, any of the disclosed film treatment steps may be performed on an underlying layer formed on the substrate, as will be disclosed in more detail below. The term “substrate surface” is intended to include any underlying layer as indicated in the context. Thus, for example, if a film / layer or partial film / layer is deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0013]

[0024] The phrase "on" indicates direct contact between elements. The phrase "directly on" indicates direct contact between elements without an intervening element.

[0014]

[0025] As used herein and in the appended claims, terms such as “precursor,” “reactant,” and “reactive gas” are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0015]

[0026] Epitaxy is a process in which a deposited film is forced into a high degree of crystallographic alignment with a substrate. Epitaxial growth is broadly defined as the condensation of a gas precursor to form a film on a substrate. Liquid precursors can also be used. Vapor precursors can be obtained by chemical vapor deposition (CVD) and laser ablation. Several epitaxy techniques have become available, such as molecular beam epitaxy (MBE), epitaxial CVD, or atomic layer epitaxy (ALE).

[0016]

[0027] A transistor is a circuit component or element that is often formed on a semiconductor device. Depending on the circuit design, transistors may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, conductive wires, or other elements. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions include doped regions of the substrate and exhibit a doping profile suitable for a particular application. The gate is located above the channel region and includes a gate dielectric interposed between the gate electrode of the substrate and the channel region.

[0017]

[0028] As used herein, the term “field-effect transistor” or “FET” refers to a transistor that uses an electric field to control the electrical behavior of a device. A field-effect transistor is a voltage-controlled device whose current-transmitting ability changes when an electric field is applied. Field-effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field within the device, which is generated by the voltage difference between the body and the gate of the device. The three terminals of an FET are the source (S) through which carriers enter the channel, the drain (D) through which carriers exit the channel, and the gate (G), which is the terminal that regulates the conductivity of the channel. Traditionally, the current entering the channel from the source (S) is denoted as IS, and the current entering the channel from the drain (D) is denoted as ID. The voltage between the drain and source is called VDS. By applying a voltage to the gate (G), the current entering the channel at the drain (i.e., ID) can be controlled.

[0018]

[0029] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are a type of field-effect transistor (FET) used in integrated circuits and high-speed switching applications. MOSFETs have an insulated gate, and the voltage applied to it determines the device's conductivity. This ability to change conductivity in response to the applied voltage is used to amplify or switch electronic signals. MOSFETs are based on the modulation of charge concentration by metal-oxide-semiconductor (MOS) capacitance between the body electrodes and the gate electrode, which is located above the body and insulated from all other device regions by the gate dielectric layer. Compared to MOS capacitors, MOSFETs include two additional terminals (source and drain), each connected to a separate, highly doped region separated by the body region. These regions can be p-type or n-type, but both are the same type and are the opposite type to the body region. The source and drain (unlike the body) are highly doped, and the doping type is followed by a "+" symbol.

[0019]

[0030] If the MOSFET is an n-channel or nMOSFET, the source and drain are n+ regions, and the body is a p-type substrate region. If the MOSFET is a p-channel or pMOSFET, the source and drain are p+ regions, and the body is an n-type substrate region. The source is so named because it is the source of charge carriers (electrons in the case of an n-channel, and holes in the case of a p-channel) flowing through the channel. Similarly, the drain is where charge carriers exit the channel.

[0020]

[0031] An nMOSFET consists of an n-type source / drain and a p-type substrate. When a voltage is applied to the gate, the holes in the body (p-type substrate) are driven away from the gate. This allows an n-type channel to form between the source and drain, and current is carried by electrons from the source to the drain through the induced n-type channel. Logic gates and other digital devices implemented using NMOS are said to have NMOS logic. NMOS has three operating modes called cutoff, triode, and saturation. Circuits with NMOS logic gates dissipate electrostatic force when the circuit is idling because DC current flows through the logic gate when the output is low.

[0021]

[0032] A pMOSFET consists of a p-type source and drain and an n-type substrate. When a positive voltage is applied between the source and gate (a negative voltage between the gate and source), a p-type channel is formed between the source and drain with opposite polarity. Current is carried through the induced p-type channel and the holes from source to drain. sLogic gates and other digital devices implemented using PMOS are said to have PMOS logic. PMOS technology is low-cost and has good noise immunity.

[0022]

[0033] In NMOS, the carriers are electrons, while in PMOS, the carriers are pores. When a high voltage is applied to the gate, NMOS conducts, but PMOS does not. Furthermore, when a low voltage is applied to the gate, NMOS does not conduct, but PMOS does. Because the electron carriers in NMOS move twice as fast as the pore carriers in PMOS, NMOS is considered faster than PMOS. However, PMOS devices are more resistant to noise than NMOS devices. In addition, NMOS can provide half the impedance offered by PMOS (with the same shape dimensions and operating conditions), so NMOS ICs will be smaller than PMOS ICs (providing the same functionality).

[0023]

[0034] As used herein, the term “Fin-field-effect transistor (FinFET)” refers to a substrate-built MOSFET transistor in which the gate is located on two, three, or four sides of the channel, or wrapped around the channel, forming a double-gate structure. FinFET devices are given the common name FinFET because the source / drain regions form “fins” on the substrate. FinFET devices have fast switching times and high current density.

[0024]

[0035] As used herein, the term “gate all around (GAA)” is used to refer to electronic devices such as transistors in which the gate material completely surrounds the channel region. The channel region of a GAA transistor may include nanowires or nanoslabs or nanosheets, rod-shaped channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device has a plurality of vertically spaced horizontal nanowires or horizontal bars, making the GAA transistor a stacked horizontal gate all around (hGAA) transistor.

[0025]

[0036] As used herein, the term "complementary field-effect transistor (CFET)" refers to a transistor comprising NMOS FET devices and PMOS FET devices stacked together. Each of the NMOS FET devices and PMOS FET devices forming the CFET is a GAA transistor or an hGAA transistor.

[0026]

[0037] As used herein, the term “nanowire” refers to a nanostructure having a diameter in units of nanometers (10⁻⁹ meters). A nanowire may also be defined as having a length-to-width ratio greater than 1000. Alternatively, a nanowire may be defined as a structure whose thickness or diameter is limited to tens of nanometers or less, but whose length is not limited. Nanowires are used in transistors and certain laser applications and, in one or more embodiments, are made of semiconductor materials, metallic materials, insulating materials, superconducting materials, or molecular materials. In one or more embodiments, nanowires are used in logic CPUs, GPUs, MPUs, and transistors for volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term “nanosheet” refers to a two-dimensional nanostructure having a thickness in the range of about 0.1 nm to about 1000 nm, or 0.5 nm to 500 nm, or 0.5 nm to 100 nm, or 1 nm to 500 nm, or 1 nm to 100 nm, or 1 nm to 50 nm.

[0027]

[0038] As used herein, the term “K value,” also known as dielectric constant, expresses the degree to which a material concentrates electric flux. In electronic devices, “K value” refers to the capacitance of a material relative to silicon dioxide. A “high K value” or “high k” dielectric generally refers to a material with a high dielectric constant relative to silicon dioxide, typically greater than about 3.9 and possibly greater than about 7.0. A “low K value” or “low dielectric constant” dielectric generally refers to a material with a low dielectric constant relative to silicon dioxide, typically less than about 3.9 and possibly less than about 3.

[0028]

[0039] As semiconductor device sizes continue to shrink, maintaining device performance requires increasing design complexity. While FinFET structures offer improved short-channel performance compared to previous planar structures, parasitic capacitances from gate-to-source / drain capacitance and gate-to-source / drain contact capacitance are becoming increasingly problematic with decreasing device size. Generally, the effective capacitance (Ceff) within a FinFET is dominated by the gate region and the contact region. Parasitic capacitance degrades device performance and can occur when parallel conductive wires are separated by a dielectric material. For example, in a transistor structure, the source and drain may be connected to a perpendicular conductive material (e.g., a conductive wire), and the gate may also be connected to a perpendicular conductive material (e.g., a conductive wire). These conductive materials may be two metallic wires running parallel to each other and separated by a dielectric material such as an oxide. This structure can cause parasitic capacitance across the dielectric, potentially degrading device performance and increasing power consumption.

[0029]

[0040] Parasitic capacitance depends on the dielectric constant of the intervening material, as well as the spacing between parallel conductive material structures (e.g., conductive wires). As the size of the device features decreases, less dielectric material is placed between the conductive structures, which can increase parasitic capacitance. While it is desirable to use low dielectric constant materials to reduce parasitic capacitance, low dielectric constant materials suffer from undesirable leakage as they become thinner. For this reason, in efforts to enable further miniaturization without increasing undesirable leakage, high dielectric constant materials are used, typically incorporated into substitutional metal gate (RMG) structures, but at the cost of increased parasitic capacitance.

[0030]

[0041] According to one or more embodiments, a semiconductor device and a method for manufacturing it are provided in which device performance, particularly effective capacitance (Ceff), is improved by reducing the effective dielectric constant of one or more material layers forming the semiconductor device. Common dielectric materials include silicon dioxide, which has a dielectric constant of about 3.9. This dielectric constant may not adequately overcome more closely spaced parallel conductive wires. Air is characterized by a dielectric constant of about 1.

[0031]

[0042] According to one or more embodiments, a semiconductor device and a method for manufacturing it are provided in which parasitic capacitance is reduced by reducing the effective dielectric constant of one or more material layers of a substitutional metal gate (RMG) structure between a source region and a drain region. According to one or more embodiments, voids are arranged within or along the RMG stack to reduce parasitic capacitance and thus improve Ceff. According to one or more embodiments, one or more RMG stacks in a FinFET structure include a high dielectric constant dielectric layer arranged along the outer side surface of the RMG stack, the high dielectric constant dielectric layer being selectively etched to form one or more voids within the RMG stack, thereby reducing the effective dielectric constant of the high dielectric constant layer.

[0032] Figures 1A-1J are cross-sectional views of various stages in forming a FinFET device according to one or more embodiments. As shown in Figure 1A, the initial FinFET structure 100 is manufactured with a dummy gate structure 110 formed across the upper surface of a semiconductor stack 113 provided on a substrate 115. Any conventional methods and materials can be used to form the semiconductor stack 113 and the dummy gate structure 110. Furthermore, Figure 1A shows a diagram in which three dummy gate structures 110 are formed on a semiconductor stack 113 having three fin structures 117, but this is only an example. Any number of dummy gates 110 and fin structures 117 may be provided in the embodiment. Furthermore, although the semiconductor stack 113 is shown to have a certain number of layers directly placed on the surface of the substrate 115, any number of layers may be provided and may be placed on the surface of the substrate 115 via one or more intermediate layers (not shown).

[0033]

[0044] As more clearly shown in Figure 1B, the dummy gate structure 110 is generally formed on the top layer 114 (e.g., silicon layer) of the semiconductor stack 113 / fin structure 117 and generally comprises a polysilicon material 111. Although described herein as a polysilicon material, other suitable materials may be used as substitutes when forming the dummy gate structure 110. Spacers 112 extend along the outer sides of the polysilicon material 111. Spacers 112 are formed from a dielectric material and may be formed from high dielectric constant dielectric materials such as HfO2 and Si3N4, or from low dielectric constant dielectric materials such as SiOCN, SiOC, and SiO2. According to one or more embodiments, an oxide layer 119 is further disposed between the top layer 114 and the polysilicon material 111. The oxide layer 119 can be manufactured from any suitable oxide material.

[0034]

[0045] As shown in Figure 1C, a FinFET structure 200 is shown after replacing the dummy gate structure 110 with a replacement metal gate (RMG) structure 210 according to one or more embodiments. Figure 1D shows an enlarged view of the RMG structure 210. Note that while a certain number of layers and types of materials are illustrated and described when forming the RMG structure 210, this is not intended to be limiting. Additional layers can be added and / or one or more of the described layers can be removed according to the manufacturing and design of known RMG structures 210. As shown, according to one or more embodiments, the polysilicon material 111 forming the dummy gate structure 110 is removed by etching or other suitable removal process, leaving a recess between the spacers 112. As shown in Figure 1D, the oxide layer 119 is also removed, or in some embodiments, the oxide layer 119 may remain. In the embodiments shown in Figures 1C to 1D, after the oxide layer 119 is removed, the gate oxide layer 121 is deposited on the top layer 114 (e.g., silicon layer) of the semiconductor stack 113 / fin structure 117. According to one or more embodiments, the gate oxide layer 121 includes one or more of silicon dioxide (SiO2), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), and silicon oxycarbide (SiOC). A high dielectric constant dielectric layer 116 is deposited on top of the gate oxide layer 121 and extends along the inner surface of the spacer 112 (as shown in the figure 1D). According to one or more embodiments, the high dielectric constant dielectric layer 116 has a dielectric constant greater than about 10. In some embodiments, the high dielectric constant dielectric layer 116 includes a metal oxide, which may include one or more of hafnium oxide, zirconium oxide, aluminum oxide, their nitrides, and combinations thereof. According to one or more embodiments, one or more work function metals (WFMs) 120 are stacked within an RMG structure 210. The work function metals 120 can advantageously be incorporated to adjust the threshold voltage (Vt) and may include, for example, one or more of TiN, TiAlC, and TaN. A gate metal filler 118 is then deposited to form the RMG structure 210 in the recess left by the dummy gate polysilicon material 111.

[0035]

[0046] According to one embodiment, after formation, the RMG structure 210 undergoes chemical mechanical planarization (CMP) to create a recess to form a vertical cavity 124, for example, as shown in Figures 1E to 1F. According to one or more embodiments, during the CMP and recess formation of the RMG structure 210, the high dielectric constant dielectric layer 116 remains in a predetermined position extending along the inner side surface of the spacer 112 (most commonly seen in the figure shown in Figure 1F).

[0036]

[0047] According to one or more embodiments, the high dielectric constant dielectric layer 116 is selectively removed to expose the inner surface of the spacer 112 and to form an opening 126 between the concave RMG structure 210 and the spacer 112. The resulting structure is shown in Figures 1G to 1H. According to the embodiments, the removal of the high dielectric constant dielectric layer 116 can be controlled to a desired depth based on the specifications and needs of the device.

[0037]

[0048] As shown in Figures 1A to 1J, the gate cap material 128 is deposited in a cavity 124 perpendicular to the surface of the concave RMG structure 210 without entering the opening 126, pinching off or blocking the opening 126 and forming a void 130. By forming a void 130 in the recessed region of the high dielectric constant dielectric layer 116, air (with a dielectric constant of 1) is incorporated into the removed portion of the high dielectric constant dielectric material layer, improving the Ceff of the semiconductor device and thereby reducing the effective dielectric constant.

[0038]

[0049] Figure 2 shows a diagram of a fin / gate structure with various capacitance components labeled. C-mol relates to the capacitance due to the spacer 112 structure and contact with the source / drain of the transistor. This component can generally be improved by using low dielectric constant materials and thicker spacers. C-do relates to the capacitance due to the direct overlap between the gate and the substrate, and can generally be improved by using low dielectric constant materials and thicker spacers. C-epi relates to the capacitance due to gate-EPI, and can generally be improved by using low dielectric constant materials and thicker spacers. C-Ox is the capacitance due to the channel gate dielectric, and can generally be improved by reducing the effective oxide film thickness (EOT). Through specific designs, these capacitance components can be improved to have a positive impact on Ceff.

[0039]

[0050] According to one or more embodiments, at least a portion of the high-dielectric-constant dielectric layer 116 is removed and pinched off while remaining closed, forming a void 130. Figure 3 graphically shows the effect of various capacitance components on Ceff when the high-dielectric-constant dielectric layer 116 is receded to different levels and replaced with a void, according to one or more embodiments. The first reference "Ref" bar shows the Ceff and individual capacitance components for a structure in which the high-dielectric-constant dielectric layer 116 is not removed and no void 130 is provided. The exemplary reference structure "Ref" shows a total height of 25 nm of the high-dielectric-constant dielectric layer 116 extending from the bottom to the top of the gate, with 0 nm removed. Next, 7 nm of the high-dielectric-constant dielectric layer 116 is removed, resulting in a 1% reduction in the effect on Ceff. Removal of 12 nm of the high-dielectric-constant dielectric layer 116 reduces the effect on Ceff by 2%. Removal of 17 nm of the high-dielectric-constant dielectric layer 116 reduces the effect on Ceff by 4%. Removing 24 nm of the high dielectric constant dielectric layer 116 reduces the impact on Ceff by 7%. As demonstrated, the benefits of removing the high dielectric constant dielectric layer 116 become significant when the removal depth reaches the recessed RMG structure 210 (e.g., removal of 17 nm and 24 nm). Furthermore, as demonstrated, C-Ox has the greatest impact on Ceff, followed by C-Epi, C-do, and C-Mol.

[0040]

[0051] The effective capacitance (Ceff) within the chip is governed by the relationship between the gate region and the contact region. Embodiments are provided in which a high dielectric constant layer, positioned on the sidewall of the RMG, is recessed, sandwiched, or closed to form a void. This method provides a simplified one-step process that effectively simplifies the device manufacturing flow and minimizes Ceff reduction. The device structure is further compatible with existing downstream processes. By forming a void within the RMG region, the capacitance reduction between the gate contact (C-Mol), channel gate dielectric (C-Ox), and gate EPI (C-Epi) components of the total effective capacitance (Ceff) can be maximized.

[0041]

[0052] Spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used here to describe the relationship between one element or feature shown in the drawing and another, for the sake of clarity. It will be understood that spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the drawing. For example, if the device in the drawing is upside down, an element described as “below” or “directly below” another element or feature will therefore be oriented “above” the other element or feature. Thus, the exemplary term “below” may encompass both up and down orientations. The device may be oriented in ways other than those described (it may be rotated 90 degrees or rotated to other orientations), and the spatially relative descriptions used herein shall be interpreted accordingly.

[0042]

[0053] In the context of describing the materials and methods discussed herein (in particular in the context of the following claims), the use of “a” and “an,” “the,” and similar referents should be interpreted as encompassing both singular and plural, unless otherwise indicated herein or unless clearly contradicted by the context. The enumeration of ranges of values ​​herein is merely intended to serve as a shorthand notation for referring individually to each individual value within the range, unless otherwise indicated herein, and each individual value is incorporated into the specification as if it were individually stated herein. All methods described herein may be performed in any appropriate order, unless otherwise indicated herein or unless clearly contradicted by the context. Any and all examples or illustrative language provided herein (e.g., “such as”) is merely intended to better describe the materials and methods and does not impose any limitation of scope unless specifically asserted otherwise. Nothing in this specification should be interpreted as indicating any unclaimed element essential to the practice of the disclosed materials and methods.

[0043]

[0054] Throughout this Specification, any reference to “one embodiment,” “a particular embodiment,” “one or more embodiments,” or “embodiment” means that any particular feature, structure, material, or property described in relation to an embodiment is included in at least one embodiment of this Disclosure. Therefore, any other occurrences of the phrases “in one or more embodiments,” “in a particular embodiment,” “in one embodiment,” or “in an embodiment” throughout this Specification do not necessarily refer to the same embodiment of this Disclosure. In one or more embodiments, the particular feature, structure, material, or property is combined in any suitable manner.

Claims

1. It is a semiconductor structure, A semiconductor stack arranged on a substrate, A metal gate structure disposed on the upper surface of the semiconductor stack, having a bottom surface, an upper surface, and side surfaces, A high dielectric constant dielectric layer disposed on the bottom of the side surface of the metal gate structure between the bottom surface of the metal gate structure and the top surface of the semiconductor stack, A spacer layer extending along the side surface of the metal gate structure, (a) A high dielectric constant dielectric layer disposed between the spacer layer at the bottom of the side surface of the metal gate structure and the metal gate structure, and (b) A gap between the spacer layer and the metal gate structure, above the bottom of the side surface of the metal gate structure, which reduces the effective dielectric constant between the side surface of the metal gate structure and the spacer layer. A spacer layer is separated from the side surface of the metal gate structure by the above, A gate cap material disposed on the upper surface of the metal gate structure, wherein the gate cap material extends above the void but does not extend into the void. A semiconductor structure comprising the features described above.

2. The semiconductor structure according to claim 1, wherein the high dielectric constant dielectric layer has a dielectric constant greater than about 10.

3. The semiconductor structure according to claim 1, wherein the high dielectric constant dielectric layer includes a metal oxide.

4. The semiconductor structure according to claim 3, wherein the high dielectric constant dielectric layer comprises one or more of hafnium oxide, zirconium oxide, aluminum oxide, and nitrides thereof.

5. The semiconductor structure according to claim 1, wherein the spacer includes a dielectric material.

6. The semiconductor structure according to claim 5, wherein the spacer includes a high dielectric constant dielectric material.

7. The aforementioned spacer is HfO ２ and Si ３ N ４ The semiconductor structure according to claim 6, comprising one or more of the above.

8. The semiconductor structure according to claim 5, wherein the spacer includes a low dielectric constant dielectric material.

9. The spacer is composed of SiOCN, SiOC, and SiO ２ The semiconductor structure according to claim 8, comprising one or more of the above.

10. A substitution metal gate structure for semiconductor devices, wherein the substitution metal gate structure is Gate metal filling and At least one work function metal layer surrounding the bottom and side surfaces of the gate metal filling, A high dielectric constant dielectric layer surrounding the bottom surface and the bottom of the side surface of the gate metal filling, A spacer layer extending along the side surface of the gate metal filling, A gap is disposed between the spacer layer and the at least one work function layer on the high dielectric constant layer, A gate cap material is disposed between the spacer layers and extends above the gap along the upper surface of the gate metal filling. Equipped with, The at least one work function layer is disposed between the high dielectric constant dielectric layer and the gate metal filling, The high dielectric constant dielectric layer is positioned between the spacer layer and the at least one work function layer at the bottom of the side surface of the gate metal filling. Replacement metal gate structure.

11. The substitution metal gate structure according to claim 10, wherein the high dielectric constant dielectric layer has a dielectric constant greater than about 10.

12. The substituted metal gate structure according to claim 10, wherein the high dielectric constant dielectric layer contains a metal oxide.

13. The substitution metal gate structure according to claim 12, wherein the high dielectric constant dielectric layer comprises one or more of hafnium oxide, zirconium oxide, aluminum oxide, and nitrides thereof.

14. The substitution metal gate structure according to claim 10, wherein the spacer includes a dielectric material.

15. The substitution metal gate structure according to claim 14, wherein the spacer includes a high dielectric constant dielectric material.

16. The aforementioned spacer is HfO ２ and Si ３ N ４ The replacement metal gate structure according to claim 15, comprising one or more of the following.

17. The substitution metal gate structure according to claim 14, wherein the spacer comprises a low dielectric constant dielectric material.

18. The spacer is composed of SiOCN, SiOC, and SiO ２ The replacement metal gate structure according to claim 17, comprising one or more of the above.

19. A method for forming a semiconductor structure, the method is To provide a semiconductor stack on a substrate surface, the semiconductor stack comprising a gate structure on the upper surface of the semiconductor stack, a spacer structure extending along the outer side surface of the gate structure, and a high dielectric constant dielectric layer disposed between the spacer structure and the gate structure, In order to provide an opening between the spacer structure and the gate structure, at least a portion of the high dielectric constant dielectric layer is selectively removed, The gate cap material is deposited on the upper surface of the gate structure to seal the opening, and a gap is formed between the spacer structure and the gate structure. A method comprising the above, wherein the void reduces the effective dielectric constant in the high dielectric constant dielectric layer and improves the effective capacitance of the semiconductor structure.

20. The method according to claim 19, wherein at least a portion of the high dielectric constant dielectric layer is located between the upper surface of the gate structure and the depth along the outer side surface of the gate structure, and the gate cap material extends over the opening along the upper surface of the gate cap structure.

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