Gate All Around 4F2 DRAM

Abstract

A vertical-cell dynamic random-access memory (DRAM) array and a method for forming an array with improved stability and word line resistance are provided. The array includes a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The array includes a plurality of channels extending vertically substantially orthogonal to the first and second horizontal directions such that the plurality of bit lines intersect the source / drain regions of the plurality of channels. In addition, the array includes a bridge extending between a first channel of the plurality of channels and a second channel of the plurality of channels, the first channel being separated from the second channel in a column extending in the second horizontal direction. The array includes gates formed around at least some of the plurality of channels and bridges.

Description

[Technical Field]

[0001] Cross-reference of related applications

[0001] This application is for "GATE ALL AROUND 4F" filed on September 5, 2023. 2 We claim the interests and priority of U.S. Patent Application No. 63 / 580,562 entitled “DRAM”, which is incorporated herein by reference in its entirety.

[0002]

[0002] This disclosure generally refers to 4F 2 This disclosure describes the design of a two-dimensional dynamic random access memory array. More specifically, this disclosure describes a gate-all-around ("GAA") 4F with improved gate control, word line resistance, and structural stability. 2 Let's discuss memory arrays. [Background technology]

[0003]

[0003] Advances in computing technology have made computing devices smaller and increased their processing power. Therefore, it is necessary to increase storage and memory to meet the programming and computing needs of the devices. By increasing the number of storage units with smaller form factors, miniaturization of devices with increased storage capacity can be achieved.

[0004]

[0004] Dynamic Random Access Memory (DRAM) architectures have been shrinking over time. For example, a one-transistor, one-capacitor (1T-1C) DRAM cell architecture is 8F 2 Sizes up to 6F 2 We successfully reduced the size to 6F (where F is the minimum feature size). 2 From 4th floor 2Further changes to the design scheme can contribute to further improvement of the area density. The manufacture of DRAM cells includes the manufacture of transistors, capacitors, and three contacts (one each for the bit line, word line, and reference voltage). In order to include more memory in a single memory chip, it is continuously desired to reduce the size of individual cells and increase the density of memory cells. However, further increases in density have proven to be problematic.

[0005]

[0005] In addition, 4F 2 In the DRAM method, the storage node (capacitor) and the bit line are located at the top and bottom of the vertical cell transistor, keeping the channel completely separated from the body. With this configuration, due to the body connection of the channel, the floating body effect that does not pose a problem in the current 8F 2 or 6F 2 DRAM cell architecture becomes a major technical issue for 4F 2 DRAM. Therefore, improvement in the art is needed.

Summary of the Invention

[0006]

[0006] The present technology generally relates to a dynamic random access memory (DRAM) array of vertical cells and a method of forming such an array. The array includes a plurality of bit lines arranged in a first horizontal direction, a plurality of channels extending in a vertical direction, a bridge extending between a first channel and a second channel among the plurality of channels, and a gate extending in a second horizontal direction. The array includes that the vertical direction is generally orthogonal to the first horizontal direction such that the plurality of bit lines intersect the source / drain regions of the plurality of channels. The array includes that the first channel is separated from the second channel in a column extending in the second horizontal direction. The array includes that the gate is formed around at least a part of the plurality of channels and the bridge.

[0007]

[0007] In embodiments, the array includes gates extending between the first channel and the second channel at positions above the bridge, below the bridge, and / or both above and below the bridge. In embodiments, the gates have a thickness of about 8 nm or less. In more embodiments, the gates have a thickness of less than 50% of the gap width between the first channel and the second channel. Furthermore, in embodiments, the bridges are formed from a dielectric material. Additionally or alternatively, in embodiments, the bridges are formed from a substrate material. In yet another embodiment, the bridges are formed from a p-doped substrate material. In further embodiments, the array includes at least a third channel among a plurality of channels spaced apart from the second channel in a second horizontally extending column, and the second bridge extends between the second channel and the third channel. In embodiments, the gates extend around the second bridge. Furthermore, in the embodiment, the first channel and the second channel define the channel height between the first source / drain region of each channel and the top surface of each channel, and the bridge is positioned between the first channel and the second channel at a height of approximately 20% to approximately 80% of the channel height.

[0008]

[0008] The technology generally covers arrays having a plurality of bit lines arranged in a first horizontal direction, a plurality of word lines arranged in a second horizontal direction, a first plurality of separated channels in a first column extending in a second horizontal direction, a second plurality of separated channels in a second column extending in a second horizontal direction separated from the first column, a plurality of bridges extending between adjacent channels in the first column and between adjacent channels in the second column, and one or more gates. The array includes one or more gates extending around a first plurality of separated channels and a plurality of bridges in the first column, a second plurality of separated channels and a plurality of bridges in the second column, or both a first plurality of separated channels and a plurality of bridges in the first column and a second plurality of separated channels and a plurality of bridges in the second column. The array includes each channel extending in a vertical direction that is substantially orthogonal to a first horizontal direction and a second horizontal direction, such that multiple bit lines intersect with the source / drain regions of multiple channels.

[0009]

[0009] In the embodiments, one or more gates extend between adjacent channels of the first and / or second rows at positions above the bridge, below the bridge, and / or both above and below the bridge. In more embodiments, one or more gates have a thickness of less than 50% of the gap width between adjacent channels of the first and / or second rows.

[0010]

[0010] The technology generally also covers methods for forming arrays. The method includes etching a substrate to form one or more shallow trench isolation structures (STIs) extending in a first horizontal direction and a plurality of vertically extending walls having a first source / drain region at the second end of the vertically extending wall. The method includes forming a dielectric material in one or more STIs and recessing the dielectric material within one or more STIs to a first depth. The method includes forming a bridge within one or more STIs that contacts a first sidewall of a first wall and a second sidewall of a second wall among the plurality of vertically extending walls. The method includes depositing a mask on the first end of the vertically extending wall and etching one or more second trenches extending in a second horizontal direction to form at least a first channel and a second channel. The method includes depositing gate material around the first channel, the second channel, and the bridge.

[0011]

[0011] In some embodiments, the gate material is deposited to a thickness of less than 50% of the width of one or more of the second trenches. In more embodiments, the gate material is deposited until the gate material deposited around the first channel and the gate material deposited around the second channel fuse within their respective STIs. Furthermore, in some embodiments, the method includes removing at least a portion of the gate material in one or more of the second trenches. Additionally or alternatively, in some embodiments, the method includes maintaining a mask while etching one or more of the second trenches and during the deposition of the gate material. In some embodiments, the method includes recessing the bridge from a first height to a second height lower than the first height before depositing the gate material. In even more embodiments, the method includes forming a protective liner in one or more of the STIs after recessing the dielectric material to a first depth, and recessing the dielectric material to a second depth in the one or more STIs lower than the first depth.

[0012]

[0012] Such a technique can provide a number of advantages over conventional systems and techniques. For example, the process and system can provide a GAA4F 2 DRAM device, particularly a GAA4F 2 DRAM device with reduced floating body effect. In addition, the processes and systems of the present document enable an improvement in resistance, such as a reduction in word line resistance. Further, the processes and systems of the present document can provide an improvement in stability in a GAA 4F 2 DRAM device. These embodiments and other embodiments are described in more detail below in the description and the accompanying drawings, along with many of their advantages and features.

[0013]

[0013] The nature and advantages of the disclosed technology can be further understood by reference to the remainder of this specification and the drawings.

Brief Description of the Drawings

[0014] [Figure 1A] Shows a top view of an exemplary processing chamber according to an embodiment of the present technology. [Figure 1B] Shows a top view of a conventional 4F2 memory array. [Figure 1C] Is a perspective view of a conventional 4F2 memory array. [Figure 2] Shows selected steps in a forming method according to an embodiment of the present technology. [Figure 3A] Shows a perspective view of a semiconductor structure according to an embodiment of the present technology having dielectric material filling after first STI formation. [Figure 3B] Shows a perspective view of a semiconductor structure according to an embodiment of the present technology having recessed dielectric material. [Figure 3C] Shows a perspective view of a semiconductor structure according to an embodiment of the present technology having a protective liner. [Figure 3D] Shows a perspective view of a semiconductor structure according to an embodiment of the present technology with the bottom of the protective liner removed. [Figure 3E] Shows a perspective view of a semiconductor structure according to an embodiment of the present technology with the dielectric material etched back. [Figure 3F] This shows a perspective view of a semiconductor structure according to an embodiment of this technology, with the exposed substrate cleaned. [Figure 3G] A perspective view of a semiconductor structure according to an embodiment of this technology is shown, in which a bridge is formed between adjacent channels. [Figure 3H] A perspective view of a semiconductor structure according to an embodiment of this technology is shown, where the bridge is recessed. [Figure 3I] A perspective view of a semiconductor structure according to an embodiment of this technology having a filler on a bridge is shown. [Figure 3J] This shows a perspective view of a semiconductor structure etched in the word line direction and with the filler removed, according to an embodiment of this technology. [Figure 3K] A perspective view of a semiconductor structure according to an embodiment of this technology in which gate metal has been deposited is shown. [Figure 3L] The bottom is open and optionally cropped, showing a perspective view of a semiconductor structure according to an embodiment of this technology. [Figure 3M] A perspective view of the semiconductor structure according to an embodiment of this technology is shown. [Figure 4A] A perspective view of the semiconductor structure according to an embodiment of this technology is shown. [Figure 4B] A perspective view of the semiconductor structure according to an embodiment of this technology is shown. [Modes for carrying out the invention]

[0015]

[0033] Some drawings are included as schematic diagrams. These diagrams are for illustrative purposes only and should not be considered to scale unless explicitly stated otherwise. Furthermore, as schematic diagrams, they are provided to aid understanding and may not include all aspects or information compared to realistic depictions, and may include exaggerated material for illustrative purposes.

[0016]

[0034] In the attached drawings, similar components and / or features may have the same reference numeral. Furthermore, various components of the same type may be distinguished according to their reference numerals by letters that distinguish between similar components. Where only a first reference numeral is used in this specification, its description is applicable to any of the similar components having the same first reference numeral, regardless of the letters used.

[0017]

[0035] Historically, DRAM chip bit density increased by approximately 25% per node. However, the increase in bit density between nodes has decreased to nearly 20% in more recent generations, mainly due to the challenges associated with scaling the cell area. The cell design architecture for the latest DRAM technology is 6F 2 Based on shape dimensions, "F" is the minimum feature size of a given technology node. 6F 2 From 4th floor 2 Switching to a cell architecture could result in a 33% increase in bit density at the same technology node. Furthermore, the patterning difficulty of 4F2DRAM is 6F 2 This is significantly reduced compared to the previous method. This is because, at least in part, in the 4F2DRAM method, the capacitor and bit lines are 6F 2 This is due to the fact that they are located at the two ends of the vertical cell transistors, rather than being tightly packed on the same side as the DRAM.

[0018]

[0036] However, 4F 2 DRAM design has its own challenges. For example, 4F 2 In memory cells, transistor channels are placed between the bit lines and the capacitor layer, and there is no common substrate remaining to connect the channels, resulting in a floating body effect in these transistors. For example, conventional 4F 2 DRAM devices are thought to exhibit off-leak current problems. Off-leak current is caused by floating-body effects (e.g., 4F due to isolated channels). 2This is due to the accumulation of holes in the body of the DRAM device. For example, electron-hole pairs can be formed within the semiconductor channel by band-to-band tunneling. Electrons can flow into the n-type source or drain region of the transistor, but holes cannot. 4F without substrate connection 2 In DRAM devices, holes have no path to leave the channel and continue to accumulate. Therefore, the floating body effect leads to channel activation without gate activation, ultimately converting into a capacitor or leakage current from the data storage side of the device. Attempts have been made to provide body connections using embedded contact schemes. However, such attempts can result in gate overlap at the source / drain junction edge, potentially leading to undesirable gate-induced drain leakage or limiting scalability to small dimensions. Furthermore, such design schemes also allow for the fabrication of high aspect ratio structures that challenge existing doping techniques.

[0019]

[0037] In addition, GAA 4F 2 DRAM devices have proven to present further challenges. For example, 4F 2 As DRAM devices continue to shrink in feature size and pitch, forming proper gate connections has proven problematic. Specifically, the reduced gap between adjacent word lines leads to fusion between adjacent word lines before or during the fusion of gate material between adjacent channels in the word line direction. Such defects cause electrical defects such as short circuits. Attempts to avoid such defects have included depositing less gate material. However, such attempts can result in high resistivity, at least partially due to insufficient merging between adjacent channels. Furthermore, attempts have been made to trim excess gate material from word line trenches. However, trimming requires sufficient distance between adjacent word lines within each trench and has proven insufficient for increasingly large devices.

[0020]

[0038] Furthermore, GAA 4F 2 DRAM devices also exhibit low structural stability during formation. Other 4F 2 Unlike DRAM devices, oxides are removed before gate formation, leaving each channel with little or no support during word line formation. This low stability can lead to device mismatches and defects, resulting in poor electrical properties.

[0021]

[0039] This technology overcomes these and other problems by connecting two or more channels of transistors arranged perpendicularly to each row of cells to a bridge outside the source / drain region of the transistor. That is, the bridge between channels along the gate, or in the word line direction, provides a support that can also be used as a platform for depositing one or more gate materials. Such a support reduces the required thickness of the gate material because a robust connection can be formed with or without complete merging between adjacent channels. In addition, surprisingly, such a support has been found to improve word line resistance because it allows for a consistent and controlled gate thickness throughout the support and therefore between adjacent channels in the word line direction. Furthermore, such a support also improves word line resistance (and consequently, subsequent 4F 2 This enables a significant improvement in structural stability during feature formation, resulting in improved consistency and reduced defects in the resulting device. Furthermore, in some embodiments, such as supports, a path for hole movement between channels can be provided when the gate is off, reducing the impact of the floating body effect on defective channels. Therefore, this technology is also 4F 2 This can reduce the floating body effect without interrupting the size or connectivity of the DRAM device.

[0022]

[0040] The remaining disclosures include GAA 4F 2While this disclosure routinely identifies specific deposition and etching processes used to form vertical cell dynamic random access memory (DRAM) arrays such as DRAM devices, it will be readily apparent that the systems and methods are equally applicable to other DRAM devices, other GAA devices, other devices with floating-body effects or poor stability, and processes for forming such device processes. Therefore, this technology should not be considered limited to use in these specific devices or systems only. Before describing additional modifications and adjustments to this device according to embodiments of this technology, this disclosure describes one possible semiconductor device that may include one or more components utilizing one or more bridges according to embodiments of this technology.

[0023]

[0041] Figure 1A shows a top view of a multi-chamber processing system 100, which may be specifically configured to implement aspects or operations according to several embodiments of the present technology. The multi-chamber processing system 100 may be configured to perform one or more manufacturing processes on individual substrates, such as any number of semiconductor substrates, in order to form semiconductor devices. The multi-chamber processing system 100 may include some or all of a transfer chamber 106, a buffer chamber 108, single wafer load locks 110 and 112 (dual load locks may also be included), processing chambers 114, 116, 118, 120, 122, and 124, preheating chambers 123 and 125, and robots 126 and 128. The single wafer load locks 110 and 112 may include a heating element 113 and may be mounted on the buffer chamber 108. The processing chambers 114, 116, 118, and 120 may be mounted on the transfer chamber 106. The processing chambers 122 and 124 may be mounted on the buffer chamber 108. Two substrate transfer platforms 102 and 104 may be positioned between the transfer chamber 106 and the buffer chamber 108 to facilitate transfer between robots 126 and 128. Platforms 102 and 104 may be open to the transfer chamber and the buffer chamber, or they may be selectively isolated or sealed from the chambers so that varying operating pressures are maintained between the transfer chamber 106 and the buffer chamber 108. Transfer platforms 102 and 104 may each include one or more tools 105 for orientation or measurement processes, etc.

[0024]

[0042] The operation of the multi-chamber processing system 100 may be controlled by a computer system 130. The computer system 130 may include any device or combination of devices configured to implement the operations described below. Thus, the computer system 130 may be a general-purpose computer comprising a controller or an array of controllers and / or software stored on a non-temporary computer-readable medium that, when executed, can perform the steps described in relation to the methods according to embodiments of this art. Each of the processing chambers 114, 116, 118, 120, 122, and 124 may be configured to perform one or more processing steps in the manufacture of a semiconductor structure. More specifically, the processing chambers 114, 116, 118, 120, 122, and 124 may be equipped to perform a number of substrate processing steps, including, among any number of other substrate processes, dry etching, periodic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, degassing, and orientation.

[0025]

[0043] Figures 1B and 1C show the conventional 4F 2 A top view and a perspective view of the memory array 150 are shown. The memory array 150 may include a plurality of word lines 152 arranged in a first layer on a substrate. The word lines 152 may be conductive traces used to select the word lines of memory cells in the memory array 150. The memory array 150 may further include a plurality of bit lines 154 arranged in a second layer on a substrate. The plurality of bit lines may be conductive traces used to select the bit lines of memory cells in the memory array 150. Individual cells in the memory array 150 can be selected by activating one of the plurality of bit lines 154 and one of the plurality of word lines 152. The first and second layers may include different metal layers formed at different times during the manufacturing process. For example, the first layer having the word lines 152 may be formed on top of the second layer having the bit lines 154 such that the two layers do not intersect.

[0026]

[0044] Multiple vertical memory cells may be arranged on the intersections between multiple word lines 152 and multiple bit lines 154. Each of the multiple vertical memory cells may include a vertical transistor 170, which may be referred to as a vertical pillar transistor or vertical column transistor. The channel material for the transistor may be formed from a single-crystal silicon pillar or any other substrate as described in more detail below. This silicon channel may be formed by etching the substrate. Each of the multiple vertical memory cells may also include a vertical capacitor 156. The vertical memory cell may operate by storing charge in the vertical capacitor 156 to indicate a stored memory state. However, please understand that Figures 1B and 1C show the arrangement of the vertical transistor 170 and capacitor in a rectangular, roughly orthogonal grid pattern (where roughly orthogonal means within about 10° of orthogonal, e.g., less than or equal to about 7.5°, e.g., less than or equal to about 5°, e.g., less than or equal to about 2.5° of orthogonal, e.g., less than or equal to about 1°, or any range or value in between), which is intended for use in this technology. For example, in one embodiment, capacitors and vertical transistors may be spaced in alternating rows offset by half the distance between vertical transistors. That is, in one embodiment, the first row of memory cells may be regularly spaced in a row in a first direction, and the second row of memory cells may also be regularly spaced in a row in a first direction, but the second row of memory cells may be offset from the first row of memory cells, for example, to be positioned approximately midway between the vertical transistors and capacitors of the first row. Such a pattern is sometimes referred to as a "honeycomb" or "hexagonal pattern" in comparison to the square pattern shown in Figures 1B and 1C. Therefore, it should be understood that any suitable orientation can be used in this technology.

[0027]

[0045] This conventional 4F 2It is useful to characterize the dimensions of the unit cell region 166 of the memory array for comparison with a simple memory array described later. For example, the capacitor footprint 158 ​​can be defined as the circular region around each vertical capacitor 156. The capacitor footprint 158 ​​may include the horizontal cross-sectional area of ​​the capacitor, which expands until its cross-sectional area contacts the capacitor region from an adjacent memory cell. Assume that the word line pitch 162 for multiple word lines 152 and the bit line pitch 164 for multiple bit lines 154 can be defined as 2F. This gives the overall cross-sectional area of ​​the unit cell region 166 to be 4F. 2 It will become.

[0028]

[0046] Figure 2 shows exemplary operation of Method 200 according to several embodiments of the present technology. This method can be carried out in various processing chambers, including the processing chamber 100 described above. Method 200 may include a number of arbitrary operations, some of which may or may not be particularly relevant to certain embodiments of the method relating to the present technology. For example, many operations are described to provide a wider range of structural forms, but may not be important to the present technology or may be carried out by alternative methods that are easily understood. In addition, while the method may describe a forming method in a perpendicular direction from the word line side of the structure to the bit line side of the structure, it should be understood that other orientations from the bit line side to the word line side may be utilized.

[0029]

[0047] Method 200 may include additional steps before commencing the enumerated steps. For example, additional processing operations may include forming a structure on a semiconductor substrate, which may include both forming and removing material. The pre-processing steps may be performed in the chamber in which Method 200 may be performed, or the processing may be performed in one or more other processing chambers before the substrate is brought into the semiconductor processing chamber in which Method 200 may be performed. In any case, Method 200 may optionally include delivering the semiconductor substrate to a processing area of ​​a semiconductor processing chamber, such as the processing chamber 100 described above, or to a processing area of ​​another chamber, which may include the components described above. The substrate may be a pedestal, such as a substrate support 104, and may be deposited on a substrate support / transfer platform that may be present in a processing area of ​​a chamber, such as the processing area of ​​the processing chamber 120 described above. Method 200 describes the steps schematically shown in Figures 3A to 3M, which are described in conjunction with the steps of Method 200. Figures 3A to 3M show only partial schematic diagrams, and it should be understood that the semiconductor substrate may include further components shown in the figures, as well as alternative components of any size or configuration from which the embodiments of this technology can still be beneficial.

[0030]

[0048] Method 200 may or may not include optional steps for developing the semiconductor structure into a specific manufacturing process. It should be understood that Method 200 can be performed on any number of semiconductor structures 300 or substrates 302, as shown in Figures 3A to 3M, including exemplary structures on which selectively deposited material can be formed. As shown in Figure 3A, the substrate 302 may be any number of materials, for example, a base wafer or substrate made from silicon or a silicon-containing material, germanium, other substrate materials, and one or more materials that can be formed on the substrate during semiconductor processing.

[0031]

[0049] In embodiments, the structure 300 may be a semiconductor substrate including a bulk substrate, an epitaxially grown substrate, and / or silicon on an insulating wafer. As used herein, the term “semiconductor substrate” refers to a substrate whose entirety is made of semiconductor material. The semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, the semiconductor layer may be crystalline silicon (e.g., Si <100> or Si <111> The semiconductor material may include one or more materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 300 includes a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 302 includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). While some examples of materials that can form substrates are described herein, any material that can serve as a basis for constructing passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) is included in the spirit and scope of this disclosure.

[0032]

[0050] In embodiments, the semiconductor material may be a doped material such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In embodiments, the substrate may be doped using any suitable process, such as an ion implantation process. As used herein, the term “n-type” refers to a semiconductor produced by doping an intrinsic semiconductor with an electron-donating element during manufacturing. The term n-type derives from the negative charge of electrons. In n-type semiconductors, electrons are majority carriers and holes are minority carriers. As used herein, the term “p-type” refers to the positive charge of wells (or holes). In contrast to n-type semiconductors, p-type semiconductors have a hole concentration greater than the electron concentration. In p-type semiconductors, holes are majority carriers and electrons are minority carriers.

[0033]

[0051] As shown in Figure 3A, a structure 300 is provided which includes a substrate 302 on which a first dielectric material 306 has already been formed, with source / drain regions 304 and STI 308 formed, and which fills the STI 308. In addition, two or more silicon walls 305 are formed between each STI 308, and the illustrated walls 305 are spaced apart in columns extending horizontally parallel to the word line direction in this embodiment. In embodiments, the formation of the source / drain regions 304 may include one or more ion implantation and subsequent annealing processes. The implantation process may be a single implantation or may include a series of multiple implantations. If multiple implantations are utilized, each implantation may utilize the same or different ions. However, it should be understood that the source / drain regions 304 may be formed from any suitable process, including after the formation of the front device, as will be described later. The method may include providing a semiconductor structure having first source / drain regions 304 for multiple vertical channels and forming multiple word lines in contact with the first source / drain regions. Overall, this process allows each stage of the transistor to be gradually formed on top of the previously completed stage.

[0034]

[0052] Furthermore, although various deposition and filling processes are described, in embodiments, the semiconductor structure may be transferred to or between one or more processing chambers 114, 116, 118, 120, 122, and 124 configured for deposition and / or filling processes, including chambers for chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal chemical vapor deposition (CVD), plasma chemical vapor deposition (PECVD), and plasma-enhanced atomic layer deposition (PEALD). Thus, unless otherwise specified, it should be understood that any one or more of the above methods known in the art may be used. Similarly, the semiconductor structure may be transferred to one or more processing chambers 114, 116, 118, 120, 122, and 124 configured for etching, for example, one or more of inductively coupled plasma (ICP) etching, reactive ion etching (RIE), capacitively coupled plasma (CCP) etching, and other etching processes known in the art.

[0035]

[0053] Nevertheless, in step 201, method 200 may include indenting the first dielectric material 306 to a first depth in one or more of the STIs 308, as shown in Figure 3B. For example, in an embodiment, the substrate 302 is loaded into load locks 110, 112 and transported via robots 126, 128 to a processing chamber (such as processing chamber 114) where the first dielectric material 306 is indented. It should be understood that the substrate may be transported between each process step, or only a portion of the process steps, because some process steps may be completed within the same processing chamber. In an embodiment, the dielectric material may be indented to approximately the midpoint of each STI 308. However, it should be understood that the first dielectric material 306 may be recessed to about 20% to about 80% of the depth of each STI 308, for example, about 30% to about 70%, for example, about 40% to about 60%, for example, about 45% to about 55%, or any range or value in between. That is, each STI 308 defined between adjacent channels has a first end 307 and a second end 309 that define the trench depth between them. Furthermore, the recess formation step 201 can be carried out by any method known in the art.

[0036]

[0054] As shown in Figure 3C, after the recess formation step 201, in step 202, a protective liner 310 is formed on the recessed first dielectric material 306 and the first sidewall 312 and second sidewall 314 (more clearly shown in Figure 3B) of each STI 308. The protective liner 310 may be formed from any dielectric material having a different etching rate than the first dielectric material 306 known in the art, such as silicon nitride, silicon oxynitride, silicon dioxide, or other similar materials. Additionally or alternatively, in embodiments, the protective liner 310 may be formed from the same material as the first dielectric material 306, but with a thickness to retain at least a portion of the protective liner 310 after the second recess formation step 204. Nevertheless, as shown in Figure 3D, after the formation of the protective liner 310, in step 203, the bottom 316 of the protective liner 310 may be etched off to expose the first dielectric material 306. Such an etching process that selectively removes the bottom surface is called "bottom punching" and is also known as anisotropic etching or directional etching. In embodiments, selective bottom etching or bottom punching can be performed by any etching process known in the art, such as reactive ion etching.

[0037]

[0055] Nevertheless, after etching the bottom of the protective liner 310, step 204 may involve a second recess formation step in the first dielectric material 306. The recess formation step 204 may be selective for the first dielectric material 306 without removing the protective liner 310 from the first sidewall 312 and the second sidewall 314 of the STI 308, or the liner 310 may have sufficient thickness to withstand at least partially the second recess formation step. That is, at least a portion of the protective liner 310 remains on the first sidewall 312 and the second sidewall 314. In any case, the first dielectric material 306 is etched from a first depth to a second depth below the first depth. By etching the first dielectric material 306 to a second depth, exposed portions 322 of the first sidewall 312 and the opposing second sidewall 314 are formed between the first dielectric material 306 at the second depth and the bottom surface 318 of the protective liner 310. In the embodiment, the second depth is a distance less than the first depth to provide a robust contact area for the bridge 320.

[0038]

[0056] Accordingly, in the embodiment, the height difference from the first depth to the second depth, and / or the length of the exposed portion of the first sidewall 312 and the second sidewall 314 may be about 2 nm or more, for example about 4 nm or more, for example about 6 nm or more, for example about 8 nm or more, for example about 10 nm or more, for example about 12 nm or more, for example about 14 nm or more, for example about 16 nm or more, for example about 18 nm or more, for example about 20 nm or more, for example about 50 nm or less, for example about 45 nm or less, for example about 40 nm or less, for example about 35 nm or less, for example about 30 nm, for example about 25 nm or less, or any range or value in between these. That is, in the embodiment, the distance and / or length may be selected so that, when the doped material is used for the bridge 320, the bridge 320 does not affect the overall doping level of the wall 305 (or the individual channels 348 described later), and provides a sufficient contact area for a robust physical and / or electrical connection.

[0039]

[0057] Regardless of the depth to which the dielectric material is etched, step 205 optionally cleans the exposed portions 322 of the first sidewall 312 and the opposing second sidewall 314. The optional cleaning step 205 may include a pre-cleaning step and / or a surface damage removal step. That is, if it is desirable that the bridges improve the hole distribution between channels, each bridge 320 may have a robust electrical connection with each of the adjacent walls 305. However, surface oxidation, damaged silicon from the recess formation step 204, and other contaminants may prevent efficient fusion of the bridges 320 with the first sidewall 312 and / or the second sidewall 314. Therefore, in embodiments, step 205 includes selectively removing surface damage (e.g., if there is damaged silicon during the recess formation step) from the exposed portions 322 of the first sidewall 312 and the second sidewall using an isotropic etching process, as shown in Figure 3F. Isotropic etching processes, such as vapor-phase etching, are available from Applied Materials (Selectra®) to remove doped and undoped silicon while retaining the dielectric material. In embodiments, only one or more layers forming or adjacent to the exposed surface 322 are removed. In embodiments, any existing surface oxides can be removed by pre-cleaning, such as Siconi® cleaning.

[0040]

[0058] However, in embodiments, cleaning may not be necessary. That is, in embodiments, method 200 may be performed entirely within the processing system 100 without removal from the vacuum, thereby limiting the formation of oxides and other surface defects after oxide removal by the recess formation step 204. Additionally or alternatively, there may be no damaged silicon after the recess formation step 204. Furthermore, in embodiments, the bridge 320 may not contribute to the hole distribution (e.g., not formed from material providing electrical connections) and therefore may not require electrical connections to adjacent channels. Thus, in embodiments, both pre-cleaning and surface damage removal steps may be utilized, only one of the pre-cleaning and surface damage removal steps may be utilized, or neither pre-cleaning nor surface damage removal steps may be utilized.

[0041]

[0059] Method 200 further includes, as shown in Figures 3F and 3G, forming a bridge 320 in step 206 between two adjacent walls 305 extending along a single column (for example, the bridge 320 is formed along or parallel to one or more gates, which will be described in more detail below, such as between the first side wall 319 of the first wall 305 and the second side wall 321 of the second wall 305, for example, the exposed portions of the first and second side walls). In embodiments, the bridge 320 can be formed from the same material as the two or more walls 305, or from a different material suitable for forming a bridge between adjacent walls 305, such as any substrate material, dielectric material, or another material that can be deposited between adjacent walls 305 to provide structural support.

[0042]

[0060] However, in embodiments where improving the floating body effect is desirable, the bridge 320 may be formed from a doped material having a higher doping level than the wall 305 adjacent to each bridge 320. That is, by utilizing a higher doping level than the wall 305 adjacent to each bridge, the voltage threshold falls below the activation threshold of the bridge 320, so that when the wall 305 is biased, charge sharing between the walls 305 via the bridge 320 may be minimal or nonexistent. Nevertheless, the doping level should not significantly exceed the doping levels of two or more walls 305, as dopant may diffuse into two or more walls 305, causing the channel threshold to rise above the bias voltage.

[0043]

[0061] Therefore, in the embodiment, each bridge 320 may have a doping level of about 1.6 times or more the doping level of the wall 305 adjacent to each bridge 320, for example, about 1.8 times or more, about 2 times or more, for example, about 2.2 times or more, for example, about 2.4 times or more, for example, about 2.6 times or more, for example, about 2.8 times or more, for example, about 3 times or less, for example, about 5 times or less, for example, about 4.8 times or less, for example, about 4.6 times or less, for example, about 4.4 times or less, for example, about 4.2 times or less, for example, about 4 times or less, for example, about 3.8 times or less, or about 3.6 times, for example, about 3.4 times or less, or any range or value in between thereof.

[0044]

[0062] That is, as described above, when doped material is used, each bridge 320 may have a doping level sufficient to prevent significant charge sharing, for example, a doping level sufficient to provide a Vt exceeding the gate threshold of the wall 305 adjacent to each bridge. Nevertheless, each bridge 320 has a higher level of dopant than the adjacent wall 305, so each bridge 320 can diffuse dopant from the center of each bridge 320 toward and into the adjacent wall 305. Thus, diffusion can form a dopant gradient from the wall 305 toward the center of each bridge 320. Such a phenomenon may cause holes to move from one or more problematic areas of the wall 305 into each bridge 320, and the holes may be distributed throughout the bridge 320 or move entirely along the bridged column between the connected bridges 320 and the wall 305, distributing the holes along a large area and diffusing the effect. However, if the doping level in one or more bridges 320 is too high compared to the adjacent walls 305, dopant diffusion may cause the doping level in one or more walls 305 to rise above the threshold level of the walls 305. Therefore, in embodiments, the doping level of each bridge compared to the adjacent walls 305 is carefully selected. Nevertheless, the technology has surprisingly found that the bridges 320 significantly reduce the floating body effect, such as by reducing the increase in channel potential and reducing leakage current.

[0045]

[0063] Nevertheless, in embodiments, several different materials may be used for one or more bridges 320. For example, one or more bridges may include crystalline semiconductors such as silicon, germanium, silicon-germanium, one or more dielectric materials, and / or other suitable structural support materials. In embodiments, the bridges may be formed from crystalline silicon such as single-crystal silicon, or any one or more of the semiconductor materials described above, a dielectric material, and any other material suitable for deposition between adjacent channels to provide structural support. Nevertheless, these materials may also be used in the form of polycrystalline semiconductors.

[0046]

[0064] In embodiments, one or more bridges 320 may be formed by epitaxially growing a bridge or support material on a first dielectric material 306 recessed with STI 308 and coalescing the epitaxial layers until contact with both the first sidewall 312 and the second sidewall 314 is achieved. Thus, in embodiments, such a process may be called a selective epitaxial deposition process. Alternatively, one or more bridges 320 may be formed by conformally filling the STI 308 with one or more bridge or support material, or by depositing one or more bridge or support material using other deposition methods known in the art. Regardless of the method used, it should be evident that the material used for one or more bridges 320 is deposited or grown in such a way as to provide good contact with the exposed portions 322 of both the first sidewall 312 and the second sidewall 314. However, in the embodiment, one or more bridges 320 may not fuse with or contact the first dielectric material 306 as long as strong contact is formed with the first sidewall 312 and the second sidewall 314.

[0047]

[0065] Nevertheless, in some embodiments, one or more metal oxides, such as aluminum oxide, can be used as bridges 320. In such embodiments, the metal oxide may be physically connected to adjacent channels but not electrically. In this way, holes can still be attracted to the metal oxide even without electrical connections to adjacent channels.

[0048]

[0066] In the embodiment, one or more bridges 320 are formed only on a portion of the STI 308. For example, as shown in Figure 3G, one or more bridges 320 have a height slightly higher than the height of the exposed portion 322 and thus may extend into the protective liner 310. However, in the embodiment, one or more bridges 320 may have a height generally equal to the height of the exposed portion 322. That is, the STI 308 may be completely filled with bridge 320 material on top of the first dielectric material 306, but such an embodiment may allow undesirable high electric fields in the upper regions of the STI 308, such as in the source / drain region, if the protective liner 310 is not formed completely or uniformly.

[0049]

[0067] Nevertheless, in embodiments, step 206 may include a recess-forming step that reduces the height of the bridge 320 from a first height to a second height below the first height, as shown in Figure 3H. In such embodiments, the bridge material may be recessed so as to be generally flush with the bottom surface 318 of the protective liner 310. However, it should be understood that in embodiments, such a recess-forming step may not be necessary. For example, in embodiments, the formation of the original bridge 320 may occur only at approximately the same level as the bottom surface 318. Nevertheless, in embodiments, such recess formation can improve the removal of the protective liner 310, as will be described in more detail below. Thus, recess formation may be performed by any recess-forming method known in the art, if available.

[0050]

[0068] Regardless of whether step 206 includes a recess formation step, in the embodiment, the thickness of one or more bridges 320 (measured from the bridge bottom 324 to the bridge top 326) may be about 2 nm or more, e.g., about 4 nm or more, e.g., about 6 nm or more, e.g., about 8 nm or more, e.g., about 10 nm or more, e.g., about 12 nm or more, e.g., about 14 nm or more, e.g., about 16 nm or more, e.g., about 18 nm or more, e.g., about 20 nm or more, e.g., about 25 nm or more, e.g., about 30 nm or more, e.g., about 70 nm or more, e.g., about 60 nm or less, e.g., 50 nm or less, e.g., about 40 nm or less, e.g., about 35 nm or less, or any range or value in between. That is, in the embodiment, the thickness may be selected to provide a sufficient contact area for a robust connection.

[0051]

[0069] In addition, as described above, in the embodiment, one or more bridges are formed at the approximate center point of two or more walls 305 (and thus STI 308), such as between a first source / drain region and a second source / drain region, or between the source / drain 304 and the top surface 307. That is, by utilizing a bridge located at the approximate center point of two or more walls 305, or any one or more of the trench depths described above, a larger support can be provided, and the word line resistivity and / or hole distribution can be improved. However, it should be understood that in the embodiment, one or more bridges 320 may be utilized between two corresponding walls 305, and neither or one of such bridges 320 may be located at the approximate center point. For example, this includes a first bridge 320 located adjacent to the second source / drain region 304 of the semiconductor structure 300, and a second bridge 320 formed adjacent to the second source / drain region. Nevertheless, regardless of the number of bridges used between two corresponding channels, adjacent channels may have a height extending between the first source / drain region and the second source / drain region, and at least one of the bridges 320 may be formed between adjacent channels at a height of about 20% to about 80%, for example, about 30% to about 70%, about 40% to about 60%, about 45% to about 55%, or any range or value in between.

[0052]

[0070] However, while Figures 3A to 3H illustrate one method of forming the bridge 320, in embodiments where only structural stability is desired, the bridge 320 may be formed by other methods. For example, in embodiments, as shown in Figure 3B, after forming a recess in the first dielectric material 306, the STI 308 may be filled with any one or more of the bridge materials described above, with or without the liner 310. After filling the STI 308 with the bridge 320 material, the bridge material may be recessed to a desired thickness, such as any one or more of the thicknesses described above. Thus, the bridge 320 material may extend over the STI 308 above the first dielectric material 306, as shown in Figure 3H.

[0053]

[0071] Regardless of how the bridge is formed, after the bridge is formed in step 206, the protective liner 310 can be removed, and the remaining portion of the STI 308 on the bridge 320 can be filled in step 207, as shown in Figure 3I. In embodiments, the protective liner 310 can be removed using any method known in the art. For example, in embodiments, the protective liner 310 can be removed by any etching process that does not damage one or more channels 305 and / or bridge 320. Thus, as shown, the second dielectric 332 can come into contact with the adjacent wall 305, as well as the upper surface 326 of the bridge 320.

[0054]

[0072] In embodiments, the second dielectric material 332 may be the same dielectric material as the first dielectric material 306, or it may be a different dielectric material from the one initially filled in STI 308 in Figure 3A. In embodiments, the first and / or second dielectric material 332 may be any one or more dielectric materials known in the Art, such as silicon oxide, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, combinations thereof, or other dielectric materials, formed using any of the filling methods described above. Although silicon oxide or silicon nitride will be discussed periodically as dielectric material and / or spacer material in the following description, any number of dielectric materials may be used in embodiments of the Art, and it should be understood that the Art should not be limited to any specific dielectric material on which features can be formed. Nevertheless, other materials may be used in step 207, as will be described in more detail below.

[0055]

[0073] Following the filling step 207, the semiconductor structure 300 undergoes mask formation and word line trench formation in step 208, after which the dielectric materials 306 and 332 can be removed in step 209. For example, Figure 3J shows etching of walls 305 into channels 348 by etching in a second horizontally extending direction using a mask 340. That is, separation between channels 348 extending parallel to or coplanar with the word lines of this embodiment, formed by the etching process, can be formed using a pattern or mask 340 that defines a second STI 346, as described above, to form STI 308 between walls 305. The resulting channels 348 may have a uniform or non-uniform width and / or a width generally equal to that of the walls 305. The second STI 346 may serve to separate adjacent channels 348.

[0056]

[0074] However, unlike conventional processes in which independent pillars are formed during GAA word line processing, in this embodiment, the mask 340 may be maintained on the channel 348 during the formation of the word line components. In this way, each channel in each column may be connected to adjacent channels by both the bridge 320 and the mask 340, which extend in the word line direction. Thus, the structure 300 according to this technique can have significantly improved structural stability during formation because connections between at least some of the adjacent channels (e.g., adjacent channels along the word line) are maintained by the bridge 320 between the bottom surface 309, the top surface 307, and the source / drain region 304. In this way, even if the dielectric materials 306, 332 are removed for GAA formation, mismatches can be reduced and improved electrical properties can be observed.

[0057]

[0075] Nevertheless, in step 210, refer to Figure 3J, which shows the formation of the third dielectric material 450 along the adjacent wall 305 and the bridge 320 of the first horizontally extending column (for example, such that the third dielectric material 350 is generally parallel to the word line direction). The third dielectric material 350 may be formed from a material such as SiO or other similar material, which may include any one or more of the dielectric materials described above. For example, in embodiments where the channel material is silicon, the third dielectric material may be SiO that can be oxidized from the wall 305 and / or 448 used as the dielectric material 450. However, in embodiments, the third dielectric material (e.g., gate oxide) 350 may be any material and may be deposited as known in the art. Notwithstanding the present method, the third dielectric material generally extends along the outer periphery of each STI 346. The thickness of the third dielectric material may be between about 1 nm and about 10 nm.

[0058]

[0076] Moving to Figure 3K, the deposition of the gate or word wire material 352 in step 210 is shown. After the formation of the third dielectric material 350, the material forming the gate 352 is deposited on the third dielectric material 350 along the outer circumference of the STI 346. In embodiments, the gate 352 may be made of materials such as low-resistance metals such as tungsten, titanium nitride, titanium, ruthenium, cobalt, molybdenum, or combinations thereof.

[0059]

[0077] In the optional step 211, the material forming the gate 352 may be trimmed and / or bottom-punched, as shown in Figure 3L. For example, in the illustrated embodiment, the gap g between adjacent gates 352 spaced apart in the bit-line direction may be widened, for example, by etching, by trimming or removing a portion of the gate material 352. Additionally or alternatively, the bottom may be "punched" according to any of the methods described above to separate adjacent gates 352. Furthermore, as illustrated, in the embodiment, the gate material 352 may be etched again below the mask layer 340. However, it should be understood that in the embodiment, trimming and / or bottom punching may not be necessary, as will be explained in more detail with respect to Figures 4A and 4B.

[0060]

[0078] In any case, as shown in Figure 3M, one or more remaining 4F 2The components may be formed in an optional step 212. For example, a spacer 354 is formed within a second STI 346 between adjacent channels 348. The spacer layer 354 may be formed from any insulating material such as SiO, SiN, a low dielectric constant dielectric, or other similar material. In embodiments, the spacer layer 354 may be filled using any method known in the art and then etched back. For example, in embodiments, the spacer layer 354 may be filled to a level below the mask 340 and etched to provide a recess for the gate material 352, followed by a second filling of the same or a different insulating material. In some embodiments, a planarization process may be performed to create a flat surface on top of the stack in order to form subsequent layers and / or to expose walls 305, 348.

[0061]

[0079] Furthermore, after the remaining word line components are formed, the semiconductor structure 300 is 4F 2 The semiconductor structure 300 can re-enter the normal processing flow of a vertical cell DRAM array, such as a DRAM array, and undergo one or more further processing steps. For example, the semiconductor structure 300 may undergo contact redistribution, bonding pad formation, and / or copper contact formation.

[0062]

[0080] Regardless of the method used to form the remaining word line components, the disclosure has found that by utilizing the bridge 320, the resistivity and connectivity between adjacent channels extending in the word line direction can be improved. Nevertheless, Figure 4A shows where the word line 352 material is deposited to a thickness such that material fuses with the adjacent channel 348 until contact of material from the adjacent channel 348 is obtained (for example, material deposited around the adjacent channel continues to deposit until the material between the channels "fuse"). Such embodiments can also result in a thicker, more uniform deposition of the gate 352 material, in addition to the other advantages described above.

[0063]

[0081] However, the technology also found that the bridge 320 allows for the target deposition of the material forming the gate 352, as shown in Figure 4B. As described above, in the embodiment, the material forming the gate 352 is deposited within the gap distance (g) between adjacent channels. 2 In embodiments, the material can be deposited with a specific thickness less than half the gap distance between oxides positioned on the first and second channel sidewalls (which may be the gap distance between oxides positioned on the first and second channel sidewalls) or between adjacent word lines. Surprisingly, the presence of the bridge 320 allows for a robust connection without depositing with a thickness that would indicate fusion of the material forming the gate 352 at the location between adjacent channels or between adjacent word lines. Thus, this technique maintains or improves word line resistance while providing GAA 4F 2 The present invention provides an apparatus and method for reducing the pitch of memory cells.

[0064]

[0082] For example, in an embodiment, step 210 may include depositing word line 352 material over one or more channel or bridge surfaces of structure 300 with a thickness of about 10 nm or less, e.g., about 9 nm or less, e.g., about 8 nm or less, e.g., about 7 nm or less, e.g., about 6.5 nm or less, e.g., about 6 nm or less, e.g., about 5 nm or less, e.g., about 4.5 nm or less, e.g., about 4 nm or less, e.g., about 3.5 nm or less, e.g., about 3 nm or less, e.g., about 2.5 nm or less, e.g., about 2 nm or less, or any range or value in between. For example, in an embodiment, the word line 352 material may be formed on the gate oxide 350 with any one or more of the above thicknesses along the trench periphery and / or bridge 320.

[0065]

[0083] Furthermore, in embodiments, the technology has been found to achieve a target high consistency in the thickness of the gate 352 by utilizing the bridge 320 provided by the technology. For example, in embodiments, the thickness of the gate 352 at any point along the gate oxide film 350 may be 50% or more, for example 60% or more, for example about 70% or more, about 80% or more, about 85% or more, about 90% or more, about 92.5% or more, about 95% or more, about 97.5% or more, or about 99% or more of the average thickness of the word line 352 material in the corresponding column extending around the corresponding channel 348 or in the word line direction, for example about 99.5% or more of the average thickness of the word line 352 material in the corresponding column extending around each channel 348 or in the word line direction.

[0066]

[0084] Nevertheless, after the word line components are formed, the semiconductor structure 300 is a vertical cell GAA DRAM array (GAA 4F 2 The semiconductor structure may re-enter the normal processing flow of a DRAM array, etc., and undergo one or more further processing steps. For example, the semiconductor structure 300 may undergo contact redistribution, coupling pad formation, and / or copper contact formation. Nevertheless, the semiconductor structure may have a significantly reduced word line resistance, improved structural stability, and / or reduced or even eliminated floating body effects, at least in part due to at least some of the channels in the column in the word line direction being connected to adjacent channels in the column.

[0067]

[0085] The specific steps shown in the drawings are performed according to various embodiments of the GAA 4F 2 It should be understood that this provides a specific method for forming a DRAM array. Other sequences of steps may also be performed according to alternative embodiments. Furthermore, the individual steps shown in the figures may include multiple substeps that can be performed in various sequences depending on the individual step. Furthermore, additional steps may be added or removed depending on the particular application. Many variations, modifications, and alternatives are also included in the scope of this disclosure.

[0068]

[0086] As used herein, the terms “about,” “approximately,” and “substantially” should be interpreted as being within the range expected by those skilled in the art in light of this specification.

[0069]

[0087] In the above description, for the sake of clarity and to provide a complete understanding of various embodiments, numerous specific details have been included. However, it will be apparent that some embodiments can be carried out without some of these specific details. In other examples, well-known structures and devices are shown in the form of block diagrams.

[0070]

[0088] The above description provides only illustrative embodiments and does not limit the scope, applicability, or configuration of this disclosure. Rather, the foregoing description of various embodiments provides a feasible disclosure for implementing at least one embodiment. It should be understood that various modifications may be made to the function and arrangement of the elements without departing from the spirit and scope of some embodiments, as described in the appended claims.

[0071]

[0089] Specific details are given in the above description to provide a complete understanding of the embodiments. However, it will be understood that embodiments can be carried out even without these specific details. For example, circuits, systems, networks, processes, and other components may be shown as components in the form of block diagrams to avoid obscuring the embodiments with unnecessary details. In other examples, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary details to avoid obscuring the embodiments.

[0072]

[0090] Furthermore, note that individual embodiments have been described as processes, shown as flowcharts, flow diagrams, data flow diagrams, structural diagrams, or block diagrams. While flowcharts may sometimes describe processes as sequential, many processes can be executed in parallel or simultaneously. Moreover, the order of processes may be rearranged. A process terminates when a process is completed, but there may be additional steps not shown in the diagram. A process can correspond to a method, function, procedure, subroutine, subprogram, etc. When a process corresponds to a function, its termination may correspond to the function's return to the calling function or main function.

[0073]

[0091] The term “computer-readable medium” includes, but is not limited to, portable or fixed-storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying one or more instructions and / or data. A code segment or machine-executable instruction may represent a procedure, function, subprogram, program, routine, subroutine, module, software package, class, or any combination of instructions, data structures, or program statements. A code segment may be connected to another code segment or hardware circuit by passing information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc., may be passed, transferred, or transmitted via any suitable means, including memory sharing, message passing, token passing, network transmission, etc.

[0074]

[0092] Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, a hardware description language, or any combination thereof. If implemented by software, firmware, middleware, or microcode, program code or code segments for performing the required tasks may be stored in a machine-readable medium. One or more processors may perform the required tasks.

[0075]

[0093] While the features are described in the above specification with reference to specific embodiments, it should be noted that not all embodiments are limited thereto. Various features and aspects of several embodiments may be used individually or collectively. Furthermore, embodiments may be used in any number of environments and applications other than those described herein without departing from the broader spirit and scope of this specification. Accordingly, this specification and the drawings should be considered illustrative, not limiting.

[0076]

[0094] Furthermore, for illustrative purposes, the method has been described in a specific order. It should be understood that in alternative embodiments, the method may be performed in an order different from that described. Furthermore, it should be understood that the method described above may be performed by hardware components or embodied by a sequence of machine-executable instructions, which can be used to cause a machine (e.g., a general-purpose or special-purpose processor, or a logic circuit programmed with instructions) to perform the method. These machine-executable instructions may be stored in one or more machine-readable media (e.g., CD-ROM or other types of optical disks, floppy diskettes, ROM, RAM, EPROM, EEPROM, magnetic or optical cards, flash memory, or other types of machine-readable media suitable for storing electronic instructions). Alternatively, the method may be implemented by a combination of hardware and software.

Claims

1. A vertical cell type dynamic random access memory (DRAM) array, A first set of horizontally arranged bit lines, The plurality of bit lines intersect with the source / drain regions of the plurality of channels, the plurality of channels extending in a vertical direction that is generally perpendicular to the first horizontal direction, A bridge extending between a first channel and a second channel among the plurality of channels, wherein the first channel is separated from the second channel in a second horizontally extending column, and The second gate, which extends horizontally and is formed around at least a portion of the plurality of channels and the bridge. A vertical-cell type dynamic random access memory (DRAM) array equipped with [a specific feature].

2. The vertical cell dynamic random access memory (DRAM) array according to claim 1, wherein the gates extend between the first channel and the second channel at positions above the bridge, below the bridge, and / or both above and below the bridge.

3. The vertical cell type dynamic random access memory (DRAM) array according to claim 1, wherein the gate has a thickness of approximately 8 nm or less.

4. The vertical cell type dynamic random access memory (DRAM) array according to claim 1, wherein the gate has a thickness of less than 50% of the gap width between the first channel and the second channel.

5. The vertical cell type dynamic random access memory (DRAM) array according to claim 1, wherein the bridge is formed from a dielectric material.

6. The vertical cell type dynamic random access memory (DRAM) array according to claim 1, wherein the bridge is formed from a substrate material.

7. The vertical cell type dynamic random access memory (DRAM) array according to claim 6, wherein the bridge is formed from a p-doped substrate material.

8. A vertical cell dynamic random access memory (DRAM) array according to claim 1, further comprising at least a third channel of the plurality of channels, separated from the second channel within the second horizontally extending row, wherein a second bridge extends between the second channel and the third channel.

9. The vertical cell type dynamic random access memory (DRAM) array according to claim 8, wherein the gates extend around the second bridge.

10. A vertical cell dynamic random access memory (DRAM) array according to claim 1, wherein the first channel and the second channel define a channel height between the first source / drain region of each channel and the top surface of each channel, and the bridge is positioned between the first channel and the second channel at a height of approximately 20% to approximately 80% of the channel height.

11. A vertical cell type dynamic random access memory (DRAM) array, Multiple bit lines arranged horizontally in the first direction, Second, multiple word lines arranged horizontally, The first plurality of spaced channels in the second horizontally extending first column, A second plurality of separated channels in the second horizontally extending second column, separated from the first column, A plurality of bridges extending between adjacent channels in the first column and between adjacent channels in the second column, and One or more gates extending around the first plurality of separated channels and the plurality of bridges in the first column, the second plurality of separated channels and the plurality of bridges in the second column, or one or more gates extending around both the first plurality of separated channels and the plurality of bridges in the first column and the second plurality of separated channels and the plurality of bridges in the second column. Equipped with, A vertical-cell dynamic random access memory (DRAM) array in which each of the channels extends in a vertical direction substantially orthogonal to the first horizontal direction and the second horizontal direction, such that the plurality of bit lines intersect with the source / drain regions of the plurality of channels.

12. The vertical cell dynamic random access memory (DRAM) array according to claim 11, wherein the one or more gates extend between adjacent channels of the first row and / or the second row at positions above the bridge, below the bridge, and / or both above and below the bridge.

13. The vertical cell dynamic random access memory (DRAM) array according to claim 11, wherein the one or more gates have a thickness of less than 50% of the gap width between adjacent channels in the first row and / or the second row.

14. A method for forming a vertical cell type dynamic random access memory (DRAM) array, Etching the substrate to form one or more STIs extending in a first horizontal direction and multiple vertically extending walls having a first source / drain region at the second end of the vertically extending wall, Forming a dielectric material in one or more of the aforementioned STIs, The dielectric material is recessed into one or more STIs to a first depth, Forming a bridge within one or more STIs, wherein the bridge contacts the first side wall of the first wall and the second side wall of the second wall among the plurality of vertically extending walls. The mask is deposited on the first end of the wall extending in the vertical direction, Etching one or more second trenches extending in the second horizontal direction to form at least a first channel and a second channel, Depositing gate material around the first channel, the second channel, and the bridge, A method that includes this.

15. The method according to claim 14, wherein the gate material is deposited to a thickness of less than 50% of the width of one or more of the second trenches.

16. The method according to claim 14, wherein the gate material is deposited until the gate material deposited around the first channel and the gate material deposited around the second channel fuse together within their respective STIs.

17. The method according to claim 16, further comprising removing at least a portion of the gate material in the one or more second trenches.

18. The method according to claim 14, further comprising maintaining the mask while etching the one or more second trenches and while depositing the gate material.

19. The method according to claim 14, further comprising recessing the bridge from a first height to a second height lower than the first height before depositing the gate material.

20. The method according to claim 14, further comprising: recessing the dielectric material to a first depth, then forming a protective liner on one or more STIs; and recessing the dielectric material to a second depth on one or more STIs that are lower than the first depth.

Images